KSZ8895MQX/RQX/FQX/ML
Integrated 5 -Port 10/100 Managed Ethernet
Switch with MII/RMI I Interfac e
Revision 1.3
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October
26, 2015
Revision 1.3
General Description
The KSZ8895MQX/RQX/FQX/ML is a highly-integrated,
Layer 2 managed, five-port switch with numerous features
designed to reduce system cost. Intended for cost-
sensitive 10/100Mbps five-port switch systems with low
power consumption, on-chip termination, and internal core
power controllers, it supports high-performance memory
bandwidth and shared memory-based switch fabric with
non-blocking configuration. Its extensive feature set
includes po wer managem ent, program mable rate limit and
priority ratio, tag/port-based VLAN, packets filtering, four-
queue QoS prioritization, m anag ement interfaces, and MIB
counters. The KSZ8895 f am ily provides multiple C PU data
interfac es to effec tivel y add res s both c urr ent an d emergin g
fast Ethernet applications when Port 5 is configured to
separate MAC5 with SW5-MII/RMII and PHY5 with P5-
MII/RMII interfaces.
The KSZ8895 family offers three configurations, providing
the flexibility to meet different requirements:
• KSZ8895MQX/ML: 5 10/100Base-T/TX transceivers, 1
SW5-MII and 1 P5-MII interface
• KSZ8895RQX: 5 10/100Base-T/TX transceivers,
1 SW5-RMII and 1 P5-RMII interface
• KSZ8895FQX: 4 10/100Base-T/TX transceivers on
Ports 1, 2, 3 and 5 (port 3 can be set to the fiber
mode). 1 100Base-FX transceivers on Port 4. 1 SW5-
MII and 1 P5-MII interface
All registers of MACs and PHYs units can be managed by
the SPI or the SMI interface. MIIM registers can be
access ed through the MDC/MDIO interfac e. EEPRO M can
set all control registers for the unmanaged mode.
KSZ8895MQX/RQX/FQX are 128-pin PQFP package.
KSZ8895ML is 128-pin LQFP package.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Functional Diagram
Look Up
Engine
Queue
Management
10/100
MAC 1
FIFO, Flow Control, VLAN
Tagging, Priority
SPI
EEPROM
Interface
LED I/F
Auto MDI/MDIX
Control Reg SPI I/F
MIB
Counters
LED0[5:1]
LED1[5:1]
LED2[5:1]
Control
Registers
MDC/MDIO for MIIM and SMI
SW5-MII/RMII or SNI
Auto MDI/MDIX
Auto MDI/MDIX
Auto MDI/MDIX
Auto MDI/MDIX
P5-MII/RMII
10/100
T/TX/FX
PHY3
10/100
T/TX/FX
PHY4
10/100
T/TX
PHY5
KSZ8895MQX/RQX/FQX/ML
10/100
T/TX
PHY1
10/100
T/TX
PHY2
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
Buffer
Management
Frame
Buffers
Note:
SW5 indicates the MAC5 of the switch side, P5 indicates the PHY5 of the Port 5.
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 2 Revision 1.3
Features
Advanced Switch Features
• IEEE 802.1q VLAN support for up to 128 active VLAN
groups (full-range 4096 of VLAN IDs).
• Static MAC table supports up to 32 entries.
• VLAN ID tag/untag options, per port basis
• IEEE 802.1p/q tag insertion or removal on a per port
basis based on ingress port (egress).
• Programmable rate limiting at the ingress and egress
on a per port basis.
• Jitter-free per packet based rate limiting support.
• Broadcast storm protection with percentage control
(global and per port basis).
• IEEE 802.1d rapid spanning tree protocol RSTP
support.
• Tail tag mode (1 byte added before FCS) support at
Port 5 to inform the processor which ingress port
receives the packet.
• 1.4Gbps high-performance memory bandwidth and
shared memory-based switch fabric with fully non-
blocking configuration.
• Dual MII with MAC5 and PHY5 on port 5, SW5-
MII/RMII for MAC 5 and P5-MII/RMII for PHY 5.
• Enable/Disable option for huge frame size up to 2000
Bytes per frame.
• IGMP v1/v2 snooping (Ipv4) support for multicast
packet filtering.
• IPv4/IPv6 QoS support.
• Support unknown unicast/multicast address and
unknown VID packet filtering.
• Self-address filtering.
Comprehe nsive C o nfiguration Regi ster Access
• Serial management interface (MDC/MDIO) to all PHYs
registers and SMI interface (MDC/MDIO) to all
registers.
• High speed SPI (up to 25MHz) and I2C master
Interface to all internal registers.
• I/0 pins strapping and EEPROM to program selective
registers in unmanaged switch mode.
• Control registers configurable on the fly (port-priority,
802.1p/d /q, AN and so on).
QoS/CoS Packet Prioritization Support
• Per port, 802.1p and DiffServ-based.
• 1/2/4-queue QoS prioritization selection.
• Programmable weighted fair queuing for ratio control.
• Re-mapping of 802.1p priority field per port basis.
Integrated Five-Port 10/100 Ethernet Switch
• New generation switch with five MACs and five PHYs
with fully compliant with IEEE 802.3u standard.
• PHYs designed with patented enhanced mixed-signal
technology.
• Non-blocking switch fabric assures fast packet
deliver y by utili zing a 1K MAC address lookup table
and a store-and-forward architecture.
• On-chip 64Kbyte memory for frame buffering (not
shared with 1K unic as t add r ess table).
• Full duplex IEEE 802.3x flow control (PAUSE) with
force mode option.
• Half-duplex back pressure flow control.
• HP Auto MDI/MDI-X and IEEE Auto crossover
support.
• SW-MII interface supports both MAC mode and PHY
mode.
• 7-wire serial network interface (SNI) support for
legacy MAC.
• Per port LED Indicators for link, activity, and 10/100
speed.
• Register port status support for link, activity, full/half
duplex and 10/100 speed.
• Micrel LinkMD® cable diagnostic capabilities.
• On-chip terminations and internal biasing technology
for cost down and lo west p o wer consumption.
Switch Monitoring Features
• Port mirroring/monitoring/sniffing: ingress and/or
egress traffic to any port or MII.
• MIB counters for fully compliant statistics gathering 34
MIB counters per port.
• Loop-back support for MAC, PHY and remote
diagnostic of failure.
• Interrupt for the link change on any ports.
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 3 Revision 1.3
Features (Continued)
Low Power Dissipation
• Full-chip hardware power-down.
• Full-chip software power-down and per port software
power down.
• Energy-detect mode support < 100mW full chip-power
consumption when all ports have no activity.
• Very low full chip power consumption (<0.5W) in
standalone 5-port, without extra power consumption
on transformers.
• Dynamic clock tree shutdown feature.
• Voltages: Single 3.3V supply with 3.3V VDDIO and
Internal 1.2V LDO controller enabled, or external 1.2V
LDO solution.
− Analog VDDAT 3.3V only.
− VDDIO support 3.3 V, 2.5V and 1.8V.
− Low 1.2V core power .
• 0.11µm CMOS technology.
• Commercial temperature range: 0°C to +70 °C.
• Industrial Temperature Range: -40°C to +85°C.
• 128-pin PQFP and 128-pin LQFP, lead-free package.
Applications
• Typical
• VOIP phone
• Set-top/game box
• Automotive
• Industrial control
• IPTV POF
• SOHO residential gateway
• Broadband gateway/firewall/VPN
• Integrated DSL/cable modem
• Wireless LAN access point + gateway
• Standalone 10/100 5-port switch
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 4 Revision 1.3
Ordering Information
Part Number Temperature Range Package Description
KSZ8895MQXCA 0°C to 70°C 128-Pin PQFP MII, Pb-Free, Commercial temperature
KSZ8895MQXIA -40°C to +85°C 128-Pin PQFP MII, Pb-Free, Industrial temperature
KSZ8895RQXCA 0°C to 70°C 128-Pin PQFP RMII, Pb-Free, Commercial temperature
KSZ8895RQXIA -40°C to +85°C 128-Pin PQFP RMII, Pb-Free, Industrial temperature
KSZ8895FQXCA 0°C to 70°C 128-Pin PQFP MII, support fiber, Pb-Free, Commercial part
KSZ8895FQXIA -40°C to +85°C 128-Pin PQFP MII, support fiber, Pb-Free, Industrial part
KSZ8895ML 0°C to 70°C 128-Pin LQFP MII, Pb-Free, Commercial temperature
KSZ8895MLI -40°C to +85°C 128-Pin LQFP MII, Pb-Free, Industrial temperature
KSZ8895MQX-EVAL Evaluation Board for KSZ8895MQX
KSZ8895RQX-EVAL Evaluation Board for KSZ8895RQX
KSZ8895FQX-EVAL Evaluation Board for KSZ8895FQX
KSZ8895ML-EVAL Evaluation Board for KSZ8895ML
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 5 Revision 1.3
Revision History
Revision Description Date
1.0 Initial document created O2/21/14
1.1
Update description for Register 1 bits [7:4], update the
descriptions in the section of the internal 1.2V LDO
controller. Update the Pin 125/Pin126 descriptions. Add
evaluation boards in ordering information.
04/28/14
1.2
Update registers 131-134 bits [4:0] descriptions. Update
Figure 16 and Figure 18. Add 100Base-FX data in
Electrical Characteristics Table. Update Figure 3. Update
pin description for Pin 107 and Pin 108. Ad ded si lv er
wire bonding part numbers to Ordering Information.
Updated Ordering Information to include Ordering Part
Number and Device Marking. Add a note for the register
14 bits [4:3].
12/9/14
1.3
Add register 137 (0x89) for 0.11µm and 0.13µm silicon
identification.
Update 1.2V core power high to 1.32V (1.2V+10%) in
Operating Ratings section.
Updated the Ordering Information Table to include only
standard part s number s.
Updated description for Figure 35.
10/26/15
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 6 Revision 1.3
Contents
List of Figures .................................................................................................................................................................. 8
List of Tables ................................................................................................................................................................... 9
System Level Applications ............................................................................................................................................ 10
Pin Configurations ......................................................................................................................................................... 12
Pin Description .............................................................................................................................................................. 14
Pins for Strap-in Options ............................................................................................................................................... 23
Introduction .................................................................................................................................................................... 27
Functional Overview: Physical Layer Transceiver ........................................................................................................ 27
100BASE-TX Transmit .............................................................................................................................................. 27
100BASE-TX Receive ............................................................................................................................................... 27
PLL Clock Synthesizer .............................................................................................................................................. 28
Scrambler/Descrambler (100BASE-TX only) ............................................................................................................ 28
100BASE-FX Operation ............................................................................................................................................ 28
100BASE-FX Signal Detection .................................................................................................................................. 28
100BASE-FX Far End Fault ...................................................................................................................................... 28
10BASE-T Transmit .................................................................................................................................................. 28
10BASE-T Receive ................................................................................................................................................... 28
MDI/MDI-X Auto Crossover ....................................................................................................................................... 28
Straight Cab le ........................................................................................................................................................ 29
Crossover Cable .................................................................................................................................................... 30
Auto-Negotiation ........................................................................................................................................................ 30
LinkMD® Cab le Di agn os tic s ...................................................................................................................................... 32
Access .................................................................................................................................................................... 32
Usage ..................................................................................................................................................................... 32
A LinkMD Example ................................................................................................................................................ 33
On-Chip Termination Resistors ................................................................................................................................. 33
Internal 1.2V LDO Controller ..................................................................................................................................... 33
Functional Overview: Power ......................................................................................................................................... 34
Using Internal 1.2V LDO Controller ........................................................................................................................... 34
Using External 1.2V LDO Regulator ......................................................................................................................... 35
Functional Overview: Power Management ................................................................................................................... 36
Normal Operation Mode ............................................................................................................................................ 36
Energy Detect Mode .................................................................................................................................................. 36
Soft Power Down Mode ............................................................................................................................................. 37
Power Saving Mod e .................................................................................................................................................. 37
Port-Based Power-Down Mode ................................................................................................................................. 37
Functional Overview: Switch Core ................................................................................................................................ 37
Address Look-Up ....................................................................................................................................................... 37
Learning ..................................................................................................................................................................... 37
Migration .................................................................................................................................................................... 37
Aging ......................................................................................................................................................................... 38
Forwarding................................................................................................................................................................. 38
Switching Engine ....................................................................................................................................................... 38
Media Access Controller (MAC) Operation ............................................................................................................... 38
Inter-Packet Gap (IPG) .......................................................................................................................................... 38
Backoff Algorithm ................................................................................................................................................... 38
Late Collision.......................................................................................................................................................... 38
Illegal Frames......................................................................................................................................................... 38
Flow Control ........................................................................................................................................................... 38
Half-Duplex Back Pressure .................................................................................................................................... 41
Broadcast Storm Protection ................................................................................................................................... 41
MII Interface Operation .............................................................................................................................................. 41
Port 5 PHY 5 P5-MII/RMII Interface .......................................................................................................................... 41
Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQX ............................................................................. 44
SNI Interface Operation ............................................................................................................................................. 46
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 7 Revision 1.3
Advanced Functionality ................................................................................................................................................. 47
QoS Priori t y Support ................................................................................................................................................. 47
Port-Bas ed Priority ................................................................................................................................................. 47
802.1p-Bas ed Priority ............................................................................................................................................ 47
DiffServ-Based Priority ........................................................................................................................................... 48
Spanning Tree Support ............................................................................................................................................. 48
Rapid Spanning Tree Support ................................................................................................................................... 49
Tail Tagging Mode ..................................................................................................................................................... 50
IGMP Support ............................................................................................................................................................ 51
IGMP Snoop ing ...................................................................................................................................................... 51
IGMP Send Back to the Subsc ribed Port ............................................................................................................... 51
Port Mirroring Support ............................................................................................................................................... 51
“Receive Only” Mirror on a Port ............................................................................................................................. 51
“Transmit Only” Mirror on a Port ............................................................................................................................ 51
“Receive and Transmit” Mirror on Two Ports ......................................................................................................... 51
VLAN Support ........................................................................................................................................................... 51
Rate Limiting Support ................................................................................................................................................ 52
Ingress Rate Limit .................................................................................................................................................. 52
Egress Rate Limit ................................................................................................................................................... 53
Transmit Queue Ratio Programming ..................................................................................................................... 53
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast ................. 53
Configuration Interface .................................................................................................................................................. 54
I2C Master Serial Bus Configuration .......................................................................................................................... 54
SPI Slave Serial Bus Conf i gurat ion ....................................................................................................................... 55
MII Management Interface (MIIM) ......................................................................................................................... 57
Serial Management Interface (SMI) ....................................................................................................................... 58
Register Descriptions .................................................................................................................................................... 59
Global Registers ........................................................................................................................................................ 60
Port Registers ............................................................................................................................................................ 70
Advanced Control Registers...................................................................................................................................... 80
Data Rate Limit Selection Limit Table ....................................................................................................................... 95
Static MAC Address Table ............................................................................................................................................ 96
Dynamic MAC Address Table ..................................................................................................................................... 101
MIB (Management Information Base) Counters ......................................................................................................... 103
For Port 1................................................................................................................................................................. 103
For Port 2................................................................................................................................................................. 104
For Port 3................................................................................................................................................................. 104
For Port 4................................................................................................................................................................. 104
For Port 5................................................................................................................................................................. 104
MIIM Registers ............................................................................................................................................................ 107
Absolute Maximum Ratings ........................................................................................................................................ 111
Operating Ratings ....................................................................................................................................................... 111
Electrical Characteristics ............................................................................................................................................. 111
Timing Diagrams ......................................................................................................................................................... 114
EEPROM Timing ..................................................................................................................................................... 114
SNI Timing ............................................................................................................................................................... 115
MII Timing ................................................................................................................................................................ 116
SPI Timing ............................................................................................................................................................... 119
Auto-Negotiation Timing .......................................................................................................................................... 121
MDC/MDIO Timing .................................................................................................................................................. 122
Reset Timing ........................................................................................................................................................... 123
Reset Circuit Diagram ............................................................................................................................................. 124
Selection of Isolation Transformer .............................................................................................................................. 125
Selection of Reference Cr ystal .................................................................................................................................... 125
Package Information and Recommended Landing Pattern ........................................................................................ 126
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 8 Revision 1.3
List of Figures
Figure 1. Broadband Gateway .................................................................................................................................... 10
Figure 2. Integrated Broadband Router ...................................................................................................................... 10
Figure 3. Standa lo ne S wit c h ....................................................................................................................................... 11
Figure 4. Using KSZ8895FQX for Dual Media Converter ........................................................................................... 11
Figure 5. T ypical Stra ig ht Cabl e Co nnect io n .............................................................................................................. 29
Figure 6. T ypic a l Cr ossover Cable Connection .......................................................................................................... 30
Figure 7. Auto-Negotiation .......................................................................................................................................... 31
Figure 8. Recommended 1.2V Power Connection using Internal 1.2V LDO Controller ............................................. 34
Figure 9. Recommended 1.2V Power Connection Using the External 1.2V Regulator .............................................. 35
Figure 10. Destination Address Lookup Flow Chart, Stage 1 ....................................................................................... 39
Figure 11. Destination Address Resolution Flow Chart, Stage 2 .................................................................................. 40
Figure 12. 802.1p Pr ior ity Field Form at......................................................................................................................... 47
Figure 13. Tail Tag Frame Format ................................................................................................................................ 50
Figure 14. KSZ88 95MQ X /R Q X /FQ X /ML EEPROM Configuration Timing Diagram ..................................................... 54
Figure 15. SPI Write Data Cycle ................................................................................................................................... 56
Figure 16. SPI Read Dat a C ycle ................................................................................................................................... 56
Figure 17. SPI Mult ip le W r ite ........................................................................................................................................ 56
Figure 18. SPI Multiple Read ........................................................................................................................................ 57
Figure 19. EEPROM Interface Input Receive Timing Diagram ................................................................................... 114
Figure 20. EEPROM Interface Output Transmit Timing Diagram ............................................................................... 114
Figure 21. SNI Input Timing ........................................................................................................................................ 115
Figure 22. SNI Output Timing ..................................................................................................................................... 115
Figure 23. MAC Mode MII Timing – Data Received from MII ..................................................................................... 116
Figure 24. MAC Mode MII Timing – Data Transmitted from MII ................................................................................. 116
Figure 25. PHY Mode MII Timing – Data Received from MII ...................................................................................... 117
Figure 26. PHY Mode MII Timing – Data Transmitted from MII .................................................................................. 117
Figure 27. RMII Timing – Data Received from RMII ................................................................................................... 118
Figure 28. RMII Timing – Data Transmitted to RMII ................................................................................................... 118
Figure 29. SPI Input Timing ........................................................................................................................................ 119
Figure 30. SPI Output Timing ...................................................................................................................................... 120
Figure 31. Auto-Negotiation Timing ............................................................................................................................ 121
Figure 32. MDC/MDIO Timing ..................................................................................................................................... 122
Figure 33. Reset T iming .............................................................................................................................................. 123
Figure 34. Recom mended Res et Circ uit ..................................................................................................................... 124
Figure 35. Recom mended Circ uit for Int erf ac ing with CPU/FPGA Reset ................................................................... 124
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 9 Revision 1.3
List of Tables
Table 1. MDI/MDI-X Pin Definitions ............................................................................................................................ 29
Table 2. Voltages and Power Pins .............................................................................................................................. 34
Table 3. Internal Function Block Status ...................................................................................................................... 36
Table 4. Port 5 PHY P5-MII/RMII Signals ................................................................................................................... 42
Table 5. Switch MAC5 MII Signals .............................................................................................................................. 43
Table 6. Port 5 MAC5 SW5-RMII Connection ............................................................................................................. 45
Table 7. SNI Signals.................................................................................................................................................... 46
Table 8. Tail Tag Rules ............................................................................................................................................... 50
Table 9. FID +DA Look -Up in the VLAN Mode ............................................................................................................ 52
Table 10. FID+SA Look-Up in the VLAN Mode............................................................................................................. 52
Table 11. SPI Connections ........................................................................................................................................... 55
Table 12. MII Management Interface Frame Format .................................................................................................... 57
Table 13. Serial Management Interface (SMI) Frame Format ...................................................................................... 58
Table 14. 10/100BT Rate Selection for the Rate limit ................................................................................................... 95
Table 15. Static MAC Address Table ............................................................................................................................ 96
Table 16. VLAN Table ................................................................................................................................................... 98
Table 17. VLAN ID and Indirect Registers .................................................................................................................. 100
Table 18. Dynamic MAC Address Table ..................................................................................................................... 101
Table 19. Port 1 MIB Counter Indirect Memory Offsets .............................................................................................. 103
Table 20. Format of “Per Port” MIB Counter ............................................................................................................... 104
Table 21. All Port Dropp ed Packet MIB Counters ....................................................................................................... 104
Table 22. Format of “All Dropped Packet” MIB Counter ............................................................................................. 105
Table 23. EEPROM Timing Parameters ..................................................................................................................... 114
Table 24. SNI Timing Parameters ............................................................................................................................... 115
Table 25. MAC Mode MII Timing Parameters ............................................................................................................. 116
Table 26. PHY Mode MII Timing Parameters ............................................................................................................. 117
Table 27. RMII Timing Parameters ............................................................................................................................. 118
Table 28. SPI Input Tim ing Parameters ...................................................................................................................... 119
Table 29. SPI Output Timing Parameters ................................................................................................................... 120
Table 30. Auto-Negotiation Timing Parameters .......................................................................................................... 121
Table 31. MDC/MDIO Typical Timing Parameters ...................................................................................................... 122
Table 32. Reset Timing Parameters ........................................................................................................................... 123
Table 33. Transformer Selection Criteria .................................................................................................................... 125
Table 34. Qualified Magnetic Vendors ........................................................................................................................ 125
Table 35. Typical Reference Crystal Characteristics .................................................................................................. 125
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 10 Revision 1.3
System Level Applications
Figure 1. Broadband Gateway
Figure 2. Integrated Broadband Router
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 11 Revision 1.3
System Level Applications (Continued)
Figure 3. Standalone Switch
Figure 4. Using KSZ8895FQX for Dual Media Converter
Switch Controller
On-Chip Frame Buffers
10/100
PHY 5
5-port
LAN
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
10/100
PHY 1
10/100
PHY 2
10/100
PHY 3
10/100
PHY 4
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 12 Revision 1.3
Pin Configurations
TXM5
VDDAT
FXSD3
TXP5
33
34
35
36
37
38
KSZ8895MQX/RQX/FQX
(Top View)
NC
PMRXDV/PMCRSDV
NC
NC
NC
NC
NC
NC
PWRDN_N
INTR_N
GNDD
VDDC
PMTXEN
PMTXD3
PMTXD2
PMTXD1
PMTXD0
PMTXER
PMTXC/PMREFCLK
GNDD
PMRXD1
VDDIO
PMRXC
PMRXD3
PMRXD2
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
64
FXSD4
LED3-1
LED4-0
LED3-2
SCONF1
SCOL
SMRXD2
VDDIO
SMTXC/SMREFCLK
SMTXD0
SMTXD2
SMTXEN
PCOL
PCRS
PMRXER
LED4-1
LED4-2
LED5-1
LED5-2
VDDC
GNDD
SCONF0
SCRS
SMRXD0
SMRXD1
SMRXD3
SMRXDV/SMCRSDV
SMRXC
GNDD
SMTXER
SMTXD1
SMTXD3
PMRXD0
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
LED2-1
LED2-2
VDDIO
GNDD
LED3-0
101
100
99
98
97
LED2-0
102
103
GNDA
LED1-0
MDIXDIS
TEST2
GNDA
IN_PWR_SEL
LDO_O
NC
X2
X1
NC
SCANEN
TESTEN
VDDC
GNDD
RST_N
PS0
PS1
SPIS_N
SPID/SDA
SPIC/SCL
SPIQ
MDIO
MDC
LED1-1
LED1-2104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VDDAR
RXP1
RXM1
GNDA
TXP1
TXM1
VDDAT
RXP2
RXM2
RXM3
TXP3
RXP4
TXM4
VDDAR
RXM5
GNDA
GNDA
TXP2
TXM2
VDDAR
GNDA
ISET
VDDAT
RXP3
GNDA
TXM3
VDDAT
RXM4
GNDA
TXP4
GNDA
RXP5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
LED5-0
128-Pin PQFP
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 13 Revision 1.3
Pin Configurations (Continue d)
TXM5
VDDAT
NC
TXP5
33
34
35
36
37
38
KSZ8895ML
(Top View)
NC
PMRXDV
NC
NC
NC
NC
NC
NC
PWRDN_N
INTR_N
GNDD
VDDC
PMTXEN
PMTXD3
PMTXD2
PMTXD1
PMTXD0
PMTXER
PMTXC
GNDD
PMRXD1
VDDIO
PMRXC
PMRXD3
PMRXD2
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
64
NC
LED3-1
LED4-0
LED3-2
SCONF1
SCOL
SMRXD2
VDDIO
SMTXC
SMTXD0
SMTXD2
SMTXEN
PCOL
PCRS
PMRXER
LED4-1
LED4-2
LED5-1
LED5-2
VDDC
GNDD
SCONF0
SCRS
SMRXD0
SMRXD1
SMRXD3
SMRXDV
SMRXC
GNDD
SMTXER
SMTXD1
SMTXD3
PMRXD0
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
LED2-1
LED2-2
VDDIO
GNDD
LED3-0
101
100
99
98
97
LED2-0 102
103
GNDA
LED1-0
MDIXDIS
TEST2
GNDA
IN_PWR_SEL
LDO_O
NC
X2
X1
NC
SCANEN
TESTEN
VDDC
GNDD
RST_N
PS0
PS1
SPIS_N
SPID/SDA
SPIC/SCL
SPIQ
MDIO
MDC
LED1-1
LED1-2 104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VDDAR
RXP1
RXM1
GNDA
TXP1
TXM1
VDDAT
RXP2
RXM2
RXM3
TXP3
RXP4
TXM4
VDDAR
RXM5
GNDA
GNDA
TXP2
TXM2
VDDAR
GNDA
ISET
VDDAT
RXP3
GNDA
TXM3
VDDAT
RXM4
GNDA
TXP4
GNDA
RXP5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
LED5-0
128-Pin LQFP Pin Configuration
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 14 Revision 1.3
Pin Description
Pin
Number Pin Name Type(1) Port Pin Function(2)
1 MDI-XDIS IPD 1 − 5 Disable auto MDI/MDI-X.
PD (default) = normal opera tio n.
PU = disable auto MDI/MDI-X on all ports.
2 GNDA GND Analog ground.
3 VDDAR P 1.2V analog VDD.
4 RXP1 I 1 Physical receive sig nal + (differentia l).
5 RXM1 I 1 Physical receiv e sig nal - (differential).
6 GNDA GND Analog ground.
7 TXP1 O 1 Physical transmit sig nal + (differenti al).
8 TXM1 O 1 Physical trans mit signal - (differential).
9 VDDAT P 3.3V analog VDD.
10 RXP2 I 2 Physical receiv e sig nal + (diff e rentia l) .
11 RXM2 I 2 Physical re ceive sig nal - (differential).
12 GNDA GND Analog ground.
13 TXP2 O 2 Physical trans mit sig nal + (dif f erent i al).
14 TXM2 O 2 Physica l tra ns mit sig na l - (differential).
15 VDDAR P 1.2V analog VDD.
16 GNDA GND Analog ground.
17 ISET Set physical transmit output current. Pull-down with a
12.4kΩ1% resistor.
18 VDDAT P 3.3V analog VDD.
19 RXP3 I 3 Physical receiv e sig nal + (diff e rentia l) .
20 RXM3 I 3 Physical re ceive sig nal - (differential).
21 GNDA GND Analog ground.
22 TXP3 O 3 Physical trans mit sig nal + (dif f erent i al).
23 TXM3 O 3 Physica l tra ns mit sig na l – (differential).
Notes:
1. P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
GND = Ground.
IPU = Input w/internal pul l -up.
IPD = Input w/internal pull-down.
IPD/O = Input w/internal pull-down during reset, output pin otherwise.
OTRI = Output tristated.
2. NC = Do not connect to PCB.
PU = Strap pin pull-up.
PD = Strap pull-down.
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 15 Revision 1.3
Pin Description (Continued)
Pin
Number Pin Name Type(1) Port Pin Function(2)
24 VDDAT P 3.3V analog VDD.
25 RXP4 I 4 Physical receiv e sig nal + (diff e rentia l) .
26 RXM4 I 4 Physical re ceive sig nal - (differential).
27 GNDA GND Analog ground.
28 TXP4 O 4 Physical trans mit sig nal + (dif f erent i al).
29 TXM4 O 4 Physica l tra ns mit sig na l - (differential).
30 GNDA GND Analog ground.
31 VDDAR P 1.2V analog VDD.
32 RXP5 I 5 Physical receiv e sig nal + (diff e rentia l) .
33 RXM5 I 5 Physical re ceive sig nal - (differential).
34 GNDA GND Analog ground.
35 TXP5 O 5 Physical trans mit sig nal + (dif f erent i al).
36 TXM5 O 5 Physica l tra ns mit sig na l - (differential).
37 VDDAT P 3.3V analog VDD.
38 NC/FXSD3 IPD 3
FQX: This pin can be floating when port 3 is used as copper port
(default). Por t 3 can be set to fiber mode by Regi ster 239 bit [7], this
pin is used for fiber si gnal detect pin on Port 3 in Fiber mode.
MQX/RQX/ML: no connection.
39 FXSD4 IPD 4 FQX: Fiber signal detect pin for Port 4.
MQX/RQX/ML: no connection.
40 NC NC No connection. Leave NC pin floating.
41 NC NC No connection. Leave NC pin floating.
42 NC NC No connection. Leave NC pin floating.
43 NC NC No connection. Leave NC pin floating.
44 NC NC No connection. Leave NC pin floating.
45 NC NC No connection. Leave NC pin floating.
46 NC NC No connection. Leave NC pin floating.
47 PWRDN_N IPU Full-chip power down. Active low.
48 INTR_N OPU Interrupt. This pin is Open-Dra in output pin.
49 GNDD GND Digital ground.
50 VDDC P 1.2V digital core VDD.
51 PMTXEN IPD 5 PHY [5] MII/RMII transmit enable.
52 PMTXD3 IPD 5 MQX/FQX/ML: PHY [ 5] MII transmit bit 3.
RQX: no connection for RMII.
53 PMTXD2 IPD 5 MQX/FQX/ML: PHY [ 5] MII transmit bit 2.
RQX: no connection for RMII.
54 PMTXD1 IPD 5 PHY [5] MII/RMII transmit bit 1.
55 PMTXD0 IPD 5 PHY [5] MII/RMII transmit bit 0.
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 16 Revision 1.3
Pin Description (Continued)
Pin
Number Pin Name Type(1) Port Pin Function(2)
56 PMTXER IPD 5 MQX/FQX/ML: PHY [ 5] MII transmit error. RQX: no connection for
RMII.
57 PMTXC/PMREFCLK I/O 5 MQX/FQX/ML: Output PHY [5] MII transmit clock
RQX: Input PHY [5] RMII reference clock, 50MHz ±50ppm, the
50MHz clock comes from PMRXC Pin 60.
58 GNDD GND Digital ground.
59 VDDIO P 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
60 PMRXC I/O 5
MQX/FQX/ML: Output PHY [5] MII receive clock.
RQX: Output PHY [ 5] RMII reference clock, this clock is used when
opposite doesn’t provide RMII 50MHz clock or the system doesn’t
provide an external 50MHz clock for the P5-RMII interface.
61 PMRXDV/PMCRSDV IPD/O 5 MQX/FQX/ML: PMRXDV is for PHY [5] MII receive data va lid .
RQX: PMCRSDV is fo r PHY [5] RMII C arrier Sense/R eceiv e D ata
Valid Output.
62 PMRXD3 IPD/O 5
MQX/FQX/ML: PHY [5] MII receive bit 3.
RQX: no connection for RMII.
Strap option:
PD (default) = enable flow control.
PU = disable flow control.
63 PMRXD2 IPD/O 5
MQX/FQX/ML: PHY [5] MII receive bit 2.
RQX: no connection for RMII.
Strap option:
PD (default) = disable back pressure.
PU = enable back pressure.
64 PMRXD1 IPD/O 5
PHY [5] MII/RMII receive bit 1.
Strap option:
PD (default) = drop excessive coll is ion pac ket s.
PU = does not drop excess iv e coll is ion packets.
65 PMRXD0 IPD/O 5
PHY [5] MII/RMII receive bit 0.
Strap option:
PD (default) = disable aggressive back-off algorithm in half-duplex
mode.
PU = enable for performance enhancement.
66 PMRXER IPD/O 5
MQX/FQX/ML:PHY [ 5] MII receive error
RQX: no connection for RMII
Strap option:
PD (default) = packet size 1518/1522 bytes.
PU = 1536 bytes.
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 17 Revision 1.3
Pin Descriptions (Continued)
Pin
Number Pin Name Type(1) Port Pin Function(2)
67 PCRS IPD/O 5
MQX/FQX/ML: PHY [5] MII carrier sense.
RQX: no connection for RMII.
Strap option for port 4 only.
PD (default) = force half-duplex if auto-negotiation is disabled or
fails.
PU = force full-duplex if auto negotiation is disabled or fails. Refer to
Register 76.
68 PCOL IPD/O 5
MQX/FQX/ML: PHY [5] MII collision detect.
RQX: no connection.
Strap option for port 4 only.
PD (default) = no force flow control, normal opera tio n.
PU = force flow control. Refer to Register 66.
69 SMTXEN IPD Port 5 Switch MII/RMII transmit enable.
70 SMTXD3 IPD MQX/FQX/ML: Port 5 Switch MII transmit bit 3.
RQX: no connection for RMII.
71 SMTXD2 IPD MQX/FQX/ML: Port 5 Switch MII transmit bit 2.
RQX: no connection for RMII.
72 SMTXD1 IPD Port 5 Switch MII/RMII transmit bit 1.
73 SMTXD0 IPD Port 5 Switch MII/RMII transmit bit 0.
74 SMTXER IPD MQX/FQX/ML: Port 5 Switch MII transmit error.
RQX: no connection for RMII.
75 SMTXC/SMREFCLK
I/O
MQX/FQX/ML: Port 5 Switch MII transmit clock,
Input: SW5-MII MAC mode, Output: SW5-MII PHY modes.
RQX: Input SW5-RMII 50MHz +/-50ppm refere nce cloc k. The
50MHz clock comes from SMRXC Pin 78 when the device is the
clock mode which the device’s clock comes from 25MHz
crystal/oscillator from Pins X1/X2. Or the 50MHz clock comes from
external 50MHz clock source when the device is the normal mode
which the device’s clock source comes from SMTXC pin not from
X1/X2 pins.
76 GNDD GND Digital ground.
77 VDDIO P 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
78 SMRXC I/O
MQX/FQX/ML: Port 5 Switch MII receive clock,
Input: SW5-MII MAC mode, Output: SW5-MII PHY mode.
RQX: Output SW5-RMII 50MHz clock, this clock is used when
opposite doesn’t provide RMII reference clock or the system doesn’t
provide an external 50MHz clock for the RMII interface.
79 SMRXDV/SMCRSDV IPD/O MQX/FQX/ML: SMRXDV is for Switch MAC 5 MI I receive data valid.
RQX: SMCRSDV is fo r MAC5 RMII Carrier Sense/Receive Data
Valid Output.
80 SMRXD3 IPD/O
MQX/FQX/ML: Port 5 Switch MII receive bit 3.
RQX: no connection for RMII
Strap option:
PD (default) = Disable Switch SW5-MII full-duplex flow control
PU = Enable Switch SW5-MII full-duplex flow control.
Micrel, Inc.
KSZ8895MQX/RQX/FQX/ML
26, 2015 18 Revision 1.3
Pin Description (Continued)
Pin
Number Pin Name Type(1) Port Pin Function(2)
81 SMRXD2 IPD/O
MQX/FQX/ML: Port 5 Switch MII receive bit 2.
RQX: no connection for RMII
Strap option:
PD (default) = Switch SW5-MII in full-duplex mode;
PU = Switch SW5-MII in half-duplex mode.
82 SMRXD1 IPD/O
Port 5 Switch MII/RMII receive bit 1.
Strap option:
PD (default) = Port 5 Switch SW5-MII in 100Mbps mode.
PU = Switch SW5-MII in 10Mbps mode.
83 SMRXD0 IPD/O
Port 5 Switch MII/RMII receive bit 0.
Strap option:
LED mode
PD (default) = mode 0; PU = mode 1. See “Register 11.”
Mode 0, link at:
100/Full LEDx[2,1,0] = 0, 0, 0
100/Half LEDx[2,1,0] = 0, 1, 0
10/Full LEDx[2,1,0] = 0, 0, 1
10/Half LEDx[2,1,0] = 0, 1, 1
Mode 1, link at:
100/Full LEDx[2,1,0] = 0, 1, 0
100/Half LEDx[2,1,0] = 0, 1, 1
10/Full LEDx[2,1,0] = 1, 0, 0
10/Half LEDx[2,1,0] = 1, 0, 1
Mode 0 Mode 1
LEDX_2 Lnk/Act 100Lnk/Act
LEDX_1 Fulld/Col 10Lnk/Act
LEDX_0 Speed Full dupl ex
84 SCOL IPD/O MQX/FQX/ML: Port switch MII collision detect,
Input: SW5-MII MAC modes, Output: SW5-MII PHY modes
RQX: no connection for RMII
85 SCRS IPD/O MQX/FQX/ML: Port switch MII collision detect,
Input: SW5-MII MAC modes, Output: SW5-MII PHY modes
RQX: no connection for RMII