9. Configuration, Design Security, and Remote System Upgrades in Stratix V Devices January 2011 SV51010-1.2 SV51010-1.2 This chapter contains information about the Stratix(R) V supported configuration schemes, instructions about how to execute the required configuration schemes, and all the necessary option pin settings. This chapter also reviews the different ways you can configure your device and explains the design security and remote system upgrade features for the Stratix V devices. This chapter includes the following sections: "Configuration Features" on page 9-2 "Power-On Reset Circuit and Configuration Pins Power Supply" on page 9-2 "Configuration Sequence" on page 9-4 "Configuration Schemes" on page 9-7 "Fast Passive Parallel Configuration" on page 9-9 "Active Serial Configuration (Serial Configuration Devices)" on page 9-16 "Passive Serial Configuration" on page 9-28 "JTAG Configuration" on page 9-34 "Device Configuration Pins" on page 9-38 "Configuration Data Decompression" on page 9-42 "Remote System Upgrades" on page 9-44 "Design Security" on page 9-53 Stratix V devices use SRAM cells to store configuration data. Because SRAM memory is volatile, you must download the configuration data to the Stratix V device each time the device powers up. You can configure Stratix V devices using one of four configuration schemes: Fast passive parallel (FPP) (x8, x16, and x32) Active serial (AS) (x1 and x4) Passive serial (PS) JTAG All configuration schemes use either an external controller (for example, a MAX(R) II device or microprocessor), a configuration device, or a download cable. For more information about the configuration features, refer to "Configuration Features" on page 9-2. (c) 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Subscribe 9-2 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Configuration Features Configuration Features Stratix V devices offer decompression, design security, and remote system upgrade features. Stratix V devices can receive a compressed configuration bitstream and decompress this data in real-time, reducing storage requirements and configuration time. Design security using configuration bitstream encryption is available in Stratix V devices, which protects your designs. You can make real-time system upgrades of your Stratix V designs from remote locations with the remote system upgrade feature. Table 9-1 lists which configuration features you can use in each configuration scheme. Table 9-1. Configuration Features for Stratix V Devices Decompression Design Security Remote System Upgrade v (1) v (1) -- AS (x1, x4) v v v PS v v -- JTAG -- -- -- Configuration Scheme FPP (x8, x16, x32) Note to Table 9-1: (1) In these configuration schemes, the host system must accommodate a different DCLK-to-DATA[] ratio. For more information, refer to "Fast Passive Parallel Configuration" on page 9-9. Power-On Reset Circuit and Configuration Pins Power Supply The following sections describe the power-on reset (POR) circuit and the power supply for the configuration pins. Secure-Mode Power-Up Stratix V devices are powered-up in secure mode. Only mandatory JTAG 1149.1 instructions are allowed after POR. f For more information, refer to the "Factory Instruction" on page 9-55. POR Delay Specification POR delay is defined as the delay between the time when all the power supplies monitored by the POR circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device is ready to begin configuration. f For more information about the POR delay, refer to the Hot Socketing and Power-On Reset in Stratix V Devices chapter. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Power-On Reset Circuit and Configuration Pins Power Supply 9-3 Table 9-2 lists the fast and standard POR delay specification. Table 9-2. Fast and Standard POR Delay Specification (Note 1) POR Delay Fast Standard Minimum Maximum 4 ms 12 ms 100 ms 300 ms Note to Table 9-2: (1) You can select the POR delay based on the MSEL settings as described in Table 9-4 on page 9-7. Power-On Reset Circuit The POR circuit keeps the entire system in reset mode until the power supply voltage levels have stabilized on power-up. After power-up, the device does not release nSTATUS until all the power supplies monitored by the POR circuitry are above the device's POR trip point. On power down, brown-out occurs if any of the power supplies monitored by the POR circuitry drops below the threshold level of the hot-socket circuitry. f For more information about which power supplies are monitored by the POR circuitry, refer to the Hot Socketing and Power-On Reset in Stratix V Devices chapter. VCCPGM Pin Stratix V devices have a power supply, VCCPGM, for all dedicated configuration pins and dual-purpose pins. The supported configuration voltages are 1.8, 2.5, and 3.0 V. Use the V CCPGM pin to power all dedicated configuration inputs, dedicated configuration outputs, dedicated configuration bidirectional pins, and the dual-purpose pins that you use for configuration. The configuration input buffers do not have to share power lines with the regular I/O buffer in Stratix V devices. The operating voltage for the configuration input pin is independent of the I/O banks power supply, V CCIO, during configuration. Therefore, Stratix V devices do not require configuration voltage constraints on VCCIO. f For more information about the configuration pins connections, refer to the Stratix V Device Family Pin Connection Guidelines. VCCPD Pin Stratix V devices have a dedicated programming power supply, VCCPD, which must be connected to 3.0 V or 2.5 V to power the I/O pre-drivers and JTAG I/O pins (TCK, TMS, TDI, TDO, and TRST). 1 VCCPD must be greater than or equal to V CCIO. If VCCIO is set to 3.0 V, VCCPD must be powered up to 3.0 V. If the VCCIO of the bank is set to 2.5 V or lower, V CCPD must be powered up to 2.5 V. This applies for all the banks containing the VCCPD and VCCIO pins. For more information about the configuration pins power supply, refer to "Device Configuration Pins" on page 9-38. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-4 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Configuration Sequence Configuration Sequence The following sections describe the general configuration process for the FPP, AS, and PS schemes. Power Up To begin the configuration process, you must fully power-up all the power supplies monitored by the POR circuitry to the appropriate voltage levels. The power supplies must ramp-up monotonically within the specified ramp-up time to ensure successful configuration. 1 All power supplies including the VCCPGM and VCCPD must ramp-up from 0 V to the desired voltage level within the ramp-up time specification. If these supplies are not ramped up within this specified time, your Stratix V device will not configure successfully. If your system cannot ramp-up the power supplies within the specified ramp-up time specification, you must hold nCONFIG low until all the power supplies are stable. f For more information about the ramp-up time specification, refer to the Hot Socketing and Power-On Reset in Stratix V Devices chapter. Reset After power-up, the Stratix V device goes through a POR. The POR delay depends on the MSEL settings. During POR, the device resets, holds nSTATUS low, clears the configuration RAM bits, and tri-states all user I/O pins. After the device successfully exits POR, all user I/O pins remain tri-stated until the device is configured. While nCONFIG is low, the device is in reset. When the device comes out of reset, nCONFIG must be at a logic-high level in order for the device to release the open-drain nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the device is ready to receive configuration data. Before and during configuration, all user I/O pins are tri-stated. If nIO_pullup is driven low during power up and configuration, the user I/O pins and dual-purpose I/O pins have weak pull-up resistors, which are on after the device exits POR, before and during configuration. If nIO_pullup is driven high, the weak pull-up resistors are disabled. For more information about the POR delay specification, refer to "POR Delay Specification" on page 9-2. Configuration Both nCONFIG and nSTATUS must be deasserted at a logic-high level in order for the configuration stage to begin. For the FPP and PS configuration schemes, the device receives configuration data on its DATA pins and the clock source on the DCLK pin. Configuration data is latched into the Stratix V device on the rising edge of DCLK. For the AS configuration scheme, the device receives configuration data on its AS_DATA[] pins and drives the clock source on the DCLK pin. Configuration data is latched into the Stratix V device on the falling edge of DCLK. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Configuration Sequence 9-5 After the Stratix V device has received all the configuration data successfully, it releases the CONF_DONE pin, which is pulled high by a pull-up resistor. A low-to-high transition on CONF_DONE indicates configuration has completed and initialization of the device can begin. For the FPP and PS schemes, DCLK must not be left floating at the end of configuration. You must drive them either high or low, whichever is convenient on your board. 1 For the FPP and PS schemes, there is no maximum DCLK period, which means you can stop the configuration by holding the DCLK low for an indefinite amount of time. To resume configuration, the external host must provide data on the DATA[] pins prior to sending the first DCLK rising edge. 1 To enhance security, Stratix V devices are powered-up in secure mode. After the device exits POR, only mandatory JTAG instructions are allowed through the JTAG interface. For more information, refer to "Factory Instruction" on page 9-55. Configuration Error If an error occurs during configuration, Stratix V devices assert the nSTATUS signal low to indicate the data frame error and the CONF_DONE signal remains low. For AS configuration scheme, if the Auto-restart configuration after error option (available in the Quartus(R) II software from the General panel of the Device and Pin Options dialog box) is turned on, the Stratix V device releases the nSTATUS pin high after the specified time and retries the configuration. If this option is turned off or if you are using a PS or FPP scheme with an external controller, the system must monitor the nSTATUS for errors and sends a low-to-high signal on nCONFIG to restart the configuration. Initialization In Stratix V devices, initialization begins after the CONF_DONE goes high. For the FPP and PS configuration schemes, two DCLK falling edges are required after the last configuration byte is sent to the Stratix V device to begin the initialization of the device for both uncompressed and compressed configuration data. The initialization clock source is from the internal oscillator, CLKUSR, or DCLK pin. By default, the internal oscillator is the clock source for initialization. If you use the internal oscillator, the Stratix V device provides itself with enough clock cycles for proper initialization. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-6 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Configuration Sequence Table 9-3 lists the initialization clock source option, the applicable configuration schemes, and the maximum frequency. Table 9-3. Initialization Clock Source Option and the Maximum Frequency Initialization Clock Source Configuration Schemes Maximum Frequency AS, PS, FPP 12.5 MHz AS, PS, FPP (2) 125 MHz Internal Oscillator CLKUSR Minimum Number of Clock Cycles (1) 17,408 (3) Notes to Table 9-3: (1) The minimum number of clock cycles required for device initialization. (2) To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II software from the General panel of the Device and Pin Options dialog box. (3) The number is still preliminary. 1 If you use the optional CLKUSR pin as the initialization clock source and nCONFIG is pulled low to restart configuration during device initialization, ensure that CLKUSR or DCLK continues toggling until nSTATUS goes low and goes high again. CLKUSR provides you with the flexibility to synchronize initialization of multiple devices or to delay initialization. Supplying a clock on the CLKUSR pin during initialization does not affect configuration. After CONF_DONE goes high, CLKUSR or DCLK is enabled after the time specified by tCD2CU. When this time period elapses, Stratix V devices require a minimum number of clock cycles to initialize properly and enter user mode as specified by the tCD2UMC parameter. User Mode The Stratix V device enters user mode when the initialization is complete. You can monitor the end of the initialization stage by enabling the optional INIT_DONE pin. If enabled, the low-to-high transition of INIT_DONE indicates the device has completed initialization and entered user mode. In this mode, your design is executed. The user I/O pins no longer have weak pull-up resistors and function as assigned in your design. 1 At any time during the configuration stage or user mode operation, you can initiate a reconfiguration by setting a low pulse on the nCONFIG pin. The pulse must meet the minimum tCFG low-pulse width. When nCONFIG is pulled low, the nSTATUS and CONF_DONE pins are pulled low and all I/O pins are tri-stated. Configuration begins when the nCONFIG and nSTATUS pins return to a logic-high level. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Configuration Schemes 9-7 Configuration Schemes The following sections describe configuration schemes for Stratix V devices. MSEL Pin Settings Select the configuration scheme by driving the Stratix V device MSEL pins either high or low, as listed in Table 9-4. The MSEL input buffers are powered by the V CCPGM power supply. Altera recommends hardwiring the MSEL pins to V CCPGM or GND. During POR and during reconfiguration, the MSEL pins must be at the LVTTL VIL and VIH levels to be considered logic low and logic high, respectively. 1 To avoid problems with detecting an incorrect configuration scheme, hardwire the MSEL pins to VCCPGM or GND without pull-up or pull-down resistors. Do not drive the MSEL pins with a microprocessor or another device. Table 9-4. Configuration Schemes for Stratix V Devices (Part 1 of 2) Configuration Scheme FPP x8 FPP x16 FPP x32 Decompression Feature Design Security Feature Configuration Voltage Standard (V) (2) Disabled Disabled 1.8/2.5/3.0 Disabled Enabled 1.8/2.5/3.0 Enabled Optional (1) 1.8/2.5/3.0 Disabled Disabled 1.8/2.5/3.0 Disabled Enabled 1.8/2.5/3.0 Enabled Optional (1) 1.8/2.5/3.0 Disabled Disabled 1.8/2.5/3.0 Disabled Enabled 1.8/2.5/3.0 Enabled Optional (1) 1.8/2.5/3.0 PS Optional (1) Optional (1) 1.8/2.5/3.0 AS (x1, x4) (3) Optional (1) Optional (1) 3.0 January 2011 Altera Corporation POR Delay (5) MSEL[4..0] Fast 10100 Standard 11000 Fast 10101 Standard 11001 Fast 10110 Standard 11010 Fast 00000 Standard 00100 Fast 00001 Standard 00101 Fast 00010 Standard 00110 Fast 01000 Standard 01100 Fast 01001 Standard 01101 Fast 01010 Standard 01110 Fast 10000 Standard 10001 Fast 10010 Standard 10011 Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-8 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Configuration Schemes Table 9-4. Configuration Schemes for Stratix V Devices (Part 2 of 2) Configuration Scheme JTAG-based configuration (4) Decompression Feature Design Security Feature Configuration Voltage Standard (V) (2) POR Delay (5) MSEL[4..0] Disabled Disabled -- -- (6) Notes to Table 9-4: (1) You can select to enable or disable this feature. (2) The configuration voltage standard applied to the VCCPGM power supply that powers all the configuration pins during configuration. (3) The AS configuration scheme supports the remote system upgrade feature. For more information about the remote system upgrade feature, refer to "Remote System Upgrades" on page 9-44. (4) JTAG-based configuration takes precedence over other configuration schemes. This means the MSEL pin settings are ignored. JTAG-based configuration does not support the design security or decompression features. (5) For POR delay specification, refer to "POR Delay Specification" on page 9-2. (6) Do not leave the MSEL pins floating. Connect them to VCCPGM or GND. This pin supports the non-JTAG configuration scheme used in production. If you only use the JTAG configuration, Altera recommends connecting the MSEL pins to GND. Raw Binary File Size For the POR delay specification, refer to "POR Delay Specification" on page 9-2. Table 9-5 lists the uncompressed raw binary file (.rbf) sizes for Stratix V devices. Table 9-5. Uncompressed .rbf Sizes for Stratix V Devices (Note 1) Device Configuration .rbf Size (bits) EP5SGXA3 134896752 EP5SGXA4 134896752 EP5SGXA5 266599584 EP5SGXA7 266599584 EP5SGXB5 218548480 EP5SGXB6 218548480 EP5SGSB7 251373664 EP5SGSB8 251373664 Note to Table 9-5: (1) These values are preliminary. Use the data in Table 9-5 to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal (.hex) or tabular text file (.ttf) format, have different file sizes. For the different types of configuration file and file sizes, refer to the Quartus II software. However, for a specific version of the Quartus II software, any design targeted for the same device has the same uncompressed configuration file size. If you are using compression, the file size can vary after each compilation because the compression ratio depends on your design. f For more information about setting device configuration options or creating configuration files, refer to the Device Configuration Options and Configuration File Formats chapters in volume 2 of the Configuration Handbook. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Fast Passive Parallel Configuration 9-9 Fast Passive Parallel Configuration The FPP configuration using an external host provides the fastest method to configure Stratix V devices. FPP is supported in multiple data widths--8-bits, 16-bits, and 32-bits. You can perform a FPP configuration of Stratix V devices using an external host such as a MAX II device or microprocessor. The external host controls the transfer of configuration data from a storage device, such as flash memory, to the target Stratix V device. You can store configuration data in .rbf, .hex, or .ttf formats. Therefore, the design that controls the configuration stages, such as fetching the data from flash memory and sending it to the device, must be stored in the MAX II device or microprocessor. The Parallel Flash Loader (PFL) feature in MAX II devices provides an efficient method to program CFI flash memory devices through the JTAG interface. PFL also acts as a controller to read configuration data from the flash memory device and configures the Stratix V device. PFL supports both the PS and FPP configuration schemes. f For more information about the PFL, refer to Parallel Flash Loader Megafunction User Guide. 1 Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device for both uncompressed and compressed configuration data in a FPP configuration. DCLK-to-DATA[] Ratio for FPP configuration FPP configuration requires a different DCLK-to-DATA[]ratio when you enable the design security, decompression, or both features. Table 9-6 lists the DCLK-to-DATA[]ratio for each combination. Table 9-6. DCLK-to-DATA[] Ratio (Note 1) (Part 1 of 2) Configuration Scheme FPP x8 FPP x16 January 2011 Altera Corporation Decompression Design Security DCLK-to-DATA[] Ratio Disabled Disabled 1 Disabled Enabled 1 Enabled Disabled 2 Enabled Enabled 2 Disabled Disabled 1 Disabled Enabled 2 Enabled Disabled 4 Enabled Enabled 4 Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-10 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Fast Passive Parallel Configuration Table 9-6. DCLK-to-DATA[] Ratio (Note 1) (Part 2 of 2) Configuration Scheme Decompression FPP x32 DCLK-to-DATA[] Ratio Design Security Disabled Disabled 1 Disabled Enabled 4 Enabled Disabled 8 Enabled Enabled 8 Note to Table 9-6: (1) Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the data rate in bytes per second (Bps), or words per second (Wps). For example, in FPP x16 when the DCLK-to-DATA[] ratio is 2, the DCLK frequency must be 2 times the data rate in Wps. Stratix V devices use the additional clock cycles to decrypt and decompress the configuration data. 1 If the DCLK-to-DATA[] ratio is greater than 1, at the end of configuration, you can only stop the DCLK (DCLK-to-DATA[] ratio - 1) clock cycles after the last data is latched into the Stratix V device. Figure 9-1 shows the configuration interface connections between the Stratix V device and a MAX II device for single device configuration. Figure 9-1. Single Device FPP Configuration Using an External Host Memory ADDR DATA[7..0] VCCPGM (1) VCCPGM (1) 10 k 10 k Stratix V Device MSEL[4..0] (3) CONF_DONE nSTATUS External Host (MAX II Device or Microprocessor) nCEO nCE GND N.C. (2) DATA[31..0] (4) nCONFIG DCLK Notes to Figure 9-1: (1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. VCCPGM must be high enough to meet the VIH specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with VCCPGM. (2) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device's nCE pin. (3) The MSEL pin settings vary for different data width, configuration voltage standards, and POR delay. To connect MSEL, refer to Table 9-4 on page 9-7. (4) If you use FPP x8, use DATA[7..0]. If you use FPP x16, use DATA[15..0]. FPP Multi-Device Configuration For FPP multi-device configuration, you can configure all devices with different sets of configuration data (multiple SRAM object files [.sofs]) or with the same configuration data (single .sof). In both cases, the nCONFIG, nSTATUS, DCLK, DATA[], and CONF_DONE pins are connected to every device in the chain. Ensure that the DCLK and data line are buffered for every fourth device. This ensures the signal integrity and prevents clock skew problems. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Fast Passive Parallel Configuration 9-11 Because all device's CONF_DONE and nSTATUS pins are tied together, all devices initialize and enter user mode at the same time. If any device detects an error, configuration stops for the entire chain and you must reconfigure all devices. For example, if the first device flags an error on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This behavior is similar to a single device detecting an error. 1 For FPP multi-device configuration, all devices in the chain must have the same data width. If you are using FPP x32, all devices in the chain must use FPP x32 configuration scheme. If you are using FPP x8, you can use the Stratix V device with other FPGA devices that support FPP x8. Figure 9-2 shows how to configure multiple devices using a MAX II device when both devices receive a different set of configuration data (multiple .sofs). Figure 9-2. Multi-Device FPP Configuration Using an External Host When Both Devices Receive a Different Set of Configuration Data Memory VCCPGM (1) VCCPGM (1) ADDR DATA[7..0] 10 k 10 k Stratix V Device 1 MSEL[4..0] CONF_DONE MSEL[4..0] (2) CONF_DONE nSTATUS External Host (MAX II Device or Microprocessor) Stratix V Device 2 (2) nSTATUS nCEO nCE nCE nCEO N.C. GND DATA[31..0] (4) DATA[31..0] (4) nCONFIG nCONFIG DCLK DCLK Notes to Figure 9-2: (1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. VCCPGM must be high enough to meet the VIH specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with VCCPGM. (2) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device's nCE pin. (3) The MSEL pin settings vary for different data width and POR delay. To connect MSEL, refer to Table 9-4 on page 9-7. (4) If you use FPP x8, use DATA[7..0]. If you use FPP x16, use DATA[15..0]. All devices in the chain must have the same data width. In Figure 9-2, after the first device completes configuration in a multi-device configuration chain, its nCEO pin drives low to activate the second device's nCE pin, which prompts the second device to begin configuration. The second device in the chain begins configuration in one clock cycle; therefore, the transfer of data to the second device is transparent to the MAX II device or microprocessor. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-12 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Fast Passive Parallel Configuration Figure 9-3 shows the FPP configuration setup for multiple devices when both Stratix V devices receive the same configuration data (single .sof). Figure 9-3. Multiple Device FPP Configuration Using an External Host When Both Devices Receive the Same Data Memory VCCPGM (1) VCCPGM (1) ADDR DATA[7..0] 10 k Stratix V Device 1 10 k MSEL[4..0] Stratix V Device 2 (3) MSEL[4..0] CONF_DONE External Host (MAX II Device or Microprocessor) nSTATUS nCE GND (3) CONF_DONE nCEO nSTATUS nCE N.C. (2) nCEO N.C. (2) GND DATA[31..0] (4) DATA[31..0] (4) nCONFIG nCONFIG DCLK DCLK Notes to Figure 9-3: (1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. VCCPGM must be high enough to meet the VIH specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with VCCPGM. (2) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device's nCE pin. (3) The MSEL pin settings vary for different data width and POR delay. To connect MSEL, refer to Table 9-4 on page 9-7. (4) If you use FPP x8, use DATA[7..0]. If you use FPP x16, use DATA[15..0]. All devices in the chain must have the same data width. In Figure 9-3, because both nCE pins are tied to GND, both devices in the chain begin and complete the configuration and enter user mode at the same time. 1 To configure FPP multi-device with a single .sof, all Stratix V devices in the chain must be in the same package and density. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Fast Passive Parallel Configuration 9-13 FPP Configuration Timing Figure 9-4 shows the timing waveform for FPP configuration when using a MAX II device as an external host. This waveform shows timing when the DCLK-to-DATA[] ratio is 1. 1 When you enable the decompression or design security feature, the DCLK-to-DATA[] ratio varies for FPP x8, FPP x16, and FPP x32. For the respective DCLK-to-DATA[] ratio, refer to Table 9-6 on page 9-9. Figure 9-4. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1 (Note 1), (2) tCF2ST1 tCFG tCF2CK nCONFIG nSTATUS (3) tSTATUS tCF2ST0 t (7) CLK CONF_DONE (4) tCF2CD tST2CK tCH tCL (5) DCLK tDH DATA[31..0](6) Word 0 Word 1 Word 2 Word 3 Word n-2 Word n-1 User Mode Word n tDSU User I/O High-Z User Mode INIT_DONE (8) tCD2UM Notes to Figure 9-4: (1) Use this timing waveform when the DCLK-to-DATA[] ratio is 1. (2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. (3) After power-up, the Stratix V device holds nSTATUS low for the time of the POR delay. (4) After power-up, before and during configuration, CONF_DONE is low. (5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient. (6) For FPP x16, use DATA[15..0]. For FPP x8, use DATA[7..0]. DATA[31..0] are available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings. (7) To ensure a successful configuration, send the entire configuration data to the Stratix V device. CONF_DONE is released high when the Stratix V device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization and enter user mode. (8) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-14 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Fast Passive Parallel Configuration Table 9-7 lists the timing parameters for Stratix V devices for FPP configuration when the DCLK-to-DATA[] ratio is 1. Table 9-7. FPP Timing Parameters for Stratix V Devices (Note 1), (2) Symbol Parameter Minimum Maximum Units tCF2CD nCONFIG low to CONF_DONE low -- 600 ns tCF2ST0 nCONFIG low to nSTATUS low -- 600 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width 268 1,506 (3) s tCF2ST1 nCONFIG high to nSTATUS high -- 1,506 (4) s tCF2CK nCONFIG high to first rising edge on DCLK 1,506 -- s tST2CK nSTATUS high to first rising edge of DCLK 2 -- s tDSU DATA[] setup time before rising edge on DCLK 5.5 -- ns tDH DATA[] hold time after rising edge on DCLK 0 -- ns tCH DCLK high time 0.45 1/fMAX -- s tCL DCLK low time 0.45 1/fMAX -- s tCLK DCLK period 1/fMAX -- s DCLK frequency (FPP 8/16) -- 125 MHz DCLK frequency (FPP 32) -- 100 MHz tR Input rise time -- 40 ns tF Input fall time -- 40 ns tCD2UM CONF_DONE high to user mode (5) 175 437 s tCD2CU CONF_DONE high to CLKUSR enabled -- -- -- -- fMAX tCD2UMC CONF_DONE high to user mode with CLKUSR option on 4 x maximum DCLK period tCD2CU + (17,408 CLKUSR period) (6) Notes to Table 9-7: (1) This information is preliminary. (2) Use these timing parameters when the decompression and design security features are disabled. (3) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (4) This value is applicable if you do not delay configuration by externally holding the nSTATUS low. (5) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. (6) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to "Initialization" on page 9-5. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Fast Passive Parallel Configuration 9-15 Figure 9-5 shows the timing waveform for FPP configuration when using a MAX II device or microprocessor as an external host. This waveform shows timing when the DCLK-to-DATA[]ratio is more than 1. Figure 9-5. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1 (Note 1), (2) tCF2ST1 tCFG tCF2CK nCONFIG nSTATUS (3) CONF_DONE (4) tSTATUS tCF2ST0 tCF2CD tCL tST2CK DCLK (6) (8) tCH 1 2 r 1 2 r (7) 1 r 1 (5) 2 tCLK Word 0 DATA[31..0] (8) tDSU User I/O Word 1 tDH Word (n-1) Word n Word 3 User Mode tDH User Mode High-Z INIT_DONE (9) tCD2UM Notes to Figure 9-5: (1) Use this timing waveform and parameters when the DCLK-to-DATA[]ratio is >1. To find out the DCLK-to-DATA[] ratio for your system, refer Table 9-6 on page 9-9. (2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. (3) After power-up, the Stratix V device holds nSTATUS low for the time as specified by the POR delay. (4) After power-up, before and during configuration, CONF_DONE is low. (5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient. (6) "r" denotes the DCLK-to-DATA[] ratio. For the DCLK-to-DATA[] ratio based on the decompression and the design security feature enable settings, refer to Table 9-6 on page 9-9. (7) If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[31..0] pins prior to sending the first DCLK rising edge. (8) To ensure a successful configuration, send the entire configuration data to the Stratix V device. CONF_DONE is released high after the Stratix V device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization and enter user mode. (9) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low. Table 9-8 lists the timing parameters for Stratix V devices for FPP configuration when the DCLK-to-DATA[]ratio is more than 1. Table 9-8. FPP Timing Parameters for Stratix V Devices When the DCLK-to-DATA[] Ratio is >1 (Note 1), (2) (Part 1 of 2) Symbol Parameter Minimum Maximum Units tCF2CD nCONFIG low to CONF_DONE low -- 600 ns tCF2ST0 nCONFIG low to nSTATUS low -- 600 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width 268 1,506 (3) s tCF2ST1 nCONFIG high to nSTATUS high -- 1,506 (3) s tCF2CK nCONFIG high to first rising edge on DCLK 1,506 -- s tST2CK nSTATUS high to first rising edge of DCLK 2 -- s tDSU DATA[] setup time before rising edge on DCLK 5.5 -- ns January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-16 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Active Serial Configuration (Serial Configuration Devices) Table 9-8. FPP Timing Parameters for Stratix V Devices When the DCLK-to-DATA[] Ratio is >1 (Note 1), (2) (Part 2 of 2) Symbol Parameter Minimum Maximum Units tDH DATA[] hold time after rising edge on DCLK 3 1/fDCLK (6) -- s tCH DCLK high time 0.45 1/fMAX -- s tCL DCLK low time 0.45 1/fMAX -- s tCLK DCLK period 1/fMAX -- s DCLK frequency (FPP 8/16) -- 125 MHz DCLK frequency (FPP 32) -- 100 MHz tR Input rise time -- 40 ns tF Input fall time -- 40 ns tCD2UM CONF_DONE high to user mode (4) 175 437 s tCD2CU CONF_DONE high to CLKUSR enabled 4 x maximum DCLK period -- -- tCD2CU + (17,408 CLKUSR period) (5) -- -- fMAX tCD2UMC CONF_DONE high to user mode with CLKUSR option on Notes to Table 9-8: (1) This information is preliminary. (2) Use these timing parameters when you use the decompression and design security features. (3) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (4) The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device. (5) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to "Initialization" on page 9-5. (6) fDCLK is the DCLK frequency the system is operating. Active Serial Configuration (Serial Configuration Devices) The AS configuration scheme is supported in 1-bit data wide (AS x1 mode) or 4-bit data wide (AS x4 mode). In the AS x1 mode, the Stratix V devices are configured using a serial configuration device (EPCS). In the AS x4 mode, a quad-serial configuration device (EPCQ) configures the Stratix V devices. The AS x4 mode provides four times faster configuration time than the AS x1 mode. EPCS and EPCQ are low-cost devices with non-volatile memory that feature a simple four-pin interface or six-pin interface, respectively, and a small form factor. These features make the AS configuration scheme an ideal low-cost configuration solution. 1 If you wish to gain control of the EPCS pins, hold the nCONFIG pin low and pull the nCE pin high. This causes the device to reset and tri-state the AS configuration pins. f For more information about EPCS and EPCQ devices, refer to the volume 2 of the Configuration Handbook. AS mode supports DCLK frequency up to 100 MHz. You can choose the CLKUSR or internal oscillator as the configuration clock source that drives DCLK. If you use the internal oscillator as the configuration clock source, you can choose a 12.5, 25, 50, or 100 MHz clock from the Configuration panel in the Device and Pins Option settings. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Active Serial Configuration (Serial Configuration Devices) 9-17 Table 9-9 lists the DCLK frequency specification in the AS configuration scheme. Table 9-9. DCLK Frequency Specification in the AS Configuration Scheme (Note 1), (2) Minimum Typical Maximum Unit 5.3 7.9 12.5 MHz 10.6 15.7 25.0 MHz 21.3 31.4 50.0 MHz 42.6 62.9 100.0 MHz Notes to Table 9-9: (1) This information is preliminary. (2) This applies to the DCLK frequency specification when using the internal oscillator as the configuration clock source. 1 You can choose the internal oscillator or CLKUSR as the DCLK clock source by selecting the option under Device and Pins Option settings, Configuration panel in the Quartus II software. This sets specific option in the programming file. By default, in AS scheme, Stratix V devices power-up and begin configuration with 12.5 MHz internal oscillator as the DCLK clock source. After reading the option bits from the programming file, Stratix V devices continue using the internal oscillator at 12.5 MHz frequency, switch to a higher internal oscillator clock frequency, or switch to the CLKUSR pin. 1 If you choose CLKUSR as configuration clock source, the maximum frequency allowed is 100 MHz. During device configuration, Stratix V devices read the configuration data using the serial interface, decompress the data if necessary, and configure their SRAM cells. In the AS scheme, the Stratix V device controls the configuration interface. In the PS scheme, the external host (a MAX II device or microprocessor) controls the interface. 1 January 2011 You can select between the AS x1 and AS x4 settings by selecting the option under Device and Pins Option settings, Configuration panel in the Quartus II software. This sets a specific option bit in the programming file. By default, in the AS scheme, Stratix V devices power-up and begin configuration as an AS x1 mode. Upon reading the option bits from the programming file, Stratix V devices either stay as an AS x1 mode or switch to an AS x4 mode for the rest of the configuration. Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-18 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Active Serial Configuration (Serial Configuration Devices) Figure 9-6 shows the single-device configuration setup for an AS x1 mode. Figure 9-6. Single Device AS x1 Mode Configuration VCCPGM (1) VCCPGM (1) VCCPGM (1) 10 k 10 k 10 k Serial Configuration Device Stratix V Device nSTATUS CONF_DONE nCONFIG nCE GND DATA AS_DATA1 DCLK DCLK nCS nCSO ASDI ASDO nCEO N.C. MSEL[4..0] (2) CLKUSR (3) Notes to Figure 9-6: (1) Connect the pull-up resistors to VCCPGM at 3.0-V supply. (2) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL, refer to Table 9-4 on page 9-7. (3) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The maximum frequency specification is 100 MHz. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Active Serial Configuration (Serial Configuration Devices) 9-19 Figure 9-7 shows the single-device configuration setup for an AS x4 mode. Figure 9-7. Single Device AS x4 Mode Configuration VCCPGM (1) VCCPGM (1) VCCPGM (1) 10 k 10 k 10 k Quad-Serial Configuration Device Stratix V Device nSTATUS CONF_DONE nCONFIG nCE GND DATA0 AS_DATA0/ ASDO DATA1 AS_DATA1 DATA2 AS_DATA2 DATA3 AS_DATA3 DCLK DCLK nCS nCSO nCEO N.C. MSEL[4..0] (2) CLKUSR (3) Notes to Figure 9-7: (1) Connect the pull-up resistors to VCCPGM at 3.0-V supply. (2) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL, refer to Table 9-4 on page 9-7. (3) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The maximum frequency specification is 100 MHz. The serial clock (DCLK) generated by the Stratix V device controls the entire configuration cycle and provides timing for the serial interface. Stratix V devices use an internal oscillator or external clock (CLKUSR) as the configuration clock source (DCLK). In the AS configuration scheme, Stratix V devices drive out control signals on the falling edge of DCLK and latch in the data on the following falling edge of DCLK. During configuration, Stratix V devices enable the EPCS or EPCQ by driving the nCSO output pin low, which connects to the chip select (nCS) pin of the EPCS or EPCQ. Stratix V devices use the serial clock (DCLK) and serial data output (ASDO) pins to send operation commands and read address signals to the EPCS or EPCQ. The EPCS or EPCQ provides data on its serial data output (DATA[]) pin, which connects to the AS_DATA[] input of the Stratix V devices. AS Multi-Device Configuration For the AS multi-device configuration scheme, you can configure all devices with different sets of configuration data (different .sof) or with the same configuration data (same .sof). In both cases, the nCONFIG, nSTATUS, DCLK, and data line (AS_DATA1 on the master device and DATA0 on the slave device) and CONF_DONE pins are connected to every device in the chain. Ensure that the DCLK and data line are buffered for every fourth device. 1 January 2011 The AS configuration scheme supports multi-device in AS x1 mode. The AS x4 mode does not support multi-device configuration setup. Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-20 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Active Serial Configuration (Serial Configuration Devices) In the AS multi-device configuration, the nSTATUS, nCONFIG, and CONF_DONE pins are tied together. Therefore, all devices initialize and enter user mode at the same time. If any device detects an error, configuration stops for the entire chain and you must reconfigure all devices. For example, if the first device flags an error on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This behavior is similar to a single device detecting an error. 1 In this configuration scheme, the first Stratix V device in the chain is the configuration master and controls the configuration of the entire chain. You must connect its MSEL pins to select the AS configuration scheme. The remaining Stratix V devices are configuration slaves. You must connect their MSEL pins to select the PS configuration scheme. Any other Altera(R) device that supports a PS configuration can also be part of the chain as the configuration slave. Figure 9-8 shows the multi-device configuration setup for AS x1 mode when both devices in the chain receive different sets of configuration data (multiple .sofs). Figure 9-8. AS Multi-Device Configuration When Both Devices in the Chain Receive Different Sets of Configuration Data (Note 1), (2) VCCPGM (1) VCCPGM (1) VCCPGM (1) 10 k 10 k 10 k Serial Configuration Device Stratix V Device Master Stratix V Device Slave nSTATUS CONF_DONE nCONFIG nCE nCEO nSTATUS CONF_DONE nCONFIG nCE nCEO N.C. (3) GND DATA AS_DATA1 DCLK DCLK nCS nCSO ASDI ASDO MSEL[4..0] (5) CLKUSR (6) DATA0 MSEL [4..0] DCLK (4) Buffers (2) Notes to Figure 9-8: (1) Connect the pull-up resistors to VCCPGM at a 3.0-V supply. (2) Connect the repeater buffers between the Stratix V master and slave device for AS_DATA1/DATA0 and DCLK. (3) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device's nCE pin. (4) For the appropriate MSEL settings based on POR delay settings, set the slave device MSEL setting to the PS scheme. Refer to Table 9-4 on page 9-7. (5) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL, refer to Table 9-4 on page 9-7. (6) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The maximum frequency specification is 100 MHz. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Active Serial Configuration (Serial Configuration Devices) 9-21 In Figure 9-8, after the first device completes configuration in a multi-device configuration chain, its nCEO pin drives low to activate the second device's nCE pin, which prompts the second device to begin configuration. The second device in the chain begins configuration in one clock cycle; therefore, the transfer of data to the second device is transparent to the first device in the chain. Figure 9-9 shows the multi-device configuration setup for AS x1 mode when all devices in the chain receive the same set of configuration data (single .sof). Figure 9-9. AS Multi-Device Configuration When the Devices Receive the Same Data Using a Single .sof (Note 1) VCCPGM (1) VCCPGM (1) VCCPGM (1) 10 k 10 k 10 k Serial Configuration Device Stratix V Device Master nSTATUS CONF_DONE nCONFIG nCE nCEO Stratix V Device Slave nSTATUS CONF_DONE nCONFIG nCE N.C. (3) GND nCEO N.C. (3) GND DATA AS_DATA1 DCLK DCLK nCS nCSO ASDI ASDO MSEL [4..0] (4) CLKUSR (5) DATA0 DCLK MSEL [4..0] (4) Buffers (2) Notes to Figure 9-9: (1) Connect the pull-up resistors to VCCPGM at a 3.0-V supply. (2) Connect the repeater buffers between the Stratix V master and slave device for AS_DATA1/DATA0 and DCLK. (3) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device's nCE pin. (4) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect the MSEL, refer to Table 9-4 on page 9-7. (5) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The maximum frequency specification is 100 MHz. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-22 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Active Serial Configuration (Serial Configuration Devices) AS Connection Guidelines For single- and multi-device AS configurations, the board trace length and loading between the supported EPCS or EPCQ and the Stratix V devices must follow the recommendations listed in Table 9-10. Table 9-10. Maximum Trace Length and Loading for AS 1/4 Configurations Stratix V Device AS Pins Maximum Board Trace Length from the Stratix V Device to the Serial Configuration Device for 12.5/ 25/ 50 MHz Operation (Inches) Maximum Board Trace Length from the Stratix V Device to the Serial Configuration Device for 100 MHz Operation (Inches) Maximum Board Load (pF) DCLK 10 6 15 DATA[3..0] 10 6 30 nCSO 10 6 30 AS Configuration Timing Figure 9-10 shows the timing waveform for the AS x1 mode and AS x4 mode configuration timing. Figure 9-10. AS Configuration Timing tPOR (1) nCONFIG nSTATUS CONF_DONE nCSO DCLK tCO tDH AS_DATA0/ASDO Read Address tSU AS_DATA1 (2) bit N bit N - 1 bit 1 bit 0 tCD2UM (3) INIT_DONE (4) User I/O User Mode Notes to Figure 9-10: (1) The AS scheme supports standard and fast POR delay (tPOR). For tPOR delay information, refer to "POR Delay Specification" on page 9-2. (2) If you are using AS x4 mode, this signal represents the AS_DATA[3..0] and EPCQ sends in 4-bits of data for each DCLK cycle. (3) The initialization clock can be from internal oscillator or CLKUSR pin. (4) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Active Serial Configuration (Serial Configuration Devices) 9-23 Table 9-11 lists the timing parameters for AS 1 and AS 4 configurations in Stratix V devices. Table 9-11. AS Timing Parameters for AS 1 and AS 4 Configurations in Stratix V Devices (Note 1), (2), (3) Symbol Parameter Minimum Maximum Units tCO DCLK falling edge to AS_DATA0/ASDO output -- 4 s tSU Data setup time before rising edge on DCLK 1.5 -- ns tH Data hold time after rising edge on DCLK 0 -- ns tCD2UM CONF_DONE high to user mode (4) 175 437 s tCD2CU CONF_DONE high to CLKUSR enabled 4 x maximum DCLK period -- -- tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (17,408 CLKUSR period) -- -- Notes to Table 9-11: (1) This information is preliminary. (2) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device. (3) tCF2CD, tCF2ST0, tCFG , tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for PS mode listed in Table 9-12 on page 9-30. (4) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on this pin, refer to "Initialization" on page 9-5. Estimating the Active Serial Configuration Time The AS configuration time is dominated by the time it takes to transfer data from the EPCS to the Stratix V device. This serial interface is clocked by the Stratix V DCLK. You can estimate the minimum AS x1 mode configuration time by using the following equation: .rbf Size x (minimum DCLK period / 1 bit per DCLK cycle) = estimated minimum configuration time. You can estimate the minimum AS x4 mode configuration time by using the following equation: .rbf Size x (minimum DCLK period / 4 bits per DCLK cycle) = estimated minimum configuration time. Enabling compression reduces the amount of configuration data that is transmitted to the Stratix V device, which also reduces the configuration time. Your configuration time is reduced based on the compression ratio. The compression ratio varies based on the design. Programming EPCS and EPCQ EPCS and EPCQ are non-volatile, flash-memory-based devices. You can program these devices in-system using a USB-BlasterTM, EthernetBlaster, or ByteBlasterTM II download cable. Alternatively, you can program EPCS or EPCQ device using a microprocessor with the SRunner software driver. f For more information about SRunner software driver, refer to AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-24 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Active Serial Configuration (Serial Configuration Devices) In-system programming offers you an option to program the EPCS or EPCQ device either using an AS programming interface or a JTAG interface. Using the AS programming interface, the configuration data is programmed into the EPCS by the Quartus II software or any supported third-party software. Using the JTAG interface, an Altera IP called Serial Flash Loader (SFL) must be downloaded into the Stratix V device to form a bridge between the JTAG interface and the EPCS or EPCQ device. This allows the EPCS or the EPCQ device to be programmed directly using the JTAG interface. Figure 9-11 shows the connection setup when programming the EPCS device using the JTAG interface. Figure 9-11. Connection Setup for Programming the EPCS Device Using the JTAG Interface VCCPGM (1) VCCPGM (1) VCCPGM (1) 10 k 10 k 10 k VCCPD (1) VCCPD (1) (2) EPCS Device (2) Stratix V Device nSTATUS CONF_DONE nCONFIG nCE GND VCCPD (1) TMS TDI Pin 1 DATA AS_DATA1 DCLK DCLK nCS nCSO ASDO ASDI TCK TDO (3) MSEL[4..0] (5) CLKUSR Serial Flash Loader (4) 1 k GND Download Cable 10-Pin Male Header (JTAG Mode) (Top View) GND Notes to Figure 9-11: (1) Connect the pull-up resistors to VCCPGM and VCCPD at a 3.0-V supply. (2) Resistor value can vary from 1 k to 10 k. Perform signal integrity analysis to select the resistor value for your setup. (3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect the MSEL, refer to Table 9-4 on page 9-7. (4) Instantiate SFL in your design to form a bridge between the EPCS device and the Stratix V device. For more information about SFL, refer to AN 370: Using the Serial Flash Loader with the Quartus II Software. (5) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The maximum frequency specification is 100 MHz. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Active Serial Configuration (Serial Configuration Devices) 9-25 Figure 9-12 shows the connection setup when programming the EPCQ device using the JTAG interface. Figure 9-12. Connection Setup for Programming the EPCQ Device Using the JTAG Interface VCCPGM (1) VCCPGM (1) VCCPGM (1) 10 k 10 k 10 k VCCPD (1) VCCPD (1) (2) EPCQ Device (2) Stratix V Device GND nSTATUS TCK CONF_DONE TDO nCONFIG nCE TMS TDI VCCPD (1) Pin 1 DATA0 AS_DATA0/ASDO DATA1 AS_DATA1 DATA2 AS_DATA2 DATA3 AS_DATA3 DCLK DCLK nCS nCSO Serial Flash Loader (4) 1 k MSEL[4..0] (3) CLKUSR (5) GND Download Cable 10-Pin Male Header (JTAG Mode) (Top View) GND Notes to Figure 9-12: (1) Connect the pull-up resistors to VCCPGM and VCCPD at a 3.0-V supply. (2) Resistor value can vary from 1 k to 10 k. Perform signal integrity analysis to select the resistor value for your setup. (3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect the MSEL, refer to Table 9-4 on page 9-7. (4) Instantiate SFL in your design to form a bridge between the EPCS device and the Stratix V device. For more information about SFL, refer to AN 370: Using the Serial Flash Loader with the Quartus II Software. (5) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The maximum frequency specification is 100 MHz. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-26 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Active Serial Configuration (Serial Configuration Devices) Figure 9-13 shows the connection setup when programming the EPCS device using the AS interface. Figure 9-13. Connection Setup for Programming the EPCS Device Using the AS Interface VCCPGM (1) VCCPGM (1) 10 k 10 k VCCPGM (1) 10 k Stratic V Device CONF_DONE nSTATUS nCONFIG nCEO N.C. EPCS Device nCE 10 k DATA AS_DATA1 DCLK DCLK nCS nCSO ASDI ASDO Pin 1 MSEL[4..0] CLKUSR (3) (4) VCCPGM (2) USB-Blaster or ByteBlaser II (AS Mode) 10-Pin Male Header GND Notes to Figure 9-13: (1) Connect the pull-up resistors to VCCPGM and VCCPD at a 3.0-V supply. (2) Power up the USB-ByteBlaster, ByteBlaster II, or EthernetBlaster cable's VCC(TRGT) with VCCPGM. (3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect the MSEL, refer to Table 9-4 on page 9-7. (4) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The maximum frequency specification is 100 MHz. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Active Serial Configuration (Serial Configuration Devices) 9-27 Figure 9-14 shows the connection setup when programming the EPCQ device using the AS interface. Figure 9-14. Connection Setup for Programming the EPCQ Device Using the AS Interface (Note 1) VCCPGM (2) VCCPGM (2) VCCPGM (2) 10 k 10 k 10 k Stratix V Device CONF_DONE nCEO nSTATUS nCONFIG nCE EPCQ Device N.C. 10 k DATA0 AS_DATA0/ASDO DATA1 AS_DATA1 DATA2 AS_DATA2 DATA3 AS_DATA3 DCLK DCLK MSEL[4..0] nCS nCSO CLKUSR Pin 1 (4) (5) VCCPGM (3) USB-Blaster or ByteBlaser II (AS Mode) 10-Pin Male Header Notes to Figure 9-14: (1) Using the AS header, the programmer transmits the operation commands and the configuration bits to the EPCQ device serially on DATA0.This is equivalent to the programming operation for the EPCS device as shown in Figure 9-14. (2) Connect the pull-up resistors to VCCPGM and VCCPD at a 3.0-V supply. (3) Power up the USB-ByteBlaster, ByteBlaster II, or EthernetBlaster cable's VCC(TRGT) with VCCPGM. (4) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect the MSEL, refer to Table 9-4 on page 9-7. (5) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The maximum frequency specification is 100 MHz. During EPCS and EPCQ programming, the download cable disables the device access to the AS interface by driving the nCE pin high. The nCONFIG line is also pulled low to hold the Stratix V device in reset stage. After programming completes, the download cable releases nCE and nCONFIG, allowing the pull-down and pull-up resistors to drive the pin to GND and VCCPGM, respectively. 1 January 2011 During EPCQ programming using the download cable, DATA0 carries the programming data, operation command, and address information from the download cable into the EPCQ device. During EPCQ verification using the download cable, DATA1 carries the programming data back to the download cable. Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-28 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Passive Serial Configuration Passive Serial Configuration You can perform PS configuration of Stratix V devices using an external host such as a MAX II device, microprocessor, or a host PC. Therefore, the design that controls the configuration stages, such as fetching the data from flash memory and sending it to the device, must be stored in the external host. The Parallel Flash Loader (PFL) feature in MAX II devices provide an efficient method to program CFI flash memory devices through the JTAG interface. PFL also acts as a controller to read configuration data from the flash memory device and configures the Stratix V device. PFL supports both the PS and FPP configuration schemes. f For more information about the PFL, refer to the Parallel Flash Loader Megafunction User Guide. PS Configuration Using a MAX II Device or Microprocessor The external host (a MAX II device or microprocessor) reads configuration data from storage devices, such as flash memory, and transfers it to Stratix V devices. You can store the configuration data in .pof, .rbf, .hex, or .ttf format. If you are using configuration data in .rbf, .hex, or .ttf format, you must send the LSB of each data byte first. For example, if the .rbf file contains the byte sequence 02 1B EE 01 FA, the serial data transmitted to the device must be 0100-0000 1101-1000 0111-0111 1000-0000 0101-1111. Figure 9-15 shows the configuration interface connections between a Stratix V device and a MAX II device for single device configuration. Figure 9-15. Single Device PS Configuration Using an External Host Memory ADDR VCCPGM(1) VCCPGM(1) DATA0 10 k Stratix V Device 10 k CONF_DONE nSTATUS External Host (MAX II Device or Microprocessor) nCE nCEO GND N.C. (2) DATA0 nCONFIG DCLK MSEL[4..0] (3) Notes to Figure 9-15: (1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. VCCPGM must be high enough to meet the VIH specification of the I/O on the device and the external host. Altera recommends powering up all the configuration system I/Os with VCCPGM. (2) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device's nCE pin. (3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL, refer to Table 9-4 on page 9-7. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Passive Serial Configuration 9-29 Figure 9-16 shows the PS multi-device configuration using an external host when all devices in the chain receive different sets of configuration data (multiple .sofs). Figure 9-16. PS Multi-device Configuration when Both Devices Receive Different Sets of Configuration Data Memory ADDR VCCPGM(1) VCCPGM(1) DATA0 10 k Stratix V Device 1 10 k Stratix V Device 2 CONF_DONE CONF_DONE nSTATUS nSTATUS nCEO nCE External Host (MAX II Device or Microprocessor) nCE nCEO GND DATA0 N.C. (2) DATA0 nCONFIG nCONFIG MSEL[4..0] DCLK DCLK (3) MSEL[4..0] (3) Notes to Figure 9-16: (1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. VCCPGM must be high enough to meet the VIH specification of the I/O on the device and the external host. Altera recommends powering up all the configuration system I/Os with VCCPGM. (2) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device's nCE pin. (3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL, refer to Table 9-4 on page 9-7. In Figure 9-16, after the first device completes configuration in a multi-device configuration chain, its nCEO pin drives low to activate the second device's nCE pin, which prompts the second device to begin configuration. The second device in the chain begins configuration in one clock cycle; therefore, the transfer of data to the second device is transparent to the external host. Figure 9-17 shows the PS multi-device configuration when all devices receive the same set of configuration data (single .sof). Figure 9-17. PS Multi-device Configuration When Both Devices Receive the Same Set of Configuration Data Memory ADDR VCCPGM(1) VCCPGM(1) DATA0 10 k Stratix V Device 1 10 k Stratix V Device 2 CONF_DONE CONF_DONE nSTATUS External Host (MAX II Device or Microprocessor) nSTATUS nCEO nCE N.C. (2) GND nCE nCEO GND DATA0 DATA0 nCONFIG DCLK N.C. (2) nCONFIG MSEL[4..0] (3) DCLK MSEL[4..0] (3) Notes to Figure 9-17: (1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. VCCPGM must be high enough to meet the VIH specification of the I/O on the device and the external host. Altera recommends powering up all the configuration system I/Os with VCCPGM. (2) You can leave the nCEO pin unconnected or use it as a user I/O pin. (3) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL, refer to Table 9-4 on page 9-7. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-30 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Passive Serial Configuration In Figure 9-17, because both nCE pins are tied to GND, both devices in the chain begin and complete the configuration and enter user mode at the same time. 1 To configure the PS multi-device with a single .sof, as shown in Figure 9-17, all Stratix V devices in the chain must be in the same package and density. PS Configuration Timing Figure 9-18 shows the timing waveform for a PS configuration when using a MAX II device or microprocessor as an external host. Figure 9-18. PS Configuration Timing Waveform (Note 1) tCF2ST1 tCFG tCF2CK nCONFIG nSTATUS (2) tSTATUS tCF2ST0 t (6) CLK CONF_DONE (3) tCF2CD tST2CK tCH tCL (4) DCLK tDH Bit 0 Bit 1 Bit 2 Bit 3 DATA0 (5) Bit n tDSU High-Z User I/O User Mode INIT_DONE (7) tCD2UM Notes to Figure 9-18: (1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. (2) After power-up, the Stratix V device holds nSTATUS low for the time of the POR delay. (3) After power-up, before and during configuration, CONF_DONE is low. (4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient. (5) DATA0 is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins Option. (6) To ensure a successful configuration, send the entire configuration data to the Stratix V device. CONF_DONE is released high after the Stratix V device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization and enter user mode. (7) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low. Table 9-12 lists the PS configuration timing parameters for Stratix V devices. Table 9-12. PS Timing Parameters for Stratix V Devices (Note 1) (Part 1 of 2) Symbol Parameter Minimum Maximum Units tCF2CD nCONFIG low to CONF_DONE low -- 600 ns tCF2ST0 nCONFIG low to nSTATUS low -- 600 ns tCFG nCONFIG low pulse width 2 -- s tSTATUS nSTATUS low pulse width 268 1,506 (2) s tCF2ST1 nCONFIG high to nSTATUS high -- 1,506 (3) s Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Passive Serial Configuration 9-31 Table 9-12. PS Timing Parameters for Stratix V Devices (Note 1) (Part 2 of 2) Symbol Parameter Minimum Maximum Units tCF2CK nCONFIG high to first rising edge on DCLK 1,506 -- s tST2CK nSTATUS high to first rising edge of DCLK 2 -- s tDSU DATA[] setup time before rising edge on DCLK 5.5 -- ns tDH DATA[] hold time after rising edge on DCLK 0 -- ns tCH DCLK high time 0.45 1/fMAX -- s tCL DCLK low time 0.45 1/fMAX -- s tCLK DCLK period 1/fMAX -- s fMAX DCLK frequency -- 125 MHz tR Input rise time -- 40 ns tF Input fall time -- 40 ns tCD2UM CONF_DONE high to user mode (4) 175 437 s tCD2CU CONF_DONE high to CLKUSR enabled 4 x maximum DCLK period -- -- tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (17,408 CLKUSR period) (5) -- -- Notes to Table 9-12: (1) This information is preliminary. (2) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (3) This value is applicable if you do not delay configuration by externally holding the nSTATUS low. (4) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device. (5) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to "Initialization" on page 9-5. 1 Two DCLK falling edges are required after CONF_DONE goes high to begin the initialization of the device for both uncompressed and compressed configuration data in the PS configuration scheme. PS Configuration Using a Download Cable 1 In this section, the generic term "download cable" includes the Altera USB-Blaster universal serial bus (USB) port download cable, ByteBlaster II parallel port download cable, and EthernetBlaster download cable. In a PS configuration with a download cable, a PC acts as a host to transfer data from a storage device to the Stratix V device using the download cable. During configuration, the programming hardware or download cable places the configuration data one bit at a time on the device's DATA0 pin. The configuration data is clocked into the target device until CONF_DONE goes high. 1 January 2011 If you turn on the CLKUSR option during PS configuration using a download cable and the Quartus II programmer, you do not have to provide a clock on the CLKUSR pin to initialize your device. Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-32 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Passive Serial Configuration Figure 9-19 shows a PS configuration for Stratix V devices using an Altera download cable. Figure 9-19. PS Configuration Using an Altera Download Cable VCCPGM (1) (2) VCCPGM (1) VCCPGM (1) VCCPGM (1) VCCPGM (1) Stratix V Device (2) CONF_DONE nSTATUS (4) MSEL[4..0] nCE GND DCLK DATA0 nCONFIG nCEO N.C. Download Cable 10-Pin Male Header (PS Mode) Pin 1 VCCIO (1) GND VIO (3) Shield GND Notes to Figure 9-19: (1) Connect the pull-up resistor to the same supply voltage (VCCIO) as the USB-Blaster, ByteBlaster II, or EthernetBlaster cable. (2) You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a MAX II device or microprocessor, you do not need the pull-up resistors on DATA0 and DCLK. (3) In the USB-Blaster and ByteBlaster II cables, this pin is connected to nCE when you use for AS programming; otherwise, it is a no connect. (4) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[4..0], refer to Table 9-4 on page 9-7. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Passive Serial Configuration 9-33 Multi-Device PS Configuration Using Download Cable You can use a download cable to configure multiple Stratix V devices as shown in Figure 9-20. Figure 9-20. Multi-Device PS Configuration Using an Altera Download Cable VCCPGM (1) 10 k Stratix V Device 1 VCCPGM (1) 10 k (2) (4) nCE 10 k GND 10 k VCCPGM (1) 10 k CONF_DONE nSTATUS DCLK MSEL[4..0] VCCPGM (1) Download Cable 10-Pin Male Header (PS Mode) VCCPGM (1) (2) Pin 1 VCCPGM (1) GND VIO (3) nCEO DATA0 nCONFIG GND Stratix V Device 2 (4) CONF_DONE MSEL[4..0] nSTATUS DCLK nCEO N.C. nCE DATA0 nCONFIG Notes to Figure 9-20: (1) Connect the pull-up resistor to the same supply voltage (VCCIO) as the USB-Blaster, ByteBlaster II, or EthernetBlaster cable. (2) You only need the pull-up resistors on DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures that DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need the pull-up resistors on DATA0 and DCLK. (3) In the USB-Blaster and ByteBlaster II cables, this pin is connected to nCE when you use it for AS programming; otherwise, it is a no connect. (4) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect MSEL[4..0], refer to Table 9-4 on page 9-7. In Figure 9-20, after the first device completes configuration, its nCEO pin drives low to activate the second device's nCE pin, which prompts the second device to begin configuration. The nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE pins are connected to every device in the chain. As all the CONF_DONE and nSTATUS pins are tied together, all devices initialize and enter user mode at the same time. If any device detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device flags an error on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This behavior is similar to a single device detecting an error. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-34 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices JTAG Configuration JTAG Configuration You can use the same JTAG interface specifically developed for boundary-scan test (BST) to shift the configuration data into the device. The Quartus II software automatically generates a .sof that you can use for JTAG configuration with a download cable in the Quartus II software programmer. 1 To use JTAG interface for JTAG programming or debugging with Stratix V devices, issue FACTORY instruction after the device exits POR and before configuration begins. For more information about the FACTORY instruction, refer to "Factory Instruction" on page 9-55. f For more information about JTAG BST and the commands available using Stratix V devices, refer to the following documents: JTAG Boundary-Scan Testing in Stratix V Devices chapter Programming Support for Jam STAPL Language Stratix V devices are designed such that JTAG instructions have precedence over any device configuration modes. JTAG configuration can take place without waiting for other configuration modes to complete. For example, if you attempt JTAG configuration of Stratix V devices during a PS configuration, the PS configuration is terminated and the JTAG configuration begins. All user I/O pins are tri-stated during the JTAG configuration. 1 You cannot use the Stratix V decompression or design security features if you are configuring your Stratix V device using JTAG-based configuration. 1 For more information about TDI, TDO, TMS, and TCK, refer to "Device Configuration Pins" on page 9-38 f For instructions to connect a JTAG chain with multiple voltages across the devices in the chain, refer to the JTAG Boundary Scan Testing in Stratix V Devices chapter. To configure a single device in a JTAG chain, the programming software places all the other devices in bypass mode. In bypass mode, devices pass programming data from the TDI pin to the TDO pin through a single bypass register without being affected internally. This scheme enables the programming software to program or verify the target device. Configuration data driven into the device appears on the TDO pin one clock cycle later. The Quartus II software verifies successful JTAG configuration after completion by checking the state of CONF_DONE through the JTAG port. If CONF_DONE is not high, the Quartus II software indicates that configuration has failed. If CONF_DONE is high, the software indicates that configuration was successful. After the configuration data is transmitted serially using the JTAG TDI port, the TCK port is clocked an additional 1,222 cycles to perform device initialization. 1 The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on Stratix V devices do not affect JTAG boundary-scan or programming operations. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices JTAG Configuration 1 9-35 You can generate a JAM File (.jam) or Jam-byte Code (.jbc) to be used with other third party programmer tools. Alternatively, you can use JRunner with .rbf to program your device. Figure 9-21 shows the JTAG configuration of a single Stratix V device. Figure 9-21. JTAG Configuration of a Single Device Using a Download Cable VCCPD (1) VCCPGM (3) VCCPGM VCCPD (1) Stratix V Device (3) nCE GND N.C. nCEO TCK TDO TMS TDI nSTATUS CONF_DONE (2) nCONFIG (2) MSEL[4..0] (2) DCLK VCCPD (1) TRST Download Cable 10-Pin Male Header (JTAG Mode) (Top View) Pin 1 V (1) CCPD GND GND GND Notes to Figure 9-21: (1) Connect the pull-up resistor VCCPD . For more information, refer to VCCPD requirement in "VCCPD Pin" on page 9-3. (2) If you only use JTAG configuration, connect nCONFIG to VCCPGM and MSEL[4..0] to GND. Pull DCLK either high or low, whichever is convenient on your board. If you are using JTAG in conjunction with another configuration scheme, connect MSEL[4..0], nCONFIG and DCLK based on the selected configuration scheme. (3) The resistor value can vary from 1 k to 10 k . Perform signal integrity analysis to select the resistor value for your setup. (4) You must connect nCE to GND or drive it low for successful JTAG configuration. Alternatively, you can use a microprocessor to program the device through the JTAG interface. You can use JRunner as your software driver. f For more information about JRunner, refer to AN 414: The JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-36 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices JTAG Configuration Figure 9-22 shows a JTAG configuration of a Stratix V device using a microprocessor. Figure 9-22. JTAG Configuration of a Single Device Using a Microprocessor Memory ADDR VCCPGM(1) VCCPGM(1) DATA VCCPD Stratix V Device 10 k 10 k nSTATUS TRST CONF_DONE TDI (4) Microprocessor TCK (4) DCLK (2) TMS (4) nCONFIG (2) TDO (4) MSEL[4..0] nCEO (2) N.C. nCE GND Notes to Figure 9-22: (1) Connect the pull-up resistor to a supply that provides an acceptable input signal for all Stratix V devices in the chain. VCCPGM must be high enough to meet the VIH specification of the I/O on the device. (2) If you only use the JTAG configuration, connect nCONFIG to VCCPGM and MSEL[4..0] to GND. Pull DCLK either high or low, whichever is convenient on your board. If you are using JTAG in conjunction with another configuration scheme, set the MSEL[4..0] and tie nCONFIG and DCLK based on the selected configuration scheme. (3) Connect nCE to GND or drive it low for successful JTAG configuration. (4) The microprocessor must use the same I/O standard as VCCPD to drive the JTAG pins. CONFIG_IO Instruction The CONFIG_IO instruction allows you to configure I/O buffers using the JTAG port and when issued, interrupts configuration. This instruction allows you to perform board-level testing prior to configuring the Stratix V device or waiting for a configuration device to complete configuration. After configuration is interrupted and JTAG testing is complete, you must reconfigure the part using the JTAG interface or if you support FPP, PS, or AS on your board, reconfigure the device by externally pulsing nCONFIG low. Alternatively, you can pulse nCONFIG low through the same JTAG interface using the PULSE_NCONFIG JTAG instruction. 1 All JTAG instructions (except BYPASS, IDCODE, and SAMPLE) can be issued by first interrupting the configuration and reprogramming the I/O pins using the CONFIG_IO instruction. Multi-Device JTAG Configuration When programming a JTAG device chain, one JTAG-compatible header is connected to several devices. The number of devices in the JTAG chain is limited only by the drive capability of the download cable. When four or more devices are connected in a JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an on-board buffer. You can place other Altera devices that have JTAG support in the same JTAG chain for device programming. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices JTAG Configuration 9-37 JTAG-chain device programming is ideal when the system contains multiple devices or when testing your system using JTAG BST circuitry. Figure 9-23 shows a multi-device JTAG configuration. Figure 9-23. JTAG Configuration of Multiple Devices Using a Download Cable Stratix V Device Download Cable 10-Pin Male Header (JTAG Mode) VCCPGM (2) (3) Pin 1 (2) VCCPD (1) (2) VCCPD (1) VIO VCCPD (1) VCCPGM 10 k 10 k VCCPD (1) Stratix V Device VCCPGM (2) MSEL[4..0] (2) nCE (4) (2) VCCPD (1) (2) MSEL[4..0] (2) nCE (4) TRST TDI TDI (2) VCCPD (1) 10 k nSTATUS nCONFIG DCLK CONF_DONE MSEL[4..0] nCE (4) TRST TDI TDO TCK VCCPGM 10 k nSTATUS nCONFIG DCLK CONF_DONE TRST TMS VCCPGM 10 k 10 k nSTATUS nCONFIG DCLK CONF_DONE Stratix V Device VCCPGM TDO TMS TCK TDO TMS TCK (3) 1 k Notes to Figure 9-23: (1) Connect the pull-up resistor VCCPD . For more information, refer to VCCPD requirement in "VCCPD Pin" on page 9-3. (2) If you only use JTAG configuration, connect nCONFIG to VCCPGM and MSEL[4..0] to GND. Pull DCLK either high or low, whichever is convenient on your board. If you are using JTAG in conjunction with another configuration scheme, connect the MSEL[4..0], nCONFIG, and DCLK based on the selected configuration scheme. (3) The resistor value can vary from 1k to 10 k. Perform signal integrity analysis to select the resistor value for your setup. (4) You must connect nCE to GND or drive it low for successful JTAG configuration. 1 If you want to use the JTAG multi-device configuration in conjunction with other schemes, such as a FPP, PS, or AS, tie CONF_DONE, nSTATUS, and nCONFIG together as recommended in the FPP, PS, or AS multi-device configuration schemes. Ensure that the JTAG chain is the same order as the multi-device FPP, PS, or AS configuration chain. 1 If you only use JTAG configuration, Altera recommends connecting the circuitry as shown in Figure 9-22, where each of the CONF_DONE and nSTATUS signals are isolated to enable each device to enter user mode individually. f For more information about combining the JTAG configuration with other configuration schemes, refer to the Combining Different Configuration Schemes chapter in volume 2 of the Configuration Handbook. f For more information about JTAG and Jam STAPL in embedded environments, refer to AN 425: Using Command-Line Jam STAPL Solution for Device Programming. To download the Jam player, visit the Altera website. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-38 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Device Configuration Pins f For more information about how to use the USB-Blaster, ByteBlaster II, or EthernetBlaster cables, refer to the following user guides: USB-Blaster Download Cable User Guide ByteBlaster II Download Cable User Guide Ethernet Blaster Communications Cable User Guide Device Configuration Pins Table 9-13 and Table 9-14 list the connections and functionality of all the configuration-related pins on the Stratix V devices. Table 9-13 lists the Stratix V configuration pins and their power supply. Table 9-13. Configuration Pin Summary for Stratix V Devices (Part 1 of 2) Description Input/Output User Mode Powered By Configuration Scheme TDI Input -- VCCPD JTAG TMS Input -- VCCPD JTAG TCK Input -- VCCPD JTAG TRST Input -- VCCPD JTAG TDO Output -- VCCPD JTAG Input I/O (1) VCCPGM/VCCIO (4) All schemes CRC_ERROR Output I/O (1) Pull-up Optional, all schemes CONF_DONE Bidirectional -- VCCPGM/Pull-up All schemes FPP, PS CLKUSR DATA0 Bidirectional I/O (2) VCCPGM/VCCIO (4) DATA[31..1] Bidirectional I/O (2) VCCPGM/VCCIO (4) FPP Input -- VCCPGM FPP, PS Output -- VCCPGM AS DEV_OE Input I/O (1) VCCPGM/VCCIO (4) Optional, all schemes DEV_CLRn Input I/O (1) VCCPGM/VCCIO (4) Optional, all schemes INIT_DONE Output I/O (1) Pull-up Optional, all schemes MSEL[4..0] Input -- VCCPGM All schemes Bidirectional -- VCCPGM All schemes Input -- VCCPGM All schemes Output I/O (3) Pull-up All schemes DCLK nSTATUS nCE nCEO nCONFIG nCSO nIO_PULLUP AS_DATA0/ASDO Input -- VCCPGM All schemes Output -- VCCPGM AS Input -- VCC (5) All schemes Bidirectional -- VCCPGM AS Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Device Configuration Pins 9-39 Table 9-13. Configuration Pin Summary for Stratix V Devices (Part 2 of 2) Description AS_DATA[3..1] Input/Output User Mode Powered By Configuration Scheme Bidirectional -- VCCPGM AS Notes to Table 9-13: (1) This is a dual-purpose pin. This pin is available as an I/O if the associated option that enables this pin is turned off from the Configuration panel in the Device and Pins Option settings. For example, the DEV_OE is available as a user I/O if the Enable device-wide output enable option is turned off. (2) This is a dual-purpose pin. The state of this pin in user mode depends on the Dual-purpose Pins settings in the Device and Pins Option. (3) This pin is available as an I/O if this pin is not feeding the next device's nCE in a multi-device configuration. To use this pin to feed the next device's nCE in a multi-device chain, turn on Enable INIT_DONE output option under Device and Pins Option, General panel in the Quartus II Software. (4) This pin is powered up by VCCPGM during configuration. It is powered up by VCCIO of the bank in which the pin resides if it is used as a regular I/O in user mode. (5) Although nIO_PULLUP is powered up by VCC, Altera recommends connecting this pin to VCCPGM or GND directly without using a pull-up or pull-down resistor. Table 9-14 lists the configuration pin descriptions. Table 9-14. Configuration Pins Description (Part 1 of 3) Pin Name TDI (1) TMS (1) Description Dedicated test data input. Serial input pin for instructions as well as test and programming data. Data is shifted on the rising edge of TCK. This pin has an internal 25-k pull-up that is always active. Dedicated test mode select. Input pin that provides the control signal to determine the transitions of the TAP controller state machine. TMS is evaluated on the rising edge of TCK. Therefore, you must set up TMS before the rising edge of TCK. Transitions in the state machine occur on the falling edge of TCK after the signal is applied to TMS. This pin has an internal 25-k pull-up that is always active. TCK (1) Dedicated test clock input. Clock input to the BST circuitry. Some operations occur at the rising edge, while others occur at the falling edge. It is expected that the clock input waveform have a nominal 50% duty cycle. This pin has an internal 25-k pull-down that is always active. TRST (1) Dedicated test reset input. Active-low input to asynchronously reset the boundary-scan circuit. The TRST pin is optional according to the IEEE Std. 1149.1 standard. Connecting this pin low disables the JTAG circuitry. This pin has an internal 25-k pull-up that is always active. TDO (1) Dedicated test data output. Serial data output pin for instructions as well as test and programming data. Data is shifted out on the falling edge of TCK. This pin is tri-stated if the data is not being shifted out of the device. CLKUSR Optional user-supplied clock input. It synchronizes the initialization of one or more devices. Enable this pin by turning on the Enable user-supplied start-up clock (CLKUSR) option under Device and Pins Option, Configuration panel in the Quartus II software. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-40 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Device Configuration Pins Table 9-14. Configuration Pins Description (Part 2 of 3) Pin Name Description Optional output pin. Signals that the device has detected a cyclical redundancy check (CRC) error during user mode operation. this pin is an open-drain output pin by default and requires a 10 k pull-up resistor. To use this pin as regular output, turn-off the Enable Open-drain on CRC_ERROR pin in Device and Pins Option, Error Detection CRC panel in the Quartus II software. CRC_ERROR The target device drives this pin low if there is no CRC error in user mode operation. As an open-drain output, if a CRC error occurs, the device releases the pin which is then pulled high by the external pull-up resistor. Enable this pin by turning on Enable CRC error detection on CRC_ERROR pin option in the Quartus II software. For more information about the CRC_ERROR pin, refer to SEU Mitigation in Stratix V Devices chapter. CONF_DONE Dedicated open-drain bidirectional pin. The target device drives the CONF_DONE pin low before and during configuration. After all the configuration data is received without error and the initialization cycle starts, the target device releases the CONF_DONE pin, which is then pulled high by the external pull-up resistor. The target device then reads the CONF_DONE pin status to ensure that the CONF_DONE is at logic high. After it is sensed high, the target device initializes and enters user mode. Driving CONF_DONE low after initialization completes does not affect the configured device. DATA0 (3) DATA[31..1] (3) Dual-purpose data input pin. The data received on DATA0 is synchronized to DCLK. After configuration completes, this pin is available as a user I/O pin. Dual-purpose data input pins. If you are using FPP x16 or FPP x32, only a subset of these pins are required for configuration. The pins that are not required for configuration, you can use them as regular I/Os. During configuration, byte-wide, or word-wide data is received on these pins. The data received on DATA[31..1] are synchronized to the DCLK. Dedicated bidirectional clock pin. In the PS and FPP configurations, DCLK is the clock input used to clock data from an external source into the target device. Data is latched into the device on the rising edge of DCLK. After configuration completes, drive DCLK high or low, whichever is more convenient. DCLK In the AS mode, DCLK is an output clock to clock the EPCS or EPCQ devices. Data is latched into the device on the falling edge of the DCLK. After AS configuration completes, this pin is tri-stated with a weak pull-up resistor. Toggling this pin after configuration does not affect the configured device. DEV_OE (2) Optional input pin that allows you to override all tri-states on the device. When this pin is driven low, all the I/O pins are tri-stated. When this pin is driven high, all the I/O pins behave as programmed. Enable this pin by turning on the Enable device-wide output enable (DEV_OE) option in the Quartus II software. DEV_CLRn (2) Optional input pin that allows you to override all clears on all the device registers. When this pin is driven low, all the registers are cleared. When this pin is driven high, all the registers behave as programmed. This pin is enabled by turning on the Enable device-wide reset (DEV_CLRn) option in the Quartus II software. Optional output pin. Signals when the device has initialized and is in user mode. During the reset stage, after the device exits POR, and during the beginning of the configuration, the INIT_DONE pin is tri-stated and pulled high due to an external pull-up resistor. INIT_DONE (2) After the option bit to enable INIT_DONE is programmed into the device (during the first frame of configuration data), the INIT_DONE pin goes low. When initialization completes, the INIT_DONE pin is released and pulled high and the device enters user mode. Thus, the monitoring circuitry must be able to detect a low-to-high transition. Enable this pin by turning on the Enable INIT_DONE output option in the Quartus II software. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Device Configuration Pins 9-41 Table 9-14. Configuration Pins Description (Part 3 of 3) Pin Name Description Dedicated input pins. Five-bit configuration input that sets the Stratix V device configuration scheme. For the appropriate connections, refer to Table 9-4 on page 9-7. MSEL[4..0] The MSEL[4..0] pins have internal 5-k pull-down resistors that are always active. Dedicated open-drain bidirectional pin. The device drives nSTATUS low immediately after power-up and releases it after the device exits POR. During user mode and regular configuration, this pin is pulled high by an external 10-k resistor. During configuration, the device drives this pin low to indicate an error during configuration. If an external source drives the nSTATUS pin low during configuration or initialization, the target device enters an error state. This mechanism is used during multi-device configuration setup. If one of the devices in the chain has an error and pulls its nSTATUS pin low, it resets the entire chain. nSTATUS Driving nSTATUS low after configuration and initialization completes does not affect the configured device. nCE Dedicated active-low chip enable input pin. Driving this pin low allows configuration. Drives the nCE pin low during configuration, initialization, and user mode for all single-device configurations. For a multi-device configuration, connect the nCE pin to GND or to the nCEO of the previous device in the chain based on the recommendation in the respective configuration setup diagram. nCEO (3) Dual-purpose open-drain output pin. This pin drives low when device configuration completes. To use this pin to feed the next device's nCE pin in a multi-device chain, turn on Enable INIT_DONE output option under Device and Pins Option, General panel in the Quartus II Software. In a single-device configuration, this pin can be used as a regular I/O. In multi-device configuration, if this pin is not feeding the nCE of the next device, you can use it as a regular I/O. Dedicated input pin. A low pulse on this pin during configuration and user mode causes the device to enter a reset state and tri-states all the I/O pins. A low-to-high logic starts a reconfiguration. nCONFIG During JTAG programming, the nCONFIG status is ignored. Dedicated output pin. Drives the control signal from the Stratix V device to the EPCS and EPCQ devices in AS mode. After AS configuration completes, these pins are tri-stated with a weak pull-up resistor. nCSO nIO_PULLUP Dedicated input pin. This input pin enables or disables the internal pull-up resistors on the user I/O pins and dual purpose I/O pins (DATA[31..0], CLKUSR, INIT_DONE, DEV_OE, and DEV_CLRN). A logic high turns off the weak internal pull-up resistors, while a logic low turns them on. This pin has an internal 5-k pull-down resistor that is always active. AS_DATA0/ASDO Dedicated bidirectional data pin. In AS 1 and AS 4 configurations, ASDO is used to send the operation command and addresses to the EPCS or EPCQ devices. During an AS 4 configuration, the data is received on an AS_DATA0 and is synchronized to DCLK. After AS configuration completes, this pin is tri-stated with a weak pull-up resistor. AS_DATA[3..1] Dedicated bidirectional data pins. During an AS configuration, the data is received on these pins and is synchronized to DCLK. After AS configuration completes, these pins are tri-stated with a weak pull-up resistor. Notes to Table 9-14: (1) If the JTAG interface is not required on the board, you can disable the JTAG circuitry by connecting this pin to logic high. For instructions to connect a JTAG chain with multiple voltages across the devices in the chain, refer to the JTAG Boundary Scan Testing chapter. (2) This is a dual-purpose pin. This pin is available as an I/O if the associated option that enables this pin is turned off from the Configuration panel in the Device and Pins Option settings. For example, the DEV_OE is available as a user I/O if the Enable device-wide output enable option is turned off. (3) This is a dual-purpose pin. The state of this pin in the user mode depends on Dual-purpose Pins settings in the Device and Pins Option settings. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-42 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Configuration Data Decompression Configuration Data Decompression Stratix V devices support configuration data decompression, which saves configuration memory space and may shorten the configuration time. This feature allows you to store compressed configuration data in the configuration or other memory devices and transmit this compressed data to the Stratix V devices. During configuration, the Stratix V device decompresses the data in real time and programs its SRAM cells. The data decompression is done on-the-fly during configuration and does not require an additional processing time. Preliminary data indicates that compression typically reduces the configuration data size by 30 to 55% based on the designs used. This reduces the storage requirement capacity for the flash memory. The decompression feature is supported in all configuration schemes except JTAG. 1 In FPP, enabling the decompression feature requires a different DCLK-to-DATA[] ratio. For more information, refer to "Fast Passive Parallel Configuration" on page 9-9. There are two ways to enable compression for Stratix V data--before design compilation (in the Compiler Settings menu) and after design compilation (in the Convert Programming Files window). To enable compression in the project's Compiler Settings menu, perform the following steps: 1. On the Assignments menu, click Device to bring up the Settings dialog box. 2. After selecting your Stratix V device, open the Device and Pin Options dialog box. 3. In the Configuration settings panel, turn on the Generate compressed bitstreams option (Figure 9-24). Figure 9-24. Enabling Compression Bitstreams in Compiler Settings for Stratix V Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Configuration Data Decompression 9-43 You can also enable compression when creating programming files from the Convert Programming Files window. To do this, perform the following steps: 1. On the File menu, click Convert Programming Files. 2. Select the programming file type (.pof, .sram, .hex, .hexout, .rbf, or .ttf). 3. For POF output files, select a configuration device. 4. In the Input files to convert box, select SOF Data. 5. Select Add File and add a Stratix V device .sof. 6. Select the name of the file you added to the SOF Data area and click Properties. 7. Check the Compression check box. If you are using a serial configuration scheme, AS x1 or PS, for multi-device configuration, you can selectively enable the compression feature for each device in the chain. Figure 9-25 shows a chain of two Stratix V devices. The first Stratix V device has compression enabled and therefore receives compressed data from the external host. The second Stratix V device has the compression feature disabled and receives uncompressed data. 1 For FPP configuration schemes, a combination of compressed and uncompressed configuration in the same multi-device chain is not allowed due to the difference of the DCLK-to-DATA[] ratio. Figure 9-25. Compressed and Uncompressed Serial Configuration Data in the Same Configuration File (Note 1) Serial Configuration Data EPCS, EPCQ, or External Host Uncompressed Configuration Data Compressed Configuration Data Decompression Controller Stratix V Device Stratix V Device nCE nCEO nCE nCEO N.C. GND Note to Figure 9-25: (1) The configuration for this setup can be generated from the Convert Programming Files menu in the Quartus II software. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-44 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Remote System Upgrades Remote System Upgrades This section describes the functionality and implementation of the dedicated remote system upgrade circuitry. It also defines several concepts related to remote system upgrades, including factory configuration, application configuration, remote update mode, and user watchdog timer. Additionally, this section provides design guidelines for implementing remote system upgrades with the supported configuration schemes. System designers sometimes face challenges such as shortened design cycles, evolving standards, and system deployments in remote locations. Stratix V devices help overcome these challenges with their inherent reprogrammability and dedicated circuitry to perform remote system upgrades. Remote system upgrades help deliver feature enhancements and bug fixes without costly recalls, reduce time-to-market, extend product life, and help to avoid system downtime. Stratix V devices feature dedicated remote system upgrade circuitry. A soft logic (either the Nios(R) II embedded processor or user logic) implemented in a Stratix V device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to start a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. Remote system upgrades are supported in AS configuration schemes with EPCS and EPCQ devices. You can also implement remote system upgrades in conjunction with advanced Stratix V features such as real-time decompression of configuration data and design security using the advanced design security standard (AES) for secure and efficient field upgrades. The largest EPCS and EPCQ device currently supports 128 Mbits and 256 Mbits configuration data respectively. 1 Remote system upgrades are supported only in single-device configurations. The remote system upgrade process in Stratix V devices involves the following steps: 1. A Nios II processor (or user logic) implemented in the Stratix V device logic array receives new configuration data from a remote location. The connection to the remote source uses a communication protocol such as TCP/IP, PCI, user datagram protocol (UDP), UART, or a proprietary interface. 2. The Nios II processor (or user logic) stores this new configuration data in non-volatile configuration memory. 3. The Nios II processor (or user logic) starts a reconfiguration cycle with the new or updated configuration data. 4. The dedicated remote system upgrade circuitry detects and recovers from any errors that might occur during or after the reconfiguration cycle and provides error status information to the user design. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Remote System Upgrades 9-45 Figure 9-26 shows these remote system upgrade steps. Figure 9-26. Functional Diagram of the Stratix V Remote System Upgrade Process 2 1 Development Location 3 Data Stratix V Remote System Upgrade Circuitry Data Configuration Memory Data Stratix V Configuration 4 Figure 9-27 shows a block diagram for implementing a remote system upgrade with the Stratix V AS configuration scheme. Figure 9-27. Remote System Upgrade Block Diagram for Stratix V AS Configuration Scheme (1) Stratix V Device Nios II Processor or User Logic EPCS or EPCQ Note to Figure 9-27: (1) You must set the mode select pins (MSEL[4..0]) to AS mode to use remote system upgrade in your system. The MSEL pin settings vary for different POR delays. To connect MSEL[4..0], refer to Table 9-4 on page 9-7. Configuration Image Types When performing a remote system upgrade, Stratix V device configuration data are classified as factory configuration images or application configuration images. An image, also referred to as a configuration image, is a design loaded into the Stratix V device that performs certain user-defined functions. The factory image is a user-defined fall-back, or safe configuration, and is responsible for initiating the reconfiguration to a new image with the dedicated circuitry. Application images implement user-defined functionality in the target Stratix V device. You may also include the default application image functionality in the factory image. Each Stratix V device in your system requires one factory image and one or more application images. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-46 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Remote System Upgrades Remote Update Mode Stratix V remote system upgrade circuitry only supports remote update mode. In remote update mode, Stratix V devices load the factory configuration image after power up. The user-defined factory configuration determines which application configuration is to be loaded and triggers a reconfiguration cycle. When a Stratix V device is first powered up in remote update mode, it loads the factory configuration located at the start address of PGM[23..0] = 24'h000000 in the EPCS and EPCQ devices. You must store your factory configuration image at this start address. 1 The application image start address can be at any EPCS or EPCQ sector boundary. Altera recommends using different sectors in the EPCS device for two images. The factory image is user-designed and contains soft logic to perform the following: Process any errors based on status information from the dedicated remote system upgrade circuitry Communicate with the remote host and receive new application configurations and store this new configuration data in the local non-volatile memory device Determine which application configuration is to be loaded into the Stratix V device Enable or disable the user watchdog timer and load its time-out value Instruct the dedicated remote system upgrade circuitry to start a reconfiguration cycle Figure 9-28 shows the transitions between the factory and application configurations in remote update mode. Figure 9-28. Transitions Between Configurations in Remote Update Mode Configuration Error Set Control Register and Reconfigure Power Up Configuration Error Factory Configuration (page 0) Application 1 Configuration Reload a Different Application Reload a Different Application Set Control Register and Reconfigure Application n Configuration Configuration Error Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Remote System Upgrades 9-47 After power up or a configuration error, the factory configuration image is loaded automatically. The system then decides to switch to the application configuration image or to stay in the factory configuration image. After the system decides to switch to an application configuration image, a reconfiguration is initiated through the remote system upgrade circuitry. In the application configuration image, the system may revert back to factory configuration image after the following reconfiguration trigger conditions are met: nSTATUS driven low externally Configuration CRC error User watchdog timer time-out Core nCONFIG signal assertion External nCONFIG signal assertion After the factory configuration image is re-loaded, the user-designed factory configuration can read the remote system upgrade status register to determine the reason for the reconfiguration. The factory configuration then takes the appropriate error recovery steps and writes to the remote system upgrade control register to determine the next application configuration to be loaded. Whenever the application configuration image is successfully loaded, the soft logic (Nios II processor or state machine and the remote communication interface) determine when the remote system update is arriving. When this occurs, the soft logic receives the incoming data, writes it to the configuration memory device, and triggers the device to load the factory configuration. The factory configuration reads the remote system upgrade status register and control register, determines the valid application configuration to load, writes the remote system upgrade control register accordingly, and initiates system reconfiguration. Dedicated Remote System Upgrade Circuitry This section describes the implementation of the Stratix V dedicated remote system upgrades circuitry. The remote system upgrade circuitry is implemented in hard logic. This dedicated circuitry interfaces with the user-defined factory and application configurations implemented in the Stratix V device logic array to provide the complete remote configuration solution. The remote system upgrade circuitry contains the remote system upgrade registers, a watchdog timer, and a state machine that controls those components. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-48 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Remote System Upgrades Figure 9-29 shows the remote system upgrade circuitry. Figure 9-29. Remote System Upgrade Circuitry (Note 1) Internal Oscillator Status Register (SR) [4..0] Control Register [37..0] Logic Array Update Register [37..0] update Shift Register dout Bit [4..0] din dout capture RSU State Machine din Bit [37..0] capture time-out User Watchdog Timer clkout capture update Logic Array clkin RU_DOUT RU_SHIFTnLD RU_CAPTnUPDT RU_CLK RU_DIN RU_nCONFIG RU_nRSTIMER Logic Array Note to Figure 9-29: (1) If you are using the ALTREMOTE_UPDATE megafunction, the RU_DOUT, RU_SHIFTnLD, RU_CAPTnUPDT, RU_CLK, RU_DIN, RU_nCONFIG, and RU_nRSTIMER signals are internally controlled by the megafunction to perform all the related remote system upgrade operations. Table 9-15 lists the timing parameter specifications for the remote system upgrade circuitry. Table 9-15. Remote System Upgrade Circuitry Timing Specifications Parameter Minimum Maximum Unit fMAX_RU_CLK (1) -- 40 MHz tRU_nCONFIG (2) 250 -- ns tRU_nRSTIMER (3) 250 -- ns Notes to Table 9-15: (1) This clock is user-supplied to the remote system upgrade circuitry. If you are using the ALTREMOTE_UPDATE megafunction, the clock user-supplied to the ALTREMOTE_UPDATE megafunction must meet this specification. (2) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE megafunction high for the minimum timing specification. For more information, refer to "Remote System Upgrade State Machine" on page 9-51. (3) This is equivalent to strobing the reset_timer input of the ALTREMOTE_UPDATE megafunction high for the minimum timing specification. For more information, refer to "User Watchdog Timer" on page 9-51. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Remote System Upgrades 9-49 Remote System Upgrade Registers The remote system upgrade block contains a series of registers that store the page addresses, watchdog timer settings, and status information. Table 9-16 lists these registers. Table 9-16. Remote System Upgrade Registers Register Description Shift register This register is accessible by the logic array and allows the update, status, and control registers to be written and sampled by user logic. Control register This register contains the current page address, user watchdog timer settings, and one bit specifying whether the current configuration is a factory configuration or an application configuration. During a read operation in an application configuration, this register is read into the shift register. When a reconfiguration cycle is initiated, the contents of the update register are written into the control register. Update register This register contains data similar to that in the control register. However, it can only be updated by the factory configuration by shifting data into the shift register and issuing an update operation. When a reconfiguration cycle is triggered by the factory configuration, the control register is updated with the contents of the update register. During a capture in a factory configuration, this register is read into the shift register. Status register This register is written to by the remote system upgrade circuitry on every reconfiguration to record the cause of the reconfiguration. This information is used by the factory configuration to determine the appropriate action following a reconfiguration. During a capture cycle, this register is read into the shift register. The remote system upgrade control and status registers are clocked by the 10-MHz internal oscillator (the same oscillator that controls the user watchdog timer). However, the remote system upgrade shift and update registers are clocked by the user clock input (RU_CLK). Control Register The control register stores the application configuration page address and user watchdog timer settings. The control register functionality depends on the remote system upgrade mode selection. A factory configuration in remote update mode has write access to this register. Figure 9-30 shows the control register bit positions. Table 9-17 defines the control register bits. In the figure, the numbers show the bit position of a setting in a register. For example, bit number 25 is the enable bit for the watchdog timer. Figure 9-30. Remote System Upgrade Control Register 37 36 35 34 33 32 31 30 29 28 27 26 Wd_timer[11..0] January 2011 Altera Corporation 25 Wd_en 24 23 22 .. 3 PGM[23..0] 2 1 0 AnF Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-50 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Remote System Upgrades The application-not-factory (AnF) bit indicates whether the current configuration loaded in the Stratix V device is the factory configuration or an application configuration. This bit is set low by the remote system upgrade circuitry when an error condition causes a fall-back to the factory configuration. When the AnF bit is high, the control register restricts the access to only read operations and enables the watchdog timer. The factory configuration design must set this bit high (1'b1) when updating the contents of the update register with the application page address and watchdog timer settings. Table 9-17 lists the remote system upgrade control register contents. Table 9-17. Remote System Upgrade Control Register Contents Control Register Bit Value (2) AnF (1) 1'b0 PGM[23..0] Application not factory 24'b0x000000 AS configuration start address (StAdd[23..0]) 1'b0 User watchdog timer enable bit Wd_en 12'b000000000000 Wd_timer[11..0] Definition User watchdog time-out value (most significant 12 bits of 29-bit count value: {Wd_timer[11..0], 17'b0}) Notes to Table 9-17: (1) Factory configuration designs must set the AnF bit to 1'b1 before triggering the reconfiguration to application configuration image. (2) This is the default value of the control register bit after the device exits POR and during reconfiguration back to the factory configuration image after reconfiguration trigger conditions. Status Register The status register specifies the reconfiguration trigger condition. Figure 9-31 shows the status register content. The following list defines each bit: Bit 0--CRC error during application configuration Bit 1--nSTATUS assertion by an external device due to an error Bit 2--Stratix V device logic array triggered a reconfiguration cycle, possibly after downloading a new application configuration image Bit 3--external configuration reset (nCONFIG) assertion Bit 4--user watchdog timer time-out Figure 9-31 specifies the contents of the status register. The numbers in the figure show the bit positions in a 5-bit register. Figure 9-31. Remote System Upgrade Status Register (Note 1) 4 Wd 3 2 1 nCONFIG Core_nCONFIG nSTATUS 0 CRC Note to Figure 9-31: (1) After the device exits POR and powers-up, the status register content is 5'b00000. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Remote System Upgrades 9-51 Remote System Upgrade State Machine After power-up, the shift register, control register, and update registers are reset to the values specified in Table 9-16, also known as POR reset values before the factory configuration image is loaded. In the factory configuration image, the user logic writes the AnF bit, page address, and watchdog timer settings for the next application configuration image to the update register. When the logic array configuration reset (RU_nCONFIG) goes low, the remote system upgrade state machine updates the control register with the contents of the update register, and triggers a reconfiguration to the new application configuration image. If there is an error during reconfiguration to the new application configuration image, the remote system upgrade state machine directs the system to re-load a factory configuration image. The control and update registers are reset to POR reset values and the status register is updated with the error information. For example, if there is a CRC error during application configuration image configuration, the status register is updated with 5'b00001. If there is no error during reconfiguration and the application configuration image is successfully loaded, the system stays in the application configuration image until another reconfiguration trigger condition occurs. This can be a core nCONFIG assertion, external nCONFIG assertion, or the watchdog timer time-out error. If this happens, the control register and update registers are reset to POR reset values and the status register is updated with the error information. Consequently, the system proceeds to load the factory configuration image. Based on the status register content, the user logic in the factory configuration image then decides to stay in the factory configuration image or reload a new application reconfiguration image. 1 Read operations during factory configuration access the contents of the update register. This feature is used by the factory configuration image user logic to verify that the page address and watchdog timer settings are written correctly. Read operations in application configurations access the contents of the control register. This information is used by the user logic in the application configuration. User Watchdog Timer The user watchdog timer prevents a faulty application configuration from stalling the device indefinitely. The system uses the timer to detect functional errors after an application configuration is successfully loaded into the Stratix V device. This feature is automatically disabled in the factory configuration image and enabled in the application configuration image. Functional errors must not exist in the factory configuration because they are stored and validated during production and must never be updated remotely. 1 January 2011 The user watchdog timer feature is automatically enabled in the application configuration image. If you do not wish to use this feature, disable it during the factory configuration image operation before triggering the reconfiguration to the application configuration image. Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-52 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Remote System Upgrades The user watchdog timer is a counter that counts down from the initial value loaded into the remote system upgrade control register by the factory configuration. The counter is 29 bits wide and has a maximum count value of 229. When specifying the user watchdog timer value, specify only the most significant 12 bits. The granularity of the timer setting is 217 cycles. The cycle time is based on the frequency of the 12.5-MHz internal oscillator. Table 9-18 lists the operating range of the 12.5-MHz internal oscillator. Table 9-18. 12.5-MHz Internal Oscillator Specifications (Note 1) Minimum Typical Maximum Units 5.3 7.9 12.5 MHz Note to Table 9-18: (1) These values are preliminary. The user watchdog timer begins counting after the application configuration enters device user mode. This timer must be periodically reset by the application configuration before the timer expires by asserting RU_nRSTIMER. If the application configuration does not reload the user watchdog timer before the count expires, a time-out signal is generated by the remote system upgrade dedicated circuitry. This causes the device to reload the factory configuration image and update the status register to reflect the watchdog timer time-out error. Enabling the Remote System Update Feature You can enable remote update for Stratix V devices in the Quartus II software before design compilation (in the Compiler Settings menu). In remote update mode, the auto-restart configuration after error option is always enabled. To enable remote update in the project's compiler settings, perform the following steps in the Quartus II software: 1. On the Assignments menu, click Device. The Settings dialog box appears. 2. Click Device and Pin Options. The Device and Pin Options dialog box appears. 3. Click the Configuration panel. 4. From the Configuration scheme list, select Active Serial x1 (you can also use Configuration Device) (Figure 9-32). 5. From the Configuration mode list, select Remote (Figure 9-32). 6. Click OK. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Design Security 9-53 7. In the Settings dialog box, click OK. Figure 9-32. Enabling Remote Update for Stratix V Devices in the Compiler Settings Menu ALTREMOTE_UPDATE Megafunction The ALTREMOTE_UPDATE megafunction provides a memory-like interface to the remote system upgrade circuitry and handles the shift register read and write protocol in the Stratix V device logic. This implementation is suitable for designs that implement the factory configuration functions using a Nios II processor or user logic in the device. Using the megafunction block instead of creating your own logic saves design time and offers more efficient logic synthesis and device implementation. f For more information about the ALTREMOTE_UPDATE megafunction, refer to the Remote Update Circuitry (ALTREMOTE_UPDATE) Megafunction User Guide. Design Security This section provides an overview of the design security features and their implementation in Stratix V devices using the advanced encryption standard (AES). It also describes the security modes available in Stratix V devices that allow you to use these new features in your designs. As Stratix V devices continue to play roles in larger and more critical designs in competitive commercial and military environments, it is increasingly important to protect your designs from copying, reverse engineering, and tampering. Stratix V design security supports the following features: January 2011 Enhanced built-in AES decryption block to support 256-key industry-standard design security algorithm (FIPS-197 Certified) Volatile and non-volatile key programming support Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-54 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Design Security 1 Secure operation mode for both volatile and non-volatile key through tamper protection bit setting Limited accessible JTAG instruction during power-up Supports board level testing Supports in-socket key programming for non-volatile key Available in all configuration schemes except JTAG Supports both remote system upgrades and decompression feature You can use the design security feature with or without the remote system upgrades or decompression features. The Stratix V design security feature provides the following security protection for your designs: Security against copying--the security key is securely stored in the Stratix V device and cannot be read out through any interface. In addition, as configuration file read-back is not supported in Stratix V devices, your design information cannot be copied. Security against reverse engineering--reverse engineering from an encrypted configuration file is very difficult and time consuming because the Stratix V configuration file formats are proprietary and the file contains millions of bits that require specific decryption. In addition, the Stratix V devices are manufactured on the most advanced 28-nm process technology, making this process very difficult. Security against tampering--Stratix V devices always power-up with limited accessible JTAG instruction. This disables tamper attempts through the JTAG interface. You can enhance this security feature with the tamper protection bit setting. After the tamper protection bit is set, the Stratix V device can only accept configuration files encrypted with the same key. Additionally, programming through the JTAG interface is blocked. This prevents any attempts to tamper with the device from both the JTAG interface and the configuration interface. 1 When you use compression with the design security feature, the configuration file is first compressed and then encrypted using the Quartus II software. During configuration, the Stratix V device first decrypts and then decompresses the configuration file. 1 When you use design security with Stratix V devices in a FPP configuration scheme, it requires a different DCLK-to-DATA[] ratio. For more information, refer to "Fast Passive Parallel Configuration" on page 9-9. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Design Security 9-55 Factory Instruction Stratix V devices only allow mandatory JTAG 1149.1 instructions after POR. These instructions are IDCODE, BYPASS, SAMPLE/PRELOAD, EXTEST, EXTEST_PULSE, EXTEST_TRAIN and FACTORY. To enable the access of other JTAG instructions, issue the FACTORY instruction. The factory instruction needs to be issued after the device exits POR and before the configuration begins. f For JTAG binary instruction code related to the FACTORY instruction, refer to the JTAG Boundary Scan Testing chapter. The FACTORY instruction puts the device in a state in which it is ready for in-house testing and board-level testing. It must be executed before configuration or key programming begins. When this instruction is executed, the CRAM bits content and volatile key are cleared and the device is reset. 1 The Quartus II software incorporates the FACTORY instruction in every operation performed through the JTAG interface. This instruction is also included in JAM STAPL (.jam), JAM Binary Code (.jbc), and Serial Vector File (.svf) generated from the Quartus II software. You do not need to issue FACTORY instructions separately if you are using the Quartus II software to perform the JTAG-related operations or if you are using a .jam, .jbc, or .svf file. Security Key Types Stratix V devices offer two types of keys--volatile and non-volatile. Table 9-19 lists the differences between the volatile key and non-volatile key. Table 9-19. Security Key Types Key Types Volatile Key Non-volatile Key Key Programmability Re-programmable Erasable One-time programming Power Supply for Key Storage Programming Method Required external battery, VCCBAT (1) On-board Does not require an external battery On-board and in-socket programming (2) Notes to Table 9-19: (1) VCCBAT is a dedicated power supply for volatile key storage and not shared with other on-chip power supplies, such as VCCIO or VCCPGM. VCCBAT continuously supplies power to the volatile register regardless of the on-chip supply condition. (2) In-socket programming is offered through third party vendors. Both non-volatile and volatile key programming offers protection from reverse engineering and copying. If you set the tamper-protection bit, the design is also protected from tampering. 1 Perform key programming through the JTAG interface. Also, ensure that the nSTATUS pin is released high before any key-programming attempts. f For more information about battery specifications, refer to the DC and Switching Characteristics for Stratix V Devices chapter. f For more information about the VCCBAT pin connection recommendations, refer to the Stratix V Device Family Pin Connection Guidelines. January 2011 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-56 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Design Security Security Modes Table 9-20 lists the security modes available in Stratix V devices. Table 9-20. Supported Security Modes Tamper protection Bit Setting Device Accepts Unencrypted File Device Accepts Encrypted File Security Level No-key -- Yes No -- Volatile Key -- Yes (2) Yes Secure Set (1) No Yes Secure with tamper resistant -- Yes (2) Yes Secure Set (1) No Yes Secure with tamper resistant Security Mode Volatile Key with Tamper Protection Bit Set Non-volatile Key Non-volatile Key with Tamper Protection Bit Set Notes to Table 9-20: (1) Enabling the tamper protection bit disables test mode in Stratix V devices and disables programming through the JTAG interface. This process is irreversible and prevents Altera from carry-out failure analysis. Contact Altera Technical Support to enable the tamper protection bit. (2) Use the unencrypted configuration bitstream support only for board-level testing. Figure 9-33 shows the sequence of the security modes available in Stratix V devices. Figure 9-33. Stratix V Security Modes--Sequence and Restrictions No Key Volatile Key Unencrypted or Encrypted Unencrypted Configuration File Configuration File Volatile Key with Tamper-Protection Bit Set Encrypted Encrypted Configuration File (1) Configuration File Non-Volatile Key Unencrypted or Encrypted Configuration File Non-Volatile Key with Tamper-Protection Bit Set Encrypted Configuration File Note to Figure 9-33: (1) Stratix V devices do not accept the encrypted configuration file if the volatile key is erased. You must use the volatile key without tamper-protection bit set to reprogram the key if the volatile key in Stratix V device is erased. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Design Security 9-57 Design Security Implementation Steps Stratix V devices are SRAM-based devices. To provide design security, Stratix V devices require a 256-bit security key for configuration bitstream design security. You can carry out secure configuration in the following four steps, as shown in Figure 9-34: 1. The Quartus II software generates the design security key programming file and encrypts the configuration data using the user-defined 256-bit key. 2. Store the encrypted configuration file in the external memory. 3. Program the AES key programming file into the Stratix V device through a JTAG interface. 4. Configure the Stratix V device. At system power-up, the external memory device sends the encrypted configuration file to the Stratix V device. Figure 9-34. Design Security Implementation Steps Stratix V FPGA AES Key Programming File Step 3 Key Storage AES Decryption Step 1 256-bit User-Defined Quartus II Key AES Encryptor Step 4 Step 1 Encrypted Configuration File January 2011 Altera Corporation Step 2 Memory or Configuration Device Stratix V Device Handbook Volume 1: Device Interfaces and Integration 9-58 Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices Document Revision History Document Revision History Table 9-21 lists the revision history for this chapter. Table 9-21. Document Revision History Date Version Changes Updated Table 9-7, Table 9-8, Table 9-12, and Table 9-14. Updated Figure 9-15 and Figure 9-21. Updated "User Watchdog Timer", "DCLK-to-DATA[] Ratio for FPP configuration", "VCCPD Pin", "POR Delay Specification", and "Programming EPCS and EPCQ" sections. January 2011 1.2 December 2010 1.1 No changes to the content of this chapter for the Quartus II software 10.1. July 2010 1.0 Initial release. Stratix V Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation