EFR32FG13 Flex Gecko Proprietary
Protocol SoC Family Data Sheet
The Flex Gecko proprietary protocol family of SoCs is part of the
Wireless Gecko portfolio. Flex Gecko SoCs are ideal for enabling
energy-friendly proprietary protocol networking for IoT devices.
The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup
times, a scalable power amplifier, an integrated balun and no-compromise MCU fea-
tures.
Flex Gecko applications include:
KEY FEATURES
• 32-bit ARM® Cortex®-M4 core with 40
MHz maximum operating frequency
• 512 kB of flash and 64 kB of RAM
• Pin-compatible with EFR32FG1 devices
(exceptions apply for 5V-tolerant pins)
• 12-channel Peripheral Reflex System
enabling autonomous interaction of MCU
peripherals
• Autonomous Hardware Crypto Accelerator
and True Random Number Generator
• Integrated PA with up to 19 dBm (2.4
GHz) or 20 dBm (Sub-GHz) tx power
• Integrated balun for 2.4 GHz
• Robust peripheral set and up to 32 GPIO
• Home and Building Automation and Security
• Metering
• Electronic Shelf Labels
• Industrial Automation
• Commercial and Retail Lighting and Sensing
Timers and Triggers
32-bit bus
Peripheral Reflex System
Serial
Interfaces
I/O Ports Analog I/F
Lowest power mode with peripheral operational:
USART
Low Energy
UARTTM
I2C
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
ADC
VDAC
Analog
Comparator
EM3—StopEM2—Deep SleepEM1—Sleep EM4—Hibernate EM4—ShutoffEM0—Active
Energy Management
Brown-Out
Detector
DC-DC
Converter
Voltage
Regulator Voltage Monitor
Power-On Reset
OtherClock Management
H-F Crystal
Oscillator
L-F Crystal
Oscillator
L-F
RC Oscillator
H-F
RC Oscillator
Auxiliary H-F RC
Oscillator
Capacitive
Touch
Op-Amp
IDAC
Radio Transceiver
DEMOD
AGC
IFADC
CRC
BUFC
RFSENSE
MOD
FRC
RAC
Frequency
Synthesizer
PGA
PA
I
Q
RF Frontend
LNA
RFSENSE
PA
I
Q
RF Frontend
LNA
To 2.4 GHz receive
I/Q mixers and PA
To Sub GHz
receive I/Q
mixers and PA
To Sub GHz
and 2.4 GHz PA
Sub GHz
2.4 GHz
BALUN
CRYPTO
CRC
True Random
Number Generator
SMU
Ultra L-F RC
Oscillator
Core / Memory
ARM CortexTM M4 processor
with DSP extensions, FPU and MPU
ETM Debug Interface RAM Memory LDMA
Controller
Flash Program
Memory
Real Time
Counter and
Calendar
Cryotimer
Timer/Counter
Low Energy
Timer
Pulse Counter Watchdog Timer
Protocol Timer
Low Energy
Sensor Interface
silabs.com | Building a more connected world. Rev. 1.0
1. Feature List
The EFR32FG13 highlighted features are listed below.
•Low Power Wireless System-on-Chip.
•High Performance 32-bit 40 MHz ARM Cortex®-M4 with
DSP instruction and floating-point unit for efficient signal
processing
• Embedded Trace Macrocell (ETM) for advanced debugging
• 512 kB flash program memory
• 64 kB RAM data memory
• 2.4 GHz and Sub-GHz radio operation
• TX power up to 19 dBm for 2.4 GHz and 20 dBm for Sub-
GHz
•Low Energy Consumption
• 8.4 mA RX current at 38.4 kbps, 2GFSK, 169 MHz
• 9.5 mA RX current at 1 Mbps, GFSK, 2.4 GHz
• 10.2 mA RX current at 250 kbps, O-QPSK DSSS, 2.4 GHz
• 8.5 mA TX current at 0 dBm output power at 2.4 GHz
• 69 μA/MHz in Active Mode (EM0)
• 1.4 μA EM2 DeepSleep current (64 kB RAM retention and
RTCC running from LFXO)
• 1.3 μA EM2 DeepSleep current (16 kB RAM retention and
RTCC running from LFRCO)
• Wake on Radio with signal strength detection, preamble
pattern detection, frame detection and timeout
•High Receiver Performance
• -94.8 dBm sensitivity at 1 Mbit/s GFSK, 2.4 GHz
• -102.7 dBm sensitivity at 250 kbps DSSS-OQPSK, 2.4 GHz
• -126.2 dBm sensitivity at 600 bps, GFSK, 916 MHz
• -120.6 dBm sensitivity at 2.4 kbps, GFSK, 868 MHz
• -107.4 dBm sensitivity at 4.8 kbps, OOK, 433 MHz
• -112.2 dBm sensitivity at 38.4 kbps, 2GFSK, 169 MHz
•Supported Modulation Formats
• 2/4 (G)FSK with fully configurable shaping
• BPSK / DBPSK TX
• OOK / ASK
• Shaped OQPSK / (G)MSK
• Configurable DSSS and FEC
•Supported Protocols:
• Proprietary Protocols
• Wireless M-Bus
• Selected IEEE 802.15.4g SUN-FSK PHYs
• Low Power Wide Area Networks
•Support for Internet Security
• General Purpose CRC
• True Random Number Generator
• 2 x Hardware Cryptographic Acceleration for AES 128/256,
SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC
•Wide selection of MCU peripherals
• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)
• 2×Analog Comparator (ACMP)
• 2×Digital to Analog Converter (VDAC)
• 3×Operational Amplifier (Opamp)
• Digital to Analog Current Converter (IDAC)
• Low-Energy Sensor Interface (LESENSE)
• Multi-channel Capacitive Sense Interface (CSEN)
• Up to 32 pins connected to analog channels (APORT)
shared between analog peripherals
• Up to 32 General Purpose I/O pins with output state reten-
tion and asynchronous interrupts
• 8 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS)
• 2×16-bit Timer/Counter
• 3 or 4 Compare/Capture/PWM channels
• 1×32-bit Timer/Counter
• 3 Compare/Capture/PWM channels
• 32-bit Real Time Counter and Calendar
• 16-bit Low Energy Timer for waveform generation
• 32-bit Ultra Low Energy Timer/Counter for periodic wake-up
from any Energy Mode
• 16-bit Pulse Counter with asynchronous operation
• 2×Watchdog Timer with dedicated RC oscillator
• 3×Universal Synchronous/Asynchronous Receiver/Trans-
mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S)
•Low Energy UART (LEUART™)
•2×I2C interface with SMBus support and address recogni-
tion in EM3 Stop
•Wide Operating Range
• 1.8 V to 3.8 V single power supply
• Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system
• Standard (-40 °C to 85 °C) and Extended (-40 °C to 125 °C)
temperature grades available
•QFN48 7x7 mm Package
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Feature List
silabs.com | Building a more connected world. Rev. 1.0 | 2
2. Ordering Information
Table 2.1. Ordering Information
Ordering Code
Protocol
Stack
Frequency Band
@ Max TX Power
Flash
(kB)
RAM
(kB) GPIO Package
Temp
Range
EFR32FG13P233F512GM48-C Proprietary • 2.4 GHz @ 19 dBm
• Sub-GHz @ 20 dBm
512 64 28 QFN48 -40 to
+85°C
EFR32FG13P232F512GM48-C Proprietary 2.4 GHz @ 19 dBm 512 64 31 QFN48 -40 to
+85°C
EFR32FG13P231F512GM48-C Proprietary Sub-GHz @ 20 dBm 512 64 32 QFN48 -40 to
+85°C
EFR32FG13P231F512IM48-C Proprietary Sub-GHz @ 20 dBm 512 64 32 QFN48 -40 to
+125°C
EFR32 –1 P F G A R
Tape and Reel (Optional)
Revision
Pin Count
Package – M (QFN), L (BGA)
Flash Memory Size in kB
Memory Type (Flash)
Feature Set Code – r2r1r0
r2: Reserved
r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)
r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)
G
X132 512 M 48
Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)
Performance Grade – P (Performance), B (Basic), V (Value)
Series
Family – M (Mighty), B (Blue), F (Flex)
Wireless Gecko 32-bit
Gecko
3
Device Configuration
Figure 2.1. Ordering Code Key
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Ordering Information
silabs.com | Building a more connected world. Rev. 1.0 | 3
Table of Contents
1. Feature List ................................2
2. Ordering Information ............................3
3. System Overview ..............................7
3.1 Introduction...............................7
3.2 Radio.................................7
3.2.1 Antenna Interface ..........................8
3.2.2 Fractional-N Frequency Synthesizer ....................8
3.2.3 Receiver Architecture .........................8
3.2.4 Transmitter Architecture ........................8
3.2.5 Wake on Radio ...........................8
3.2.6 RFSENSE .............................9
3.2.7 Flexible Frame Handling ........................9
3.2.8 Packet and State Trace ........................9
3.2.9 Data Buffering............................9
3.2.10 Radio Controller (RAC) ........................9
3.2.11 Random Number Generator ......................10
3.3 Power ................................11
3.3.1 Energy Management Unit (EMU) .....................11
3.3.2 DC-DC Converter ..........................11
3.3.3 Power Domains ...........................11
3.4 General Purpose Input/Output (GPIO)......................11
3.5 Clocking ................................12
3.5.1 Clock Management Unit (CMU) ......................12
3.5.2 Internal and External Oscillators......................12
3.6 Counters/Timers and PWM .........................12
3.6.1 Timer/Counter (TIMER) ........................12
3.6.2 Wide Timer/Counter (WTIMER) ......................12
3.6.3 Real Time Counter and Calendar (RTCC) ..................12
3.6.4 Low Energy Timer (LETIMER) ......................13
3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER) ................13
3.6.6 Pulse Counter (PCNT) .........................13
3.6.7 Watchdog Timer (WDOG) ........................13
3.7 Communications and Other Digital Peripherals ...................13
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) .........13
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) .........13
3.7.3 Inter-Integrated Circuit Interface (I2C) ....................13
3.7.4 Peripheral Reflex System (PRS) .....................13
3.7.5 Low Energy Sensor Interface (LESENSE) ..................14
3.8 Security Features.............................14
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check) ..............14
3.8.2 Crypto Accelerator (CRYPTO) ......................14
3.8.3 True Random Number Generator (TRNG) ..................14
3.8.4 Security Management Unit (SMU) .....................14
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3.9 Analog ................................14
3.9.1 Analog Port (APORT) .........................14
3.9.2 Analog Comparator (ACMP) .......................14
3.9.3 Analog to Digital Converter (ADC) .....................15
3.9.4 Capacitive Sense (CSEN) ........................15
3.9.5 Digital to Analog Current Converter (IDAC) ..................15
3.9.6 Digital to Analog Converter (VDAC) ....................15
3.9.7 Operational Amplifiers .........................15
3.10 Reset Management Unit (RMU) .......................15
3.11 Core and Memory ............................15
3.11.1 Processor Core ...........................15
3.11.2 Memory System Controller (MSC) ....................16
3.11.3 Linked Direct Memory Access Controller (LDMA) ...............16
3.12 Memory Map ..............................17
3.13 Configuration Summary ..........................18
4. Electrical Specifications ..........................19
4.1 Electrical Characteristics ..........................19
4.1.1 Absolute Maximum Ratings .......................20
4.1.2 Operating Conditions .........................21
4.1.3 Thermal Characteristics ........................23
4.1.4 DC-DC Converter ..........................24
4.1.5 Current Consumption .........................26
4.1.6 Wake Up Times ...........................36
4.1.7 Brown Out Detector (BOD) .......................37
4.1.8 Frequency Synthesizer .........................38
4.1.9 2.4 GHz RF Transceiver Characteristics ...................39
4.1.10 Sub-GHz RF Transceiver Characteristics ..................53
4.1.11 Modem..............................77
4.1.12 Oscillators ............................78
4.1.13 Flash Memory Characteristics ......................82
4.1.14 General-Purpose I/O (GPIO) ......................83
4.1.15 Voltage Monitor (VMON) ........................85
4.1.16 Analog to Digital Converter (ADC) ....................86
4.1.17 Analog Comparator (ACMP) ......................88
4.1.18 Digital to Analog Converter (VDAC) ....................91
4.1.19 Current Digital to Analog Converter (IDAC) .................94
4.1.20 Capacitive Sense (CSEN) .......................96
4.1.21 Operational Amplifier (OPAMP) .....................98
4.1.22 Pulse Counter (PCNT) .......................101
4.1.23 Analog Port (APORT) ........................101
4.1.24 I2C ..............................102
4.1.25 USART SPI ...........................105
4.2 Typical Performance Curves ........................106
4.2.1 Supply Current ..........................107
4.2.2 DC-DC Converter .........................112
4.2.3 2.4 GHz Radio ..........................114
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5. Typical Connection Diagrams ........................116
5.1 Power ...............................116
5.2 RF Matching Networks ..........................118
5.3 Other Connections ...........................119
6. Pin Definitions ..............................120
6.1 QFN48 2.4 GHz and Sub-GHz Device Pinout ..................120
6.2 QFN48 2.4 GHz Device Pinout .......................122
6.3 QFN48 Sub-GHz Device Pinout .......................124
6.4 GPIO Functionality Table .........................126
6.5 Alternate Functionality Overview ......................138
6.6 Analog Port (APORT) Client Maps ......................148
7. QFN48 Package Specifications........................157
7.1 QFN48 Package Dimensions ........................157
7.2 QFN48 PCB Land Pattern .........................159
7.3 QFN48 Package Marking .........................161
8. Revision History .............................162
8.1 Revision 1.0 .............................162
8.2 Revision 0.5 .............................162
8.3 Revision 0.1 .............................162
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3. System Overview
3.1 Introduction
The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. The devices are well suited for
any battery operated application as well as other systems requiring high performance and low energy consumption. This section gives a
short introduction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG13 Reference
Manual.
A block diagram of the EFR32FG13 family is shown in Figure 3.1 Detailed EFR32FG13 Block Diagram on page 7. The diagram
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult
Ordering Information.
Analog Peripherals
Clock Management
HFRCO
IDAC
ARM Cortex-M4 Core
512 KB ISP Flash
Program Memory
64 KB RAM A
H
B
Watchdog
Timer
RESETn
Digital Peripherals
Input Mux
Port
Mapper
Port I/O Configuration
Analog Comparator
12-bit ADC
Temp
Sense
VDD
Internal
Reference
IOVDD
AUXHFRCO
LFXO
ULFRCO
HFXO
Memory Protection Unit
LFRCO
A
P
B
DMA Controller
+
-
APORT
Floating Point Unit
Energy Management
DVDD
VREGVDD
VREGSW
bypass
AVDD
PAVDD
RFVDD
DECOUPLE
IOVDD
Voltage
Monitor
Radio Transceiver
2G4RF_IOP
2G4RF_ION
2.4 GHz RF
PA
I
Q
LNA Frequency
Synthesizer
DEMOD
AGC
IFADC
CRC
BUFC
MOD
FRC
RAC
PGA
SUBGRF_OP
SUBGRF_ON
Sub-GHz RF
I
Q
PA
SUBGRF_IP
SUBGRF_IN LNA
To RF
Frontend
Circuits
BALUN
RFSENSE
VDAC
+
-
Op-Amp
Capacitive
Touch
LESENSE
CRC
CRYPTO
I2C
LEUART
USART
RTC / RTCC
PCNT
CRYOTIMER
TIMER
LETIMER
Port F
Drivers PFn
Port D
Drivers PDn
Port C
Drivers PCn
Port B
Drivers PBn
Port A
Drivers PAn
Mux & FB
HFXTAL_P
HFXTAL_N
LFXTAL_P
LFXTAL_N
Voltage
Regulator
DC-DC
Converter
Debug Signals
(shared w/GPIO)
Brown Out /
Power-On
Reset
Reset
Management
Unit
Serial Wire
and ETM
Debug /
Programming
Figure 3.1. Detailed EFR32FG13 Block Diagram
3.2 Radio
The Flex Gecko family features a radio transceiver supporting proprietary wireless protocols.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.0 | 7
3.2.1 Antenna Interface
The EFR32FG13 family includes devices which support both single-band and dual-band RF communication over separate physical RF
interfaces.
The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The
2G4RF_ION pin should be grounded externally.
The sub-GHz antenna interface consists of a differential transmit interface (pins SUBGRF_OP and SUBGRF_ON) and a differential re-
ceive interface (pinsSUBGRF_IP and SUBGRF_IN).
The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching
Networks section.
3.2.2 Fractional-N Frequency Synthesizer
The EFR32FG13 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is
used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly
generate the modulated RF carrier.
The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with
low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to
optimize system energy consumption.
3.2.3 Receiver Architecture
The EFR32FG13 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion
mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital
converter (IFADC).
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-
ing flexibility with respect to known interferers at the image frequency.
The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-
tivity and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance. The sub-GHz
radio can be calibrated on-demand by the user for the desired frequency band.
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.
The EFR32FG13 features integrated support for antenna diversity to improve link budget for 802.15.4 DSSS-OQPSK PHY configura-
tion in the 2.4GHz band, using complementary control outputs to an external switch. Internal configurable hardware controls automatic
switching between antennae during RF receive detection operations.
3.2.4 Transmitter Architecture
The EFR32FG13 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-
ing.
Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32FG13. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-
tween devices that otherwise lack synchronized RF channel access.
3.2.5 Wake on Radio
The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-
ing a subsystem of the EFR32FG13 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripher-
als.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.0 | 8
3.2.6 RFSENSE
The RFSENSE module generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, providing
true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.
RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con-
sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by
enabling normal RF reception.
Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using
available timer peripherals.
3.2.7 Flexible Frame Handling
EFR32FG13 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.
The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/Demodula-
tor:
• Highly adjustable preamble length
• Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts
• Frame disassembly and address matching (filtering) to accept or reject frames
• Automatic ACK frame assembly and transmission
• Fully flexible CRC generation and verification:
• Multiple CRC values can be embedded in a single frame
• 8, 16, 24 or 32-bit CRC value
• Configurable CRC bit and byte ordering
• Selectable bit-ordering (least significant or most significant bit first)
• Optional data whitening
• Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding
• Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing
• Optional symbol interleaving, typically used in combination with FEC
• Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware
• UART encoding over air, with start and stop bit insertion / removal
• Test mode support, such as modulated or unmodulated carrier output
• Received frame timestamping
3.2.8 Packet and State Trace
The EFR32FG13 Frame Controller has a packet and state trace unit that provides valuable information during the development phase.
It features:
• Non-intrusive trace of transmit data, receive data and state information
• Data observability on a single-pin UART data output, or on a two-pin SPI data output
• Configurable data output bitrate / baudrate
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream
3.2.9 Data Buffering
The EFR32FG13 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.
3.2.10 Radio Controller (RAC)
The Radio Controller controls the top level state of the radio subsystem in the EFR32FG13. It performs the following tasks:
• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry
• Run-time calibration of receiver, transmitter and frequency synthesizer
• Detailed frame transmission timing, including optional LBT or CSMA-CA
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.0 | 9
3.2.11 Random Number Generator
The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.
The data is suitable for use in cryptographic applications.
Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-
ber generator algorithms such as Fortuna.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
silabs.com | Building a more connected world. Rev. 1.0 | 10
3.3 Power
The EFR32FG13 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only
a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator
can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capaci-
tor.
The EFR32FG13 device family includes support for internal supply voltage scaling, as well as two different power domains groups for
peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.
AVDD and VREGVDD need to be 1.8 V or higher for the MCU to operate across all conditions; however the rest of the system will
operate down to 1.62 V, including the digital supply and I/O. This means that the device is fully compatible with 1.8 V components.
Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB
components, supplying up to a total of 200 mA.
3.3.1 Energy Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the DC-DC regulator and the Voltage Monitor (VMON). The VMON is used to monitor multi-
ple supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has
fallen below a chosen threshold.
3.3.2 DC-DC Converter
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation
of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,
short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low
for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance
switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran-
sients.
3.3.3 Power Domains
The EFR32FG13 has two peripheral power domains for operation in EM2 and lower. If all of the peripherals in a peripheral power do-
main are configured as unused, the power domain for that group will be powered off in the low-power mode, reducing the overall cur-
rent consumption of the device.
Table 3.1. Peripheral Power Subdomains
Peripheral Power Domain 1 Peripheral Power Domain 2
ACMP0 ACMP1
PCNT0 CSEN
ADC0 VDAC0
LETIMER0 LEUART0
LESENSE I2C0
APORT I2C1
- IDAC
3.4 General Purpose Input/Output (GPIO)
EFR32FG13 has up to 32 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or in-
put. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO
pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to
several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-
als. The GPIO subsystem supports asynchronous external pin interrupts.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
System Overview
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3.5 Clocking
3.5.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFR32FG13. Individual enabling and disabling of clocks to all periph-
eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility
allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and
oscillators.
3.5.2 Internal and External Oscillators
The EFR32FG13 supports two crystal oscillators and fully integrates four RC oscillators, listed below.
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-
ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can
also be applied to the HFXO input for improved accuracy over temperature.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire Viewer port with a wide frequency range.
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-
tal accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.
3.6 Counters/Timers and PWM
3.6.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.6.2 Wide Timer/Counter (WTIMER)
WTIMER peripherals function just as TIMER peripherals, but are 32 bits wide. They keep track of timing, count events, generate PWM
outputs and trigger timed actions in other peripherals through the PRS system. The core of each WTIMER is a 32-bit counter with up to
4 compare/capture channels. Each channel is configurable in one of three modes. In capture mode, the counter state is stored in a
buffer at a selected input event. In compare mode, the channel output reflects the comparison of the counter to a programmed thresh-
old value. In PWM mode, the WTIMER supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by
the sequence of values written to the compare registers, with optional dead-time insertion available in timer unit WTIMER_0 only.
3.6.3 Real Time Counter and Calendar (RTCC)
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-
tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy
and convenient data storage in all energy modes down to EM4H.
A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for appli-
cation software.
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3.6.4 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-
forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be
configured to start counting on compare matches from the RTCC.
3.6.5 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-
rupt periods, facilitating flexible ultra-low energy operation.
3.6.6 Pulse Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2
Deep Sleep, and EM3 Stop.
3.6.7 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.
3.7 Communications and Other Digital Peripherals
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-
porting:
• ISO7816 SmartCards
• IrDA
•I2S
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
3.7.3 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10
kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The
interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans-
fers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.7.4 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-
erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT)
can be applied by the PRS to the signals. The PRS allows peripheral to act autonomously without waking the MCU core, saving power.
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3.7.5 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface LESENSETM is a highly configurable sensor interface with support for up to 16 individually configura-
ble sensors. By controlling the analog comparators, ADC, and DAC, LESENSE is capable of supporting a wide range of sensors and
measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a
programmable finite state machine which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy
budget.
3.8 Security Features
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check)
The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The sup-
ported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application.
3.8.2 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-
port AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and
SHA-256).
Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO1 block is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on
data buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention.
CRYPTO also provides trigger signals for DMA read and write operations.
3.8.3 True Random Number Generator (TRNG)
The TRNG module is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with
NIST800-22 and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key genera-
tion).
3.8.4 Security Management Unit (SMU)
The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the
Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to
the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and
can optionally generate an interrupt.
3.9 Analog
3.9.1 Analog Port (APORT)
The Analog Port (APORT) is an analog interconnect matrix allowing access to many analog modules on a flexible selection of pins.
Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differentially, buses are
grouped by X/Y pairs.
3.9.2 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
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3.9.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output
sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.
The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of
sources, including pins configurable as either single-ended or differential.
3.9.4 Capacitive Sense (CSEN)
The CSEN module is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a switches
and sliders. The CSEN module uses a charge ramping measurement technique, which provides robust sensing even in adverse condi-
tions including radiated noise and moisture. The module can be configured to take measurements on a single port pin or scan through
multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the combined ca-
pacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an averaging filter,
as well as digital threshold comparators to reduce software overhead.
3.9.5 Digital to Analog Current Converter (IDAC)
The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin
or routed to the selected ADC input pin for capacitive sensing. The full-scale current is programmable between 0.05 µA and 64 µA with
several ranges consisting of various step sizes.
3.9.6 Digital to Analog Converter (VDAC)
The Digital to Analog Converter (VDAC) can convert a digital value to an analog output voltage. The VDAC is a fully differential, 500
ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single-
ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications
such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low
frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any
CPU intervention. The VDAC is available in all energy modes down to and including EM3.
3.9.7 Operational Amplifiers
The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and
are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple
common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to
rail output. They can be used in conjunction with the VDAC module or in stand-alone configurations. The opamps save energy, PCB
space, and cost as compared with standalone opamps because they are integrated on-chip.
3.10 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFR32FG13. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.
3.11 Core and Memory
3.11.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• Up to 512 kB flash program memory
• Up to 64 kB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire debug interface
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3.11.2 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-
ergy modes EM0 Active and EM1 Sleep.
3.11.3 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-
phisticated operations to be implemented.
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3.12 Memory Map
The EFR32FG13 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2. EFR32FG13 Memory Map — Core Peripherals and Code Space
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Figure 3.3. EFR32FG13 Memory Map — Peripherals
3.13 Configuration Summary
The features of the EFR32FG13 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.
Table 3.2. Configuration Summary
Module Configuration Pin Connections
USART0 IrDA SmartCard US0_TX, US0_RX, US0_CLK, US0_CS
USART1 IrDA I2S SmartCard US1_TX, US1_RX, US1_CLK, US1_CS
USART2 IrDA SmartCard US2_TX, US2_RX, US2_CLK, US2_CS
TIMER0 with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 - TIM1_CC[3:0]
WTIMER0 with DTI WTIM0_CC[2:0], WTIM0_CDTI[2:0]
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4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω source or load.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Refer to 4.1.2.1 General Operating Conditions for more details about operational supply and temperature limits.
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4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-
bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Parameter Symbol Test Condition Min Typ Max Unit
Storage temperature range TSTG -50 — 150 °C
Voltage on any supply pin VDDMAX -0.3 — 3.8 V
Voltage ramp rate on any
supply pin
VDDRAMPMAX — — 1 V / µs
DC voltage on any GPIO pin VDIGPIN 5V tolerant GPIO pins1-0.3 — Min of 5.25
and IOVDD
+2
V
Non-5V tolerant GPIO pins -0.3 — IOVDD+0.3 V
Voltage on HFXO pins VHFXOPIN -0.3 — 1.4 V
Input RF level on pins
2G4RF_IOP and
2G4RF_ION
PRFMAX2G4 — — 10 dBm
Voltage differential between
RF pins (2G4RF_IOP -
2G4RF_ION)
VMAXDIFF2G4 -50 — 50 mV
Absolute voltage on RF pins
2G4RF_IOP and
2G4RF_ION
VMAX2G4 -0.3 — 3.3 V
Absolute voltage on Sub-
GHz RF pins
VMAXSUBG Pins SUBGRF_OP and
SUBGRF_ON
-0.3 — 3.3 V
Pins SUBGRF_IP and
SUBGRF_IN,
-0.3 — 0.3 V
Total current into VDD power
lines
IVDDMAX Source — — 200 mA
Total current into VSS
ground lines
IVSSMAX Sink — — 200 mA
Current per I/O pin IIOMAX Sink — — 50 mA
Source — — 50 mA
Current for all I/O pins IIOALLMAX Sink — — 200 mA
Source — — 200 mA
Junction temperature TJ-G grade devices -40 — 105 °C
-I grade devices -40 — 125 °C
Note:
1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.
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4.1.2 Operating Conditions
When assigning supply sources, the following requirements must be observed:
• VREGVDD must be greater than or equal to AVDD, DVDD, RFVDD, PAVDD and all IOVDD supplies.
• VREGVDD = AVDD
• DVDD ≤ AVDD
• IOVDD ≤ AVDD
• RFVDD ≤ AVDD
• PAVDD ≤ AVDD
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4.1.2.1 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Operating ambient tempera-
ture range5
TA-G temperature grade -40 25 85 °C
-I temperature grade -40 25 125 °C
AVDD supply voltage2VAVDD 1.8 3.3 3.8 V
VREGVDD operating supply
voltage2 1
VVREGVDD DCDC in regulation 2.4 3.3 3.8 V
DCDC in bypass, 50mA load 1.8 3.3 3.8 V
DCDC not in use. DVDD external-
ly shorted to VREGVDD
1.8 3.3 3.8 V
VREGVDD current IVREGVDD DCDC in bypass, T ≤ 85 °C — — 200 mA
DCDC in bypass, T > 85 °C — — 100 mA
RFVDD operating supply
voltage
VRFVDD 1.62 — VVREGVDD V
DVDD operating supply volt-
age
VDVDD 1.62 — VVREGVDD V
PAVDD operating supply
voltage
VPAVDD 1.62 — VVREGVDD V
IOVDD operating supply volt-
age
VIOVDD All IOVDD pins41.62 — VVREGVDD V
DECOUPLE output capaci-
tor3
CDECOUPLE 0.75 1.0 2.75 µF
Difference between AVDD
and VREGVDD, ABS(AVDD-
VREGVDD)2
dVDD — — 0.1 V
HFCORECLK frequency fCORE VSCALE2, MODE = WS1 — — 40 MHz
VSCALE0, MODE = WS0 — — 20 MHz
HFCLK frequency fHFCLK VSCALE2 — — 40 MHz
VSCALE0 — — 20 MHz
Note:
1. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for
other loads can be calculated as VDVDD_min+ILOAD * RBYP_max.
2. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.
3. The system designer should consult the characteristic specs of the capacitor used on DECOUPLE to ensure its capacitance val-
ue stays within the specified bounds across temperature and DC bias.
4. When the CSEN peripheral is used with chopping enabled (CSEN_CTRL_CHOPEN = ENABLE), IOVDD must be equal to AVDD.
5. The maximum limit on TA may be lower due to device self-heating, which depends on the power dissipation of the specific appli-
cation. TA (max) = TJ (max) - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal
Characteristics table for TJ and THETAJA.
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4.1.3 Thermal Characteristics
Table 4.3. Thermal Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
Thermal resistance THETAJA QFN48 Package, 2-Layer PCB,
Air velocity = 0 m/s
— 75.7 — °C/W
QFN48 Package, 2-Layer PCB,
Air velocity = 1 m/s
— 61.5 — °C/W
QFN48 Package, 2-Layer PCB,
Air velocity = 2 m/s
— 55.4 — °C/W
QFN48 Package, 4-Layer PCB,
Air velocity = 0 m/s
— 30.2 — °C/W
QFN48 Package, 4-Layer PCB,
Air velocity = 1 m/s
— 26.3 — °C/W
QFN48 Package, 4-Layer PCB,
Air velocity = 2 m/s
— 24.9 — °C/W
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4.1.4 DC-DC Converter
Test conditions: L_DCDC=4.7 µH (Murata LQH3NPN4R7MM0L), C_DCDC=4.7 µF (Samsung CL10B475KQ8NQNC), V_DCDC_I=3.3
V, V_DCDC_O=1.8 V, I_DCDC_LOAD=50 mA, Heavy Drive configuration, F_DCDC_LN=7 MHz, unless otherwise indicated.
Table 4.4. DC-DC Converter
Parameter Symbol Test Condition Min Typ Max Unit
Input voltage range VDCDC_I Bypass mode, IDCDC_LOAD = 50
mA
1.8 — VVREGVDD_
MAX
V
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 100 mA, or
Low power (LP) mode, 1.8 V out-
put, IDCDC_LOAD = 10 mA
2.4 — VVREGVDD_
MAX
V
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 200 mA
2.6 — VVREGVDD_
MAX
V
Output voltage programma-
ble range1
VDCDC_O 1.8 — VVREGVDD V
Regulation DC accuracy ACCDC Low Noise (LN) mode, 1.8 V tar-
get output
1.7 — 1.9 V
Regulation window4WINREG Low Power (LP) mode,
LPCMPBIASEMxx3 = 0, 1.8 V tar-
get output, IDCDC_LOAD ≤ 75 µA
1.63 — 2.2 V
Low Power (LP) mode,
LPCMPBIASEMxx3 = 3, 1.8 V tar-
get output, IDCDC_LOAD ≤ 10 mA
1.63 — 2.1 V
Steady-state output ripple VRRadio disabled — 3 — mVpp
Output voltage under/over-
shoot
VOV CCM Mode (LNFORCECCM3 =
1), Load changes between 0 mA
and 100 mA
— 25 60 mV
DCM Mode (LNFORCECCM3 =
0), Load changes between 0 mA
and 10 mA
— 45 90 mV
Overshoot during LP to LN
CCM/DCM mode transitions com-
pared to DC level in LN mode
— 200 — mV
Undershoot during BYP/LP to LN
CCM (LNFORCECCM3 = 1) mode
transitions compared to DC level
in LN mode
— 40 — mV
Undershoot during BYP/LP to LN
DCM (LNFORCECCM3 = 0) mode
transitions compared to DC level
in LN mode
— 100 — mV
DC line regulation VREG Input changes between
VVREGVDD_MAX and 2.4 V
— 0.1 — %
DC load regulation IREG Load changes between 0 mA and
100 mA in CCM mode
— 0.1 — %
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Parameter Symbol Test Condition Min Typ Max Unit
Max load current ILOAD_MAX Low noise (LN) mode, Heavy
Drive2, T ≤ 85 °C
— — 200 mA
Low noise (LN) mode, Heavy
Drive2, T > 85 °C
— — 100 mA
Low noise (LN) mode, Medium
Drive2
— — 100 mA
Low noise (LN) mode, Light
Drive2
— — 50 mA
Low power (LP) mode,
LPCMPBIASEMxx3 = 0
— — 75 µA
Low power (LP) mode,
LPCMPBIASEMxx3 = 3
— — 10 mA
DCDC nominal output ca-
pacitor5
CDCDC 25% tolerance 1 4.7 4.7 µF
DCDC nominal output induc-
tor
LDCDC 20% tolerance 4.7 4.7 4.7 µH
Resistance in Bypass mode RBYP — 1.2 2.5 Ω
Note:
1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD.
2. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-
um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.
3. LPCMPBIASEMxx refers to either LPCMPBIASEM234H in the EMU_DCDCMISCCTRL register or LPCMPBIASEM01 in the
EMU_DCDCLOEM01CFG register, depending on the energy mode.
4. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits.
5. Output voltage under/over-shoot and regulation are specified with CDCDC 4.7 µF. Different settings for DCDCLNCOMPCTRL
must be used if CDCDC is lower than 4.7 µF. See Application Note AN0948 for details.
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4.1.5 Current Consumption
4.1.5.1 Current Consumption 3.3 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. T = 25 °C. DCDC is off.
Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.
Table 4.5. Current Consumption 3.3 V without DC-DC Converter
Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in EM0
mode with all peripherals dis-
abled
IACTIVE 38.4 MHz crystal, CPU running
while loop from flash1
— 128 — µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
— 97 — µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
— 98 107 µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
— 119 — µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
— 100 109 µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
— 246 430 µA/MHz
Current consumption in EM0
mode with all peripherals dis-
abled and voltage scaling
enabled
IACTIVE_VS 19 MHz HFRCO, CPU running
while loop from flash
— 86 — µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
— 209 — µA/MHz
Current consumption in EM1
mode with all peripherals dis-
abled
IEM1 38.4 MHz crystal1— 76 — µA/MHz
38 MHz HFRCO — 47 51 µA/MHz
26 MHz HFRCO — 49 55 µA/MHz
1 MHz HFRCO — 195 374 µA/MHz
Current consumption in EM1
mode with all peripherals dis-
abled and voltage scaling
enabled
IEM1_VS 19 MHz HFRCO — 43 — µA/MHz
1 MHz HFRCO — 167 — µA/MHz
Current consumption in EM2
mode, with voltage scaling
enabled
IEM2_VS Full 64 kB RAM retention and
RTCC running from LFXO
— 1.9 — µA
Full 64 kB RAM retention and
RTCC running from LFRCO
— 2.2 — µA
1 bank (16 kB) RAM retention and
RTCC running from LFRCO2
— 1.9 3.3 µA
Current consumption in EM3
mode, with voltage scaling
enabled
IEM3_VS Full 64 kB RAM retention and
CRYOTIMER running from ULFR-
CO
— 1.53 3.0 µA
Current consumption in
EM4H mode, with voltage
scaling enabled
IEM4H_VS 128 byte RAM retention, RTCC
running from LFXO
— 0.93 — µA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
— 0.45 — µA
128 byte RAM retention, no RTCC — 0.44 0.9 µA
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Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in
EM4S mode
IEM4S No RAM retention, no RTCC — 0.04 0.085 µA
Note:
1. CMU_HFXOCTRL_LOWPOWER=0.
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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4.1.5.2 Current Consumption 3.3 V using DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC
output. T = 25 °C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process varia-
tion at T = 25 °C.
Table 4.6. Current Consumption 3.3 V using DC-DC Converter
Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in EM0
mode with all peripherals dis-
abled, DCDC in Low Noise
DCM mode2
IACTIVE_DCM 38.4 MHz crystal, CPU running
while loop from flash4
— 87 — µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
— 69 — µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
— 70 — µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
— 82 — µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
— 76 — µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
— 615 — µA/MHz
Current consumption in EM0
mode with all peripherals dis-
abled, DCDC in Low Noise
CCM mode1
IACTIVE_CCM 38.4 MHz crystal, CPU running
while loop from flash4
— 97 — µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
— 80 — µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
— 81 — µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
— 92 — µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
— 94 — µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
— 1145 — µA/MHz
Current consumption in EM0
mode with all peripherals dis-
abled and voltage scaling
enabled, DCDC in Low
Noise CCM mode1
IACTIVE_CCM_VS 19 MHz HFRCO, CPU running
while loop from flash
— 101 — µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
— 1124 — µA/MHz
Current consumption in EM1
mode with all peripherals dis-
abled, DCDC in Low Noise
DCM mode2
IEM1_DCM 38.4 MHz crystal4— 56 — µA/MHz
38 MHz HFRCO — 39 — µA/MHz
26 MHz HFRCO — 46 — µA/MHz
1 MHz HFRCO — 588 — µA/MHz
Current consumption in EM1
mode with all peripherals dis-
abled and voltage scaling
enabled, DCDC in Low
Noise DCM mode2
IEM1_DCM_VS 19 MHz HFRCO — 50 — µA/MHz
1 MHz HFRCO — 572 — µA/MHz
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Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in EM2
mode, with voltage scaling
enabled, DCDC in LP mode3
IEM2_VS Full 64 kB RAM retention and
RTCC running from LFXO
— 1.4 — µA
Full 64 kB RAM retention and
RTCC running from LFRCO
— 1.5 — µA
1 bank RAM retention and RTCC
running from LFRCO5
— 1.3 — µA
Current consumption in EM3
mode, with voltage scaling
enabled
IEM3_VS Full 64 kB RAM retention and
CRYOTIMER running from ULFR-
CO
— 1.14 — µA
Current consumption in
EM4H mode, with voltage
scaling enabled
IEM4H_VS 128 byte RAM retention, RTCC
running from LFXO
— 0.75 — µA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
— 0.44 — µA
128 byte RAM retention, no RTCC — 0.42 — µA
Current consumption in
EM4S mode
IEM4S No RAM retention, no RTCC — 0.07 — µA
Note:
1. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD.
2. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD.
3. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPCMPBIASEM234H=0, LPCLIMILIM-
SEL=1, ANASW=DVDD.
4. CMU_HFXOCTRL_LOWPOWER=0.
5. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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4.1.5.3 Current Consumption 1.8 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.8 V. T = 25 °C. DCDC is off.
Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25 °C.
Table 4.7. Current Consumption 1.8 V without DC-DC Converter
Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in EM0
mode with all peripherals dis-
abled
IACTIVE 38.4 MHz crystal, CPU running
while loop from flash1
— 128 — µA/MHz
38 MHz HFRCO, CPU running
Prime from flash
— 97 — µA/MHz
38 MHz HFRCO, CPU running
while loop from flash
— 98 — µA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
— 119 — µA/MHz
26 MHz HFRCO, CPU running
while loop from flash
— 100 — µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
— 243 — µA/MHz
Current consumption in EM0
mode with all peripherals dis-
abled and voltage scaling
enabled
IACTIVE_VS 19 MHz HFRCO, CPU running
while loop from flash
— 86 — µA/MHz
1 MHz HFRCO, CPU running
while loop from flash
— 206 — µA/MHz
Current consumption in EM1
mode with all peripherals dis-
abled
IEM1 38.4 MHz crystal1— 76 — µA/MHz
38 MHz HFRCO — 47 — µA/MHz
26 MHz HFRCO — 48 — µA/MHz
1 MHz HFRCO — 191 — µA/MHz
Current consumption in EM1
mode with all peripherals dis-
abled and voltage scaling
enabled
IEM1_VS 19 MHz HFRCO — 43 — µA/MHz
1 MHz HFRCO — 163 — µA/MHz
Current consumption in EM2
mode, with voltage scaling
enabled
IEM2_VS Full 64 kB RAM retention and
RTCC running from LFXO
— 1.8 — µA
Full 64 kB RAM retention and
RTCC running from LFRCO
— 2.0 — µA
1 bank (16 kB) RAM retention and
RTCC running from LFRCO2
— 1.6 — µA
Current consumption in EM3
mode, with voltage scaling
enabled
IEM3_VS Full 64 kB RAM retention and
CRYOTIMER running from ULFR-
CO
— 1.43 — µA
Current consumption in
EM4H mode, with voltage
scaling enabled
IEM4H_VS 128 byte RAM retention, RTCC
running from LFXO
— 0.83 — µA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
— 0.37 — µA
128 byte RAM retention, no RTCC — 0.36 — µA
Current consumption in
EM4S mode
IEM4S no RAM retention, no RTCC — 0.05 — µA
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. CMU_HFXOCTRL_LOWPOWER=0.
2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1
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4.1.5.4 Current Consumption Using Radio 3.3 V with DC-DC
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V. T = 25
°C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at T = 25
°C.
Table 4.8. Current Consumption Using Radio 3.3 V with DC-DC
Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in re-
ceive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled), T ≤ 85 °C
IRX_ACTIVE 500 kbit/s, 2GFSK, F = 915 MHz,
Radio clock prescaled by 4
— 9.3 10.2 mA
38.4 kbit/s, 2GFSK, F = 868 MHz,
Radio clock prescaled by 4
— 8.6 10.2 mA
38.4 kbit/s, 2GFSK, F = 490 MHz,
Radio clock prescaled by 4
— 8.6 10.2 mA
50 kbit/s, 2GFSK, F = 433 MHz,
Radio clock prescaled by 4
— 8.6 10.2 mA
38.4 kbit/s, 2GFSK, F = 315 MHz,
Radio clock prescaled by 4
— 8.6 10.2 mA
38.4 kbit/s, 2GFSK, F = 169 MHz,
Radio clock prescaled by 4
— 8.4 10.2 mA
125 kbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
— 9.2 — mA
500 kbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
— 9.3 — mA
1 Mbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
— 9.5 — mA
2 Mbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
— 10.6 — mA
802.15.4 receiving frame, F = 2.4
GHz, Radio clock prescaled by 3
— 10.2 — mA
Current consumption in re-
ceive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled), T > 85 °C
IRX_ACTIVE_HT 500 kbit/s, 2GFSK, F = 915 MHz,
Radio clock prescaled by 4
— — 13 mA
38.4 kbit/s, 2GFSK, F = 868 MHz,
Radio clock prescaled by 4
— — 13 mA
38.4 kbit/s, 2GFSK, F = 490 MHz,
Radio clock prescaled by 4
— — 13 mA
50 kbit/s, 2GFSK, F = 433 MHz,
Radio clock prescaled by 4
— — 13 mA
38.4 kbit/s, 2GFSK, F = 315 MHz,
Radio clock prescaled by 4
— — 13 mA
38.4 kbit/s, 2GFSK, F = 169 MHz,
Radio clock prescaled by 4
— — 13 mA
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Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in re-
ceive mode, listening for
packet (MCU in EM1 @ 38.4
MHz, peripheral clocks disa-
bled), T ≤ 85 °C
IRX_LISTEN 500 kbit/s, 2GFSK, F = 915 MHz,
No radio clock prescaling
— 10.2 11 mA
38.4 kbit/s, 2GFSK, F = 868 MHz,
No radio clock prescaling
— 9.5 11 mA
38.4 kbit/s, 2GFSK, F = 490 MHz,
No radio clock prescaling
— 9.5 11 mA
50 kbit/s, 2GFSK, F = 433 MHz,
No radio clock prescaling
— 9.5 11 mA
38.4 kbit/s, 2GFSK, F = 315 MHz,
No radio clock prescaling
— 9.4 11 mA
38.4 kbit/s, 2GFSK, F = 169 MHz,
No radio clock prescaling
— 9.3 11 mA
125 kbit/s, 2GFSK, F = 2.4 GHz,
No radio clock prescaling
— 10.4 — mA
500 kbit/s, 2GFSK, F = 2.4 GHz,
No radio clock prescaling
— 10.4 — mA
1 Mbit/s, 2GFSK, F = 2.4 GHz, No
radio clock prescaling
— 10.5 — mA
2 Mbit/s, 2GFSK, F = 2.4 GHz, No
radio clock prescaling
— 11.3 — mA
802.15.4, F = 2.4 GHz, No radio
clock prescaling
— 11.6 — mA
Current consumption in re-
ceive mode, listening for
packet (MCU in EM1 @ 38.4
MHz, peripheral clocks disa-
bled), T > 85 °C
IRX_LISTEN_HT 500 kbit/s, 2GFSK, F = 915 MHz,
No radio clock prescaling
— — 14 mA
38.4 kbit/s, 2GFSK, F = 868 MHz,
No radio clock prescaling
— — 14 mA
38.4 kbit/s, 2GFSK, F = 490 MHz,
No radio clock prescaling
— — 14 mA
50 kbit/s, 2GFSK, F = 433 MHz,
No radio clock prescaling
— — 14 mA
38.4 kbit/s, 2GFSK, F = 315 MHz,
No radio clock prescaling
— — 14 mA
38.4 kbit/s, 2GFSK, F = 169 MHz,
No radio clock prescaling
— — 14 mA
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Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled), T ≤ 85 °C
ITX F = 915 MHz, CW, 20 dBm
match, PAVDD connected directly
to external 3.3V supply
— 90.2 134.3 mA
F = 915 MHz, CW, 14 dBm
match, PAVDD connected to
DCDC output
— 36 42.5 mA
F = 868 MHz, CW, 20 dBm
match, PAVDD connected directly
to external 3.3V supply
— 79.7 106.7 mA
F = 868 MHz, CW, 14 dBm
match, PAVDD connected to
DCDC output
— 35.3 41 mA
F = 490 MHz, CW, 20 dBm
match, PAVDD connected directly
to external 3.3V supply
— 93.8 125.4 mA
F = 433 MHz, CW, 10 dBm
match, PAVDD connected to
DCDC output
— 20.3 24 mA
F = 433 MHz, CW, 14 dBm
match, PAVDD connected to
DCDC output
— 34 41.5 mA
F = 315 MHz, CW, 14 dBm
match, PAVDD connected to
DCDC output
— 33.5 42 mA
F = 169 MHz, CW, 20 dBm
match, PAVDD connected directly
to external 3.3V supply
— 88.6 116.7 mA
F = 2.4 GHz, CW, 0 dBm output
power, Radio clock prescaled by 3
— 8.5 — mA
F = 2.4 GHz, CW, 0 dBm output
power, Radio clock prescaled by 1
— 9.5 — mA
F = 2.4 GHz, CW, 3 dBm output
power
— 16.5 — mA
F = 2.4 GHz, CW, 8 dBm output
power
— 26.0 — mA
F = 2.4 GHz, CW, 10.5 dBm out-
put power
— 34.0 — mA
F = 2.4 GHz, CW, 16.5 dBm out-
put power, PAVDD connected di-
rectly to external 3.3V supply
— 86.0 — mA
F = 2.4 GHz, CW, 19.5 dBm out-
put power, PAVDD connected di-
rectly to external 3.3V supply
— 131.0 — mA
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Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled), T > 85 °C
ITX_HT F = 915 MHz, CW, 20 dBm
match, PAVDD connected directly
to external 3.3V supply
— — 134.3 mA
F = 915 MHz, CW, 14 dBm
match, PAVDD connected to
DCDC output
— — 42.5 mA
F = 868 MHz, CW, 20 dBm
match, PAVDD connected directly
to external 3.3V supply
— — 109.8 mA
F = 868 MHz, CW, 14 dBm
match, PAVDD connected to
DCDC output
— — 41.3 mA
F = 490 MHz, CW, 20 dBm
match, PAVDD connected directly
to external 3.3V supply
— — 130.8 mA
F = 433 MHz, CW, 10 dBm
match, PAVDD connected to
DCDC output
— — 24.4 mA
F = 433 MHz, CW, 14 dBm
match, PAVDD connected to
DCDC output
— — 41.5 mA
F = 315 MHz, CW, 14 dBm
match, PAVDD connected to
DCDC output
— — 42 mA
F = 169 MHz, CW, 20 dBm
match, PAVDD connected directly
to external 3.3V supply
— — 122.8 mA
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4.1.6 Wake Up Times
Table 4.9. Wake Up Times
Parameter Symbol Test Condition Min Typ Max Unit
Wakeup time from EM1 tEM1_WU — 3 — AHB
Clocks
Wake up from EM2 tEM2_WU Code execution from flash — 10.9 — µs
Code execution from RAM — 3.8 — µs
Wake up from EM3 tEM3_WU Code execution from flash — 10.9 — µs
Code execution from RAM — 3.8 — µs
Wake up from EM4H1tEM4H_WU Executing from flash — 90 — µs
Wake up from EM4S1tEM4S_WU Executing from flash — 300 — µs
Time from release of reset
source to first instruction ex-
ecution
tRESET Soft Pin Reset released — 51 — µs
Any other reset released — 358 — µs
Power mode scaling time tSCALE VSCALE0 to VSCALE2, HFCLK =
19 MHz4 2
— 31.8 — µs
VSCALE2 to VSCALE0, HFCLK =
19 MHz3
— 4.3 — µs
Note:
1. Time from wakeup request until first instruction is executed. Wakeup results in device reset.
2. VSCALE0 to VSCALE2 voltage change transitions occur at a rate of 10 mV/µs for approximately 20 µs. During this transition,
peak currents will be dependent on the value of the DECOUPLE output capacitor, from 35 mA (with a 1 µF capacitor) to 70 mA
(with a 2.7 µF capacitor).
3. Scaling down from VSCALE2 to VSCALE0 requires approximately 2.8 µs + 29 HFCLKs.
4. Scaling up from VSCALE0 to VSCALE2 requires approximately 30.3 µs + 28 HFCLKs.
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4.1.7 Brown Out Detector (BOD)
Table 4.10. Brown Out Detector (BOD)
Parameter Symbol Test Condition Min Typ Max Unit
DVDD BOD threshold VDVDDBOD DVDD rising — — 1.62 V
DVDD falling (EM0/EM1) 1.35 — — V
DVDD falling (EM2/EM3) 1.3 — — V
DVDD BOD hysteresis VDVDDBOD_HYST — 18 — mV
DVDD BOD response time tDVDDBOD_DELAY Supply drops at 0.1V/µs rate — 2.4 — µs
AVDD BOD threshold VAVDDBOD AVDD rising — — 1.8 V
AVDD falling (EM0/EM1) 1.62 — — V
AVDD falling (EM2/EM3) 1.53 — — V
AVDD BOD hysteresis VAVDDBOD_HYST — 20 — mV
AVDD BOD response time tAVDDBOD_DELAY Supply drops at 0.1V/µs rate — 2.4 — µs
EM4 BOD threshold VEM4DBOD AVDD rising — — 1.7 V
AVDD falling 1.45 — — V
EM4 BOD hysteresis VEM4BOD_HYST — 25 — mV
EM4 BOD response time tEM4BOD_DELAY Supply drops at 0.1V/µs rate — 300 — µs
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4.1.8 Frequency Synthesizer
Table 4.11. Frequency Synthesizer
Parameter Symbol Test Condition Min Typ Max Unit
RF synthesizer frequency
range
fRANGE 2400 - 2483.5 MHz 2400 — 2483.5 MHz
779 - 956 MHz 779 — 956 MHz
584 - 717 MHz 584 — 717 MHz
358 - 574 MHz 358 — 574 MHz
191 - 358 MHz 191 — 358 MHz
110 - 191 MHz 110 — 191 MHz
LO tuning frequency resolu-
tion with 38.4 MHz crystal
fRES 2400 - 2483.5 MHz — — 73 Hz
779 - 956 MHz — — 24 Hz
584 - 717 MHz — — 18.3 Hz
358 - 574 MHz — — 12.2 Hz
191 - 358 MHz — — 7.3 Hz
110 - 191 MHz — — 4.6 Hz
Frequency deviation resolu-
tion with 38.4 MHz crystal
dfRES 2400 - 2483.5 MHz — — 73 Hz
779 - 956 MHz — — 24 Hz
584 - 717 MHz — — 18.3 Hz
358 - 574 MHz — — 12.2 Hz
191 - 358 MHz — — 7.3 Hz
110 - 191 MHz — — 4.6 Hz
Maximum frequency devia-
tion with 38.4 MHz crystal
dfMAX 2400 - 2483.5 MHz — — 1677 kHz
779 - 956 MHz — — 559 kHz
584 - 717 MHz — — 419 kHz
358 - 574 MHz — — 280 kHz
191 - 358 MHz — — 167 kHz
110 - 191 MHz — — 105 kHz
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4.1.9 2.4 GHz RF Transceiver Characteristics
4.1.9.1 RF Transmitter General Characteristics for 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.12. RF Transmitter General Characteristics for 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Maximum TX power1POUTMAX 19 dBm-rated part numbers.
PAVDD connected directly to ex-
ternal 3.3V supply
— 19.5 — dBm
Minimum active TX Power POUTMIN CW -30 — dBm
Output power step size POUTSTEP -5 dBm< Output power < 0 dBm — 1 — dB
0 dBm < output power <
POUTMAX
— 0.5 — dB
Output power variation vs
supply at POUTMAX
POUTVAR_V 1.8 V < VVREGVDD < 3.3 V,
PAVDD connected directly to ex-
ternal supply, for output power >
10 dBm.
— 4.5 — dB
1.8 V < VVREGVDD < 3.3 V using
DC-DC converter
— 2.2 — dB
Output power variation vs
temperature at POUTMAX
POUTVAR_T From -40 to +85 °C, PAVDD con-
nected to DC-DC output
— 1.5 — dB
From -40 to +125 °C, PAVDD
connected to DC-DC output
— 2.2 — dB
From -40 to +85 °C, PAVDD con-
nected to external supply
— 1.5 — dB
From -40 to +125 °C, PAVDD
connected to external supply
— 3.4 — dB
Output power variation vs RF
frequency at POUTMAX
POUTVAR_F Over RF tuning frequency range — 0.4 — dB
RF tuning frequency range FRANGE 2400 — 2483.5 MHz
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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4.1.9.2 RF Receiver General Characteristics for 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.13. RF Receiver General Characteristics for 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 2400 — 2483.5 MHz
Receive mode maximum
spurious emission
SPURRX 30 MHz to 1 GHz — -57 — dBm
1 GHz to 12 GHz — -47 — dBm
Max spurious emissions dur-
ing active receive mode, per
FCC Part 15.109(a)
SPURRX_FCC 216 MHz to 960 MHz, Conducted
Measurement
— -55.2 — dBm
Above 960 MHz, Conducted
Measurement
— -47.2 — dBm
Level above which
RFSENSE will trigger1
RFSENSETRIG CW at 2.45 GHz — -24 — dBm
Level below which
RFSENSE will not trigger1
RFSENSETHRES CW at 2.45 GHz — -50 — dBm
1% PER sensitivity SENS2GFSK 2 Mbps 2GFSK signal — -89.6 — dBm
250 kbps 2GFSK signal — -100.7 — dBm
Note:
1. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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4.1.9.3 RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of
85%.
Table 4.14. RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate
Parameter Symbol Test Condition Min Typ Max Unit
Transmit 6dB bandwidth TXBW 10 dBm — 763 — kHz
Power spectral density limit PSDLIMIT Per FCC part 15.247 at 10 dBm — -9.1 — dBm/
3kHz
Per FCC part 15.247 at 20 dBm — -2 — dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
— 10 — dBm
Occupied channel bandwidth
per ETSI EN300.328
OCPETSI328 99% BW at highest and lowest
channels in band, 10 dBm
— 1.1 — MHz
Emissions of harmonics out-
of-band, per FCC part
15.247
SPURHRM_FCC 2nd,3rd, 5, 6, 8, 9,10 harmonics;
continuous transmission of modu-
lated carrier
— -47 — dBm
Spurious emissions out-of-
band, excluding harmonics
captured in SPURHARM,FCC.
Emissions taken at
POUTMAX, PAVDD connec-
ted to external 3.3 V supply
SPUROOB_FCC Per FCC part 15.205/15.209,
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
CW carrier, Restricted Bands1 2
— -47 — dBm
Per FCC part 15.247, Above
2.483 GHz or below 2.4 GHz;
continuous transmission of CW
carrier, Non-Restricted Bands
— -26 — dBc
Spurious emissions out-of-
band; per ETSI 300.328
SPURETSI328 [2400-BW to 2400] MHz, [2483.5
to 2483.5+BW] MHz
— -16 — dBm
[2400-2BW to 2400-BW] MHz,
[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
— -26 — dBm
Spurious emissions per ETSI
EN300.440
SPURETSI440 47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
— -60 — dBm
25-1000 MHz — -42 — dBm
1-12 GHz — -36 — dBm
Note:
1. For 2476 MHz, 1.5 dB of power backoff is used to achieve this value.
2. For 2478 MHz, 4.2 dB of power backoff is used to achieve this value.
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4.1.9.4 RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz.
Table 4.15. RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 1 Mbps Data Rate
Parameter Symbol Test Condition Min Typ Max Unit
Max usable receiver input
level, 0.1% BER
SAT Signal is reference signal1. Packet
length is 20 bytes.
— 10 — dBm
Sensitivity, 0.1% BER SENS Signal is reference signal1. Using
DC-DC converter.
— -94.8 — dBm
Signal to co-channel interfer-
er, 0.1% BER
C/ICC Desired signal 3 dB above refer-
ence sensitivity.
— 7.8 — dB
N+1 adjacent channel selec-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
reference signal at -67 dBm
C/I1+ Interferer is reference signal at +1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -6.6 — dB
N-1 adjacent channel selec-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
reference signal at -67 dBm
C/I1- Interferer is reference signal at -1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -4.8 — dB
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I2Interferer is reference signal at ± 2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -44.5 — dB
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I3Interferer is reference signal at ± 3
MHz offset. Desired frequency
2404 MHz ≤ Fc ≤ 2480 MHz
— -46.4 — dB
Selectivity to image frequen-
cy, 0.1% BER. Desired is ref-
erence signal at -67 dBm
C/IIM Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion
— -37.2 — dB
Selectivity to image frequen-
cy ± 1 MHz, 0.1% BER. De-
sired is reference signal at
-67 dBm
C/IIM+1 Interferer is reference signal at im-
age frequency ± 1 MHz with 1
MHz precision
— -46.5 — dB
Blocking, 0.1% BER, Desired
is reference signal at -67
dBm. Interferer is CW in
OOB range
BLOCKOOB Interferer frequency 30 MHz ≤ f ≤
2000 MHz
— -27 — dBm
Interferer frequency 2003 MHz ≤ f
≤ 2399 MHz
— -32 — dBm
Interferer frequency 2484 MHz ≤ f
≤ 2997 MHz
— -32 — dBm
Interferer frequency 3 GHz ≤ f ≤
12.75 GHz
— -27 — dBm
Note:
1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm.
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4.1.9.5 RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of
85%.
Table 4.16. RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate
Parameter Symbol Test Condition Min Typ Max Unit
Transmit 6dB bandwidth TXBW 10 dBm — 1395 — kHz
Power spectral density limit PSDLIMIT Per FCC part 15.247 at 10 dBm — -12.7 — dBm/
3kHz
Per FCC part 15.247 at 20 dBm — -4.7 — dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
— 10 — dBm
Occupied channel bandwidth
per ETSI EN300.328
OCPETSI328 99% BW at highest and lowest
channels in band, 10 dBm
— 2.1 — MHz
Emissions of harmonics out-
of-band, per FCC part
15.247
SPURHRM_FCC 2nd,3rd, 5, 6, 8, 9,10 harmonics;
continuous transmission of modu-
lated carrier
— -47 — dBm
Spurious emissions out-of-
band, excluding harmonics
captured in SPURHARM,FCC.
Emissions taken at
POUTMAX, PAVDD connec-
ted to external 3.3 V supply
SPUROOB_FCC Per FCC part 15.205/15.209,
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
CW carrier, Restricted Bands1 2 3
4
— -47 — dBm
Per FCC part 15.247, Above
2.483 GHz or below 2.4 GHz;
continuous transmission of CW
carrier, Non-Restricted Bands
— -26 — dBc
Spurious emissions out-of-
band; per ETSI 300.328
SPURETSI328 [2400-BW to 2400] MHz, [2483.5
to 2483.5+BW] MHz
— -16 — dBm
[2400-2BW to 2400-BW] MHz,
[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
— -26 — dBm
Spurious emissions per ETSI
EN300.440
SPURETSI440 47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
— -60 — dBm
25-1000 MHz — -42 — dBm
1-12 GHz — -36 — dBm
Note:
1. For 2472 MHz, 1.3 dB of power backoff is used to achieve this value.
2. For 2474 MHz, 3.8 dB of power backoff is used to achieve this value.
3. For 2476 MHz, 7 dB of power backoff is used to achieve this value.
4. For 2478 MHz, 11.2 dB of power backoff is used to achieve this value.
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4.1.9.6 RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz1.
Table 4.17. RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 2 Mbps Data Rate
Parameter Symbol Test Condition Min Typ Max Unit
Max usable receiver input
level, 0.1% BER
SAT Signal is reference signal2. Packet
length is 20 bytes.
— 10 — dBm
Sensitivity, 0.1% BER SENS Signal is reference signal2. Using
DC-DC converter.
— -91.5 — dBm
Signal to co-channel interfer-
er, 0.1% BER
C/ICC Desired signal 3 dB above refer-
ence sensitivity.
— 7.3 — dB
N+1 adjacent channel selec-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
reference signal at -67 dBm
C/I1+ Interferer is reference signal at +2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -10.5 — dB
N-1 adjacent channel selec-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
reference signal at -67 dBm
C/I1- Interferer is reference signal at -2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -14.3 — dB
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I2Interferer is reference signal at ± 4
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -40.3 — dB
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I3Interferer is reference signal at ± 6
MHz offset. Desired frequency
2404 MHz ≤ Fc ≤ 2480 MHz
— -42.2 — dB
Selectivity to image frequen-
cy, 0.1% BER. Desired is ref-
erence signal at -67 dBm
C/IIM Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion
— -10.5 — dB
Selectivity to image frequen-
cy ± 2 MHz, 0.1% BER. De-
sired is reference signal at
-67 dBm
C/IIM+1 Interferer is reference signal at im-
age frequency ± 2 MHz with 2
MHz precision
— -39 — dB
Blocking, 0.1% BER, Desired
is reference signal at -67
dBm. Interferer is CW in
OOB range
BLOCKOOB Interferer frequency 30 MHz ≤ f ≤
2000 MHz
— -27 — dBm
Interferer frequency 2003 MHz ≤ f
≤ 2399 MHz
— -32 — dBm
Interferer frequency 2484 MHz ≤ f
≤ 2997 MHz
— -32 — dBm
Interferer frequency 3 GHz ≤ f ≤
12.75 GHz
— -27 — dBm
Note:
1. For the BLE 2Mbps in-band blocking performance, there may be up to 5 spurious response channels where the requirement of
30.8% PER is not met and therefore an exception will need to be taken for each of these frequencies to meet the requirements of
the BLE standard.
2. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 2 Mbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm.
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4.1.9.7 RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 500 kbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of
85%.
Table 4.18. RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 500 kbps Data Rate
Parameter Symbol Test Condition Min Typ Max Unit
Transmit 6dB bandwidth TXBW 10 dBm — 761 — kHz
Power spectral density limit PSDLIMIT Per FCC part 15.247 at 10 dBm — -8.9 — dBm/
3kHz
Per FCC part 15.247 at 20 dBm — -1.7 — dBm/
3kHz
Occupied channel bandwidth
per ETSI EN300.328
OCPETSI328 99% BW at highest and lowest
channels in band, 10 dBm
— 1.1 — MHz
Emissions of harmonics out-
of-band, per FCC part
15.247
SPURHRM_FCC 2nd,3rd, 5, 6, 8, 9,10 harmonics;
continuous transmission of modu-
lated carrier
— -47 — dBm
Spurious emissions out-of-
band, excluding harmonics
captured in SPURHARM,FCC.
Emissions taken at
POUTMAX, PAVDD connec-
ted to external 3.3 V supply
SPUROOB_FCC Per FCC part 15.205/15.209,
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
CW carrier, Restricted Bands1 2
— -47 — dBm
Per FCC part 15.247, Above
2.483 GHz or below 2.4 GHz;
continuous transmission of CW
carrier, Non-Restricted Bands
— -26 — dBc
Spurious emissions out-of-
band; per ETSI 300.328
SPURETSI328 [2400-BW to 2400] MHz, [2483.5
to 2483.5+BW] MHz
— -16 — dBm
[2400-2BW to 2400-BW] MHz,
[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
— -26 — dBm
Spurious emissions per ETSI
EN300.440
SPURETSI440 47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
— -60 — dBm
25-1000 MHz — -42 — dBm
1-12 GHz — -36 — dBm
Note:
1. For 2476 MHz, 1.2 dB of power backoff is used to achieve this value.
2. For 2478 MHz, 5.8 dB of power backoff is used to achieve this value.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
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4.1.9.8 RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 500 kbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz.
Table 4.19. RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 500 kbps Data Rate
Parameter Symbol Test Condition Min Typ Max Unit
Max usable receiver input
level, 0.1% BER
SAT Signal is reference signal1. Packet
length is 20 bytes.
— 10 — dBm
Sensitivity, 0.1% BER SENS Signal is reference signal1. Using
DC-DC converter.
— -99 — dBm
N+1 adjacent channel selec-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
reference signal at -67 dBm
C/I1+ Interferer is reference signal at +1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -9 — dB
N-1 adjacent channel selec-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
reference signal at -67 dBm
C/I1- Interferer is reference signal at -1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -9 — dB
Alternate selectivity, 0.1%
BER, with allowable excep-
tions. Desired is reference
signal at -67 dBm
C/I2Interferer is reference signal at ± 2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -50.8 — dB
Selectivity to image frequen-
cy, 0.1% BER. Desired is ref-
erence signal at -67 dBm
C/IIM Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion
— -46.2 — dB
Selectivity to image frequen-
cy ± 1 MHz, 0.1% BER. De-
sired is reference signal at
-67 dBm
C/IIM+1 Interferer is reference signal at im-
age frequency ± 1 MHz with 1
MHz precision
— -56.1 — dB
Note:
1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 500 kbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm.
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4.1.9.9 RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 125 kbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz. Maximum duty cycle of
85%.
Table 4.20. RF Transmitter Characteristics for 2GFSK in the 2.4GHz Band, 125 kbps Data Rate
Parameter Symbol Test Condition Min Typ Max Unit
Transmit 6dB bandwidth TXBW 10 dBm — 756 — kHz
Power spectral density limit PSDLIMIT Per FCC part 15.247 at 10 dBm — -9 — dBm/
3kHz
Per FCC part 15.247 at 20 dBm — -1.7 — dBm/
3kHz
Occupied channel bandwidth
per ETSI EN300.328
OCPETSI328 99% BW at highest and lowest
channels in band, 10 dBm
— 1.1 — MHz
Emissions of harmonics out-
of-band, per FCC part
15.247
SPURHRM_FCC 2nd,3rd, 5, 6, 8, 9,10 harmonics;
continuous transmission of modu-
lated carrier
— -47 — dBm
Spurious emissions out-of-
band, excluding harmonics
captured in SPURHARM,FCC.
Emissions taken at
POUTMAX, PAVDD connec-
ted to external 3.3 V supply
SPUROOB_FCC Per FCC part 15.205/15.209,
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
CW carrier, Restricted Bands1 2
— -47 — dBm
Per FCC part 15.247, Above
2.483 GHz or below 2.4 GHz;
continuous transmission of CW
carrier, Non-Restricted Bands
— -26 — dBc
Spurious emissions out-of-
band; per ETSI 300.328
SPURETSI328 [2400-BW to 2400] MHz, [2483.5
to 2483.5+BW] MHz
— -16 — dBm
[2400-2BW to 2400-BW] MHz,
[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
— -26 — dBm
Spurious emissions per ETSI
EN300.440
SPURETSI440 47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
— -60 — dBm
25-1000 MHz — -42 — dBm
1-12 GHz — -36 — dBm
Note:
1. For 2476 MHz, 1.2 dB of power backoff is used to achieve this value.
2. For 2478 MHz, 5.8 dB of power backoff is used to achieve this value.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
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4.1.9.10 RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 125 kbps Data Rate
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz.
Table 4.21. RF Receiver Characteristics for 2GFSK in the 2.4GHz Band, 125 kbps Data Rate
Parameter Symbol Test Condition Min Typ Max Unit
Max usable receiver input
level, 0.1% BER
SAT Signal is reference signal1. Packet
length is 20 bytes.
— 10 — dBm
Sensitivity, 0.1% BER SENS Signal is reference signal1. Using
DC-DC converter.
— -103.3 — dBm
N+1 adjacent channel selec-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
reference signal at -67 dBm
C/I1+ Interferer is reference signal at +1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -13.6 — dB
N-1 adjacent channel selec-
tivity, 0.1% BER, with allowa-
ble exceptions. Desired is
reference signal at -67 dBm
C/I1- Interferer is reference signal at -1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -13.1 — dB
Selectivity to image frequen-
cy, 0.1% BER. Desired is ref-
erence signal at -67 dBm
C/IIM Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion
— -49.7 — dB
Selectivity to image frequen-
cy ± 1 MHz, 0.1% BER. De-
sired is reference signal at
-67 dBm
C/IIM+1 Interferer is reference signal at im-
age frequency ± 1 MHz with 1
MHz precision
— -59.6 — dB
Note:
1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 125 kbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
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4.1.9.11 RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz. Maximum duty cycle of
66%.
Table 4.22. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Error vector magnitude (off-
set EVM), per
802.15.4-2011, not including
2415 MHz channel
EVM Average across frequency. Signal
is DSSS-OQPSK reference pack-
et1
— 3.8 — % rms
Power spectral density limit PSDLIMIT Relative, at carrier ± 3.5 MHz, out-
put power at POUTMAX
— -26 — dBc/
100kHz
Absolute, at carrier ± 3.5 MHz,
output power at POUTMAX3
— -36 — dBm/
100kHz
Per FCC part 15.247, output pow-
er at POUTMAX
— -4.0 — dBm/
3kHz
ETSI — 12.1 — dBm
Occupied channel bandwidth
per ETSI EN300.328
OCPETSI328 99% BW at highest and lowest
channels in band
— 2.25 — MHz
Spurious emissions of har-
monics in restricted bands
per FCC Part 15.205/15.209,
Emissions taken at
POUTMAX, PAVDD connec-
ted to external 3.3 V supply,
Test Frequency is 2450 MHz
SPURHRM_FCC_
R
Continuous transmission of modu-
lated carrier
— -45.8 — dBm
Spurious emissions of har-
monics in non-restricted
bands per FCC Part
15.247/15.35, Emissions tak-
en at POUTMAX, PAVDD
connected to external 3.3 V
supply, Test Frequency is
2450 MHz
SPURHRM_FCC_
NRR
Continuous transmission of modu-
lated carrier
— -26 — dBc
Spurious emissions out-of-
band (above 2.483 GHz or
below 2.4 GHz) in restricted
bands, per FCC part
15.205/15.209, Emissions
taken at POUTMAX, PAVDD
connected to external 3.3 V
supply, Test Frequency =
2450 MHz
SPUROOB_FCC_
R
Restricted bands 30-88 MHz; con-
tinuous transmission of modulated
carrier
— -61 — dBm
Restricted bands 88-216 MHz;
continuous transmission of modu-
lated carrier
— -58 — dBm
Restricted bands 216-960 MHz;
continuous transmission of modu-
lated carrier
— -55 — dBm
Restricted bands >960 MHz; con-
tinuous transmission of modulated
carrier4 5
— -47 — dBm
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Spurious emissions out-of-
band in non-restricted bands
per FCC Part 15.247, Emis-
sions taken at POUTMAX,
PAVDD connected to exter-
nal 3.3 V supply, Test Fre-
quency = 2450 MHz
SPUROOB_FCC_
NR
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
modulated carrier
— -26 — dBc
Spurious emissions out-of-
band; per ETSI 300.3282
SPURETSI328 [2400-BW to 2400], [2483.5 to
2483.5+BW];
— -16 — dBm
[2400-2BW to 2400-BW],
[2483.5+BW to 2483.5+2BW]; per
ETSI 300.328
— -26 — dBm
Spurious emissions per ETSI
EN300.4402
SPURETSI440 47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
— -60 — dBm
25-1000 MHz, excluding above
frequencies
— -42 — dBm
1G-14G — -36 — dBm
Note:
1. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with
pseudo-random packet data content.
2. Specified at maximum power output level of 10 dBm.
3. For 2415 MHz, 2 dB of power backoff is used to achieve this value.
4. For 2475 MHz, 2 dB of power backoff is used to achieve this value.
5. For 2480 MHz, 13 dB of power backoff is used to achieve this value.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
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4.1.9.12 RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.
Table 4.23. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Max usable receiver input
level, 1% PER
SAT Signal is reference signal3. Packet
length is 20 octets.
— 10 — dBm
Sensitivity, 1% PER SENS Signal is reference signal. Packet
length is 20 octets. Using DC-DC
converter.
— -102.7 — dBm
Signal is reference signal. Packet
length is 20 octets. Without DC-
DC converter.
— -102.7 — dBm
Co-channel interferer rejec-
tion, 1% PER
CCR Desired signal 3 dB above sensi-
tivity limit
— -4.6 — dB
High-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
level4
ACRP1 Interferer is reference signal at +1
channel-spacing.
— 40.7 — dB
Interferer is filtered reference sig-
nal1 at +1 channel-spacing.
— 47 — dB
Interferer is CW at +1 channel-
spacing2.
— 54.3 — dB
Low-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
level4
ACRM1 Interferer is reference signal at -1
channel-spacing.
— 40.8 — dB
Interferer is filtered reference sig-
nal1 at -1 channel-spacing.
— 47.5 — dB
Interferer is CW at -1 channel-
spacing.
— 56.5 — dB
Alternate channel rejection,
1% PER. Desired is refer-
ence signal at 3dB above
reference sensitivity level4
ACR2Interferer is reference signal at ± 2
channel-spacing
— 51.5 — dB
Interferer is filtered reference sig-
nal1 at ± 2 channel-spacing
— 53.7 — dB
Interferer is CW at ± 2 channel-
spacing
— 62.4 — dB
Image rejection , 1% PER,
Desired is reference signal at
3dB above reference sensi-
tivity level4
IR Interferer is CW in image band2— 50.4 — dB
Blocking rejection of all other
channels. 1% PER, Desired
is reference signal at 3dB
above reference sensitivity
level4. Interferer is reference
signal
BLOCK Interferer frequency < Desired fre-
quency - 3 channel-spacing
— 58.5 — dB
Interferer frequency > Desired fre-
quency + 3 channel-spacing
— 56.4 — dB
Blocking rejection of 802.11g
signal centered at +12MHz
or -13MHz
BLOCK80211G Desired is reference signal at 6dB
above reference sensitivity level4
— 50 — dB
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX — — 5 dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — — dBm
RSSI resolution RSSIRES over RSSIMIN to RSSIMAX — 0.25 — dB
RSSI accuracy in the linear
region as defined by
802.15.4-2003
RSSILIN — +/-6 — dB
Note:
1. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stop-
band rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier.
2. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker
tests place the Interferer center frequency at the Desired frequency ± 5 MHz on the channel raster, whereas the image rejection
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.
3. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-
bols/s.
4. Reference sensitivity level is -85 dBm.
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Electrical Specifications
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4.1.10 Sub-GHz RF Transceiver Characteristics
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Electrical Specifications
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4.1.10.1 Sub-GHz RF Transmitter characteristics for 915 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 915 MHz.
Table 4.24. Sub-GHz RF Transmitter characteristics for 915 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 902 — 930 MHz
Maximum TX Power1POUTMAX PAVDD connected directly to ex-
ternal 3.3V supply, 20 dBm output
power setting
18 19.8 23.3 dBm
PAVDD connected to DC-DC out-
put, 14 dBm output power setting
12.6 14.2 16.1 dBm
Minimum active TX Power POUTMIN — -45.5 — dBm
Output power step size POUTSTEP output power > 0 dBm — 0.5 — dB
Output power variation vs
supply at POUTMAX
POUTVAR_V 1.8 V < VVREGVDD < 3.3 V,
PAVDD connected to external
supply, T = 25 °C
— 4.8 — dB
1.8 V < VVREGVDD < 3.3 V,
PAVDD connected to DC-DC out-
put, T = 25 °C
— 1.9 — dB
Output power variation vs
temperature, peak to peak
POUTVAR_T -40 to +85 °C with PAVDD con-
nected to external supply
— 0.6 1.3 dB
-40 to +125 °C with PAVDD con-
nected to external supply
— 0.8 1.6 dB
-40 to +85 °C with PAVDD con-
nected to DC-DC output
— 0.7 1.4 dB
-40 to +125 °C with PAVDD con-
nected to DC-DC output
— 1.0 1.9 dB
Output power variation vs RF
frequency
POUTVAR_F PAVDD connected to external
supply, T = 25 °C
— 0.2 0.6 dB
PAVDD connected to DC-DC out-
put, T = 25 °C
— 0.3 0.6 dB
Spurious emissions of har-
monics at 20 dBm output
power, Conducted measure-
ment, 20dBm match, PAVDD
= 3.3V, Test Frequency =
915 MHz
SPURHARM_FCC
_20
In restricted bands, per FCC Part
15.205 / 15.209
— -45 -42 dBm
In non-restricted bands, per FCC
Part 15.231
— -26 -20 dBc
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Spurious emissions out-of-
band at 20 dBm output pow-
er, Conducted measurement,
20dBm match, PAVDD =
3.3V, Test Frequency = 915
MHz
SPUROOB_FCC_
20
In non-restricted bands, per FCC
Part 15.231
— -26 -20 dBc
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
— -52 -46 dBm
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
— -61 -56 dBm
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
— -58 -52 dBm
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
— -47 -42 dBm
Spurious emissions of har-
monics at 14 dBm output
power, Conducted measure-
ment, 14dBm match, PAVDD
connected to DC-DC output,
Test Frequency = 915 MHz
SPURHARM_FCC
_14
In restricted bands, per FCC Part
15.205 / 15.209
— -47 -42 dBm
In non-restricted bands, per FCC
Part 15.231
— -26 -20 dBc
Spurious emissions out-of-
band at 14 dBm output pow-
er, Conducted measurement,
14dBm match, PAVDD con-
nected to DC-DC output,
Test Frequency = 915 MHz
SPUROOB_FCC_
14
In non-restricted bands, per FCC
Part 15.231
— -26 -20 dBc
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
— -52 -46 dBm
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
— -61 -56 dBm
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
— -58 -52 dBm
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
— -45 -42 dBm
Error vector magnitude (off-
set EVM), per 802.15.4-2011
EVM Signal is DSSS-OQPSK reference
packet. Modulated according to
802.15.4-2011 DSSS-OQPSK in
the 915MHz band, with pseudo-
random packet data content.
PAVDD connected to external
3.3V supply.
— 1.0 2.8 %rms
Power spectral density limit PSD Relative, at carrier ± 1.2 MHz.
Average spectral power shall be
measured using a 100kHz resolu-
tion bandwidth. The reference lev-
el shall be the highest average
spectral power measured within ±
600kHz of the carrier frequency.
PAVDD connected to external
3.3V supply.
— -37.1 -24.8 dBc/
100kHz
Absolute, at carrier ± 1.2 MHz.
Average spectral power shall be
measured using a 100kHz resolu-
tion bandwidth. PAVDD connec-
ted to external 3.3V supply.
— -24.2 -20 dBm/
100kHz
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.0 | 55
4.1.10.2 Sub-GHz RF Receiver Characteristics for 915 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 915 MHz.
Table 4.25. Sub-GHz RF Receiver Characteristics for 915 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Tuning frequency range FRANGE 902 — 930 MHz
Max usable input level, 0.1%
BER
SAT500K Desired is reference 500 kbps
GFSK signal4
— 10 — dBm
Sensitivity SENS Desired is reference 4.8 kbps
OOK signal3, 20% PER, T ≤ 85 °C
— -105.2 -100.7 dBm
Desired is reference 4.8 kbps
OOK signal3, 20% PER, T > 85
°C
— — -99.5 dBm
Desired is reference 600 bps
GFSK signal6, 0.1% BER
— -126.2 — dBm
Desired is reference 50 kbps
GFSK signal5, 0.1% BER, T ≤ 85
°C
— -108.2 -104.2 dBm
Desired is reference 50 kbps
GFSK signal5, 0.1% BER, T > 85
°C
— — -103.1 dBm
Desired is reference 100 kbps
GFSK signal1, 0.1% BER, T ≤ 85
°C
— -105.1 -101.5 dBm
Desired is reference 100 kbps
GFSK signal1, 0.1% BER, T > 85
°C
— — -101.3 dBm
Desired is reference 500 kbps
GFSK signal4, 0.1% BER, T ≤ 85
°C
— -98.2 -93.2 dBm
Desired is reference 500 kbps
GFSK signal4, 0.1% BER, T > 85
°C
— — -93.1 dBm
Desired is reference 400 kbps
GFSK signal2, 1% PER, T ≤ 85 °C
— -95.2 -91 dBm
Desired is reference 400 kbps
GFSK signal2, 1% PER, T > 85 °C
— — -91 dBm
Level above which
RFSENSE will trigger7
RFSENSETRIG CW at 915 MHz — -28.1 — dBm
Level below which
RFSENSE will not trigger7
RFSENSETHRES CW at 915 MHz — -50 — dBm
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
— 48.1 — dB
Desired is 600 bps GFSK signal6
at 3dB above sensitivity level,
0.1% BER
— 71.4 — dB
Desired is 50 kbps GFSK signal5
at 3dB above sensitivity level,
0.1% BER
— 49.8 — dB
Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
— 51.1 — dB
Desired is 500 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
— 48.1 — dB
Desired is 400 kbps 4GFSK sig-
nal2 at 3dB above sensitivity level,
0.1% BER
— 41.4 — dB
Alternate channel selectivity,
Interferer is CW at ± 2 ×
channel-spacing
C/I2Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
— 56.3 — dB
Desired is 600 bps GFSK signal6
at 3dB above sensitivity level,
0.1% BER
— 74.7 — dB
Desired is 50 kbps GFSK signal5
at 3dB above sensitivity level,
0.1% BER
— 55.8 — dB
Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
— 56.4 — dB
Desired is 500 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
— 51.8 — dB
Desired is 400 kbps 4GFSK sig-
nal2 at 3dB above sensitivity level,
0.1% BER
— 46.8 — dB
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Image rejection, Interferer is
CW at image frequency
C/IIMAGE Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
— 48.4 — dB
Desired is 50 kbps GFSK signal5
at 3dB above sensitivity level,
0.1% BER
— 54.9 — dB
Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
— 49.1 — dB
Desired is 500 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
— 47.9 — dB
Desired is 400 kbps 4GFSK sig-
nal2 at 3dB above sensitivity level,
0.1% BER
— 42.8 — dB
Blocking selectivity, 0.1%
BER. Desired is 100 kbps
GFSK signal at 3dB above
sensitivity level
C/IBLOCKER Interferer CW at Desired ± 1 MHz — 58.7 — dB
Interferer CW at Desired ± 2 MHz — 62.5 — dB
Interferer CW at Desired ± 10
MHz
— 76.4 — dB
Intermod selectivity, 0.1%
BER. CW interferers at 400
kHz and 800 kHz offsets
C/IIM Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level
— 45 — dB
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX — — 5 dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — — dBm
RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX range — 0.25 — dBm
Max spurious emissions dur-
ing active receive mode, per
FCC Part 15.109(a)
SPURRX_FCC 216-960 MHz — -55 -49.2 dBm
Above 960 MHz — -47 -41.2 dBm
Max spurious emissions dur-
ing active receive mode,per
ARIB STD-T108 Section 3.3
SPURRX_ARIB Below 710 MHz, RBW=100kHz — -60 -54 dBm
710-900 MHz, RBW=1MHz — -61 -55 dBm
900-915 MHz, RBW=100kHz — -61 -55 dBm
915-930 MHz, RBW=100kHz — -61 -55 dBm
930-1000 MHz, RBW=100kHz — -60 -54 dBm
Above 1000 MHz, RBW=1MHz — -53 -47 dBm
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz, channel spacing = 400
kHz.
2. Definition of reference signal is 400 kbps 4GFSK, BT=0.5, inner deviation = 33.3 kHz, RX channel BW = 368.920 kHz, channel
spacing = 600 kHz.
3. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 306.036 kHz, channel spacing = 500 kHz.
4. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 175 kHz, RX channel BW = 835.076 kHz, channel spacing = 1
MHz.
5. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 99.012 kHz, channel spacing = 200 kHz.
6. Definition of reference signal is 600 bps 2GFSK, BT=0.5, Δf = 0.3 kHz, RX channel BW = 1.2 kHz, channel spacing = 300 kHz.
7. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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Electrical Specifications
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4.1.10.3 Sub-GHz RF Transmitter characteristics for 868 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 868 MHz.
Table 4.26. Sub-GHz RF Transmitter characteristics for 868 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 863 — 876 MHz
Maximum TX Power1POUTMAX PAVDD connected directly to ex-
ternal 3.3V supply, 20 dBm output
power setting
17.1 19.3 22.9 dBm
PAVDD connected to DC-DC out-
put, 14 dBm output power setting
11.4 13.7 16.5 dBm
Minimum active TX Power POUTMIN — -43.5 — dBm
Output power step size POUTSTEP output power > 0 dBm — 0.5 — dB
Output power variation vs
supply at POUTMAX
POUTVAR_V 1.8 V < VVREGVDD < 3.3 V,
PAVDD connected to external
supply, T = 25 °C
— 5 — dB
1.8 V < VVREGVDD < 3.3 V,
PAVDD connected to DC-DC out-
put, T = 25 °C
— 2 — dB
Output power variation vs
temperature, peak to peak
POUTVAR_T -40 to +85 °C with PAVDD con-
nected to external supply
— 0.6 0.9 dB
-40 to +125 °C with PAVDD con-
nected to external supply
— 0.8 1.3 dB
-40 to +85 °C with PAVDD con-
nected to DC-DC output
— 0.5 1.2 dB
-40 to +125 °C with PAVDD con-
nected to DC-DC output
— 0.7 1.5 dB
Output power variation vs RF
frequency
POUTVAR_F PAVDD connected to external
supply, T = 25 °C
— 0.2 0.6 dB
PAVDD connected to DC-DC out-
put, T = 25 °C
— 0.2 0.8 dB
Spurious emissions of har-
monics, Conducted meas-
urement, PAVDD connected
to DC-DC output, Test Fre-
quency = 868 MHz
SPURHARM_ETSI Per ETSI EN 300-220, Section
7.8.2.1
— -35 -30 dBm
Spurious emissions out-of-
band, Conducted measure-
ment, PAVDD connected to
DC-DC output, Test Fre-
quency = 868 MHz
SPUROOB_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
— -59 -54 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
— -42 -36 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
— -36 -30 dBm
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Error vector magnitude (off-
set EVM), per 802.15.4-2015
EVM Signal is DSSS-BPSK reference
packet. Modulated according to
802.15.4-2015 DSSS-BPSK in the
868MHz band, with pseudo-ran-
dom packet data content. PAVDD
connected to external 3.3V supply
— 5.7 — %rms
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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Electrical Specifications
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4.1.10.4 Sub-GHz RF Receiver Characteristics for 868 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 868 MHz.
Table 4.27. Sub-GHz RF Receiver Characteristics for 868 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Tuning frequency range FRANGE 863 — 876 MHz
Max usable input level, 0.1%
BER
SAT2k4 Desired is reference 2.4 kbps
GFSK signal1
— 10 — dBm
Max usable input level, 0.1%
BER
SAT38k4 Desired is reference 38.4 kbps
GFSK signal2
— 10 — dBm
Sensitivity SENS Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER
— -120.6 — dBm
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
— -109.5 -105.4 dBm
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T > 85
°C
— — -105.2 dBm
Desired is reference 500 kbps
GFSK signal3, 0.1% BER
— -96.4 — dBm
Level above which
RFSENSE will trigger4
RFSENSETRIG CW at 868 MHz — -28.1 — dBm
Level below which
RFSENSE will not trigger4
RFSENSETHRES CW at 868 MHz — -50 — dBm
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
44.5 56.9 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
35.4 43 — dB
Alternate channel selectivity,
Interferer is CW at ± 2 ×
channel-spacing
C/I2Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
— 56.8 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
— 48.2 — dB
Image rejection, Interferer is
CW at image frequency
C/IIMAGE Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
— 50.2 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
— 48.7 — dB
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IBLOCKER Interferer CW at Desired ± 1 MHz — 72.1 — dB
Interferer CW at Desired ± 2 MHz — 77.5 — dB
Interferer CW at Desired ± 10
MHz
— 90.4 — dB
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.0 | 62
Parameter Symbol Test Condition Min Typ Max Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX — — 5 dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — — dBm
RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX range — 0.25 — dBm
Max spurious emissions dur-
ing active receive mode
SPURRX 30 MHz to 1 GHz — -63 -57 dBm
1 GHz to 12 GHz — -53 -47 dBm
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.797 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.
4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
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4.1.10.5 Sub-GHz RF Transmitter characteristics for 490 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 490 MHz.
Table 4.28. Sub-GHz RF Transmitter characteristics for 490 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 470 — 510 MHz
Maximum TX Power1POUTMAX PAVDD connected directly to ex-
ternal 3.3V supply
18.1 20.3 23.7 dBm
Minimum active TX Power POUTMIN -44.9 — dBm
Output power step size POUTSTEP output power > 0 dBm — 0.5 — dB
Output power variation vs
supply, peak to peak
POUTVAR_V at 20 dBm;1.8 V < VVREGVDD <
3.3 V, PAVDD connected directly
to external supply, T = 25 °C
— 4.3 — dB
Output power variation vs
temperature, peak to peak
POUTVAR_T -40 to +85 °C at 20 dBm — 0.2 0.9 dB
-40 to +125 °C at 20 dBm — 0.3 1.3 dB
Output power variation vs RF
frequency
POUTVAR_F T = 25 °C — 0.2 0.4 dB
Harmonic emissions, 20
dBm output power setting,
490 MHz
SPURHARM_CN Per China SRW Requirement,
Section 2.1, frequencies below
1GHz
— -40 -36 dBm
Per China SRW Requirement,
Section 2.1, frequencies above
1GHz
— -36 -30 dBm
Spurious emissions, 20 dBm
output power setting, 490
MHz
SPUROOB_CN Per China SRW Requirement,
Section 3 (48.5-72.5MHz,
76-108MHz, 167-223MHz,
470-556MHz, and 606-798MHz)
— -54 — dBm
Per China SRW Requirement,
Section 2.1 (other frequencies be-
low 1GHz)
— -42 — dBm
Per China SRW Requirement,
Section 2.1 (frequencies above
1GHz)
— -36 — dBm
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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Electrical Specifications
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4.1.10.6 Sub-GHz RF Receiver Characteristics for 490 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 490 MHz.
Table 4.29. Sub-GHz RF Receiver Characteristics for 490 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Tuning frequency range FRANGE 470 — 510 dBm
Max usable input level, 0.1%
BER
SAT2k4 Desired is reference 2.4 kbps
GFSK signal3
— 10 — dBm
Max usable input level, 0.1%
BER
SAT38k4 Desired is reference 38.4 kbps
GFSK signal4
— 10 — dBm
Sensitivity SENS Desired is reference 2.4 kbps
GFSK signal3, 0.1% BER
— -122.2 — dBm
Desired is reference 38.4 kbps
GFSK signal4, 0.1% BER, T ≤ 85
°C
— -111.4 -108.9 dBm
Desired is reference 38.4 kbps
GFSK signal4, 0.1% BER, T > 85
°C
— — -107.9 dBm
Desired is reference 10 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
— -116.8 -113.9 dBm
Desired is reference 10 kbps
GFSK signal2, 0.1% BER, T > 85
°C
— — -113.2 dBm
Desired is reference 100 kbps
GFSK signal1, 0.1% BER, T ≤ 85
°C
— -107.3 -104.7 dBm
Desired is reference 100 kbps
GFSK signal1, 0.1% BER, T > 85
°C
— — -104 dBm
Level above which
RFSENSE will trigger5
RFSENSETRIG Desired is reference 100 kbps
GFSK signal1, 0.1% BER
— -28.1 — dBm
Level below which
RFSENSE will not trigger5
RFSENSETHRES CW at 490 MHz — -50 — dBm
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1Desired is 2.4 kbps GFSK signal3
at 3dB above sensitivity level,
0.1% BER
48 60.3 — dB
Desired is 38.4kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
38.3 45.6 — dB
Alternate channel selectivity,
Interferer is CW at ± 2 ×
channel-spacing
C/I2Desired is 2.4kbps GFSK signal3
at 3dB above sensitivity level,
0.1% BER
— 60.4 — dB
Desired is 38.4kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
— 52.6 — dB
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Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Image rejection, Interferer is
CW at image frequency
C/IIMAGE Desired is 2.4kbps GFSK signal3
at 3dB above sensitivity level,
0.1% BER
— 56.5 — dB
Desired is 38.4kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
— 54.1 — dB
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal3 at 3 dB above
sensitivity level
C/IBLOCKER Interferer CW at Desired ± 1 MHz — 73.9 — dB
Interferer CW at Desired ± 2 MHz — 75.4 — dB
Interferer CW at Desired ± 10
MHz
— 90.2 — dB
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX — — 5 dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — — dBm
RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX range — 0.25 — dBm
Max spurious emissions dur-
ing active receive mode
SPURRX 30 MHz to 1 GHz — -53 -47 dBm
1 GHz to 12 GHz — -53 -47 dBm
Note:
1. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz.
2. Definition of reference signal is 10 kbps 2GFSK, BT=0.5, Δf = 5 kHz, RX channel BW = 20.038 kHz.
3. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
4. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
5. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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Electrical Specifications
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4.1.10.7 Sub-GHz RF Transmitter characteristics for 433 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 433 MHz.
Table 4.30. Sub-GHz RF Transmitter characteristics for 433 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 426 — 445 MHz
Maximum TX Power1POUTMAX PAVDD connected to DCDC out-
put, 14dBm output power
12.5 15.1 17.4 dBm
PAVDD connected to DCDC out-
put, 10dBm output power
8.3 10.6 13.3 dBm
Minimum active TX Power POUTMIN — -42 — dBm
Output power step size POUTSTEP output power > 0 dBm — 0.5 — dB
Output power variation vs
supply, peak to peak, Pout =
10dBm
POUTVAR_V At 10 dBm;1.8 V < VVREGVDD <
3.3 V, PAVDD = DC-DC output, T
= 25 °C
— 1.7 — dB
Output power variation vs
temperature, peak to peak,
Pout= 10dBm
POUTVAR_T -40 to +85C at 10dBm — 0.5 1.2 dB
-40 to +125C at 10dBm — 0.7 1.7 dB
Output power variation vs RF
frequency, Pout = 10dBm
POUTVAR_F T = 25 °C — 0.1 0.2 dB
Spurious emissions of har-
monics FCC, Conducted
measurement, 14dBm
match, PAVDD connected to
DCDC output, Test Frequen-
cy = 434 MHz
SPURHARM_FCC In restricted bands, per FCC Part
15.205 / 15.209
— -47 -42 dBm
In non-restricted bands, per FCC
Part 15.231
— -26 -20 dBc
Spurious emissions out-of-
band FCC, Conducted
measurement, 14dBm
match, PAVDD connected to
DCDC output, Test Frequen-
cy = 434 MHz
SPUROOB_FCC In non-restricted bands, per FCC
Part 15.231
— -26 -20 dBc
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
— -52 -46 dBm
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
— -61 -56 dBm
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
— -58 -52 dBm
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
— -47 -42 dBm
Spurious emissions of har-
monics ETSI, Conducted
measurement, 14dBm
match, PAVDD connected to
DCDC output, Test Frequen-
cy = 434 MHz
SPURHARM_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (frequencies below 1Ghz)
— -42 -36 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1Ghz)
— -36 -30 dBm
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Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Spurious emissions out-of-
band ETSI, Conducted
measurement, 14dBm
match, PAVDD connected to
DCDC output, Test Frequen-
cy = 434 MHz
SPUROOB_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
— -60 -54 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
— -42 -36 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
— -36 -30 dBm
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Electrical Specifications
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4.1.10.8 Sub-GHz RF Receiver Characteristics for 433 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 433 MHz.
Table 4.31. Sub-GHz RF Receiver Characteristics for 433 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Tuning frequency range FRANGE 426 — 445 MHz
Max usable input level, 0.1%
BER
SAT2k4 Desired is reference 2.4 kbps
GFSK signal2
— 10 — dBm
Max usable input level, 0.1%
BER
SAT50k Desired is reference 50 kbps
GFSK signal4
— 10 — dBm
Sensitivity SENS Desired is reference 4.8 kbps
OOK signal3, 20% PER
— -107.4 — dBm
Desired is reference 100 kbps
GFSK signal1, 0.1% BER, T ≤ 85
°C
— -107.3 -105 dBm
Desired is reference 100 kbps
GFSK signal1, 0.1% BER, T > 85
°C
— — -104 dBm
Desired is reference 50 kbps
GFSK signal4, 0.1% BER, T ≤ 85
°C
— -110.3 -107.2 dBm
Desired is reference 50 kbps
GFSK signal4, 0.1% BER, T > 85
°C
— — -106.6 dBm
Desired is reference 2.4 kbps
GFSK signal2, 0.1% BER
— -123.1 — dBm
Desired is reference 9.6 kbps
GFSK signal5, 1% PER, T ≤ 85 °C
— -112.6 -109 dBm
Desired is reference 9.6 kbps
GFSK signal5, 1% PER, T > 85 °C
— — -108 dBm
Level above which
RFSENSE will trigger6
RFSENSETRIG CW at 433 MHz — -28.1 — dBm
Level below which
RFSENSE will not trigger6
RFSENSETHRES CW at 433 MHz — -50 — dBm
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Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
— 51.6 — dB
Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
35 44.1 — dB
Desired is 2.4 kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
47 61.5 — dB
Desired is 50 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
45.6 53.1 — dB
Desired is 9.6 kbps 4GFSK sig-
nal5 at 3dB above sensitivity level,
1% PER
— 35.7 — dB
Alternate channel selectivity,
Interferer is CW at ± 2 ×
channel-spacing
C/I2Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
— 57.8 — dB
Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
— 54.6 — dB
Desired is 2.4 kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
— 62.4 — dB
Desired is 50 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
— 58.1 — dB
Desired is 9.6 kbps 4GFSK sig-
nal5 at 3dB above sensitivity level,
1% PER
— 50.6 — dB
Image rejection, Interferer is
CW at image frequency
C/IIMAGE Desired is 4.8 kbps OOK signal3
at 3dB above sensitivity level,
20% PER
— 46.5 — dB
Desired is 100 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
— 51.7 — dB
Desired is 2.4 kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
— 57.5 — dB
Desired is 50 kbps GFSK signal4
at 3dB above sensitivity level,
0.1% BER
— 54.4 — dB
Desired is 9.6 kbps 4GFSK sig-
nal5 at 3dB above sensitivity level,
1% PER
— 48 — dB
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal2 at 3dB above
sensitivity level
C/IBLOCKER Interferer CW at Desired ± 1 MHz — 75.7 — dB
Interferer CW at Desired ± 2 MHz — 77.2 — dB
Interferer CW at Desired ± 10
MHz
— 92 — dB
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Parameter Symbol Test Condition Min Typ Max Unit
Intermod selectivity, 0.1%
BER. CW interferers at 12.5
kHz and 25 kHz offsets
C/IIM Desired is 2.4 kbps GFSK signal2
at 3dB above sensitivity level
— 58.8 — dB
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX — — 5 dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — — dBm
RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX range — 0.25 — dBm
Max spurious emissions dur-
ing active receive mode, per
FCC Part 15.109(a)
SPURRX_FCC 216-960 MHz — -55 -49 dBm
Above 960 MHz — -47 -41 dBm
Max spurious emissions dur-
ing active receive mode, per
ETSI 300-220 Section 8.6
SPURRX_ETSI Below 1000 MHz — -63 -57 dBm
Above 1000 MHz — -53 -47 dBm
Max spurious emissions dur-
ing active receive mode, per
ARIB STD T67 Section
3.3(5)
SPURRX_ARIB Below 710 MHz, RBW=100kHz — -60 -54 dBm
Note:
1. Definition of reference signal is 100 kbps 2GFSK, BT=0.5, Δf = 50 kHz, RX channel BW = 198.024 kHz, channel spacing = 200
kHz.
2. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
3. Definition of reference signal is 4.8 kbps OOK, RX channel BW = 306.036 kHz, channel spacing = 500 kHz.
4. Definition of reference signal is 50 kbps 2GFSK, BT=0.5, Δf = 25 kHz, RX channel BW = 99.012 kHz, channel spacing = 200 kHz.
5. Definition of reference signal is 9.6 kbps 4GFSK, BT=0.5, inner deviation = 0.8 kHz, RX channel BW = 8.5 kHz, channel spacing
= 12.5 kHz.
6. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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4.1.10.9 Sub-GHz RF Transmitter characteristics for 315 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 315 MHz.
Table 4.32. Sub-GHz RF Transmitter characteristics for 315 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 195 — 358 MHz
Maximum TX Power1POUTMAX PAVDD connected to DC-DC out-
put
13.8 17.2 21.1 dBm
Minimum active TX Power POUTMIN -43.9 — dBm
Output power step size POUTSTEP output power > 0 dBm — 0.5 — dB
Output power variation vs
supply
POUTVAR_V 1.8 V < VVREGVDD < 3.3 V,
PAVDD = DC-DC output, T = 25
°C
— 1.8 — dB
Output power variation vs
temperature
POUTVAR_T -40 to +85C — 0.5 1.2 dB
-40 to +125C — 0.7 1.5 dB
Output power variation vs RF
frequency
POUTVAR_F T = 25 °C — 0.1 0.7 dB
Spurious emissions of har-
monics at 14 dBm output
power, Conducted measure-
ment, 14dBm match, PAVDD
connected to DC-DC output,
Test Frequency = 303 MHz
SPURHARM_FCC In restricted bands, per FCC Part
15.205 / 15.209
— -47 -42 dBm
In non-restricted bands, per FCC
Part 15.231
— -26 -20 dBc
Spurious emissions out-of-
band at 14 dBm output pow-
er, Conducted measurement,
14dBm match, PAVDD con-
nected to DC-DC output,
Test Frequency = 303 MHz
SPUROOB_FCC In non-restricted bands, per FCC
Part 15.231
— -26 -20 dBc
In restricted bands (30-88 MHz),
per FCC Part 15.205 / 15.209
— -52 -46 dBm
In restricted bands (88-216 MHz),
per FCC Part 15.205 / 15.209
— -61 -56 dBm
In restricted bands (216-960
MHz), per FCC Part 15.205 /
15.209
— -58 -52 dBm
In restricted bands (>960 MHz),
per FCC Part 15.205 / 15.209
— -47 -42 dBm
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
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Electrical Specifications
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4.1.10.10 Sub-GHz RF Receiver Characteristics for 315 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 315 MHz.
Table 4.33. Sub-GHz RF Receiver Characteristics for 315 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Tuning frequency range FRANGE 195 — 358 dBm
Max usable input level, 0.1%
BER
SAT2k4 Desired is reference 2.4 kbps
GFSK signal1
— 10 — dBm
Max usable input level, 0.1%
BER
SAT38k4 Desired is reference 38.4 kbps
GFSK signal2
— 10 — dBm
Sensitivity SENS Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER, T ≤ 85
°C
— -123.2 -120.7 dBm
Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER, T > 85
°C
— — -120 dBm
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
— -111.4 -108.6 dBm
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T > 85
°C
— — -107.9 dBm
Desired is reference 500 kbps
GFSK signal3, 0.1% BER, T ≤ 85
°C
— -98.8 -95.5 dBm
Desired is reference 500 kbps
GFSK signal3, 0.1% BER, T > 85
°C
— — -94.5 dBm
Level above which
RFSENSE will trigger4
RFSENSETRIG CW at 315 MHz — -28.1 — dBm
Level below which
RFSENSE will not trigger4
RFSENSETHRES CW at 315 MHz — -50 — dBm
Adjacent channel selectivity,
Interferer is CW at ± 1 ×
channel-spacing
C/I1Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
54.1 63.6 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
— 49.9 — dB
Alternate channel selectivity,
Interferer is CW at ± 2 ×
channel-spacing
C/I2Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
— 64.2 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level2,
0.1% BER
— 56.2 — dB
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Electrical Specifications
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Parameter Symbol Test Condition Min Typ Max Unit
Image rejection, Interferer is
CW at image frequency
C/IIMAGE Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
— 53 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
— 51.4 — dB
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IBLOCKER Interferer CW at Desired ± 1 MHz — 75 — dB
Interferer CW at Desired ± 2 MHz — 76.5 — dB
Interferer CW at Desired ± 10
MHz
72.6 91.9 — dB
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX — — 5 dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — — dBm
RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX range — 0.25 — dBm
Max spurious emissions dur-
ing active receive mode, per
FCC Part 15.109(a)
SPURRX_FCC 216-960 MHz — -63 -57 dBm
Above 960MHz — -53 -47 dBm
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.
4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
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4.1.10.11 Sub-GHz RF Transmitter Characteristics for 169 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 169 MHz.
Table 4.34. Sub-GHz RF Transmitter Characteristics for 169 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 169 — 170 MHz
Maximum TX Power1POUTMAX PAVDD connected to external 3.3
V supply
18.1 19.7 22.4 dBm
Minimum active TX Power POUTMIN -42.6 — dBm
Output power step size POUTSTEP output power > 0 dBm — 0.5 — dB
Output power variation vs
supply, peak to peak
POUTVAR_V 1.8 V < VVREGVDD < 3.3 V,
PAVDD connected to external
supply, T = 25 °C
— 4.8 5.0 dB
Output power variation vs
temperature, peak to peak
POUTVAR_T -40 to +85 °C at 20 dBm — 0.6 1.2 dB
-40 to +125 °C at 20 dBm — 0.8 1.5 dB
Spurious emissions of har-
monics, Conducted meas-
urement, PAVDD = 3.3V,
Test Frequency = 169 MHz
SPURHARM_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
— -42 — dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)2
— -38 — dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)2
— -36 — dBm
Spurious emissions out-of-
band, Conducted measure-
ment, PAVDD = 3.3V, Test
Frequency = 169 MHz
SPUROOB_ETSI Per ETSI EN 300-220, Section
7.8.2.1 (47-74 MHz, 87.5-118
MHz, 174-230 MHz, and 470-862
MHz)
— -42 -36 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (other frequencies below 1
GHz)
— -42 -36 dBm
Per ETSI EN 300-220, Section
7.8.2.1 (frequencies above 1
GHz)
— -36 -30 dBm
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of the Ordering Information Table.
2. Typical value marginally passes specification. Additional margin can be obtained by increasing the order of the harmonic filter.
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4.1.10.12 Sub-GHz RF Receiver Characteristics for 169 MHz Band
Unless otherwise indicated, typical conditions are: T = 25 °C, VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 169 MHz.
Table 4.35. Sub-GHz RF Receiver Characteristics for 169 MHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Tuning frequency range FRANGE 169 — 170 dBm
Max usable input level, 0.1%
BER
SAT2k4 Desired is reference 2.4 kbps
GFSK signal1
— 10 — dBm
Max usable input level, 0.1%
BER
SAT38k4 Desired is reference 38.4 kbps
GFSK signal2
— 10 — dBm
Sensitivity SENS Desired is reference 2.4 kbps
GFSK signal1, 0.1% BER
— -124 — dBm
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T ≤ 85
°C
— -112.2 -108 dBm
Desired is reference 38.4 kbps
GFSK signal2, 0.1% BER, T > 85
°C
— — -107 dBm
Desired is reference 500 kbps
GFSK signal3, 0.1% BER, T ≤ 85
°C
— -99.2 -96 dBm
Desired is reference 500 kbps
GFSK signal3, 0.1% BER, T > 85
°C
— — -95 dBm
Level above which
RFSENSE will trigger4
RFSENSETRIG CW at 169 MHz — -28.1 — dBm
Level below which
RFSENSE will not trigger4
RFSENSETHRES CW at 169 MHz — -50 — dBm
Adjacent channel selectivity,
Interferer is CW at ± 1 x
channel-spacing
C/I1Desired is 2.4 kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
— 64.8 — dB
Desired is 38.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
43.3 51.4 — dB
Alternate channel selectivity,
Interferer is CW at ± 2 x
channel-spacing
C/I2Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
— 67.4 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
— 60.6 — dB
Image rejection, Interferer is
CW at image frequency
C/IIMAGE Desired is 2.4kbps GFSK signal1
at 3dB above sensitivity level,
0.1% BER
— 47.1 — dB
Desired is 38.4kbps GFSK signal2
at 3dB above sensitivity level,
0.1% BER
— 47.1 — dB
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Parameter Symbol Test Condition Min Typ Max Unit
Blocking selectivity, 0.1%
BER. Desired is 2.4 kbps
GFSK signal1 at 3 dB above
sensitivity level
C/IBLOCKER Interferer CW at Desired ± 1 MHz — 73.4 — dB
Interferer CW at Desired ± 2 MHz — 75 — dB
Interferer CW at Desired ± 10
MHz
80 90.1 — dB
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX — — 5 dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN -98 — — dBm
RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX range — 0.25 — dBm
Max spurious emissions dur-
ing active receive mode
SPURRX 30 MHz to 1 GHz — -63 -57 dBm
1 GHz to 12 GHz — -53 -47 dBm
Note:
1. Definition of reference signal is 2.4 kbps 2GFSK, BT=0.5, Δf = 1.2 kHz, RX channel BW = 4.798 kHz, channel spacing = 12.5
kHz.
2. Definition of reference signal is 38.4 kbps 2GFSK, BT=0.5, Δf = 20 kHz, RX channel BW = 74.809 kHz, channel spacing = 100
kHz.
3. Definition of reference signal is 500 kbps 2GFSK, BT=0.5, Δf = 125 kHz, RX channel BW = 753.320 kHz.
4. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
4.1.11 Modem
Table 4.36. Modem
Parameter Symbol Test Condition Min Typ Max Unit
Receive bandwidth BWRX Configurable range with 38.4 MHz
crystal
0.1 — 2530 kHz
IF frequency fIF Configurable range with 38.4 MHz
crystal. Selected steps available.
150 — 1371 kHz
DSSS symbol length SLDSSS Configurable in steps of 1 chip 2 — 32 chips
DSSS bits per symbol BPSDSSS Configurable 1 — 4 bits/
symbol
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4.1.12 Oscillators
4.1.12.1 Low-Frequency Crystal Oscillator (LFXO)
Table 4.37. Low-Frequency Crystal Oscillator (LFXO)
Parameter Symbol Test Condition Min Typ Max Unit
Crystal frequency fLFXO — 32.768 — kHz
Supported crystal equivalent
series resistance (ESR)
ESRLFXO — — 70 kΩ
Supported range of crystal
load capacitance 1
CLFXO_CL 6 — 18 pF
On-chip tuning cap range 2CLFXO_T On each of LFXTAL_N and
LFXTAL_P pins
8 — 40 pF
On-chip tuning cap step size SSLFXO — 0.25 — pF
Current consumption after
startup 3
ILFXO ESR = 70 kOhm, CL = 7 pF,
GAIN4 = 2, AGC4 = 1
— 273 — nA
Start- up time tLFXO ESR = 70 kOhm, CL = 7 pF,
GAIN4 = 2
— 308 — ms
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
4. In CMU_LFXOCTRL register.
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4.1.12.2 High-Frequency Crystal Oscillator (HFXO)
Table 4.38. High-Frequency Crystal Oscillator (HFXO)
Parameter Symbol Test Condition Min Typ Max Unit
Crystal frequency fHFXO 38.4 MHz required for radio trans-
ciever operation
38 38.4 40 MHz
Supported crystal equivalent
series resistance (ESR)
ESRHFXO_38M4 Crystal frequency 38.4 MHz — — 60 Ω
Supported range of crystal
load capacitance 1
CHFXO_CL 6 — 12 pF
On-chip tuning cap range 2CHFXO_T On each of HFXTAL_N and
HFXTAL_P pins
9 20 25 pF
On-chip tuning capacitance
step
SSHFXO — 0.04 — pF
Startup time tHFXO 38.4 MHz, ESR = 50 Ohm, CL =
10 pF
— 300 — µs
Frequency tolerance for the
crystal
FTHFXO 38.4 MHz, ESR = 50 Ohm, CL =
10 pF
-40 — 40 ppm
Note:
1. Total load capacitance as seen by the crystal.
2. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
4.1.12.3 Low-Frequency RC Oscillator (LFRCO)
Table 4.39. Low-Frequency RC Oscillator (LFRCO)
Parameter Symbol Test Condition Min Typ Max Unit
Oscillation frequency fLFRCO ENVREF2 = 1 31.3 32.768 33.6 kHz
ENVREF2 = 1, T > 85 °C 31.6 32.768 36.8 kHz
ENVREF2 = 0 31.3 32.768 33.4 kHz
ENVREF2 = 0, T > 85 °C 30 32.768 33.4 kHz
Startup time tLFRCO — 500 — µs
Current consumption 1ILFRCO ENVREF = 1 in
CMU_LFRCOCTRL
— 342 — nA
ENVREF = 0 in
CMU_LFRCOCTRL
— 494 — nA
Note:
1. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register.
2. In CMU_LFRCOCTRL register.
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4.1.12.4 High-Frequency RC Oscillator (HFRCO)
Table 4.40. High-Frequency RC Oscillator (HFRCO)
Parameter Symbol Test Condition Min Typ Max Unit
Frequency accuracy fHFRCO_ACC At production calibrated frequen-
cies, across supply voltage and
temperature
-2.5 — 2.5 %
Start-up time tHFRCO fHFRCO ≥ 19 MHz — 300 — ns
4 < fHFRCO < 19 MHz — 1 — µs
fHFRCO ≤ 4 MHz — 2.5 — µs
Current consumption on all
supplies
IHFRCO fHFRCO = 38 MHz — 267 299 µA
fHFRCO = 32 MHz — 224 248 µA
fHFRCO = 26 MHz — 189 211 µA
fHFRCO = 19 MHz — 154 172 µA
fHFRCO = 16 MHz — 133 148 µA
fHFRCO = 13 MHz — 118 135 µA
fHFRCO = 7 MHz — 89 100 µA
fHFRCO = 4 MHz — 34 44 µA
fHFRCO = 2 MHz — 29 40 µA
fHFRCO = 1 MHz — 26 36 µA
Coarse trim step size (% of
period)
SSHFRCO_COARS
E
— 0.8 — %
Fine trim step size (% of pe-
riod)
SSHFRCO_FINE — 0.1 — %
Period jitter PJHFRCO — 0.2 — % RMS
Frequency limits fHFRCO_BAND FREQRANGE = 0, FINETUNIN-
GEN = 0
3.47 — 6.15 MHz
FREQRANGE = 3, FINETUNIN-
GEN = 0
6.24 — 11.45 MHz
FREQRANGE = 6, FINETUNIN-
GEN = 0
11.3 — 19.8 MHz
FREQRANGE = 7, FINETUNIN-
GEN = 0
13.45 — 22.8 MHz
FREQRANGE = 8, FINETUNIN-
GEN = 0
16.5 — 29.0 MHz
FREQRANGE = 10, FINETUNIN-
GEN = 0
23.11 — 40.63 MHz
FREQRANGE = 11, FINETUNIN-
GEN = 0
27.27 — 48 MHz
FREQRANGE = 12, FINETUNIN-
GEN = 0
33.33 — 54 MHz
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4.1.12.5 Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Table 4.41. Auxiliary High-Frequency RC Oscillator (AUXHFRCO)
Parameter Symbol Test Condition Min Typ Max Unit
Frequency accuracy fAUXHFRCO_ACC At production calibrated frequen-
cies, across supply voltage and
temperature
-3 — 3 %
Start-up time tAUXHFRCO fAUXHFRCO ≥ 19 MHz — 400 — ns
4 < fAUXHFRCO < 19 MHz — 1.4 — µs
fAUXHFRCO ≤ 4 MHz — 2.5 — µs
Current consumption on all
supplies
IAUXHFRCO fAUXHFRCO = 38 MHz — 187 207 µA
fAUXHFRCO = 32 MHz — 152 168 µA
fAUXHFRCO = 26 MHz — 131 145 µA
fAUXHFRCO = 19 MHz — 106 118 µA
fAUXHFRCO = 16 MHz — 98 110 µA
fAUXHFRCO = 13 MHz — 75 86 µA
fAUXHFRCO = 7 MHz — 52 61 µA
fAUXHFRCO = 4 MHz — 29 37 µA
fAUXHFRCO = 2 MHz — 26 35 µA
fAUXHFRCO = 1 MHz — 25 33 µA
Coarse trim step size (% of
period)
SSAUXHFR-
CO_COARSE
— 0.8 — %
Fine trim step size (% of pe-
riod)
SSAUXHFR-
CO_FINE
— 0.1 — %
Period jitter PJAUXHFRCO — 0.2 — % RMS
4.1.12.6 Ultra-low Frequency RC Oscillator (ULFRCO)
Table 4.42. Ultra-low Frequency RC Oscillator (ULFRCO)
Parameter Symbol Test Condition Min Typ Max Unit
Oscillation frequency fULFRCO 0.95 1 1.07 kHz
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4.1.13 Flash Memory Characteristics5
Table 4.43. Flash Memory Characteristics5
Parameter Symbol Test Condition Min Typ Max Unit
Flash erase cycles before
failure
ECFLASH 10000 — — cycles
Flash data retention RETFLASH T ≤ 85 °C 10 — — years
T ≤ 125 °C 10 — — years
Word (32-bit) programming
time
tW_PROG Burst write, 128 words, average
time per word
20 26.3 30 µs
Single word 62 68.9 80 µs
Page erase time4tPERASE 20 29.5 40 ms
Mass erase time1tMERASE 20 30 40 ms
Device erase time2 3tDERASE T ≤ 85 °C — 56.2 70 ms
T ≤ 125 °C — 56.2 75 ms
Erase current6IERASE Page Erase — — 2.0 mA
Write current6IWRITE — — 3.5 mA
Supply voltage during flash
erase and write
VFLASH 1.62 — 3.6 V
Note:
1. Mass erase is issued by the CPU and erases all flash.
2. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock
Word (ULW).
3. From setting the DEVICEERASE bit in AAP_CMD to 1 until the ERASEBUSY bit in AAP_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
4. From setting the ERASEPAGE bit in MSC_WRITECMD to 1 until the BUSY bit in MSC_STATUS is cleared to 0. Internal setup
and hold times for flash control signals are included.
5. Flash data retention information is published in the Quarterly Quality and Reliability Report.
6. Measured at 25 °C.
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4.1.14 General-Purpose I/O (GPIO)
Table 4.44. General-Purpose I/O (GPIO)
Parameter Symbol Test Condition Min Typ Max Unit
Input low voltage VIL GPIO pins — — IOVDD*0.3 V
Input high voltage VIH GPIO pins IOVDD*0.7 — — V
Output high voltage relative
to IOVDD
VOH Sourcing 3 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH1 = WEAK
IOVDD*0.8 — — V
Sourcing 1.2 mA, IOVDD ≥ 1.62
V,
DRIVESTRENGTH1 = WEAK
IOVDD*0.6 — — V
Sourcing 20 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH1 = STRONG
IOVDD*0.8 — — V
Sourcing 8 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH1 = STRONG
IOVDD*0.6 — — V
Output low voltage relative to
IOVDD
VOL Sinking 3 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH1 = WEAK
— — IOVDD*0.2 V
Sinking 1.2 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH1 = WEAK
— — IOVDD*0.4 V
Sinking 20 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH1 = STRONG
— — IOVDD*0.2 V
Sinking 8 mA, IOVDD ≥ 1.62 V,
DRIVESTRENGTH1 = STRONG
— — IOVDD*0.4 V
Input leakage current IIOLEAK All GPIO except LFXO pins, GPIO
≤ IOVDD, T ≤ 85 °C
— 0.1 30 nA
LFXO Pins, GPIO ≤ IOVDD, T ≤
85 °C
— 0.1 50 nA
All GPIO except LFXO pins, GPIO
≤ IOVDD, T > 85 °C
— — 110 nA
LFXO Pins, GPIO ≤ IOVDD, T >
85 °C
— — 250 nA
Input leakage current on
5VTOL pads above IOVDD
I5VTOLLEAK IOVDD < GPIO ≤ IOVDD + 2 V — 3.3 15 µA
I/O pin pull-up/pull-down re-
sistor
RPUD 30 40 65 kΩ
Pulse width of pulses re-
moved by the glitch suppres-
sion filter
tIOGLITCH 15 25 45 ns
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Parameter Symbol Test Condition Min Typ Max Unit
Output fall time, From 70%
to 30% of VIO
tIOOF CL = 50 pF,
DRIVESTRENGTH1 = STRONG,
SLEWRATE1 = 0x6
— 1.8 — ns
CL = 50 pF,
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
— 4.5 — ns
Output rise time, From 30%
to 70% of VIO
tIOOR CL = 50 pF,
DRIVESTRENGTH1 = STRONG,
SLEWRATE = 0x61
— 2.2 — ns
CL = 50 pF,
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
— 7.4 — ns
Note:
1. In GPIO_Pn_CTRL register.
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4.1.15 Voltage Monitor (VMON)
Table 4.45. Voltage Monitor (VMON)
Parameter Symbol Test Condition Min Typ Max Unit
Supply current (including
I_SENSE)
IVMON In EM0 or EM1, 1 supply moni-
tored, T ≤ 85 °C
— 6.3 8 µA
In EM0 or EM1, 1 supply moni-
tored, T > 85 °C
— — 10 µA
In EM0 or EM1, 4 supplies moni-
tored, T ≤ 85 °C
— 12.5 15 µA
In EM0 or EM1, 4 supplies moni-
tored, T > 85 °C
— — 18 µA
In EM2, EM3 or EM4, 1 supply
monitored and above threshold
— 62 — nA
In EM2, EM3 or EM4, 1 supply
monitored and below threshold
— 62 — nA
In EM2, EM3 or EM4, 4 supplies
monitored and all above threshold
— 99 — nA
In EM2, EM3 or EM4, 4 supplies
monitored and all below threshold
— 99 — nA
Loading of monitored supply ISENSE In EM0 or EM1 — 2 — µA
In EM2, EM3 or EM4 — 2 — nA
Threshold range VVMON_RANGE 1.62 — 3.4 V
Threshold step size NVMON_STESP Coarse — 200 — mV
Fine — 20 — mV
Response time tVMON_RES Supply drops at 1V/µs rate — 460 — ns
Hysteresis VVMON_HYST — 26 — mV
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4.1.16 Analog to Digital Converter (ADC)
Specified at 1 Msps, ADCCLK = 16 MHz, BIASPROG = 0, GPBIASACC = 0, unless otherwise indicated.
Table 4.46. Analog to Digital Converter (ADC)
Parameter Symbol Test Condition Min Typ Max Unit
Resolution VRESOLUTION 6 — 12 Bits
Input voltage range5VADCIN Single ended — — VFS V
Differential -VFS/2 — VFS/2 V
Input range of external refer-
ence voltage, single ended
and differential
VADCREFIN_P 1 — VAVDD V
Power supply rejection2PSRRADC At DC — 80 — dB
Analog input common mode
rejection ratio
CMRRADC At DC — 80 — dB
Current from all supplies, us-
ing internal reference buffer.
Continous operation. WAR-
MUPMODE4 = KEEPADC-
WARM
IADC_CONTI-
NOUS_LP
1 Msps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1 3
— 270 290 µA
250 ksps / 4 MHz ADCCLK, BIA-
SPROG = 6, GPBIASACC = 1 3
— 125 — µA
62.5 ksps / 1 MHz ADCCLK, BIA-
SPROG = 15, GPBIASACC = 1 3
— 80 — µA
Current from all supplies, us-
ing internal reference buffer.
Duty-cycled operation. WAR-
MUPMODE4 = NORMAL
IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1 3
— 45 — µA
5 ksps / 16 MHz ADCCLK BIA-
SPROG = 0, GPBIASACC = 1 3
— 8 — µA
Current from all supplies, us-
ing internal reference buffer.
Duty-cycled operation.
AWARMUPMODE4 = KEEP-
INSTANDBY or KEEPIN-
SLOWACC
IADC_STAND-
BY_LP
125 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1 3
— 105 — µA
35 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 1 3
— 70 — µA
Current from all supplies, us-
ing internal reference buffer.
Continous operation. WAR-
MUPMODE4 = KEEPADC-
WARM
IADC_CONTI-
NOUS_HP
1 Msps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0 3
— 325 — µA
250 ksps / 4 MHz ADCCLK, BIA-
SPROG = 6, GPBIASACC = 0 3
— 175 — µA
62.5 ksps / 1 MHz ADCCLK, BIA-
SPROG = 15, GPBIASACC = 0 3
— 125 — µA
Current from all supplies, us-
ing internal reference buffer.
Duty-cycled operation. WAR-
MUPMODE4 = NORMAL
IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0 3
— 85 — µA
5 ksps / 16 MHz ADCCLK BIA-
SPROG = 0, GPBIASACC = 0 3
— 16 — µA
Current from all supplies, us-
ing internal reference buffer.
Duty-cycled operation.
AWARMUPMODE4 = KEEP-
INSTANDBY or KEEPIN-
SLOWACC
IADC_STAND-
BY_HP
125 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0 3
— 160 — µA
35 ksps / 16 MHz ADCCLK, BIA-
SPROG = 0, GPBIASACC = 0 3
— 125 — µA
Current from HFPERCLK IADC_CLK HFPERCLK = 16 MHz — 140 — µA
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Parameter Symbol Test Condition Min Typ Max Unit
ADC clock frequency fADCCLK — — 16 MHz
Throughput rate fADCRATE — — 1 Msps
Conversion time1tADCCONV 6 bit — 7 — cycles
8 bit — 9 — cycles
12 bit — 13 — cycles
Startup time of reference
generator and ADC core
tADCSTART WARMUPMODE4 = NORMAL — — 5 µs
WARMUPMODE4 = KEEPIN-
STANDBY
— — 2 µs
WARMUPMODE4 = KEEPINSLO-
WACC
— — 1 µs
SNDR at 1Msps and fIN =
10kHz
SNDRADC Internal reference7, differential
measurement
58 67 — dB
External reference6, differential
measurement
— 68 — dB
Spurious-free dynamic range
(SFDR)
SFDRADC 1 MSamples/s, 10 kHz full-scale
sine wave
— 75 — dB
Differential non-linearity
(DNL)
DNLADC 12 bit resolution, No missing co-
des
-1 — 2 LSB
Integral non-linearity (INL),
End point method
INLADC 12 bit resolution -6 — 6 LSB
Offset error VADCOFFSETERR -3 0 3 LSB
Gain error in ADC VADCGAIN Using internal reference — -0.2 3.5 %
Using external reference — -1 — %
Temperature sensor slope VTS_SLOPE — -1.84 — mV/°C
Note:
1. Derived from ADCCLK.
2. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL.
3. In ADCn_BIASPROG register.
4. In ADCn_CNTL register.
5. The absolute voltage allowed at any ADC input is dictated by the power rail supplied to on-chip circuitry, and may be lower than
the effective full scale voltage. All ADC inputs are limited to the ADC supply (AVDD or DVDD depending on
EMU_PWRCTRL_ANASW). Any ADC input routed through the APORT will further be limited by the IOVDD supply to the pin.
6. External reference is 1.25 V applied externally to ADCnEXTREFP, with the selection CONF in the SINGLECTRL_REF or
SCANCTRL_REF register field and VREFP in the SINGLECTRLX_VREFSEL or SCANCTRLX_VREFSEL field. The differential
input range with this configuration is ± 1.25 V.
7. Internal reference option used corresponds to selection 2V5 in the SINGLECTRL_REF or SCANCTRL_REF register field. The
differential input range with this configuration is ± 1.25 V. Typical value is characterized using full-scale sine wave input. Minimum
value is production-tested using sine wave input at 1.5 dB lower than full scale.
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4.1.17 Analog Comparator (ACMP)
Table 4.47. Analog Comparator (ACMP)
Parameter Symbol Test Condition Min Typ Max Unit
Input voltage range VACMPIN ACMPVDD =
ACMPn_CTRL_PWRSEL 1
— — VACMPVDD V
Supply voltage VACMPVDD BIASPROG4 ≤ 0x10 or FULL-
BIAS4 = 0
1.8 — VVREGVDD_
MAX
V
0x10 < BIASPROG4 ≤ 0x20 and
FULLBIAS4 = 1
2.1 — VVREGVDD_
MAX
V
Active current not including
voltage reference2
IACMP BIASPROG4 = 1, FULLBIAS4 = 0 — 50 — nA
BIASPROG4 = 0x10, FULLBIAS4
= 0
— 306 — nA
BIASPROG4 = 0x02, FULLBIAS4
= 1
— 6.1 11 µA
BIASPROG4 = 0x20, FULLBIAS4
= 1
— 74 92 µA
Current consumption of inter-
nal voltage reference2
IACMPREF VLP selected as input using 2.5 V
Reference / 4 (0.625 V)
— 50 — nA
VLP selected as input using VDD — 20 — nA
VBDIV selected as input using
1.25 V reference / 1
— 4.1 — µA
VADIV selected as input using
VDD/1
— 2.4 — µA
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Parameter Symbol Test Condition Min Typ Max Unit
Hysteresis (VCM = 1.25 V,
BIASPROG4 = 0x10, FULL-
BIAS4 = 1)
VACMPHYST HYSTSEL5 = HYST0 -3 0 3 mV
HYSTSEL5 = HYST1 5 18 27 mV
HYSTSEL5 = HYST2 12 33 50 mV
HYSTSEL5 = HYST3 17 46 67 mV
HYSTSEL5 = HYST4 23 57 86 mV
HYSTSEL5 = HYST5 26 68 104 mV
HYSTSEL5 = HYST6 30 79 130 mV
HYSTSEL5 = HYST7 34 90 155 mV
HYSTSEL5 = HYST8 -3 0 3 mV
HYSTSEL5 = HYST9 -27 -18 -5 mV
HYSTSEL5 = HYST10 -50 -33 -12 mV
HYSTSEL5 = HYST11 -67 -45 -17 mV
HYSTSEL5 = HYST12 -86 -57 -23 mV
HYSTSEL5 = HYST13 -104 -67 -26 mV
HYSTSEL5 = HYST14 -130 -78 -30 mV
HYSTSEL5 = HYST15 -155 -88 -34 mV
Comparator delay3tACMPDELAY BIASPROG4 = 1, FULLBIAS4 = 0 — 30 95 µs
BIASPROG4 = 0x10, FULLBIAS4
= 0
— 3.7 10 µs
BIASPROG4 = 0x02, FULLBIAS4
= 1
— 360 1000 ns
BIASPROG4 = 0x20, FULLBIAS4
= 1
— 35 — ns
Offset voltage VACMPOFFSET BIASPROG4 =0x10, FULLBIAS4
= 1
-35 — 35 mV
Reference voltage VACMPREF Internal 1.25 V reference 1 1.25 1.47 V
Internal 2.5 V reference 1.98 2.5 2.8 V
Capacitive sense internal re-
sistance
RCSRES CSRESSEL6 = 0 — infinite — kΩ
CSRESSEL6 = 1 — 15 — kΩ
CSRESSEL6 = 2 — 27 — kΩ
CSRESSEL6 = 3 — 39 — kΩ
CSRESSEL6 = 4 — 51 — kΩ
CSRESSEL6 = 5 — 102 — kΩ
CSRESSEL6 = 6 — 164 — kΩ
CSRESSEL6 = 7 — 239 — kΩ
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD.
2. The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference. IACMPTOTAL = IACMP +
IACMPREF.
3. ± 100 mV differential drive.
4. In ACMPn_CTRL register.
5. In ACMPn_HYSTERESIS register.
6. In ACMPn_INPUTSEL register.
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4.1.18 Digital to Analog Converter (VDAC)
DRIVESTRENGTH = 2 unless otherwise specified. Primary VDAC output.
Table 4.48. Digital to Analog Converter (VDAC)
Parameter Symbol Test Condition Min Typ Max Unit
Output voltage VDACOUT Single-Ended 0 — VVREF V
Differential2-VVREF — VVREF V
Current consumption includ-
ing references (2 channels)1
IDAC 500 ksps, 12-bit, DRIVES-
TRENGTH = 2, REFSEL = 4
— 396 — µA
44.1 ksps, 12-bit, DRIVES-
TRENGTH = 1, REFSEL = 4
— 72 — µA
200 Hz refresh rate, 12-bit Sam-
ple-Off mode in EM2, DRIVES-
TRENGTH = 2, BGRREQTIME =
1, EM2REFENTIME = 9, REFSEL
= 4, SETTLETIME = 0x0A, WAR-
MUPTIME = 0x02
— 1.2 — µA
Current from HFPERCLK4IDAC_CLK — 5.8 — µA/MHz
Sample rate SRDAC — — 500 ksps
DAC clock frequency fDAC — — 1 MHz
Conversion time tDACCONV fDAC = 1MHz 2 — — µs
Settling time tDACSETTLE 50% fs step settling to 5 LSB — 2.5 — µs
Startup time tDACSTARTUP Enable to 90% fs output, settling
to 10 LSB
— — 12 µs
Output impedance ROUT DRIVESTRENGTH = 2, 0.4 V ≤
VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Full supply range
— 2 — Ω
DRIVESTRENGTH = 0 or 1, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -400 µA <
IOUT < 400 µA, Full supply range
— 2 — Ω
DRIVESTRENGTH = 2, 0.1 V ≤
VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Full supply range
— 2 — Ω
DRIVESTRENGTH = 0 or 1, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -100 µA <
IOUT < 100 µA, Full supply range
— 2 — Ω
Power supply rejection ratio6PSRR Vout = 50% fs. DC — 65.5 — dB
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Parameter Symbol Test Condition Min Typ Max Unit
Signal to noise and distortion
ratio (1 kHz sine wave),
Noise band limited to 250
kHz
SNDRDAC 500 ksps, single-ended, internal
1.25V reference
— 60.4 — dB
500 ksps, single-ended, internal
2.5V reference
— 61.6 — dB
500 ksps, single-ended, 3.3V
VDD reference
— 64.0 — dB
500 ksps, differential, internal
1.25V reference
— 63.3 — dB
500 ksps, differential, internal
2.5V reference
— 64.4 — dB
500 ksps, differential, 3.3V VDD
reference
— 65.8 — dB
Signal to noise and distortion
ratio (1 kHz sine wave),
Noise band limited to 22 kHz
SNDRDAC_BAND 500 ksps, single-ended, internal
1.25V reference
— 65.3 — dB
500 ksps, single-ended, internal
2.5V reference
— 66.7 — dB
500 ksps, single-ended, 3.3V
VDD reference
— 70.0 — dB
500 ksps, differential, internal
1.25V reference
— 67.8 — dB
500 ksps, differential, internal
2.5V reference
— 69.0 — dB
500 ksps, differential, 3.3V VDD
reference
— 68.5 — dB
Total harmonic distortion THD — 70.2 — dB
Differential non-linearity3DNLDAC -0.99 — 1 LSB
Intergral non-linearity INLDAC -4 — 4 LSB
Offset error5VOFFSET T = 25 °C -8 — 8 mV
Across operating temperature
range
-25 — 25 mV
Gain error5VGAIN T = 25 °C, Low-noise internal ref-
erence (REFSEL = 1V25LN or
2V5LN)
-1.5 — 1.5 %
T = 25 °C, Internal reference (RE-
FSEL = 1V25 or 2V5)
-5 — 5 %
T = 25 °C, External reference
(REFSEL = VDD or EXT)
-1.5 — 1.5 %
Across operating temperature
range, Low-noise internal refer-
ence (REFSEL = 1V25LN or
2V5LN)
-3.5 — 3.5 %
Across operating temperature
range, Internal reference (RE-
FSEL = 1V25 or 2V5)
-7.5 — 7.5 %
Across operating temperature
range, External reference (RE-
FSEL = VDD or EXT)
-1.5 — 1.5 %
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Parameter Symbol Test Condition Min Typ Max Unit
External load capactiance,
OUTSCALE=0
CLOAD — — 75 pF
Note:
1. Supply current specifications are for VDAC circuitry operating with static output only and do not include current required to drive
the load.
2. In differential mode, the output is defined as the difference between two single-ended outputs. Absolute voltage on each output is
limited to the single-ended range.
3. Entire range is monotonic and has no missing codes.
4. Current from HFPERCLK is dependent on HFPERCLK frequency. This current contributes to the total supply current used when
the clock to the DAC module is enabled in the CMU.
5. Gain is calculated by measuring the slope from 10% to 90% of full scale. Offset is calculated by comparing actual VDAC output at
10% of full scale to ideal VDAC output at 10% of full scale with the measured gain.
6. PSRR calculated as 20 * log10(ΔVDD / ΔVOUT), VDAC output at 90% of full scale
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4.1.19 Current Digital to Analog Converter (IDAC)
Table 4.49. Current Digital to Analog Converter (IDAC)
Parameter Symbol Test Condition Min Typ Max Unit
Number of ranges NIDAC_RANGES — 4 — ranges
Output current IIDAC_OUT RANGSEL1 = RANGE0 0.05 — 1.6 µA
RANGSEL1 = RANGE1 1.6 — 4.7 µA
RANGSEL1 = RANGE2 0.5 — 16 µA
RANGSEL1 = RANGE3 2 — 64 µA
Linear steps within each
range
NIDAC_STEPS — 32 — steps
Step size SSIDAC RANGSEL1 = RANGE0 — 50 — nA
RANGSEL1 = RANGE1 — 100 — nA
RANGSEL1 = RANGE2 — 500 — nA
RANGSEL1 = RANGE3 — 2 — µA
Total accuracy, STEPSEL1 =
0x10
ACCIDAC EM0 or EM1, AVDD=3.3 V, T = 25
°C
-3 — 3 %
EM0 or EM1, Across operating
temperature range
-18 — 22 %
EM2 or EM3, Source mode,
RANGSEL1 = RANGE0,
AVDD=3.3 V, T = 25 °C
— -2 — %
EM2 or EM3, Source mode,
RANGSEL1 = RANGE1,
AVDD=3.3 V, T = 25 °C
— -1.7 — %
EM2 or EM3, Source mode,
RANGSEL1 = RANGE2,
AVDD=3.3 V, T = 25 °C
— -0.8 — %
EM2 or EM3, Source mode,
RANGSEL1 = RANGE3,
AVDD=3.3 V, T = 25 °C
— -0.5 — %
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE0, AVDD=3.3 V, T
= 25 °C
— -0.7 — %
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE1, AVDD=3.3 V, T
= 25 °C
— -0.6 — %
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE2, AVDD=3.3 V, T
= 25 °C
— -0.5 — %
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE3, AVDD=3.3 V, T
= 25 °C
— -0.5 — %
Start up time tIDAC_SU Output within 1% of steady state
value
— 5 — µs
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Parameter Symbol Test Condition Min Typ Max Unit
Settling time, (output settled
within 1% of steady state val-
ue),
tIDAC_SETTLE Range setting is changed — 5 — µs
Step value is changed — 1 — µs
Current consumption2IIDAC EM0 or EM1 Source mode, ex-
cluding output current, Across op-
erating temperature range
— 11 15 µA
EM0 or EM1 Sink mode, exclud-
ing output current, Across operat-
ing temperature range
— 13 18 µA
EM2 or EM3 Source mode, ex-
cluding output current, T = 25 °C
— 0.023 — µA
EM2 or EM3 Sink mode, exclud-
ing output current, T = 25 °C
— 0.041 — µA
EM2 or EM3 Source mode, ex-
cluding output current, T ≥ 85 °C
— 11 — µA
EM2 or EM3 Sink mode, exclud-
ing output current, T ≥ 85 °C
— 13 — µA
Output voltage compliance in
source mode, source current
change relative to current
sourced at 0 V
ICOMP_SRC RANGESEL1=0, output voltage =
min(VIOVDD, VAVDD2-100 mv)
— 0.11 — %
RANGESEL1=1, output voltage =
min(VIOVDD, VAVDD2-100 mV)
— 0.06 — %
RANGESEL1=2, output voltage =
min(VIOVDD, VAVDD2-150 mV)
— 0.04 — %
RANGESEL1=3, output voltage =
min(VIOVDD, VAVDD2-250 mV)
— 0.03 — %
Output voltage compliance in
sink mode, sink current
change relative to current
sunk at IOVDD
ICOMP_SINK RANGESEL1=0, output voltage =
100 mV
— 0.12 — %
RANGESEL1=1, output voltage =
100 mV
— 0.05 — %
RANGESEL1=2, output voltage =
150 mV
— 0.04 — %
RANGESEL1=3, output voltage =
250 mV
— 0.03 — %
Note:
1. In IDAC_CURPROG register.
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and
PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects be-
tween AVDD (0) and DVDD (1).
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4.1.20 Capacitive Sense (CSEN)
Table 4.50. Capacitive Sense (CSEN)
Parameter Symbol Test Condition Min Typ Max Unit
Single conversion time (1x
accumulation)
tCNV 12-bit SAR Conversions — 20.2 — µs
16-bit SAR Conversions — 26.4 — µs
Delta Modulation Conversion (sin-
gle comparison)
— 1.55 — µs
Maximum external capacitive
load
CEXTMAX CS0CG=7 (Gain = 1x), including
routing parasitics
— 68 — pF
CS0CG=0 (Gain = 10x), including
routing parasitics
— 680 — pF
Maximum external series im-
pedance
REXTMAX — 1 — kΩ
Supply current, EM2 bonded
conversions, WARMUP-
MODE=NORMAL, WAR-
MUPCNT=0
ICSEN_BOND 12-bit SAR conversions, 20 ms
conversion rate, CS0CG=7 (Gain
= 1x), 10 channels bonded (total
capacitance of 330 pF)1
— 326 — nA
Delta Modulation conversions, 20
ms conversion rate, CS0CG=7
(Gain = 1x), 10 channels bonded
(total capacitance of 330 pF)1
— 226 — nA
12-bit SAR conversions, 200 ms
conversion rate, CS0CG=7 (Gain
= 1x), 10 channels bonded (total
capacitance of 330 pF)1
— 33 — nA
Delta Modulation conversions,
200 ms conversion rate,
CS0CG=7 (Gain = 1x), 10 chan-
nels bonded (total capacitance of
330 pF)1
— 25 — nA
Supply current, EM2 scan
conversions, WARMUP-
MODE=NORMAL, WAR-
MUPCNT=0
ICSEN_EM2 12-bit SAR conversions, 20 ms
scan rate, CS0CG=0 (Gain =
10x), 8 samples per scan1
— 690 — nA
Delta Modulation conversions, 20
ms scan rate, 8 comparisons per
sample (DMCR = 1, DMR = 2),
CS0CG=0 (Gain = 10x), 8 sam-
ples per scan1
— 515 — nA
12-bit SAR conversions, 200 ms
scan rate, CS0CG=0 (Gain =
10x), 8 samples per scan1
— 79 — nA
Delta Modulation conversions,
200 ms scan rate, 8 comparisons
per sample (DMCR = 1, DMR =
2), CS0CG=0 (Gain = 10x), 8
samples per scan1
— 57 — nA
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Parameter Symbol Test Condition Min Typ Max Unit
Supply current, continuous
conversions, WARMUP-
MODE=KEEPCSENWARM
ICSEN_ACTIVE SAR or Delta Modulation conver-
sions of 33 pF capacitor,
CS0CG=0 (Gain = 10x), always
on
— 90.5 — µA
HFPERCLK supply current ICSEN_HFPERCLK Current contribution from
HFPERCLK when clock to CSEN
block is enabled.
— 2.25 — µA/MHz
Note:
1. Current is specified with a total external capacitance of 33 pF per channel. Average current is dependent on how long the module
is actively sampling channels within the scan period, and scales with the number of samples acquired. Supply current for a specif-
ic application can be estimated by multiplying the current per sample by the total number of samples per period (total_current =
single_sample_current * (number_of_channels * accumulation)).
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4.1.21 Operational Amplifier (OPAMP)
Unless otherwise indicated, specified conditions are: Non-inverting input configuration, VDD = 3.3 V, DRIVESTRENGTH = 2, MAIN-
OUTEN = 1, CLOAD = 75 pF with OUTSCALE = 0, or CLOAD = 37.5 pF with OUTSCALE = 1. Unit gain buffer and 3X-gain connection as
specified in table footnotes8 1.
Table 4.51. Operational Amplifier (OPAMP)
Parameter Symbol Test Condition Min Typ Max Unit
Supply voltage VOPA HCMDIS = 0, Rail-to-rail input
range
2 — 3.8 V
HCMDIS = 1 1.62 — 3.8 V
Input voltage VIN HCMDIS = 0, Rail-to-rail input
range
VVSS — VOPA V
HCMDIS = 1 VVSS — VOPA-1.2 V
Input impedance RIN 100 — — MΩ
Output voltage VOUT VVSS — VOPA V
Load capacitance2CLOAD OUTSCALE = 0 — — 75 pF
OUTSCALE = 1 — — 37.5 pF
Output impedance ROUT DRIVESTRENGTH = 2 or 3, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -8 mA <
IOUT < 8 mA, Buffer connection,
Full supply range
— 0.25 — Ω
DRIVESTRENGTH = 0 or 1, 0.4 V
≤ VOUT ≤ VOPA - 0.4 V, -400 µA <
IOUT < 400 µA, Buffer connection,
Full supply range
— 0.6 — Ω
DRIVESTRENGTH = 2 or 3, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -2 mA <
IOUT < 2 mA, Buffer connection,
Full supply range
— 0.4 — Ω
DRIVESTRENGTH = 0 or 1, 0.1 V
≤ VOUT ≤ VOPA - 0.1 V, -100 µA <
IOUT < 100 µA, Buffer connection,
Full supply range
— 1 — Ω
Internal closed-loop gain GCL Buffer connection 0.99 1 1.01 -
3x Gain connection 2.93 2.99 3.05 -
16x Gain connection 15.07 15.7 16.33 -
Active current4IOPA DRIVESTRENGTH = 3, OUT-
SCALE = 0
— 580 — µA
DRIVESTRENGTH = 2, OUT-
SCALE = 0
— 176 — µA
DRIVESTRENGTH = 1, OUT-
SCALE = 0
— 13 — µA
DRIVESTRENGTH = 0, OUT-
SCALE = 0
— 4.7 — µA
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Parameter Symbol Test Condition Min Typ Max Unit
Open-loop gain GOL DRIVESTRENGTH = 3 — 135 — dB
DRIVESTRENGTH = 2 — 137 — dB
DRIVESTRENGTH = 1 — 121 — dB
DRIVESTRENGTH = 0 — 109 — dB
Loop unit-gain frequency7UGF DRIVESTRENGTH = 3, Buffer
connection
— 3.38 — MHz
DRIVESTRENGTH = 2, Buffer
connection
— 0.9 — MHz
DRIVESTRENGTH = 1, Buffer
connection
— 132 — kHz
DRIVESTRENGTH = 0, Buffer
connection
— 34 — kHz
DRIVESTRENGTH = 3, 3x Gain
connection
— 2.57 — MHz
DRIVESTRENGTH = 2, 3x Gain
connection
— 0.71 — MHz
DRIVESTRENGTH = 1, 3x Gain
connection
— 113 — kHz
DRIVESTRENGTH = 0, 3x Gain
connection
— 28 — kHz
Phase margin PM DRIVESTRENGTH = 3, Buffer
connection
— 67 — °
DRIVESTRENGTH = 2, Buffer
connection
— 69 — °
DRIVESTRENGTH = 1, Buffer
connection
— 63 — °
DRIVESTRENGTH = 0, Buffer
connection
— 68 — °
Output voltage noise NOUT DRIVESTRENGTH = 3, Buffer
connection, 10 Hz - 10 MHz
— 146 — µVrms
DRIVESTRENGTH = 2, Buffer
connection, 10 Hz - 10 MHz
— 163 — µVrms
DRIVESTRENGTH = 1, Buffer
connection, 10 Hz - 1 MHz
— 170 — µVrms
DRIVESTRENGTH = 0, Buffer
connection, 10 Hz - 1 MHz
— 176 — µVrms
DRIVESTRENGTH = 3, 3x Gain
connection, 10 Hz - 10 MHz
— 313 — µVrms
DRIVESTRENGTH = 2, 3x Gain
connection, 10 Hz - 10 MHz
— 271 — µVrms
DRIVESTRENGTH = 1, 3x Gain
connection, 10 Hz - 1 MHz
— 247 — µVrms
DRIVESTRENGTH = 0, 3x Gain
connection, 10 Hz - 1 MHz
— 245 — µVrms
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Parameter Symbol Test Condition Min Typ Max Unit
Slew rate5SR DRIVESTRENGTH = 3,
INCBW=13
— 4.7 — V/µs
DRIVESTRENGTH = 3,
INCBW=0
— 1.5 — V/µs
DRIVESTRENGTH = 2,
INCBW=13
— 1.27 — V/µs
DRIVESTRENGTH = 2,
INCBW=0
— 0.42 — V/µs
DRIVESTRENGTH = 1,
INCBW=13
— 0.17 — V/µs
DRIVESTRENGTH = 1,
INCBW=0
— 0.058 — V/µs
DRIVESTRENGTH = 0,
INCBW=13
— 0.044 — V/µs
DRIVESTRENGTH = 0,
INCBW=0
— 0.015 — V/µs
Startup time6TSTART DRIVESTRENGTH = 2 — — 12 µs
Input offset voltage VOSI DRIVESTRENGTH = 2 or 3, T =
25 °C
-2 — 2 mV
DRIVESTRENGTH = 1 or 0, T =
25 °C
-2 — 2 mV
DRIVESTRENGTH = 2 or 3,
across operating temperature
range
-12 — 12 mV
DRIVESTRENGTH = 1 or 0,
across operating temperature
range
-30 — 30 mV
DC power supply rejection
ratio9
PSRRDC Input referred — 70 — dB
DC common-mode rejection
ratio9
CMRRDC Input referred — 70 — dB
Total harmonic distortion THDOPA DRIVESTRENGTH = 2, 3x Gain
connection, 1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
— 90 — dB
DRIVESTRENGTH = 0, 3x Gain
connection, 0.1 kHz, VOUT = 0.1 V
to VOPA - 0.1 V
— 90 — dB
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. Specified configuration for 3X-Gain configuration is: INCBW = 1, HCMDIS = 1, RESINSEL = VSS, VINPUT = 0.5 V, VOUTPUT = 1.5
V. Nominal voltage gain is 3.
2. If the maximum CLOAD is exceeded, an isolation resistor is required for stability. See AN0038 for more information.
3. When INCBW is set to 1 the OPAMP bandwidth is increased. This is allowed only when the non-inverting close-loop gain is ≥ 3,
or the OPAMP may not be stable.
4. Current into the load resistor is excluded. When the OPAMP is connected with closed-loop gain > 1, there will be extra current to
drive the resistor feedback network. The internal resistor feedback network has total resistance of 143.5 kOhm, which will cause
another ~10 µA current when the OPAMP drives 1.5 V between output and ground.
5. Step between 0.2V and VOPA-0.2V, 10%-90% rising/falling range.
6. From enable to output settled. In sample-and-off mode, RC network after OPAMP will contribute extra delay. Settling error < 1mV.
7. In unit gain connection, UGF is the gain-bandwidth product of the OPAMP. In 3x Gain connection, UGF is the gain-bandwidth
product of the OPAMP and 1/3 attenuation of the feedback network.
8. Specified configuration for Unit gain buffer configuration is: INCBW = 0, HCMDIS = 0, RESINSEL = DISABLE. VINPUT = 0.5 V,
VOUTPUT = 0.5 V.
9. When HCMDIS=1 and input common mode transitions the region from VOPA-1.4V to VOPA-1V, input offset will change. PSRR
and CMRR specifications do not apply to this transition region.
4.1.22 Pulse Counter (PCNT)
Table 4.52. Pulse Counter (PCNT)
Parameter Symbol Test Condition Min Typ Max Unit
Input frequency FIN Asynchronous Single and Quad-
rature Modes
— — 10 MHz
Sampled Modes with Debounce
filter set to 0.
— — 8 kHz
4.1.23 Analog Port (APORT)
Table 4.53. Analog Port (APORT)
Parameter Symbol Test Condition Min Typ Max Unit
Supply current2 1IAPORT Operation in EM0/EM1 — 7 — µA
Operation in EM2/EM3 — 63 — nA
Note:
1. Specified current is for continuous APORT operation. In applications where the APORT is not requested continuously (e.g. peri-
odic ACMP requests from LESENSE in EM2), the average current requirements can be estimated by mutiplying the duty cycle of
the requests by the specified continuous current number.
2. Supply current increase that occurs when an analog peripheral requests access to APORT. This current is not included in repor-
ted module currents. Additional peripherals requesting access to APORT do not incur further current.
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4.1.24 I2C
4.1.24.1 I2C Standard-mode (Sm)1
Table 4.54. I2C Standard-mode (Sm)1
Parameter Symbol Test Condition Min Typ Max Unit
SCL clock frequency2fSCL 0 — 100 kHz
SCL clock low time tLOW 4.7 — — µs
SCL clock high time tHIGH 4 — — µs
SDA set-up time tSU_DAT 250 — — ns
SDA hold time3tHD_DAT 100 — 3450 ns
Repeated START condition
set-up time
tSU_STA 4.7 — — µs
(Repeated) START condition
hold time
tHD_STA 4 — — µs
STOP condition set-up time tSU_STO 4 — — µs
Bus free time between a
STOP and START condition
tBUF 4.7 — — µs
Note:
1. For CLHR set to 0 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD_DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
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4.1.24.2 I2C Fast-mode (Fm)1
Table 4.55. I2C Fast-mode (Fm)1
Parameter Symbol Test Condition Min Typ Max Unit
SCL clock frequency2fSCL 0 — 400 kHz
SCL clock low time tLOW 1.3 — — µs
SCL clock high time tHIGH 0.6 — — µs
SDA set-up time tSU_DAT 100 — — ns
SDA hold time3tHD_DAT 100 — 900 ns
Repeated START condition
set-up time
tSU_STA 0.6 — — µs
(Repeated) START condition
hold time
tHD_STA 0.6 — — µs
STOP condition set-up time tSU_STO 0.6 — — µs
Bus free time between a
STOP and START condition
tBUF 1.3 — — µs
Note:
1. For CLHR set to 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual.
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
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4.1.24.3 I2C Fast-mode Plus (Fm+)1
Table 4.56. I2C Fast-mode Plus (Fm+)1
Parameter Symbol Test Condition Min Typ Max Unit
SCL clock frequency2fSCL 0 — 1000 kHz
SCL clock low time tLOW 0.5 — — µs
SCL clock high time tHIGH 0.26 — — µs
SDA set-up time tSU_DAT 50 — — ns
SDA hold time tHD_DAT 100 — — ns
Repeated START condition
set-up time
tSU_STA 0.26 — — µs
(Repeated) START condition
hold time
tHD_STA 0.26 — — µs
STOP condition set-up time tSU_STO 0.26 — — µs
Bus free time between a
STOP and START condition
tBUF 0.5 — — µs
Note:
1. For CLHR set to 0 or 1 in the I2Cn_CTRL register.
2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual.
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4.1.25 USART SPI
SPI Master Timing
Table 4.57. SPI Master Timing
Parameter Symbol Test Condition Min Typ Max Unit
SCLK period 1 3 2tSCLK 2 *
tHFPERCLK
— — ns
CS to MOSI 1 3tCS_MO -12.5 — 14 ns
SCLK to MOSI 1 3tSCLK_MO -8.5 — 10.5 ns
MISO setup time 1 3tSU_MI IOVDD = 1.62 V 90 — — ns
IOVDD = 3.0 V 42 — — ns
MISO hold time 1 3tH_MI -9 — — ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. tHFPERCLK is one period of the selected HFPERCLK.
3. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
CS
SCLK
CLKPOL = 0
MOSI
MISO
tCS_MO
tH_MI
tSU_MI
tSCKL_MO
tSCLK
SCLK
CLKPOL = 1
Figure 4.1. SPI Master Timing Diagram
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SPI Slave Timing
Table 4.58. SPI Slave Timing
Parameter Symbol Test Condition Min Typ Max Unit
SCLK period 1 3 2tSCLK 6 *
tHFPERCLK
— — ns
SCLK high time1 3 2tSCLK_HI 2.5 *
tHFPERCLK
— — ns
SCLK low time1 3 2tSCLK_LO 2.5 *
tHFPERCLK
— — ns
CS active to MISO 1 3tCS_ACT_MI 4 — 70 ns
CS disable to MISO 1 3tCS_DIS_MI 4 — 50 ns
MOSI setup time 1 3tSU_MO 8 — — ns
MOSI hold time 1 3 2tH_MO 7 — — ns
SCLK to MISO 1 3 2tSCLK_MI 10 + 1.5 *
tHFPERCLK
— 65 + 2.5 *
tHFPERCLK
ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. tHFPERCLK is one period of the selected HFPERCLK.
3. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
CS
SCLK
CLKPOL = 0
MOSI
MISO
tCS_ACT_MI
tSCLK_HI
tSCLK
tSU_MO
tH_MO
tSCLK_MI
tCS_DIS_MI
tSCLK_LO
SCLK
CLKPOL = 1
Figure 4.2. SPI Slave Timing Diagram
4.2 Typical Performance Curves
Typical performance curves indicate typical characterized performance under the stated conditions.
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4.2.1 Supply Current
Figure 4.3. EM0 Active Mode Typical Supply Current vs. Temperature
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Figure 4.4. EM1 Sleep Mode Typical Supply Current vs. Temperature
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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Figure 4.5. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Temperature
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Figure 4.6. EM0 and EM1 Mode Typical Supply Current vs. Supply
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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Figure 4.7. EM2, EM3, EM4H and EM4S Typical Supply Current vs. Supply
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4.2.2 DC-DC Converter
Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 4.7 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz
Figure 4.8. DC-DC Converter Typical Performance Characteristics
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100μs/div 10μs/div
2V/div
offset:1.8V
20mV/div
offset:1.8V
100mA
1mA
ILOAD
60mV/div
offset:1.8V
VSW
DVDD
DVDD
Load Step Response in LN (CCM) mode
(Heavy Drive)
LN (CCM) and LP mode transition (load: 5mA)
Figure 4.9. DC-DC Converter Transition Waveforms
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4.2.3 2.4 GHz Radio
Figure 4.10. 2.4 GHz RF Transmitter Output Power
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Figure 4.11. 2.4 GHz RF Receiver Sensitivity
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5. Typical Connection Diagrams
5.1 Power
Typical power supply connections for direct supply, without using the internal DC-DC converter, are shown in the following figure.
Main
Supply
VDD
VREGVDD AVDD IOVDD
VREGSW
VREGVSS
DVDD
DECOUPLE
RFVDD PAVDD
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
+
–
Figure 5.1. EFR32FG13 Typical Application Circuit: Direct Supply Configuration without DC-DC converter
Typical power supply circuits using the internal DC-DC converter are shown below. The MCU operates from the DC-DC converter sup-
ply. For low RF transmit power applications less than 13dBm, the RF PA may be supplied by the DC-DC converter. For OPNs support-
ing high power RF transmission, the RF PA must be directly supplied by VDD for RF transmit power greater than 13 dBm.
Main
Supply
VDCDC
VDD
VREGVDD AVDD IOVDD
VREGSW
VREGVSS
DVDD
DECOUPLE
RFVDD PAVDD
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
+
–
Figure 5.2. EFR32FG13 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC)
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Main
Supply
VDCDC
VDD
VREGVDD AVDD IOVDD
VREGSW
VREGVSS
DVDD
DECOUPLE
RFVDD PAVDD
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
+
–
Figure 5.3. EFR32FG13 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDD)
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5.2 RF Matching Networks
Typical RF matching network circuit diagrams are shown in Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on
page 118 for applications in the 2.4GHz band, and in Figure 5.5 Typical Sub-GHz RF impedance-matching network circuits on page
118 for applications in the sub-GHz band. Application-specific component values can be found in the EFR32xG13 Reference Manual.
For low RF transmit power applications less than 13dBm, the two-element match is recommended. For OPNs supporting high power
RF transmission, the four-element match is recommended for high RF transmit power (> 13dBm).
2-Element Match for 2.4GHz Band 4-Element Match for 2.4GHz Band
L0
C0
50Ω2G4RF_IOP
2G4RF_ION 2G4RF_ION
2G4RF_IOP
L0 L1
C0 C1
50Ω
PAVDD PAVDD
PAVDD PAVDD
Figure 5.4. Typical 2.4 GHz RF impedance-matching network circuits
Sub-GHz Match Topology I (169-500 MHz)
Sub-GHz Match Topology 2 (500-915 MHz)
SUBGRF_IN
SUBGRF_IP
SUBGRF_ON
SUBGRF_OP
50Ω
PAVDD
L0
C0
C1
L3
L4
C4 C7
BAL1
C8 C9
L5 L6
50Ω
PAVDD
L0
C0
C1
L3
L4
C4 C7
BAL1
C8 C9
L5 L6
L1 L2
C2
C3
C5
C6
C10
L7
SUBGRF_IN
SUBGRF_IP
SUBGRF_ON
SUBGRF_OP
Figure 5.5. Typical Sub-GHz RF impedance-matching network circuits
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5.3 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN0002: "Hardware De-
sign Considerations" contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs
website (www.silabs.com/32bit-appnotes).
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6. Pin Definitions
6.1 QFN48 2.4 GHz and Sub-GHz Device Pinout
Figure 6.1. QFN48 2.4 GHz and Sub-GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.4 GPIO Functionality Table or 6.5 Alternate Functionality Overview.
Table 6.1. QFN48 2.4 GHz and Sub-GHz Device Pinout
Pin Name Pin(s) Description Pin Name Pin(s) Description
VSS 0 Ground PF0 1 GPIO (5V)
PF1 2 GPIO (5V) PF2 3 GPIO (5V)
PF3 4 GPIO (5V) PF4 5 GPIO (5V)
PF5 6 GPIO (5V) PF6 7 GPIO (5V)
PF7 8 GPIO (5V) RFVDD 9 Radio power supply
HFXTAL_N 10 High Frequency Crystal input pin. HFXTAL_P 11 High Frequency Crystal output pin.
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Pin Name Pin(s) Description Pin Name Pin(s) Description
RESETn 12
Reset input, active low. To apply an ex-
ternal reset source to this pin, it is re-
quired to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
SUBGRF_OP 13 Sub GHz Differential RF output, positive
path.
SUBGRF_ON 14 Sub GHz Differential RF output, nega-
tive path. SUBGRF_IP 15 Sub GHz Differential RF input, positive
path.
SUBGRF_IN 16 Sub GHz Differential RF input, negative
path. RFVSS 17 Radio Ground
PAVSS 18 Power Amplifier (PA) voltage regulator
VSS 2G4RF_ION 19
2.4 GHz Differential RF input/output,
negative path. This pin should be exter-
nally grounded.
2G4RF_IOP 20 2.4 GHz Differential RF input/output,
positive path. PAVDD 21 Power Amplifier (PA) voltage regulator
VDD input
PD13 22 GPIO PD14 23 GPIO
PD15 24 GPIO PA0 25 GPIO
PA1 26 GPIO PA2 27 GPIO
PA3 28 GPIO PA4 29 GPIO
PA5 30 GPIO (5V) PB11 31 GPIO
PB12 32 GPIO PB13 33 GPIO
AVDD 34 Analog power supply. PB14 35 GPIO
PB15 36 GPIO VREGVSS 37 Voltage regulator VSS
VREGSW 38 DCDC regulator switching node VREGVDD 39 Voltage regulator VDD input
DVDD 40 Digital power supply. DECOUPLE 41
Decouple output for on-chip voltage
regulator. An external decoupling ca-
pacitor is required at this pin.
IOVDD 42 Digital IO power supply. PC6 43 GPIO (5V)
PC7 44 GPIO (5V) PC8 45 GPIO (5V)
PC9 46 GPIO (5V) PC10 47 GPIO (5V)
PC11 48 GPIO (5V)
Note:
1. GPIO with 5V tolerance are indicated by (5V).
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6.2 QFN48 2.4 GHz Device Pinout
Figure 6.2. QFN48 2.4 GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.4 GPIO Functionality Table or 6.5 Alternate Functionality Overview.
Table 6.2. QFN48 2.4 GHz Device Pinout
Pin Name Pin(s) Description Pin Name Pin(s) Description
VSS 0 Ground PF0 1 GPIO (5V)
PF1 2 GPIO (5V) PF2 3 GPIO (5V)
PF3 4 GPIO (5V) PF4 5 GPIO (5V)
PF5 6 GPIO (5V) PF6 7 GPIO (5V)
PF7 8 GPIO (5V) RFVDD 9 Radio power supply
HFXTAL_N 10 High Frequency Crystal input pin. HFXTAL_P 11 High Frequency Crystal output pin.
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Pin Name Pin(s) Description Pin Name Pin(s) Description
RESETn 12
Reset input, active low. To apply an ex-
ternal reset source to this pin, it is re-
quired to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
NC 13 No Connect.
RFVSS 14 Radio Ground PAVSS 15 Power Amplifier (PA) voltage regulator
VSS
2G4RF_ION 16
2.4 GHz Differential RF input/output,
negative path. This pin should be exter-
nally grounded.
2G4RF_IOP 17 2.4 GHz Differential RF input/output,
positive path.
PAVDD 18 Power Amplifier (PA) voltage regulator
VDD input PD10 19 GPIO (5V)
PD11 20 GPIO (5V) PD12 21 GPIO (5V)
PD13 22 GPIO PD14 23 GPIO
PD15 24 GPIO PA0 25 GPIO
PA1 26 GPIO PA2 27 GPIO
PA3 28 GPIO PA4 29 GPIO
PA5 30 GPIO (5V) PB11 31 GPIO
PB12 32 GPIO PB13 33 GPIO
AVDD 34 Analog power supply. PB14 35 GPIO
PB15 36 GPIO VREGVSS 37 Voltage regulator VSS
VREGSW 38 DCDC regulator switching node VREGVDD 39 Voltage regulator VDD input
DVDD 40 Digital power supply. DECOUPLE 41
Decouple output for on-chip voltage
regulator. An external decoupling ca-
pacitor is required at this pin.
IOVDD 42 Digital IO power supply. PC6 43 GPIO (5V)
PC7 44 GPIO (5V) PC8 45 GPIO (5V)
PC9 46 GPIO (5V) PC10 47 GPIO (5V)
PC11 48 GPIO (5V)
Note:
1. GPIO with 5V tolerance are indicated by (5V).
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6.3 QFN48 Sub-GHz Device Pinout
Figure 6.3. QFN48 Sub-GHz Device Pinout
The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.4 GPIO Functionality Table or 6.5 Alternate Functionality Overview.
Table 6.3. QFN48 Sub-GHz Device Pinout
Pin Name Pin(s) Description Pin Name Pin(s) Description
VSS 0 Ground PF0 1 GPIO (5V)
PF1 2 GPIO (5V) PF2 3 GPIO (5V)
PF3 4 GPIO (5V) PF4 5 GPIO (5V)
PF5 6 GPIO (5V) PF6 7 GPIO (5V)
PF7 8 GPIO (5V) RFVDD 9 Radio power supply
HFXTAL_N 10 High Frequency Crystal input pin. HFXTAL_P 11 High Frequency Crystal output pin.
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Pin Name Pin(s) Description Pin Name Pin(s) Description
RESETn 12
Reset input, active low. To apply an ex-
ternal reset source to this pin, it is re-
quired to only drive this pin low during
reset, and let the internal pull-up ensure
that reset is released.
SUBGRF_OP 13 Sub GHz Differential RF output, positive
path.
SUBGRF_ON 14 Sub GHz Differential RF output, nega-
tive path. SUBGRF_IP 15 Sub GHz Differential RF input, positive
path.
SUBGRF_IN 16 Sub GHz Differential RF input, negative
path. RFVSS 17 Radio Ground
PD9 18 GPIO (5V) PD10 19 GPIO (5V)
PD11 20 GPIO (5V) PD12 21 GPIO (5V)
PD13 22 GPIO PD14 23 GPIO
PD15 24 GPIO PA0 25 GPIO
PA1 26 GPIO PA2 27 GPIO
PA3 28 GPIO PA4 29 GPIO
PA5 30 GPIO (5V) PB11 31 GPIO
PB12 32 GPIO PB13 33 GPIO
AVDD 34 Analog power supply. PB14 35 GPIO
PB15 36 GPIO VREGVSS 37 Voltage regulator VSS
VREGSW 38 DCDC regulator switching node VREGVDD 39 Voltage regulator VDD input
DVDD 40 Digital power supply. DECOUPLE 41
Decouple output for on-chip voltage
regulator. An external decoupling ca-
pacitor is required at this pin.
IOVDD 42 Digital IO power supply. PC6 43 GPIO (5V)
PC7 44 GPIO (5V) PC8 45 GPIO (5V)
PC9 46 GPIO (5V) PC10 47 GPIO (5V)
PC11 48 GPIO (5V)
Note:
1. GPIO with 5V tolerance are indicated by (5V).
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6.4 GPIO Functionality Table
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of each GPIO
pin, followed by the functionality available on that pin. Refer to 6.5 Alternate Functionality Overview for a list of GPIO locations available
for each function.
Table 6.4. GPIO Functionality Table
GPIO Name Pin Alternate Functionality / Description
Analog Timers Communication Radio Other
PF0 BUSBY BUSAX
TIM0_CC0 #24
TIM0_CC1 #23
TIM0_CC2 #22
TIM0_CDTI0 #21
TIM0_CDTI1 #20
TIM0_CDTI2 #19
TIM1_CC0 #24
TIM1_CC1 #23
TIM1_CC2 #22
TIM1_CC3 #21
WTIM0_CDTI1 #30
WTIM0_CDTI2 #28
LETIM0_OUT0 #24
LETIM0_OUT1 #23
PCNT0_S0IN #24
PCNT0_S1IN #23
US0_TX #24
US0_RX #23
US0_CLK #22
US0_CS #21
US0_CTS #20
US0_RTS #19
US1_TX #24
US1_RX #23
US1_CLK #22
US1_CS #21
US1_CTS #20
US1_RTS #19
US2_TX #14
US2_RX #13
US2_CLK #12
US2_CS #11
US2_CTS #10
US2_RTS #9
LEU0_TX #24
LEU0_RX #23
I2C0_SDA #24
I2C0_SCL #23
FRC_DCLK #24
FRC_DOUT #23
FRC_DFRAME #22
MODEM_DCLK #24
MODEM_DIN #23
MODEM_DOUT #22
MODEM_ANT0 #21
MODEM_ANT1 #20
PRS_CH0 #0
PRS_CH1 #7
PRS_CH2 #6
PRS_CH3 #5
ACMP0_O #24
ACMP1_O #24
DBG_SWCLKTCK
BOOT_TX
PF1 BUSAY BUSBX
TIM0_CC0 #25
TIM0_CC1 #24
TIM0_CC2 #23
TIM0_CDTI0 #22
TIM0_CDTI1 #21
TIM0_CDTI2 #20
TIM1_CC0 #25
TIM1_CC1 #24
TIM1_CC2 #23
TIM1_CC3 #22
WTIM0_CDTI1 #31
WTIM0_CDTI2 #29
LETIM0_OUT0 #25
LETIM0_OUT1 #24
PCNT0_S0IN #25
PCNT0_S1IN #24
US0_TX #25
US0_RX #24
US0_CLK #23
US0_CS #22
US0_CTS #21
US0_RTS #20
US1_TX #25
US1_RX #24
US1_CLK #23
US1_CS #22
US1_CTS #21
US1_RTS #20
US2_TX #15
US2_RX #14
US2_CLK #13
US2_CS #12
US2_CTS #11
US2_RTS #10
LEU0_TX #25
LEU0_RX #24
I2C0_SDA #25
I2C0_SCL #24
FRC_DCLK #25
FRC_DOUT #24
FRC_DFRAME #23
MODEM_DCLK #25
MODEM_DIN #24
MODEM_DOUT #23
MODEM_ANT0 #22
MODEM_ANT1 #21
PRS_CH0 #1
PRS_CH1 #0
PRS_CH2 #7
PRS_CH3 #6
ACMP0_O #25
ACMP1_O #25
DBG_SWDIOTMS
BOOT_RX
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GPIO Name Pin Alternate Functionality / Description
Analog Timers Communication Radio Other
PF2 BUSBY BUSAX
TIM0_CC0 #26
TIM0_CC1 #25
TIM0_CC2 #24
TIM0_CDTI0 #23
TIM0_CDTI1 #22
TIM0_CDTI2 #21
TIM1_CC0 #26
TIM1_CC1 #25
TIM1_CC2 #24
TIM1_CC3 #23
WTIM0_CDTI2 #30
LETIM0_OUT0 #26
LETIM0_OUT1 #25
PCNT0_S0IN #26
PCNT0_S1IN #25
US0_TX #26
US0_RX #25
US0_CLK #24
US0_CS #23
US0_CTS #22
US0_RTS #21
US1_TX #26
US1_RX #25
US1_CLK #24
US1_CS #23
US1_CTS #22
US1_RTS #21
LEU0_TX #26
LEU0_RX #25
I2C0_SDA #26
I2C0_SCL #25
FRC_DCLK #26
FRC_DOUT #25
FRC_DFRAME #24
MODEM_DCLK #26
MODEM_DIN #25
MODEM_DOUT #24
MODEM_ANT0 #23
MODEM_ANT1 #22
CMU_CLK0 #6
PRS_CH0 #2
PRS_CH1 #1
PRS_CH2 #0
PRS_CH3 #7
ACMP0_O #26
ACMP1_O #26
DBG_TDO
DBG_SWO #0
GPIO_EM4WU0
PF3 BUSAY BUSBX
TIM0_CC0 #27
TIM0_CC1 #26
TIM0_CC2 #25
TIM0_CDTI0 #24
TIM0_CDTI1 #23
TIM0_CDTI2 #22
TIM1_CC0 #27
TIM1_CC1 #26
TIM1_CC2 #25
TIM1_CC3 #24
WTIM0_CDTI2 #31
LETIM0_OUT0 #27
LETIM0_OUT1 #26
PCNT0_S0IN #27
PCNT0_S1IN #26
US0_TX #27
US0_RX #26
US0_CLK #25
US0_CS #24
US0_CTS #23
US0_RTS #22
US1_TX #27
US1_RX #26
US1_CLK #25
US1_CS #24
US1_CTS #23
US1_RTS #22
US2_TX #16
US2_RX #15
US2_CLK #14
US2_CS #13
US2_CTS #12
US2_RTS #11
LEU0_TX #27
LEU0_RX #26
I2C0_SDA #27
I2C0_SCL #26
FRC_DCLK #27
FRC_DOUT #26
FRC_DFRAME #25
MODEM_DCLK #27
MODEM_DIN #26
MODEM_DOUT #25
MODEM_ANT0 #24
MODEM_ANT1 #23
CMU_CLK1 #6
PRS_CH0 #3
PRS_CH1 #2
PRS_CH2 #1
PRS_CH3 #0
ACMP0_O #27
ACMP1_O #27
DBG_TDI
PF4 BUSBY BUSAX
TIM0_CC0 #28
TIM0_CC1 #27
TIM0_CC2 #26
TIM0_CDTI0 #25
TIM0_CDTI1 #24
TIM0_CDTI2 #23
TIM1_CC0 #28
TIM1_CC1 #27
TIM1_CC2 #26
TIM1_CC3 #25 LE-
TIM0_OUT0 #28 LE-
TIM0_OUT1 #27
PCNT0_S0IN #28
PCNT0_S1IN #27
US0_TX #28
US0_RX #27
US0_CLK #26
US0_CS #25
US0_CTS #24
US0_RTS #23
US1_TX #28
US1_RX #27
US1_CLK #26
US1_CS #25
US1_CTS #24
US1_RTS #23
US2_TX #17
US2_RX #16
US2_CLK #15
US2_CS #14
US2_CTS #13
US2_RTS #12
LEU0_TX #28
LEU0_RX #27
I2C0_SDA #28
I2C0_SCL #27
FRC_DCLK #28
FRC_DOUT #27
FRC_DFRAME #26
MODEM_DCLK #28
MODEM_DIN #27
MODEM_DOUT #26
MODEM_ANT0 #25
MODEM_ANT1 #24
PRS_CH0 #4
PRS_CH1 #3
PRS_CH2 #2
PRS_CH3 #1
ACMP0_O #28
ACMP1_O #28
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.0 | 127
GPIO Name Pin Alternate Functionality / Description
Analog Timers Communication Radio Other
PF5 BUSAY BUSBX
TIM0_CC0 #29
TIM0_CC1 #28
TIM0_CC2 #27
TIM0_CDTI0 #26
TIM0_CDTI1 #25
TIM0_CDTI2 #24
TIM1_CC0 #29
TIM1_CC1 #28
TIM1_CC2 #27
TIM1_CC3 #26 LE-
TIM0_OUT0 #29 LE-
TIM0_OUT1 #28
PCNT0_S0IN #29
PCNT0_S1IN #28
US0_TX #29
US0_RX #28
US0_CLK #27
US0_CS #26
US0_CTS #25
US0_RTS #24
US1_TX #29
US1_RX #28
US1_CLK #27
US1_CS #26
US1_CTS #25
US1_RTS #24
US2_TX #18
US2_RX #17
US2_CLK #16
US2_CS #15
US2_CTS #14
US2_RTS #13
LEU0_TX #29
LEU0_RX #28
I2C0_SDA #29
I2C0_SCL #28
FRC_DCLK #29
FRC_DOUT #28
FRC_DFRAME #27
MODEM_DCLK #29
MODEM_DIN #28
MODEM_DOUT #27
MODEM_ANT0 #26
MODEM_ANT1 #25
PRS_CH0 #5
PRS_CH1 #4
PRS_CH2 #3
PRS_CH3 #2
ACMP0_O #29
ACMP1_O #29
PF6 BUSBY BUSAX
TIM0_CC0 #30
TIM0_CC1 #29
TIM0_CC2 #28
TIM0_CDTI0 #27
TIM0_CDTI1 #26
TIM0_CDTI2 #25
TIM1_CC0 #30
TIM1_CC1 #29
TIM1_CC2 #28
TIM1_CC3 #27 LE-
TIM0_OUT0 #30 LE-
TIM0_OUT1 #29
PCNT0_S0IN #30
PCNT0_S1IN #29
US0_TX #30
US0_RX #29
US0_CLK #28
US0_CS #27
US0_CTS #26
US0_RTS #25
US1_TX #30
US1_RX #29
US1_CLK #28
US1_CS #27
US1_CTS #26
US1_RTS #25
US2_TX #19
US2_RX #18
US2_CLK #17
US2_CS #16
US2_CTS #15
US2_RTS #14
LEU0_TX #30
LEU0_RX #29
I2C0_SDA #30
I2C0_SCL #29
FRC_DCLK #30
FRC_DOUT #29
FRC_DFRAME #28
MODEM_DCLK #30
MODEM_DIN #29
MODEM_DOUT #28
MODEM_ANT0 #27
MODEM_ANT1 #26
CMU_CLK1 #7
PRS_CH0 #6
PRS_CH1 #5
PRS_CH2 #4
PRS_CH3 #3
ACMP0_O #30
ACMP1_O #30
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.0 | 128
GPIO Name Pin Alternate Functionality / Description
Analog Timers Communication Radio Other
PF7 BUSAY BUSBX
TIM0_CC0 #31
TIM0_CC1 #30
TIM0_CC2 #29
TIM0_CDTI0 #28
TIM0_CDTI1 #27
TIM0_CDTI2 #26
TIM1_CC0 #31
TIM1_CC1 #30
TIM1_CC2 #29
TIM1_CC3 #28 LE-
TIM0_OUT0 #31 LE-
TIM0_OUT1 #30
PCNT0_S0IN #31
PCNT0_S1IN #30
US0_TX #31
US0_RX #30
US0_CLK #29
US0_CS #28
US0_CTS #27
US0_RTS #26
US1_TX #31
US1_RX #30
US1_CLK #29
US1_CS #28
US1_CTS #27
US1_RTS #26
US2_TX #20
US2_RX #19
US2_CLK #18
US2_CS #17
US2_CTS #16
US2_RTS #15
LEU0_TX #31
LEU0_RX #30
I2C0_SDA #31
I2C0_SCL #30
FRC_DCLK #31
FRC_DOUT #30
FRC_DFRAME #29
MODEM_DCLK #31
MODEM_DIN #30
MODEM_DOUT #29
MODEM_ANT0 #28
MODEM_ANT1 #27
CMU_CLKI0 #1
CMU_CLK0 #7
PRS_CH0 #7
PRS_CH1 #6
PRS_CH2 #5
PRS_CH3 #4
ACMP0_O #31
ACMP1_O #31
GPIO_EM4WU1
PD9 BUSCY BUSDX
TIM0_CC0 #17
TIM0_CC1 #16
TIM0_CC2 #15
TIM0_CDTI0 #14
TIM0_CDTI1 #13
TIM0_CDTI2 #12
TIM1_CC0 #17
TIM1_CC1 #16
TIM1_CC2 #15
TIM1_CC3 #14
WTIM0_CC1 #31
WTIM0_CC2 #29
WTIM0_CDTI0 #25
WTIM0_CDTI1 #23
WTIM0_CDTI2 #21
LETIM0_OUT0 #17
LETIM0_OUT1 #16
PCNT0_S0IN #17
PCNT0_S1IN #16
US0_TX #17
US0_RX #16
US0_CLK #15
US0_CS #14
US0_CTS #13
US0_RTS #12
US1_TX #17
US1_RX #16
US1_CLK #15
US1_CS #14
US1_CTS #13
US1_RTS #12
LEU0_TX #17
LEU0_RX #16
I2C0_SDA #17
I2C0_SCL #16
FRC_DCLK #17
FRC_DOUT #16
FRC_DFRAME #15
MODEM_DCLK #17
MODEM_DIN #16
MODEM_DOUT #15
MODEM_ANT0 #14
MODEM_ANT1 #13
CMU_CLK0 #4
PRS_CH3 #8
PRS_CH4 #0
PRS_CH5 #6
PRS_CH6 #11
ACMP0_O #17
ACMP1_O #17
LES_CH1
PD10 BUSDY BUSCX
TIM0_CC0 #18
TIM0_CC1 #17
TIM0_CC2 #16
TIM0_CDTI0 #15
TIM0_CDTI1 #14
TIM0_CDTI2 #13
TIM1_CC0 #18
TIM1_CC1 #17
TIM1_CC2 #16
TIM1_CC3 #15
WTIM0_CC2 #30
WTIM0_CDTI0 #26
WTIM0_CDTI1 #24
WTIM0_CDTI2 #22
LETIM0_OUT0 #18
LETIM0_OUT1 #17
PCNT0_S0IN #18
PCNT0_S1IN #17
US0_TX #18
US0_RX #17
US0_CLK #16
US0_CS #15
US0_CTS #14
US0_RTS #13
US1_TX #18
US1_RX #17
US1_CLK #16
US1_CS #15
US1_CTS #14
US1_RTS #13
LEU0_TX #18
LEU0_RX #17
I2C0_SDA #18
I2C0_SCL #17
FRC_DCLK #18
FRC_DOUT #17
FRC_DFRAME #16
MODEM_DCLK #18
MODEM_DIN #17
MODEM_DOUT #16
MODEM_ANT0 #15
MODEM_ANT1 #14
CMU_CLK1 #4
PRS_CH3 #9
PRS_CH4 #1
PRS_CH5 #0
PRS_CH6 #12
ACMP0_O #18
ACMP1_O #18
LES_CH2
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.0 | 129
GPIO Name Pin Alternate Functionality / Description
Analog Timers Communication Radio Other
PD11 BUSCY BUSDX
TIM0_CC0 #19
TIM0_CC1 #18
TIM0_CC2 #17
TIM0_CDTI0 #16
TIM0_CDTI1 #15
TIM0_CDTI2 #14
TIM1_CC0 #19
TIM1_CC1 #18
TIM1_CC2 #17
TIM1_CC3 #16
WTIM0_CC2 #31
WTIM0_CDTI0 #27
WTIM0_CDTI1 #25
WTIM0_CDTI2 #23
LETIM0_OUT0 #19
LETIM0_OUT1 #18
PCNT0_S0IN #19
PCNT0_S1IN #18
US0_TX #19
US0_RX #18
US0_CLK #17
US0_CS #16
US0_CTS #15
US0_RTS #14
US1_TX #19
US1_RX #18
US1_CLK #17
US1_CS #16
US1_CTS #15
US1_RTS #14
LEU0_TX #19
LEU0_RX #18
I2C0_SDA #19
I2C0_SCL #18
FRC_DCLK #19
FRC_DOUT #18
FRC_DFRAME #17
MODEM_DCLK #19
MODEM_DIN #18
MODEM_DOUT #17
MODEM_ANT0 #16
MODEM_ANT1 #15
PRS_CH3 #10
PRS_CH4 #2
PRS_CH5 #1
PRS_CH6 #13
ACMP0_O #19
ACMP1_O #19
LES_CH3
PD12
VDAC0_OUT1ALT /
OPA1_OUTALT #0
BUSDY BUSCX
TIM0_CC0 #20
TIM0_CC1 #19
TIM0_CC2 #18
TIM0_CDTI0 #17
TIM0_CDTI1 #16
TIM0_CDTI2 #15
TIM1_CC0 #20
TIM1_CC1 #19
TIM1_CC2 #18
TIM1_CC3 #17
WTIM0_CDTI0 #28
WTIM0_CDTI1 #26
WTIM0_CDTI2 #24
LETIM0_OUT0 #20
LETIM0_OUT1 #19
PCNT0_S0IN #20
PCNT0_S1IN #19
US0_TX #20
US0_RX #19
US0_CLK #18
US0_CS #17
US0_CTS #16
US0_RTS #15
US1_TX #20
US1_RX #19
US1_CLK #18
US1_CS #17
US1_CTS #16
US1_RTS #15
LEU0_TX #20
LEU0_RX #19
I2C0_SDA #20
I2C0_SCL #19
FRC_DCLK #20
FRC_DOUT #19
FRC_DFRAME #18
MODEM_DCLK #20
MODEM_DIN #19
MODEM_DOUT #18
MODEM_ANT0 #17
MODEM_ANT1 #16
PRS_CH3 #11
PRS_CH4 #3
PRS_CH5 #2
PRS_CH6 #14
ACMP0_O #20
ACMP1_O #20
LES_CH4
PD13
VDAC0_OUT0ALT /
OPA0_OUTALT #1
BUSCY BUSDX
OPA1_P
TIM0_CC0 #21
TIM0_CC1 #20
TIM0_CC2 #19
TIM0_CDTI0 #18
TIM0_CDTI1 #17
TIM0_CDTI2 #16
TIM1_CC0 #21
TIM1_CC1 #20
TIM1_CC2 #19
TIM1_CC3 #18
WTIM0_CDTI0 #29
WTIM0_CDTI1 #27
WTIM0_CDTI2 #25
LETIM0_OUT0 #21
LETIM0_OUT1 #20
PCNT0_S0IN #21
PCNT0_S1IN #20
US0_TX #21
US0_RX #20
US0_CLK #19
US0_CS #18
US0_CTS #17
US0_RTS #16
US1_TX #21
US1_RX #20
US1_CLK #19
US1_CS #18
US1_CTS #17
US1_RTS #16
LEU0_TX #21
LEU0_RX #20
I2C0_SDA #21
I2C0_SCL #20
FRC_DCLK #21
FRC_DOUT #20
FRC_DFRAME #19
MODEM_DCLK #21
MODEM_DIN #20
MODEM_DOUT #19
MODEM_ANT0 #18
MODEM_ANT1 #17
PRS_CH3 #12
PRS_CH4 #4
PRS_CH5 #3
PRS_CH6 #15
ACMP0_O #21
ACMP1_O #21
LES_CH5
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.0 | 130
GPIO Name Pin Alternate Functionality / Description
Analog Timers Communication Radio Other
PD14
BUSDY BUSCX
VDAC0_OUT1 /
OPA1_OUT
TIM0_CC0 #22
TIM0_CC1 #21
TIM0_CC2 #20
TIM0_CDTI0 #19
TIM0_CDTI1 #18
TIM0_CDTI2 #17
TIM1_CC0 #22
TIM1_CC1 #21
TIM1_CC2 #20
TIM1_CC3 #19
WTIM0_CDTI0 #30
WTIM0_CDTI1 #28
WTIM0_CDTI2 #26
LETIM0_OUT0 #22
LETIM0_OUT1 #21
PCNT0_S0IN #22
PCNT0_S1IN #21
US0_TX #22
US0_RX #21
US0_CLK #20
US0_CS #19
US0_CTS #18
US0_RTS #17
US1_TX #22
US1_RX #21
US1_CLK #20
US1_CS #19
US1_CTS #18
US1_RTS #17
LEU0_TX #22
LEU0_RX #21
I2C0_SDA #22
I2C0_SCL #21
FRC_DCLK #22
FRC_DOUT #21
FRC_DFRAME #20
MODEM_DCLK #22
MODEM_DIN #21
MODEM_DOUT #20
MODEM_ANT0 #19
MODEM_ANT1 #18
CMU_CLK0 #5
PRS_CH3 #13
PRS_CH4 #5
PRS_CH5 #4
PRS_CH6 #16
ACMP0_O #22
ACMP1_O #22
LES_CH6
GPIO_EM4WU4
PD15
VDAC0_OUT0ALT /
OPA0_OUTALT #2
BUSCY BUSDX
OPA1_N
TIM0_CC0 #23
TIM0_CC1 #22
TIM0_CC2 #21
TIM0_CDTI0 #20
TIM0_CDTI1 #19
TIM0_CDTI2 #18
TIM1_CC0 #23
TIM1_CC1 #22
TIM1_CC2 #21
TIM1_CC3 #20
WTIM0_CDTI0 #31
WTIM0_CDTI1 #29
WTIM0_CDTI2 #27
LETIM0_OUT0 #23
LETIM0_OUT1 #22
PCNT0_S0IN #23
PCNT0_S1IN #22
US0_TX #23
US0_RX #22
US0_CLK #21
US0_CS #20
US0_CTS #19
US0_RTS #18
US1_TX #23
US1_RX #22
US1_CLK #21
US1_CS #20
US1_CTS #19
US1_RTS #18
LEU0_TX #23
LEU0_RX #22
I2C0_SDA #23
I2C0_SCL #22
FRC_DCLK #23
FRC_DOUT #22
FRC_DFRAME #21
MODEM_DCLK #23
MODEM_DIN #22
MODEM_DOUT #21
MODEM_ANT0 #20
MODEM_ANT1 #19
CMU_CLK1 #5
PRS_CH3 #14
PRS_CH4 #6
PRS_CH5 #5
PRS_CH6 #17
ACMP0_O #23
ACMP1_O #23
LES_CH7
DBG_SWO #2
PA0 BUSDY BUSCX
ADC0_EXTN
TIM0_CC0 #0
TIM0_CC1 #31
TIM0_CC2 #30
TIM0_CDTI0 #29
TIM0_CDTI1 #28
TIM0_CDTI2 #27
TIM1_CC0 #0
TIM1_CC1 #31
TIM1_CC2 #30
TIM1_CC3 #29
WTIM0_CC0 #0 LE-
TIM0_OUT0 #0 LE-
TIM0_OUT1 #31
PCNT0_S0IN #0
PCNT0_S1IN #31
US0_TX #0 US0_RX
#31 US0_CLK #30
US0_CS #29
US0_CTS #28
US0_RTS #27
US1_TX #0 US1_RX
#31 US1_CLK #30
US1_CS #29
US1_CTS #28
US1_RTS #27
LEU0_TX #0
LEU0_RX #31
I2C0_SDA #0
I2C0_SCL #31
FRC_DCLK #0
FRC_DOUT #31
FRC_DFRAME #30
MODEM_DCLK #0
MODEM_DIN #31
MODEM_DOUT #30
MODEM_ANT0 #29
MODEM_ANT1 #28
CMU_CLK1 #0
PRS_CH6 #0
PRS_CH7 #10
PRS_CH8 #9
PRS_CH9 #8
ACMP0_O #0
ACMP1_O #0
LES_CH8
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.0 | 131
GPIO Name Pin Alternate Functionality / Description
Analog Timers Communication Radio Other
PA1
BUSCY BUSDX
ADC0_EXTP
VDAC0_EXT
TIM0_CC0 #1
TIM0_CC1 #0
TIM0_CC2 #31
TIM0_CDTI0 #30
TIM0_CDTI1 #29
TIM0_CDTI2 #28
TIM1_CC0 #1
TIM1_CC1 #0
TIM1_CC2 #31
TIM1_CC3 #30
WTIM0_CC0 #1 LE-
TIM0_OUT0 #1 LE-
TIM0_OUT1 #0
PCNT0_S0IN #1
PCNT0_S1IN #0
US0_TX #1 US0_RX
#0 US0_CLK #31
US0_CS #30
US0_CTS #29
US0_RTS #28
US1_TX #1 US1_RX
#0 US1_CLK #31
US1_CS #30
US1_CTS #29
US1_RTS #28
LEU0_TX #1
LEU0_RX #0
I2C0_SDA #1
I2C0_SCL #0
FRC_DCLK #1
FRC_DOUT #0
FRC_DFRAME #31
MODEM_DCLK #1
MODEM_DIN #0
MODEM_DOUT #31
MODEM_ANT0 #30
MODEM_ANT1 #29
CMU_CLK0 #0
PRS_CH6 #1
PRS_CH7 #0
PRS_CH8 #10
PRS_CH9 #9
ACMP0_O #1
ACMP1_O #1
LES_CH9
PA2
VDAC0_OUT1ALT /
OPA1_OUTALT #1
BUSDY BUSCX
OPA0_P
TIM0_CC0 #2
TIM0_CC1 #1
TIM0_CC2 #0
TIM0_CDTI0 #31
TIM0_CDTI1 #30
TIM0_CDTI2 #29
TIM1_CC0 #2
TIM1_CC1 #1
TIM1_CC2 #0
TIM1_CC3 #31
WTIM0_CC0 #2
WTIM0_CC1 #0 LE-
TIM0_OUT0 #2 LE-
TIM0_OUT1 #1
PCNT0_S0IN #2
PCNT0_S1IN #1
US0_TX #2 US0_RX
#1 US0_CLK #0
US0_CS #31
US0_CTS #30
US0_RTS #29
US1_TX #2 US1_RX
#1 US1_CLK #0
US1_CS #31
US1_CTS #30
US1_RTS #29
LEU0_TX #2
LEU0_RX #1
I2C0_SDA #2
I2C0_SCL #1
FRC_DCLK #2
FRC_DOUT #1
FRC_DFRAME #0
MODEM_DCLK #2
MODEM_DIN #1
MODEM_DOUT #0
MODEM_ANT0 #31
MODEM_ANT1 #30
PRS_CH6 #2
PRS_CH7 #1
PRS_CH8 #0
PRS_CH9 #10
ACMP0_O #2
ACMP1_O #2
LES_CH10
PA3
BUSCY BUSDX
VDAC0_OUT0 /
OPA0_OUT
TIM0_CC0 #3
TIM0_CC1 #2
TIM0_CC2 #1
TIM0_CDTI0 #0
TIM0_CDTI1 #31
TIM0_CDTI2 #30
TIM1_CC0 #3
TIM1_CC1 #2
TIM1_CC2 #1
TIM1_CC3 #0
WTIM0_CC0 #3
WTIM0_CC1 #1 LE-
TIM0_OUT0 #3 LE-
TIM0_OUT1 #2
PCNT0_S0IN #3
PCNT0_S1IN #2
US0_TX #3 US0_RX
#2 US0_CLK #1
US0_CS #0
US0_CTS #31
US0_RTS #30
US1_TX #3 US1_RX
#2 US1_CLK #1
US1_CS #0
US1_CTS #31
US1_RTS #30
LEU0_TX #3
LEU0_RX #2
I2C0_SDA #3
I2C0_SCL #2
FRC_DCLK #3
FRC_DOUT #2
FRC_DFRAME #1
MODEM_DCLK #3
MODEM_DIN #2
MODEM_DOUT #1
MODEM_ANT0 #0
MODEM_ANT1 #31
PRS_CH6 #3
PRS_CH7 #2
PRS_CH8 #1
PRS_CH9 #0
ACMP0_O #3
ACMP1_O #3
LES_CH11
GPIO_EM4WU8
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.0 | 132
GPIO Name Pin Alternate Functionality / Description
Analog Timers Communication Radio Other
PA4
VDAC0_OUT1ALT /
OPA1_OUTALT #2
BUSDY BUSCX
OPA0_N
TIM0_CC0 #4
TIM0_CC1 #3
TIM0_CC2 #2
TIM0_CDTI0 #1
TIM0_CDTI1 #0
TIM0_CDTI2 #31
TIM1_CC0 #4
TIM1_CC1 #3
TIM1_CC2 #2
TIM1_CC3 #1
WTIM0_CC0 #4
WTIM0_CC1 #2
WTIM0_CC2 #0 LE-
TIM0_OUT0 #4 LE-
TIM0_OUT1 #3
PCNT0_S0IN #4
PCNT0_S1IN #3
US0_TX #4 US0_RX
#3 US0_CLK #2
US0_CS #1
US0_CTS #0
US0_RTS #31
US1_TX #4 US1_RX
#3 US1_CLK #2
US1_CS #1
US1_CTS #0
US1_RTS #31
LEU0_TX #4
LEU0_RX #3
I2C0_SDA #4
I2C0_SCL #3
FRC_DCLK #4
FRC_DOUT #3
FRC_DFRAME #2
MODEM_DCLK #4
MODEM_DIN #3
MODEM_DOUT #2
MODEM_ANT0 #1
MODEM_ANT1 #0
PRS_CH6 #4
PRS_CH7 #3
PRS_CH8 #2
PRS_CH9 #1
ACMP0_O #4
ACMP1_O #4
LES_CH12
PA5
VDAC0_OUT0ALT /
OPA0_OUTALT #0
BUSCY BUSDX
TIM0_CC0 #5
TIM0_CC1 #4
TIM0_CC2 #3
TIM0_CDTI0 #2
TIM0_CDTI1 #1
TIM0_CDTI2 #0
TIM1_CC0 #5
TIM1_CC1 #4
TIM1_CC2 #3
TIM1_CC3 #2
WTIM0_CC0 #5
WTIM0_CC1 #3
WTIM0_CC2 #1 LE-
TIM0_OUT0 #5 LE-
TIM0_OUT1 #4
PCNT0_S0IN #5
PCNT0_S1IN #4
US0_TX #5 US0_RX
#4 US0_CLK #3
US0_CS #2
US0_CTS #1
US0_RTS #0
US1_TX #5 US1_RX
#4 US1_CLK #3
US1_CS #2
US1_CTS #1
US1_RTS #0
US2_TX #0 US2_RX
#31 US2_CLK #30
US2_CS #29
US2_CTS #28
US2_RTS #27
LEU0_TX #5
LEU0_RX #4
I2C0_SDA #5
I2C0_SCL #4
FRC_DCLK #5
FRC_DOUT #4
FRC_DFRAME #3
MODEM_DCLK #5
MODEM_DIN #4
MODEM_DOUT #3
MODEM_ANT0 #2
MODEM_ANT1 #1
CMU_CLKI0 #4
PRS_CH6 #5
PRS_CH7 #4
PRS_CH8 #3
PRS_CH9 #2
ACMP0_O #5
ACMP1_O #5
LES_CH13
ETM_TCLK #1
PB11 BUSCY BUSDX
OPA2_P
TIM0_CC0 #6
TIM0_CC1 #5
TIM0_CC2 #4
TIM0_CDTI0 #3
TIM0_CDTI1 #2
TIM0_CDTI2 #1
TIM1_CC0 #6
TIM1_CC1 #5
TIM1_CC2 #4
TIM1_CC3 #3
WTIM0_CC0 #15
WTIM0_CC1 #13
WTIM0_CC2 #11
WTIM0_CDTI0 #7
WTIM0_CDTI1 #5
WTIM0_CDTI2 #3
LETIM0_OUT0 #6
LETIM0_OUT1 #5
PCNT0_S0IN #6
PCNT0_S1IN #5
US0_TX #6 US0_RX
#5 US0_CLK #4
US0_CS #3
US0_CTS #2
US0_RTS #1
US1_TX #6 US1_RX
#5 US1_CLK #4
US1_CS #3
US1_CTS #2
US1_RTS #1
LEU0_TX #6
LEU0_RX #5
I2C0_SDA #6
I2C0_SCL #5
FRC_DCLK #6
FRC_DOUT #5
FRC_DFRAME #4
MODEM_DCLK #6
MODEM_DIN #5
MODEM_DOUT #4
MODEM_ANT0 #3
MODEM_ANT1 #2
PRS_CH6 #6
PRS_CH7 #5
PRS_CH8 #4
PRS_CH9 #3
ACMP0_O #6
ACMP1_O #6
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GPIO Name Pin Alternate Functionality / Description
Analog Timers Communication Radio Other
PB12 BUSDY BUSCX
OPA2_OUT
TIM0_CC0 #7
TIM0_CC1 #6
TIM0_CC2 #5
TIM0_CDTI0 #4
TIM0_CDTI1 #3
TIM0_CDTI2 #2
TIM1_CC0 #7
TIM1_CC1 #6
TIM1_CC2 #5
TIM1_CC3 #4
WTIM0_CC0 #16
WTIM0_CC1 #14
WTIM0_CC2 #12
WTIM0_CDTI0 #8
WTIM0_CDTI1 #6
WTIM0_CDTI2 #4
LETIM0_OUT0 #7
LETIM0_OUT1 #6
PCNT0_S0IN #7
PCNT0_S1IN #6
US0_TX #7 US0_RX
#6 US0_CLK #5
US0_CS #4
US0_CTS #3
US0_RTS #2
US1_TX #7 US1_RX
#6 US1_CLK #5
US1_CS #4
US1_CTS #3
US1_RTS #2
LEU0_TX #7
LEU0_RX #6
I2C0_SDA #7
I2C0_SCL #6
FRC_DCLK #7
FRC_DOUT #6
FRC_DFRAME #5
MODEM_DCLK #7
MODEM_DIN #6
MODEM_DOUT #5
MODEM_ANT0 #4
MODEM_ANT1 #3
PRS_CH6 #7
PRS_CH7 #6
PRS_CH8 #5
PRS_CH9 #4
ACMP0_O #7
ACMP1_O #7
PB13 BUSCY BUSDX
OPA2_N
TIM0_CC0 #8
TIM0_CC1 #7
TIM0_CC2 #6
TIM0_CDTI0 #5
TIM0_CDTI1 #4
TIM0_CDTI2 #3
TIM1_CC0 #8
TIM1_CC1 #7
TIM1_CC2 #6
TIM1_CC3 #5
WTIM0_CC0 #17
WTIM0_CC1 #15
WTIM0_CC2 #13
WTIM0_CDTI0 #9
WTIM0_CDTI1 #7
WTIM0_CDTI2 #5
LETIM0_OUT0 #8
LETIM0_OUT1 #7
PCNT0_S0IN #8
PCNT0_S1IN #7
US0_TX #8 US0_RX
#7 US0_CLK #6
US0_CS #5
US0_CTS #4
US0_RTS #3
US1_TX #8 US1_RX
#7 US1_CLK #6
US1_CS #5
US1_CTS #4
US1_RTS #3
LEU0_TX #8
LEU0_RX #7
I2C0_SDA #8
I2C0_SCL #7
FRC_DCLK #8
FRC_DOUT #7
FRC_DFRAME #6
MODEM_DCLK #8
MODEM_DIN #7
MODEM_DOUT #6
MODEM_ANT0 #5
MODEM_ANT1 #4
CMU_CLKI0 #0
PRS_CH6 #8
PRS_CH7 #7
PRS_CH8 #6
PRS_CH9 #5
ACMP0_O #8
ACMP1_O #8
DBG_SWO #1
GPIO_EM4WU9
PB14 BUSDY BUSCX
LFXTAL_N
TIM0_CC0 #9
TIM0_CC1 #8
TIM0_CC2 #7
TIM0_CDTI0 #6
TIM0_CDTI1 #5
TIM0_CDTI2 #4
TIM1_CC0 #9
TIM1_CC1 #8
TIM1_CC2 #7
TIM1_CC3 #6
WTIM0_CC0 #18
WTIM0_CC1 #16
WTIM0_CC2 #14
WTIM0_CDTI0 #10
WTIM0_CDTI1 #8
WTIM0_CDTI2 #6
LETIM0_OUT0 #9
LETIM0_OUT1 #8
PCNT0_S0IN #9
PCNT0_S1IN #8
US0_TX #9 US0_RX
#8 US0_CLK #7
US0_CS #6
US0_CTS #5
US0_RTS #4
US1_TX #9 US1_RX
#8 US1_CLK #7
US1_CS #6
US1_CTS #5
US1_RTS #4
LEU0_TX #9
LEU0_RX #8
I2C0_SDA #9
I2C0_SCL #8
FRC_DCLK #9
FRC_DOUT #8
FRC_DFRAME #7
MODEM_DCLK #9
MODEM_DIN #8
MODEM_DOUT #7
MODEM_ANT0 #6
MODEM_ANT1 #5
CMU_CLK1 #1
PRS_CH6 #9
PRS_CH7 #8
PRS_CH8 #7
PRS_CH9 #6
ACMP0_O #9
ACMP1_O #9
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Pin Definitions
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GPIO Name Pin Alternate Functionality / Description
Analog Timers Communication Radio Other
PB15 BUSCY BUSDX
LFXTAL_P
TIM0_CC0 #10
TIM0_CC1 #9
TIM0_CC2 #8
TIM0_CDTI0 #7
TIM0_CDTI1 #6
TIM0_CDTI2 #5
TIM1_CC0 #10
TIM1_CC1 #9
TIM1_CC2 #8
TIM1_CC3 #7
WTIM0_CC0 #19
WTIM0_CC1 #17
WTIM0_CC2 #15
WTIM0_CDTI0 #11
WTIM0_CDTI1 #9
WTIM0_CDTI2 #7
LETIM0_OUT0 #10
LETIM0_OUT1 #9
PCNT0_S0IN #10
PCNT0_S1IN #9
US0_TX #10
US0_RX #9
US0_CLK #8
US0_CS #7
US0_CTS #6
US0_RTS #5
US1_TX #10
US1_RX #9
US1_CLK #8
US1_CS #7
US1_CTS #6
US1_RTS #5
LEU0_TX #10
LEU0_RX #9
I2C0_SDA #10
I2C0_SCL #9
FRC_DCLK #10
FRC_DOUT #9
FRC_DFRAME #8
MODEM_DCLK #10
MODEM_DIN #9
MODEM_DOUT #8
MODEM_ANT0 #7
MODEM_ANT1 #6
CMU_CLK0 #1
PRS_CH6 #10
PRS_CH7 #9
PRS_CH8 #8
PRS_CH9 #7
ACMP0_O #10
ACMP1_O #10
PC6 BUSBY BUSAX
TIM0_CC0 #11
TIM0_CC1 #10
TIM0_CC2 #9
TIM0_CDTI0 #8
TIM0_CDTI1 #7
TIM0_CDTI2 #6
TIM1_CC0 #11
TIM1_CC1 #10
TIM1_CC2 #9
TIM1_CC3 #8
WTIM0_CC0 #26
WTIM0_CC1 #24
WTIM0_CC2 #22
WTIM0_CDTI0 #18
WTIM0_CDTI1 #16
WTIM0_CDTI2 #14
LETIM0_OUT0 #11
LETIM0_OUT1 #10
PCNT0_S0IN #11
PCNT0_S1IN #10
US0_TX #11
US0_RX #10
US0_CLK #9
US0_CS #8
US0_CTS #7
US0_RTS #6
US1_TX #11
US1_RX #10
US1_CLK #9
US1_CS #8
US1_CTS #7
US1_RTS #6
LEU0_TX #11
LEU0_RX #10
I2C0_SDA #11
I2C0_SCL #10
FRC_DCLK #11
FRC_DOUT #10
FRC_DFRAME #9
MODEM_DCLK #11
MODEM_DIN #10
MODEM_DOUT #9
MODEM_ANT0 #8
MODEM_ANT1 #7
CMU_CLK0 #2
CMU_CLKI0 #2
PRS_CH0 #8
PRS_CH9 #11
PRS_CH10 #0
PRS_CH11 #5
ACMP0_O #11
ACMP1_O #11
ETM_TCLK #3
PC7 BUSAY BUSBX
TIM0_CC0 #12
TIM0_CC1 #11
TIM0_CC2 #10
TIM0_CDTI0 #9
TIM0_CDTI1 #8
TIM0_CDTI2 #7
TIM1_CC0 #12
TIM1_CC1 #11
TIM1_CC2 #10
TIM1_CC3 #9
WTIM0_CC0 #27
WTIM0_CC1 #25
WTIM0_CC2 #23
WTIM0_CDTI0 #19
WTIM0_CDTI1 #17
WTIM0_CDTI2 #15
LETIM0_OUT0 #12
LETIM0_OUT1 #11
PCNT0_S0IN #12
PCNT0_S1IN #11
US0_TX #12
US0_RX #11
US0_CLK #10
US0_CS #9
US0_CTS #8
US0_RTS #7
US1_TX #12
US1_RX #11
US1_CLK #10
US1_CS #9
US1_CTS #8
US1_RTS #7
LEU0_TX #12
LEU0_RX #11
I2C0_SDA #12
I2C0_SCL #11
FRC_DCLK #12
FRC_DOUT #11
FRC_DFRAME #10
MODEM_DCLK #12
MODEM_DIN #11
MODEM_DOUT #10
MODEM_ANT0 #9
MODEM_ANT1 #8
CMU_CLK1 #2
PRS_CH0 #9
PRS_CH9 #12
PRS_CH10 #1
PRS_CH11 #0
ACMP0_O #12
ACMP1_O #12
ETM_TD0
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Pin Definitions
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GPIO Name Pin Alternate Functionality / Description
Analog Timers Communication Radio Other
PC8 BUSBY BUSAX
TIM0_CC0 #13
TIM0_CC1 #12
TIM0_CC2 #11
TIM0_CDTI0 #10
TIM0_CDTI1 #9
TIM0_CDTI2 #8
TIM1_CC0 #13
TIM1_CC1 #12
TIM1_CC2 #11
TIM1_CC3 #10
WTIM0_CC0 #28
WTIM0_CC1 #26
WTIM0_CC2 #24
WTIM0_CDTI0 #20
WTIM0_CDTI1 #18
WTIM0_CDTI2 #16
LETIM0_OUT0 #13
LETIM0_OUT1 #12
PCNT0_S0IN #13
PCNT0_S1IN #12
US0_TX #13
US0_RX #12
US0_CLK #11
US0_CS #10
US0_CTS #9
US0_RTS #8
US1_TX #13
US1_RX #12
US1_CLK #11
US1_CS #10
US1_CTS #9
US1_RTS #8
LEU0_TX #13
LEU0_RX #12
I2C0_SDA #13
I2C0_SCL #12
FRC_DCLK #13
FRC_DOUT #12
FRC_DFRAME #11
MODEM_DCLK #13
MODEM_DIN #12
MODEM_DOUT #11
MODEM_ANT0 #10
MODEM_ANT1 #9
PRS_CH0 #10
PRS_CH9 #13
PRS_CH10 #2
PRS_CH11 #1
ACMP0_O #13
ACMP1_O #13
ETM_TD1
PC9 BUSAY BUSBX
TIM0_CC0 #14
TIM0_CC1 #13
TIM0_CC2 #12
TIM0_CDTI0 #11
TIM0_CDTI1 #10
TIM0_CDTI2 #9
TIM1_CC0 #14
TIM1_CC1 #13
TIM1_CC2 #12
TIM1_CC3 #11
WTIM0_CC0 #29
WTIM0_CC1 #27
WTIM0_CC2 #25
WTIM0_CDTI0 #21
WTIM0_CDTI1 #19
WTIM0_CDTI2 #17
LETIM0_OUT0 #14
LETIM0_OUT1 #13
PCNT0_S0IN #14
PCNT0_S1IN #13
US0_TX #14
US0_RX #13
US0_CLK #12
US0_CS #11
US0_CTS #10
US0_RTS #9
US1_TX #14
US1_RX #13
US1_CLK #12
US1_CS #11
US1_CTS #10
US1_RTS #9
LEU0_TX #14
LEU0_RX #13
I2C0_SDA #14
I2C0_SCL #13
FRC_DCLK #14
FRC_DOUT #13
FRC_DFRAME #12
MODEM_DCLK #14
MODEM_DIN #13
MODEM_DOUT #12
MODEM_ANT0 #11
MODEM_ANT1 #10
PRS_CH0 #11
PRS_CH9 #14
PRS_CH10 #3
PRS_CH11 #2
ACMP0_O #14
ACMP1_O #14
ETM_TD2
PC10 BUSBY BUSAX
TIM0_CC0 #15
TIM0_CC1 #14
TIM0_CC2 #13
TIM0_CDTI0 #12
TIM0_CDTI1 #11
TIM0_CDTI2 #10
TIM1_CC0 #15
TIM1_CC1 #14
TIM1_CC2 #13
TIM1_CC3 #12
WTIM0_CC0 #30
WTIM0_CC1 #28
WTIM0_CC2 #26
WTIM0_CDTI0 #22
WTIM0_CDTI1 #20
WTIM0_CDTI2 #18
LETIM0_OUT0 #15
LETIM0_OUT1 #14
PCNT0_S0IN #15
PCNT0_S1IN #14
US0_TX #15
US0_RX #14
US0_CLK #13
US0_CS #12
US0_CTS #11
US0_RTS #10
US1_TX #15
US1_RX #14
US1_CLK #13
US1_CS #12
US1_CTS #11
US1_RTS #10
LEU0_TX #15
LEU0_RX #14
I2C0_SDA #15
I2C0_SCL #14
I2C1_SDA #19
I2C1_SCL #18
FRC_DCLK #15
FRC_DOUT #14
FRC_DFRAME #13
MODEM_DCLK #15
MODEM_DIN #14
MODEM_DOUT #13
MODEM_ANT0 #12
MODEM_ANT1 #11
CMU_CLK1 #3
PRS_CH0 #12
PRS_CH9 #15
PRS_CH10 #4
PRS_CH11 #3
ACMP0_O #15
ACMP1_O #15
ETM_TD3
GPIO_EM4WU12
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Pin Definitions
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GPIO Name Pin Alternate Functionality / Description
Analog Timers Communication Radio Other
PC11 BUSAY BUSBX
TIM0_CC0 #16
TIM0_CC1 #15
TIM0_CC2 #14
TIM0_CDTI0 #13
TIM0_CDTI1 #12
TIM0_CDTI2 #11
TIM1_CC0 #16
TIM1_CC1 #15
TIM1_CC2 #14
TIM1_CC3 #13
WTIM0_CC0 #31
WTIM0_CC1 #29
WTIM0_CC2 #27
WTIM0_CDTI0 #23
WTIM0_CDTI1 #21
WTIM0_CDTI2 #19
LETIM0_OUT0 #16
LETIM0_OUT1 #15
PCNT0_S0IN #16
PCNT0_S1IN #15
US0_TX #16
US0_RX #15
US0_CLK #14
US0_CS #13
US0_CTS #12
US0_RTS #11
US1_TX #16
US1_RX #15
US1_CLK #14
US1_CS #13
US1_CTS #12
US1_RTS #11
LEU0_TX #16
LEU0_RX #15
I2C0_SDA #16
I2C0_SCL #15
I2C1_SDA #20
I2C1_SCL #19
FRC_DCLK #16
FRC_DOUT #15
FRC_DFRAME #14
MODEM_DCLK #16
MODEM_DIN #15
MODEM_DOUT #14
MODEM_ANT0 #13
MODEM_ANT1 #12
CMU_CLK0 #3
PRS_CH0 #13
PRS_CH9 #16
PRS_CH10 #5
PRS_CH11 #4
ACMP0_O #16
ACMP1_O #16
DBG_SWO #3
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Pin Definitions
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6.5 Alternate Functionality Overview
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alter-
nate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings and the associated GPIO
pin. Refer to 6.4 GPIO Functionality Table for a list of functions available on each GPIO pin.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 6.5. Alternate Functionality Overview
Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
ACMP0_O
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP0, digital out-
put.
ACMP1_O
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Analog comparator
ACMP1, digital out-
put.
ADC0_EXTN
0: PA0 Analog to digital
converter ADC0 ex-
ternal reference in-
put negative pin.
ADC0_EXTP
0: PA1 Analog to digital
converter ADC0 ex-
ternal reference in-
put positive pin.
BOOT_RX
0: PF1
Bootloader RX.
BOOT_TX
0: PF0
Bootloader TX.
CMU_CLK0
0: PA1
1: PB15
2: PC6
3: PC11
4: PD9
5: PD14
6: PF2
7: PF7
Clock Management
Unit, clock output
number 0.
CMU_CLK1
0: PA0
1: PB14
2: PC7
3: PC10
4: PD10
5: PD15
6: PF3
7: PF6
Clock Management
Unit, clock output
number 1.
CMU_CLKI0
0: PB13
1: PF7
2: PC6
4: PA5 Clock Management
Unit, clock output
number I0.
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Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
DBG_SWCLKTCK
0: PF0 Debug-interface
Serial Wire clock
input and JTAG
Test Clock.
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull down.
DBG_SWDIOTMS
0: PF1 Debug-interface
Serial Wire data in-
put / output and
JTAG Test Mode
Select.
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull up.
DBG_SWO
0: PF2
1: PB13
2: PD15
3: PC11
Debug-interface
Serial Wire viewer
Output.
Note that this func-
tion is not enabled
after reset, and
must be enabled by
software to be
used.
DBG_TDI
0: PF3 Debug-interface
JTAG Test Data In.
Note that this func-
tion becomes avail-
able after the first
valid JTAG com-
mand is received,
and has a built-in
pull up when JTAG
is active.
DBG_TDO
0: PF2 Debug-interface
JTAG Test Data
Out.
Note that this func-
tion becomes avail-
able after the first
valid JTAG com-
mand is received.
ETM_TCLK 1: PA5
3: PC6
Embedded Trace
Module ETM clock .
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Pin Definitions
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Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
ETM_TD0
3: PC7
Embedded Trace
Module ETM data
0.
ETM_TD1
3: PC8
Embedded Trace
Module ETM data
1.
ETM_TD2
3: PC9
Embedded Trace
Module ETM data
2.
ETM_TD3
3: PC10
Embedded Trace
Module ETM data
3.
FRC_DCLK
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Frame Controller,
Data Sniffer Clock.
FRC_DFRAME
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
15: PD9
16: PD10
17: PD11
18: PD12
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
Frame Controller,
Data Sniffer Frame
active
FRC_DOUT
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
Frame Controller,
Data Sniffer Out-
put.
GPIO_EM4WU0
0: PF2 Pin can be used to
wake the system
up from EM4
GPIO_EM4WU1
0: PF7 Pin can be used to
wake the system
up from EM4
GPIO_EM4WU4
0: PD14 Pin can be used to
wake the system
up from EM4
GPIO_EM4WU8
0: PA3 Pin can be used to
wake the system
up from EM4
GPIO_EM4WU9
0: PB13 Pin can be used to
wake the system
up from EM4
GPIO_EM4WU12
0: PC10 Pin can be used to
wake the system
up from EM4
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.0 | 140
Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
I2C0_SCL
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
I2C0 Serial Clock
Line input / output.
I2C0_SDA
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
I2C0 Serial Data in-
put / output.
I2C1_SCL 18: PC10
19: PC11
I2C1 Serial Clock
Line input / output.
I2C1_SDA
19: PC10
20: PC11
I2C1 Serial Data in-
put / output.
LES_CH1
0: PD9
LESENSE channel
1.
LES_CH2
0: PD10
LESENSE channel
2.
LES_CH3
0: PD11
LESENSE channel
3.
LES_CH4
0: PD12
LESENSE channel
4.
LES_CH5
0: PD13
LESENSE channel
5.
LES_CH6
0: PD14
LESENSE channel
6.
LES_CH7
0: PD15
LESENSE channel
7.
LES_CH8
0: PA0
LESENSE channel
8.
LES_CH9
0: PA1
LESENSE channel
9.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.0 | 141
Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
LES_CH10
0: PA2
LESENSE channel
10.
LES_CH11
0: PA3
LESENSE channel
11.
LES_CH12
0: PA4
LESENSE channel
12.
LES_CH13
0: PA5
LESENSE channel
13.
LETIM0_OUT0
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Low Energy Timer
LETIM0, output
channel 0.
LETIM0_OUT1
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
Low Energy Timer
LETIM0, output
channel 1.
LEU0_RX
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
LEUART0 Receive
input.
LEU0_TX
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
LEUART0 Transmit
output. Also used
as receive input in
half duplex commu-
nication.
LFXTAL_N
0: PB14 Low Frequency
Crystal (typically
32.768 kHz) nega-
tive pin. Also used
as an optional ex-
ternal clock input
pin.
LFXTAL_P
0: PB15 Low Frequency
Crystal (typically
32.768 kHz) posi-
tive pin.
MODEM_ANT0
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
14: PD9
15: PD10
16: PD11
17: PD12
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
MODEM antenna
control output 0,
used for antenna
diversity.
MODEM_ANT1
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
11: PC10
12: PC11
13: PD9
14: PD10
15: PD11
16: PD12
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
MODEM antenna
control output 1,
used for antenna
diversity.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.0 | 142
Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
MODEM_DCLK
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
MODEM data clock
out.
MODEM_DIN
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
MODEM data in.
MODEM_DOUT
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
15: PD9
16: PD10
17: PD11
18: PD12
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
MODEM data out.
OPA0_N
0: PA4 Operational Amplifi-
er 0 external nega-
tive input.
OPA0_P
0: PA2 Operational Amplifi-
er 0 external posi-
tive input.
OPA1_N
0: PD15 Operational Amplifi-
er 1 external nega-
tive input.
OPA1_P
0: PD13 Operational Amplifi-
er 1 external posi-
tive input.
OPA2_N
0: PB13 Operational Amplifi-
er 2 external nega-
tive input.
OPA2_OUT
0: PB12
Operational Amplifi-
er 2 output.
OPA2_P
0: PB11 Operational Amplifi-
er 2 external posi-
tive input.
PCNT0_S0IN
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Pulse Counter
PCNT0 input num-
ber 0.
PCNT0_S1IN
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
Pulse Counter
PCNT0 input num-
ber 1.
PRS_CH0
0: PF0
1: PF1
2: PF2
3: PF3
4: PF4
5: PF5
6: PF6
7: PF7
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11 Peripheral Reflex
System PRS, chan-
nel 0.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.0 | 143
Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
PRS_CH1
0: PF1
1: PF2
2: PF3
3: PF4
4: PF5
5: PF6
6: PF7
7: PF0
Peripheral Reflex
System PRS, chan-
nel 1.
PRS_CH2
0: PF2
1: PF3
2: PF4
3: PF5
4: PF6
5: PF7
6: PF0
7: PF1
Peripheral Reflex
System PRS, chan-
nel 2.
PRS_CH3
0: PF3
1: PF4
2: PF5
3: PF6
4: PF7
5: PF0
6: PF1
7: PF2
8: PD9
9: PD10
10: PD11
11: PD12
12: PD13
13: PD14
14: PD15
Peripheral Reflex
System PRS, chan-
nel 3.
PRS_CH4
0: PD9
1: PD10
2: PD11
3: PD12
4: PD13
5: PD14
6: PD15
Peripheral Reflex
System PRS, chan-
nel 4.
PRS_CH5
0: PD10
1: PD11
2: PD12
3: PD13
4: PD14
5: PD15
6: PD9
Peripheral Reflex
System PRS, chan-
nel 5.
PRS_CH6
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PD9
12: PD10
13: PD11
14: PD12
15: PD13
16: PD14
17: PD15 Peripheral Reflex
System PRS, chan-
nel 6.
PRS_CH7
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PA0
Peripheral Reflex
System PRS, chan-
nel 7.
PRS_CH8
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PA0
10: PA1
Peripheral Reflex
System PRS, chan-
nel 8.
PRS_CH9
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PA0
9: PA1
10: PA2
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11 Peripheral Reflex
System PRS, chan-
nel 9.
PRS_CH10
0: PC6
1: PC7
2: PC8
3: PC9
4: PC10
5: PC11 Peripheral Reflex
System PRS, chan-
nel 10.
PRS_CH11
0: PC7
1: PC8
2: PC9
3: PC10
4: PC11
5: PC6 Peripheral Reflex
System PRS, chan-
nel 11.
TIM0_CC0
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Timer 0 Capture
Compare input /
output channel 0.
TIM0_CC1
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
Timer 0 Capture
Compare input /
output channel 1.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.0 | 144
Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
TIM0_CC2
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
15: PD9
16: PD10
17: PD11
18: PD12
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
Timer 0 Capture
Compare input /
output channel 2.
TIM0_CDTI0
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
14: PD9
15: PD10
16: PD11
17: PD12
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
Timer 0 Compli-
mentary Dead Time
Insertion channel 0.
TIM0_CDTI1
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
11: PC10
12: PC11
13: PD9
14: PD10
15: PD11
16: PD12
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
Timer 0 Compli-
mentary Dead Time
Insertion channel 1.
TIM0_CDTI2
0: PA5
1: PB11
2: PB12
3: PB13
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
10: PC10
11: PC11
12: PD9
13: PD10
14: PD11
15: PD12
16: PD13
17: PD14
18: PD15
19: PF0
20: PF1
21: PF2
22: PF3
23: PF4
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
Timer 0 Compli-
mentary Dead Time
Insertion channel 2.
TIM1_CC0
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
Timer 1 Capture
Compare input /
output channel 0.
TIM1_CC1
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
Timer 1 Capture
Compare input /
output channel 1.
TIM1_CC2
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
15: PD9
16: PD10
17: PD11
18: PD12
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
Timer 1 Capture
Compare input /
output channel 2.
TIM1_CC3
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
14: PD9
15: PD10
16: PD11
17: PD12
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
Timer 1 Capture
Compare input /
output channel 3.
US0_CLK
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
15: PD9
16: PD10
17: PD11
18: PD12
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
USART0 clock in-
put / output.
US0_CS
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
14: PD9
15: PD10
16: PD11
17: PD12
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
USART0 chip se-
lect input / output.
US0_CTS
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
11: PC10
12: PC11
13: PD9
14: PD10
15: PD11
16: PD12
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART0 Clear To
Send hardware
flow control input.
US0_RTS
0: PA5
1: PB11
2: PB12
3: PB13
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
10: PC10
11: PC11
12: PD9
13: PD10
14: PD11
15: PD12
16: PD13
17: PD14
18: PD15
19: PF0
20: PF1
21: PF2
22: PF3
23: PF4
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
USART0 Request
To Send hardware
flow control output.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
silabs.com | Building a more connected world. Rev. 1.0 | 145
Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
US0_RX
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
USART0 Asynchro-
nous Receive.
USART0 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US0_TX
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
USART0 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
USART0 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
US1_CLK
0: PA2
1: PA3
2: PA4
3: PA5
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PC6
10: PC7
11: PC8
12: PC9
13: PC10
14: PC11
15: PD9
16: PD10
17: PD11
18: PD12
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
26: PF4
27: PF5
28: PF6
29: PF7
30: PA0
31: PA1
USART1 clock in-
put / output.
US1_CS
0: PA3
1: PA4
2: PA5
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PC6
9: PC7
10: PC8
11: PC9
12: PC10
13: PC11
14: PD9
15: PD10
16: PD11
17: PD12
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
25: PF4
26: PF5
27: PF6
28: PF7
29: PA0
30: PA1
31: PA2
USART1 chip se-
lect input / output.
US1_CTS
0: PA4
1: PA5
2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
7: PC6
8: PC7
9: PC8
10: PC9
11: PC10
12: PC11
13: PD9
14: PD10
15: PD11
16: PD12
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
24: PF4
25: PF5
26: PF6
27: PF7
28: PA0
29: PA1
30: PA2
31: PA3
USART1 Clear To
Send hardware
flow control input.
US1_RTS
0: PA5
1: PB11
2: PB12
3: PB13
4: PB14
5: PB15
6: PC6
7: PC7
8: PC8
9: PC9
10: PC10
11: PC11
12: PD9
13: PD10
14: PD11
15: PD12
16: PD13
17: PD14
18: PD15
19: PF0
20: PF1
21: PF2
22: PF3
23: PF4
24: PF5
25: PF6
26: PF7
27: PA0
28: PA1
29: PA2
30: PA3
31: PA4
USART1 Request
To Send hardware
flow control output.
US1_RX
0: PA1
1: PA2
2: PA3
3: PA4
4: PA5
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PC6
11: PC7
12: PC8
13: PC9
14: PC10
15: PC11
16: PD9
17: PD10
18: PD11
19: PD12
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
27: PF4
28: PF5
29: PF6
30: PF7
31: PA0
USART1 Asynchro-
nous Receive.
USART1 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US1_TX
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
11: PC6
12: PC7
13: PC8
14: PC9
15: PC10
16: PC11
17: PD9
18: PD10
19: PD11
20: PD12
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
28: PF4
29: PF5
30: PF6
31: PF7
USART1 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
USART1 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
US2_CLK
12: PF0
13: PF1
14: PF3
15: PF4
16: PF5
17: PF6
18: PF7 30: PA5
USART2 clock in-
put / output.
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Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
US2_CS
11: PF0
12: PF1
13: PF3
14: PF4
15: PF5
16: PF6
17: PF7 29: PA5 USART2 chip se-
lect input / output.
US2_CTS 10: PF0
11: PF1
12: PF3
13: PF4
14: PF5
15: PF6
16: PF7 28: PA5 USART2 Clear To
Send hardware
flow control input.
US2_RTS 9: PF0
10: PF1
11: PF3
12: PF4
13: PF5
14: PF6
15: PF7 27: PA5
USART2 Request
To Send hardware
flow control output.
US2_RX
13: PF0
14: PF1
15: PF3
16: PF4
17: PF5
18: PF6
19: PF7 31: PA5
USART2 Asynchro-
nous Receive.
USART2 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US2_TX
0: PA5
14: PF0
15: PF1
16: PF3
17: PF4
18: PF5
19: PF6
20: PF7 USART2 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
USART2 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
VDAC0_EXT
0: PA1 Digital to analog
converter VDAC0
external reference
input pin.
VDAC0_OUT0 /
OPA0_OUT
0: PA3 Digital to Analog
Converter DAC0
output channel
number 0.
VDAC0_OUT0AL
T / OPA0_OUT-
ALT
0: PA5
1: PD13
2: PD15
Digital to Analog
Converter DAC0 al-
ternative output for
channel 0.
VDAC0_OUT1 /
OPA1_OUT
0: PD14 Digital to Analog
Converter DAC0
output channel
number 1.
VDAC0_OUT1AL
T / OPA1_OUT-
ALT
0: PD12
1: PA2
2: PA4
Digital to Analog
Converter DAC0 al-
ternative output for
channel 1.
WTIM0_CC0
0: PA0
1: PA1
2: PA2
3: PA3
4: PA4
5: PA5
15: PB11
16: PB12
17: PB13
18: PB14
19: PB15
26: PC6
27: PC7
28: PC8
29: PC9
30: PC10
31: PC11
Wide timer 0 Cap-
ture Compare in-
put / output channel
0.
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Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
WTIM0_CC1
0: PA2
1: PA3
2: PA4
3: PA5
13: PB11
14: PB12
15: PB13
16: PB14
17: PB15
24: PC6
25: PC7
26: PC8
27: PC9
28: PC10
29: PC11
31: PD9
Wide timer 0 Cap-
ture Compare in-
put / output channel
1.
WTIM0_CC2
0: PA4
1: PA5
11: PB11
12: PB12
13: PB13
14: PB14
15: PB15
22: PC6
23: PC7
24: PC8
25: PC9
26: PC10
27: PC11
29: PD9
30: PD10
31: PD11
Wide timer 0 Cap-
ture Compare in-
put / output channel
2.
WTIM0_CDTI0
7: PB11
8: PB12
9: PB13
10: PB14
11: PB15
18: PC6
19: PC7
20: PC8
21: PC9
22: PC10
23: PC11
25: PD9
26: PD10
27: PD11
28: PD12
29: PD13
30: PD14
31: PD15
Wide timer 0 Com-
plimentary Dead
Time Insertion
channel 0.
WTIM0_CDTI1 5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
16: PC6
17: PC7
18: PC8
19: PC9
20: PC10
21: PC11
23: PD9
24: PD10
25: PD11
26: PD12
27: PD13
28: PD14
29: PD15
30: PF0
31: PF1
Wide timer 0 Com-
plimentary Dead
Time Insertion
channel 1.
WTIM0_CDTI2
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
14: PC6
15: PC7
16: PC8
17: PC9
18: PC10
19: PC11
21: PD9
22: PD10
23: PD11
24: PD12
25: PD13
26: PD14
27: PD15
28: PF0
29: PF1
30: PF2
31: PF3
Wide timer 0 Com-
plimentary Dead
Time Insertion
channel 2.
Certain alternate function locations may have non-interference priority. These locations will take precedence over any other functions
selected on that pin (i.e. another alternate function enabled to the same pin inadvertently).
Some alternate functions may also have high speed priority on certain locations. These locations ensure the fastest possible paths to
the pins for timing-critical signals.
The following table lists the alternate functions and locations with special priority.
Table 6.6. Alternate Functionality Priority
Alternate Functionality Location Priority
CMU_CLKI0 1: PF7 High Speed
6.6 Analog Port (APORT) Client Maps
The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,
DACs, etc. The APORT consists of a set of shared buses, switches, and control logic needed to configurably implement the signal rout-
ing. A complete description of APORT functionality can be found in the Reference Manual.
Client maps for each analog circuit using the APORT are shown in the following tables. The maps are organized by bus, and show the
peripheral's port connection, the shared bus, and the connection from specific bus channel numbers to GPIO pins.
In general, enumerations for the pin selection field in an analog peripheral's register can be determined by finding the desired pin con-
nection in the table and then combining the value in the Port column (APORT__), and the channel identifier (CH__). For example, if pin
PF7 is available on port APORT2X as CH23, the register field enumeration to connect to PF7 would be APORT2XCH23. The shared
bus used by this connection is indicated in the Bus column.
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Table 6.7. ACMP0 Bus and Pin Mapping
Port
Bus
CH31
CH30
CH29
CH28
CH27
CH26
CH25
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
APORT1X
BUSAX
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT1Y
BUSAY
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT2X
BUSBX
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT2Y
BUSBY
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT3X
BUSCX
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
APORT3Y
BUSCY
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
APORT4X
BUSDX
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
APORT4Y
BUSDY
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
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Table 6.8. ACMP1 Bus and Pin Mapping
Port
Bus
CH31
CH30
CH29
CH28
CH27
CH26
CH25
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
APORT1X
BUSAX
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT1Y
BUSAY
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT2X
BUSBX
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT2Y
BUSBY
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT3X
BUSCX
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
APORT3Y
BUSCY
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
APORT4X
BUSDX
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
APORT4Y
BUSDY
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
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Table 6.9. ADC0 Bus and Pin Mapping
Port
Bus
CH31
CH30
CH29
CH28
CH27
CH26
CH25
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
APORT1X
BUSAX
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT1Y
BUSAY
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT2X
BUSBX
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT2Y
BUSBY
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT3X
BUSCX
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
APORT3Y
BUSCY
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
APORT4X
BUSDX
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
APORT4Y
BUSDY
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
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Table 6.10. CSEN Bus and Pin Mapping
Port
Bus
CH31
CH30
CH29
CH28
CH27
CH26
CH25
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
CEXT
APORT1X
BUSAX
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT1Y
BUSAY
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT3X
BUSCX
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
APORT3Y
BUSCY
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
CEXT_SENSE
APORT2X
BUSBX
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT2Y
BUSBY
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT4X
BUSDX
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
APORT4Y
BUSDY
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
Table 6.11. IDAC0 Bus and Pin Mapping
Port
Bus
CH31
CH30
CH29
CH28
CH27
CH26
CH25
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
APORT1X
BUSCX
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
APORT1Y
BUSCY
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
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Table 6.12. VDAC0 / OPA Bus and Pin Mapping
Port
Bus
CH31
CH30
CH29
CH28
CH27
CH26
CH25
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
OPA0_N
APORT1Y
BUSAY
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT2Y
BUSBY
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT3Y
BUSCY
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
APORT4Y
BUSDY
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
OPA0_P
APORT1X
BUSAX
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT2X
BUSBX
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT3X
BUSCX
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
APORT4X
BUSDX
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
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Port
Bus
CH31
CH30
CH29
CH28
CH27
CH26
CH25
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
OPA1_N
APORT1Y
BUSAY
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT2Y
BUSBY
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT3Y
BUSCY
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
APORT4Y
BUSDY
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
OPA1_P
APORT1X
BUSAX
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT2X
BUSBX
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT3X
BUSCX
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
APORT4X
BUSDX
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
OPA2_N
APORT1Y
BUSAY
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT2Y
BUSBY
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT3Y
BUSCY
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
APORT4Y
BUSDY
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
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Port
Bus
CH31
CH30
CH29
CH28
CH27
CH26
CH25
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
OPA2_OUT
APORT1Y
BUSAY
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT2Y
BUSBY
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT3Y
BUSCY
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
APORT4Y
BUSDY
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
OPA2_P
APORT1X
BUSAX
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT2X
BUSBX
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT3X
BUSCX
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
APORT4X
BUSDX
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
VDAC0_OUT0 / OPA0_OUT
APORT1Y
BUSAY
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT2Y
BUSBY
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT3Y
BUSCY
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
APORT4Y
BUSDY
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
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Port
Bus
CH31
CH30
CH29
CH28
CH27
CH26
CH25
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
VDAC0_OUT1 / OPA1_OUT
APORT1Y
BUSAY
PF7
PF5
PF3
PF1
PC11
PC9
PC7
APORT2Y
BUSBY
PF6
PF4
PF2
PF0
PC10
PC8
PC6
APORT3Y
BUSCY
PB15
PB13
PB11
PA5
PA3
PA1
PD15
PD13
PD11
PD9
APORT4Y
BUSDY
PB14
PB12
PA4
PA2
PA0
PD14
PD12
PD10
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Pin Definitions
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7. QFN48 Package Specifications
7.1 QFN48 Package Dimensions
Figure 7.1. QFN48 Package Drawing
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
QFN48 Package Specifications
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Table 7.1. QFN48 Package Dimensions
Dimension Min Typ Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.18 0.25 0.30
D 6.90 7.00 7.10
E 6.90 7.00 7.10
D2 5.15 5.30 5.45
E2 5.15 5.30 5.45
e 0.50 BSC
L 0.30 0.40 0.50
K 0.20 — —
R 0.09 — —
aaa 0.15
bbb 0.10
ccc 0.10
ddd 0.05
eee 0.08
fff 0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
QFN48 Package Specifications
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7.2 QFN48 PCB Land Pattern
Figure 7.2. QFN48 PCB Land Pattern Drawing
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
QFN48 Package Specifications
silabs.com | Building a more connected world. Rev. 1.0 | 159
Table 7.2. QFN48 PCB Land Pattern Dimensions
Dimension Typ
S1 6.01
S 6.01
L1 4.70
W1 4.70
e 0.50
W 0.26
L 0.86
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 4x4 array of 0.75 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
QFN48 Package Specifications
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7.3 QFN48 Package Marking
EFR32
PPPPPPPPPP
YYWWTTTTTT
Figure 7.3. QFN48 Package Marking
The package marking consists of:
• PPPPPPPPP – The part number designation.
1. Family Code (B | M | F)
2. G (Gecko)
3. Series (1, 2,...)
4. Device Configuration (1, 2,...)
5. Performance Grade (P | B | V)
6. Feature Code (1 to 7)
7. TRX Code (3 = TXRX | 2= RX | 1 = TX)
8. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)
9. Flash (J = 1024K | H = 512K | G = 256K | F = 128K | E = 64K | D = 32K)
10. Temperature Grade (G = -40 to 85 | I = -40 to 125)
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
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QFN48 Package Specifications
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8. Revision History
8.1 Revision 1.0
2017-08-02
• Updated spcification tables with latest characterization values and production test min/max limits.
• Added high-temperature OPNs and associated specifications.
• Added performance specifications and supported radio modulations/protocols to Feature List.
• Clarified / corrected energy mode mentions in RTCC and Opamp sections of the System Overview.
•Sub-GHz RF Transmitter characteristics for 868 MHz Band Electrical Specifications Table:
• POUTVAR_V_NODCDC specification symbol corrected to POUTVAR_V
• POUTVAR_F_NODCDC specification symbol corrected to POUTVAR_F
•Sub-GHz RF Transmitter characteristice for 433 MHz Band Electrical Specifications Table: POTMIN specification symbol correc-
ted to POUTMIN
•Analog to Digital Converter (ADC) Electrical Specifications Table: Added footnote for clarification of input voltage limits.
•Typical Sub-GHz Impedance-matching network circuits Figure: Corrected split between two examples from 450 MHz to 500
MHz.
•RF Transmitter General Characteristics for 2.4 GHz Band Electrical Specifications Table:
• Test Conditions changed from "19.5 dBm" to "19 dBm" and from "10.5 dBm" to "10 dBm"
•RF Receiver Characteristics for Bluetooth Low Energy in the 2.4GHz Band, 1 Mbps Data Rate Electrical Specifications Table:
• Sensitivity (SENS) for Reference Signal changed from "-95.8 dBm" to "-94.8 dBm"
8.2 Revision 0.5
2017-04-25
• Added RFSENSE section to System Overview.
• Updated specification tables with latest characterization results.
• Split 2.4 GHz 2GFSK tables into separate tables for 1 Mbps, 2 Mbps, 500kbps, and 125kbps data rates.
• Added typical performance graphs.
• Condensed pin function tables with new formatting.
• Added APORT Connection Diagram.
• Corrected package marking flash size designator.
• Removed OPNs for QFN32 package options.
8.3 Revision 0.1
2016-11-15
Initial release.
EFR32FG13 Flex Gecko Proprietary Protocol SoC Family Data Sheet
Revision History
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Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
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