INTEGRATED CIRCUITS DATA SHEET TDA8766 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter Product specification Supersedes data of 2001 Apr 19 2002 Jul 02 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 FEATURES APPLICATIONS * 10-bit resolution High-speed analog-to-digital conversion for: * 3.0 to 5.25 V operation * Video data digitizing * Sampling rate up to 20 MHz * Camera * DC sampling allowed * Camcorder * High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 1.0 MHz; full-scale input at fclk = 20 MHz) * Radio communication. GENERAL DESCRIPTION * In-Range (IR) CMOS output The TDA8766 is a 10-bit high-speed Analog-to-Digital Converter (ADC) for professional video and other applications. It converts with 3.0 to 5.25 V operation the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 20 MHz. All digital inputs and outputs are CMOS compatible. A standby mode allows reduction of the device power consumption down to 4 mW. * CMOS/TTL compatible digital inputs and outputs * External reference voltage regulator * Power dissipation only 53 mW (typical value) * Low analog input capacitance, no buffer amplifier required * Standby mode * No sample-and-hold circuit required. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDA analog supply voltage 3.0 3.3 5.25 V VDDD1 digital supply voltage 1 3.0 3.3 5.25 V VDDD2 digital supply voltage 2 3.0 3.3 5.25 V VDDO output stages supply voltage 3.0 3.3 5.25 V IDDA analog supply current - 7.5 10 mA IDDD digital supply current - 7.5 10 mA IDDO output stages supply current fclk = 20 MHz; CL = 20 pF; ramp input - 1 2 mA INL integral non-linearity fclk = 20 MHz; ramp input - 1 2 LSB DNL differential non-linearity fclk = 20 MHz; ramp input - 0.25 0.7 LSB fclk(max) maximum clock frequency 20 - - MHz Ptot total power dissipation VDDA = VDDD = VDDO = 3.3 V - 53 73 mW ORDERING INFORMATION TYPE NUMBER TDA8766G 2002 Jul 02 PACKAGE NAME DESCRIPTION VERSION LQFP32 plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm SOT401-1 2 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 BLOCK DIAGRAM handbook, full pagewidth V DDA CLK VDDD2 OE 7 5 18 16 6 CLOCK DRIVER STDBY TDA8766 V RT 15 1 D9 31 D8 MSB 30 D7 RLAD analog voltage input VI 29 D6 28 D5 14 ANALOG -TO - DIGITAL CONVERTER CMOS OUTPUTS LATCHES 27 D4 data outputs 26 D3 V RM 11 25 D2 23 D1 22 D0 20 VRB 10 CMOS OUTPUT IN-RANGE LATCH 2 4 9 VSSA analog ground 19 VSSD2 21 VSSO digital ground 2 output ground Fig.1 Block diagram. 2002 Jul 02 3 3 VSSD1 digital ground 1 MLC853 LSB VDDO IR output VDDD1 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 PINNING SYMBOL PIN SYMBOL PIN DESCRIPTION DESCRIPTION n.c. 17 not connected D9 1 data output; bit 9 (MSB) VDDD2 18 digital supply voltage 2 (3.0 to 5.25 V) IR 2 in-range data output VSSD2 19 digital ground 2 VSSD1 3 digital ground 1 VDDO 20 VDDD1 4 digital supply voltage 1 (3.0 to 5.25 V) positive supply voltage for output stage (3.0 to 5.25 V) CLK 5 clock input VSSO 21 output stage ground 22 data output; bit 0 (LSB) STDBY 6 standby mode input D0 VDDA 7 analog supply voltage (3.0 to 5.25 V) D1 23 data output; bit 1 n.c. 8 not connected n.c. 24 not connected VSSA 9 analog ground D2 25 data output; bit 2 26 data output; bit 3 VRB 10 reference voltage BOTTOM input D3 VRM 11 reference voltage MIDDLE input D4 27 data output; bit 4 n.c. 12 not connected D5 28 data output; bit 5 29 data output; bit 6 data output; bit 7 VRT 15 reference voltage TOP input D8 31 data output; bit 8 output enable input (active LOW) n.c. 32 not connected handbook, full pagewidth D9 1 24 n.c. IR 2 23 D1 VSSD1 3 22 D0 VDDD1 4 CLK 5 20 VDDO STDBY 6 19 VSSD2 VDDA 7 18 VDDD2 n.c. 8 17 n.c. 21 VSSO Fig.2 Pin configuration. 2002 Jul 02 4 OE 16 VRT 15 VI 14 n.c. 13 n.c. 12 VSSA 9 TDA8766 VRM 11 16 VRB 10 OE 25 D2 30 26 D3 D7 27 D4 analog voltage input 28 D5 14 29 D6 VI 30 D7 not connected 31 D8 13 32 n.c. n.c. D6 MLC854 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDA analog supply voltage note 1 -0.3 +7.0 V VDDD digital supply voltage note 1 -0.3 +7.0 V VDDO output stages supply voltage note 1 -0.3 +7.0 V VDD supply voltage difference VDDA - VDDD -1.0 +4.0 V VDDD - VDDO -1.0 +4.0 V -1.0 +4.0 V VI input voltage VDDA - VDDO referenced to VSSA -0.3 +7.0 V Vi(p-p) AC input voltage for switching (peak-to-peak value) referenced to VSSD - VDDD V IO output current - 10 mA Tstg storage temperature -55 +150 C Tamb ambient temperature -20 +75 C Tj junction temperature - 150 C Note 1. The supply voltages VDDA, VDDD and VDDO may have any value between -0.3 and +7.0 V provided that the supply voltage differences VDD are respected. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(jj-a) 2002 Jul 02 PARAMETER CONDITIONS thermal resistance from junction to ambient 5 in free air VALUE UNIT 90 K/W Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 CHARACTERISTICS VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO short-circuited together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 to 70 C; typical values measured at Tamb = 25 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA analog supply voltage 3.0 3.3 5.25 V VDDD1 digital supply voltage 1 3.0 3.3 5.25 V VDDD2 digital supply voltage 2 3.0 3.3 5.25 V VDDO output stages supply voltage 3.0 3.3 5.25 V VDD voltage difference VDDA - VDDD -0.2 - +0.2 V VDDA - VDDO -0.2 - +0.2 V VDDD - VDDO -0.2 - +0.2 V IDDA analog supply current - 7.5 10 mA IDDD digital supply current - 7.5 10 mA IDDO output stages supply current fclk = 20 MHz; ramp input; CL = 20 pF - 1 2 mA Ptot total power dissipation operating; VDD = 3.3 V - 53 73 mW standby mode - 4 - mW 0 - 0.3VDDD V Inputs CLOCK INPUT CLK (REFERENCED TO VSSD); note 1 VIL LOW-level input voltage VIH HIGH-level input voltage VDDD 3.6 V 0.6VDDD - VDDD V VDDD = 3.3 V 0.7VDDD - VDDD V IIL LOW-level input current VCLK = 0.3VDDD -1 0 +1 A IIH HIGH-level input current VCLK = 0.7VDDD - - 5 A Zi input impedance fclk = 20 MHz - 4 - k Ci input capacitance fclk = 20 MHz - 3 - pF 0 - 0.3VDDD V 0.6VDDD - VDDD V INPUTS OE AND STDBY (REFERENCED TO VSSD); see Tables 1 and 2 VIL LOW-level input voltage VIH HIGH-level input voltage VDDD = 3.3 V 0.7VDDD - VDDD V IIL LOW-level input current VIL = 0.3 VDDD -1 - - A IIH HIGH-level input current VIH = 0.7 VDDD - - 1 A VDDD 3.6 V ANALOG INPUT VI (REFERENCED TO VSSA) IIL LOW-level input current VI = VRB - 0 - A IIH HIGH-level input current VI = VRT - 35 - A Zi input impedance fi = 1 MHz - 5 - k Ci input capacitance fi = 1 MHz - 8 - pF 2002 Jul 02 6 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter SYMBOL TDA8766 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Reference voltages for resistor ladder; see Table 3 VRB reference voltage BOTTOM 1.1 1.2 - V VRT reference voltage TOP 3.0 3.3 VDDA V Vdiff(ref) differential reference voltage VRT - VRB 1.9 2.1 3.0 V Iref reference current - 7.2 - mA RLAD ladder resistance - 290 - TCRLAD temperature coefficient of ladder resistance - 539 - m/K - 1860 - ppm Voffset(B) offset voltage BOTTOM note 2 - 135 - mV Voffset(T) offset voltage TOP note 2 - 135 - mV VI(p-p) analog input voltage (peak-to-peak value) note 3 1.66 1.83 2.35 V Outputs DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO VSSD) VOL LOW-level output voltage IO = 1 mA 0 - 0.5 V VOH HIGH-level output voltage IO = -1 mA VDDO - 0.5 - VDDO V IOZ output current in 3-state mode 0.5 V < VO < VDDO -20 - +20 A Switching characteristics CLOCK INPUT CLK; see Fig.4; note 1 fclk(max) maximum clock frequency 20 - - MHz tCPH clock pulse width HIGH 15 - - ns tCPL clock pulse width LOW 15 - - ns Analog signal processing (fclk = 20 MHz) LINEARITY INL integral non-linearity ramp input; see Fig.6 - 1 2 LSB DNL differential non-linearity ramp input; see Fig.7 - 0.25 0.7 LSB INPUT SET RESPONSE; see Fig.8; note 4 tSTLH analog input settling time LOW-to-HIGH full-scale square wave - 4 6 ns tSTHL analog input settling time HIGH-to-LOW full-scale square wave - 4 6 ns fi = 1 MHz - -63 - dB without harmonics; fi = 1 MHz - 60 - dB HARMONICS; see Fig.9; note 5 THD total harmonic distortion SIGNAL-TO-NOISE RATIO; see Fig.9; note 5 S/N 2002 Jul 02 signal-to-noise ratio (full-scale) 7 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter SYMBOL TDA8766 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT EFFECTIVE BITS; see Fig.9; note 5 EB effective bits fi = 300 kHz - 9.5 - bits fi = 1 MHz - 9.3 - bits fi = 3.58 MHz - 8.0 - bits Timing (fclk = 20 MHz; CL = 20 pF); see Fig.4; note 6 tds sampling delay time - - 5 ns th output hold time 5 - - ns td output delay time VDDO = 4.75 V 8 12 15 ns VDDO = 3.15 V 8 17 20 ns 3-state output delay times; see Fig.5 tdZH enable HIGH - 14 18 ns tdZL enable LOW - 16 20 ns tdHZ disable HIGH - 16 20 ns tdLZ disable LOW - 14 18 ns Standby mode output delay times td(stb)LH standby LOW-to-HIGH transition - - 200 ns td(stb)HL start-up HIGH-to-LOW transition - - 500 ns Notes 1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. 2. Analog input voltages producing code 0 up to and including 1023: a) Voffset(B) (offset voltage BOTTOM) is the difference between the analog input which produces data equal to 00 and the reference voltage BOTTOM (VRB) at Tamb = 25 C. b) Voffset(T) (offset voltage TOP) is the difference between VRT (reference voltage TOP) and the analog input which produces data outputs equal to 1023 at Tamb = 25 C. 3. In order to ensure the optimum linearity performance of such converter architecture, the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3. V RT - V RB a) The current flowing into the resistor ladder is I L = ----------------------------------------- and the full-scale input range at the converter, R OB + R L + R OT RL to cover code 0 to code 1023, is V I = R L x I L = ------------------------------------------ x ( V RT - V RB ) = 0.871 x ( V RT - V RB ) R OB + R L + R OT b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio RL ----------------------------------------- will be kept reasonably constant from device to device. Consequently variation of the output R OB + R L + R OT codes at a given input voltage depends mainly on the difference VRT - VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. 4. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input change (square-wave signal) in order to sample the signal and obtain correct output data. 2002 Jul 02 8 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 5. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8k acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (Nyquist frequency). Conversion to signal-to-noise ratio: S/N = EB x 6.02 + 1.76 dB. 6. Output data acquisition: the output data is available after the maximum delay time of td. handbook, halfpage VRT ROT code 1023 RL VRM IL RLAD code 0 ROB VRB MGD281 Fig.3 Converter reference resistor ladder. 2002 Jul 02 9 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter Table 1 Mode selection OE Table 2 D9 to D0 IR 1 high impedance high impedance 0 active (binary) active Standby selection STDBY Table 3 TDA8766 D9 to D0 IDDA + IDDD 1 last logic state 1.2 mA (typical value) 0 active 15 mA (typical value) Output coding and input voltage (typical values; referenced to VSSA) BINARY OUTPUT BITS VI(p-p) IR Underflow <1.335 V 0 STEP D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 1.335 V 1 0 0 0 0 0 0 0 0 0 0 1 : 1 0 0 0 0 0 0 0 0 0 1 : : : : : : : : : : : : : 1022 : 1 1 1 1 1 1 1 1 1 1 0 1023 3.165 V 1 1 1 1 1 1 1 1 1 1 1 Overflow >3.165 V 0 1 1 1 1 1 1 1 1 1 1 t CPL handbook, full pagewidth t CPH 50% CLK sample N sample N + 1 sample N + 2 Vl t ds DATA D0 to D9 th VDDO DATA N-2 DATA N-1 DATA N DATA N+1 50% 0V td Fig.4 Timing diagram. 2002 Jul 02 10 MGD346 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter handbook, full pagewidth TDA8766 V DDD 50 % OE t dHZ t dZH HIGH 90 % output data 50 % t dLZ LOW t dZL HIGH output data 50 % LOW 10 % V DDD 3.3 k S1 TDA8766 20 pF TEST S1 t dLZ t dZL VDDD VDDD t dHZ GND t dZH GND OE MLC855 fOE = 100 kHz. Fig.5 Timing diagram and test conditions of 3-state output delay time. 2002 Jul 02 11 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 MLD115 0.6 handbook, full pagewidth A (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 0 200 400 600 800 1000 f (codes) 1100 1023 Fig.6 Typical Integral Non-Linearity (INL) performance. MLD116 0.25 handbook, full pagewidth A (LSB) 0.15 0.05 -0.05 -0.15 -0.25 0 200 400 600 800 1000 f (codes) Fig.7 Typical Differential Non-Linearity (DNL) performance. 2002 Jul 02 12 1023 1100 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 t STHL t STLH handbook, full pagewidth code 1023 VI 50 % 50 % code 0 5 ns 5 ns CLK 50 % 50 % 2 ns MBD875 2 ns Fig.8 Analog input settling-time diagram. MLD117 0 handbook, full pagewidth A (dB) 20 40 60 80 100 120 0 1.25 2.5 3.76 5.01 6.26 7.51 8.76 10 f (MHz) Effective bits: 9.59; THD = -76.60 dB. Harmonic levels (dB): 2nd = -81.85; 3rd = -87.56; 4th = -88.81; 5th = -88.96; 6th = -79.58. Fig.9 Typical fast Fourier transform (fclk = 20 MHz; fi = 1 MHz). 2002 Jul 02 13 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 INTERNAL PIN CONFIGURATION handbook, halfpage handbook, halfpage VDDO V DDA D9 to D0, IR VI VSSO VSSA MLC856 MLC857 Fig.10 D9 to D0 and IR outputs. Fig.11 VI analog input. handbook, halfpage handbook, halfpage VDDA VDDO VRT VRM OE, STDBY VRB VSSA VSSO MLC859 MLC858 Fig.12 OE and STDBY inputs. 2002 Jul 02 R LAD Fig.13 VRB, VRM and VRT inputs. 14 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 V DDD handbook, halfpage 1/2V CLK DDD VSSD MLC860 Fig.14 CLK input. 2002 Jul 02 15 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 APPLICATION INFORMATION Additional application information will be supplied upon request (please quote number "AN00014"). handbook, full pagewidth (2) n.c. 32 D9 IR V SSD1 VDDD1 CLK STDBY VDDA D8 31 D7 30 D6 29 D5 D4 28 27 D3 26 D2 25 (2) 1 24 2 23 3 22 4 21 TDA8766 5 20 6 19 7 18 8 17 (2) n.c. n.c. D1 D0 VSSO VDDO VSSD2 VDDD2 (2) 9 10 VSSA 100 nF 11 12 13 VRB(1) VRM (1) n.c.(2) (3) VSSA 14 (2) n.c. 15 VI (4) VRT n.c. 16 (1) OE MLC861 100 nF VSSA 100 nF VSSA The analog and digital supplies should be separated and decoupled. The external voltage reference generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages can be derived from a well regulated VDDA supply through a resistor bridge and a decoupling capacitor. (1) (2) (3) (4) VRB, VRM and VRT are decoupled to VSSA. Pins 8, 12, 13, 17, 24 and 32 should be connected to the closest ground pin in order to prevent noise influence. When VRM is not used, pin 11 can be left open-circuit, avoiding the decoupling capacitor. In any case, pin 11 must not be grounded. When analog input signal is AC coupled, an input bias or a clamping level must be applied to VI input (pin 14). Fig.15 Application diagram. 2002 Jul 02 16 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 PACKAGE OUTLINE SOT401-1 LQFP32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm c y X A 17 24 ZE 16 25 e A A2 E HE (A 3) A1 w M pin 1 index bp 32 Lp 9 L 1 8 detail X ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.15 0.05 1.5 1.3 0.25 0.27 0.17 0.18 0.12 5.1 4.9 5.1 4.9 0.5 7.15 6.85 7.15 6.85 1.0 0.75 0.45 0.2 0.12 0.1 Z D (1) Z E (1) 0.95 0.55 7 0o 0.95 0.55 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT401-1 136E01 MS-026 2002 Jul 02 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 17 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 SOLDERING If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. To overcome these problems the double-wave soldering method was specifically developed. 2002 Jul 02 18 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable(3) HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(4), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(2) suitable suitable suitable not recommended(4)(5) suitable not recommended(6) suitable Notes 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 Jul 02 19 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 DATA SHEET STATUS DATA SHEET STATUS(1) PRODUCT STATUS(2) DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2002 Jul 02 20 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 NOTES 2002 Jul 02 21 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 NOTES 2002 Jul 02 22 Philips Semiconductors Product specification 10-bit high-speed 3.0 to 5.25 V analog-to-digital converter TDA8766 NOTES 2002 Jul 02 23 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. SCA74 (c) Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/05/pp24 Date of release: 2002 Jul 02 Document order number: 9397 750 10029