TC74HC563AP/AF TC74HC573AP/AF/AFW OCTAL DO-TYPE LATCH WITH 3-STATE OUTPUT TC74HCE6G3AP/AF INVERTING TC74HCE573AP/AF/AFW NON-INVERTING The TC74HC563A and TC74HC573A are high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate C27MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power 20 dissipation. { These 8bit D-type latches are controlled by a latch enable input (LE) and a output enable input(OE). When the OE input is high, the eight outputs are in a high impedance state. The TC74HC5S63A has inverting outputs, and 20 2 1 1 TC74HC573A has non-inverting outputs. All inputs are equipped with protection circuits against F(SOP20-P-300) FW(SOL20-P-300) static dischage or transient excess voltage. P(DIP20~P~300A) FEATURES: * High Speed s--rreeesrseees corte eeesee eee tpy =13ns(Typ.)at Voc=5V PIN ASSIGNMENT * Low Power Dissipation :*-++++-+-* Ipc =4 4 A( Max. )at Ta=25C TC74HC563A * High Noise Immunity -++++++++-+-> Vain = Vnit 28% Voc (Min. ) _. * Qutput Drive Capability +--+ 15 LSTTL Loads OE 1 1} 20 Vee * Symmetrical Output Impedance -* | Iq4|=Ig, =6mA(Min.) Do 2 1 19 do * Balanced Propagation Delays ------ tous teat, D1 3 18 Gi * Wide Operating Voltage Range ~- Voc (opr.)=2V~6V D2 4 17 G2 * Pin and Function Compatible with 74LS563/573 D3 5 rN 16 03 D4 15 Gs D5 7 14 06 D6 8 13 06 D7? 9 ; 12 a7 GND 10 nu Le TRUTH TABLE TC74HC573A OE 1] 20 Vee INPUTS OUTPUTS pe 19 a0 E]) LE QHesmay O(HCHA) D1 1 ai x z z 02 H 17 a2 L a, | a, D3 16 Q3 H L H o4 1 a4 HIH H L O& ql 14 Q6 x Dont Gare Ds 13 a6 z igh Impedance pO7 Q,(0,) : :Q(G) ov output: are, latched ft itt t 2 a7 time wh en the LE input GND 10 a] 11 LE to a low logic ioral HC-568 rilx<|x1o rie|[r-|z19} oan numaeawn TC74HCS63AP/AF TC74HCS73AP/AF/AFW IEC LOGIC SYMBOL TC74HC5E3A TC74HC 573A OE EN Le for EN cl DO 10 bY ol D2 1D Qo al Q2 R28 ol 9| 9! Ql Ql Qi Ol QI 28aeg8 SYSTEM DIAGRAM TCT4HCE63A TCI4HCS73A D0 D1 b2 D3 ls D o D Loh | coh | coh | 10 : x # a 4 _& : Qo al Q2 HC-569TC74HCS563AP/AF TC74HC573AP/AF/AFW ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL VALUE UNIT Supply Voltage Range Voc -0.5~7 Vv *500mW in the. range. of Ta= 15 ~ -40C~ 65, From Ta=65C DC Input Voltage Vin 0.5 ~Vog +0.5 Vv to 85C a derating factor of DC Output Voltage Vour -0.5 ~VQ-t 0.5: Vv -10mW/"C shall be applied Input Diode Current In +20 mA until 300mW. Output Diode Current lox +20 mA DC Output Current lot +35 mA DC Vo-/Ground Current loo +75 mA Power Dissipation Ph 500(DIP)+/180(MFP) mw Storage Temperature Tstg ~65 ~150 c Lead Temperature 10sec Ti 300 c RECOMMENDED OPERATING CONDITIONS PARAMETER SYMBOL VALUE UNIT Supply Voltage Vor 2~6 Vv Input Voltage Vix O~ Ve Vv Output Voltage Vout 0~ Voc Vv Operating Temperature Topr -40 ~ 85 Cc 0 ~ 1000( VQ, =2.0V) Input Rise and Fall Time | tr, tr O~ 500( Voc =4.5V) ns O~ 400(Voc-=6.0V) DC ELECTRICAL CHARACTERISTICS Ta=25C Ta=-40 ~85C PARAMETER |SYMBOL TEST CONDITION Voc | MINT] TYP. AXP MIN: TMAX. UNIT . 2.0] 1 - ~ 1.5 - High-Level . . Vin 4.5] 3. - - 3.15 - Vv Input Voltage 6.0 4 _ _ 42 _ 20] - =~ os | - [| 05 Low~ Level . Vit 4.5 - - 1.35 - 135 | V Input Voltage 6.0 _ _ 18 _ 18 2.0 lL. 2.0 - 1.9 - High-Level Vix = Toy =-20H A] 4.5 | 4. 4.5 - 4.4 - Output Voltage Vor | v,.orV 8.0 | 5. 6.0 5.9 = Vv Hee gp =-6 mA] 4.5 | 4 4.31 = 4.13 [= lon =-7.8mA] 6.0 | 5. 5. 80 = 5. 63 = 2.0 - 0, 0 0.1 - 0.1 Low-Level Vo. Vix = to. =20 A be _ 0 0. _ 5 i Vv Output Voltage VnorYi, Ty 6 mA] 4.5) > | 0.17 | 0.28, - | 0.33 Io. =7.8mA | 6.0 = 0. 18 0. 26 ~ 0.33 3-State Output Vix =Vin or Vi. _ _ Off-State Current loz Vat =Voco or GND 6.0 #0.5 *5.0 A Input Leakage Current | Tix Vix =Vec orGND_ [6.0] - [ #07; = [10] * Quiescent Supply Current Tor Vix =Voc or GND 6.0 - 4.0 = 40.0 HC-570TC74HCS563AP/AF TC74HC573AP/AF/AFW TIMING REQUIREMENTS(Input t-=ty=6ns) PARAMETER _|sYMBOL] TEST CONDITION --y Ty Mt rato ee UNIT Minimum Pulse Width 2.0 7 6 95 twa 4.5 7 15 19 (LE) 6.0 - 13 16 Minimum Set-up Time t i . ns (Data) 6.0 ~ 9 il Minimum Hold Time |, it - (Data) " 6.0 - 5 5 AC ELECTRICAL CHARACTERISTICS(input t,=t;=6ns) TEST Ta=25C Ta=40 ~85C PARAMETER _|SYMBOL! CONDITION CL | Voc] MIN | TYP. [MAX.| MIN. [MAX_|UNIT : 20/[ - 20 60 = 75 Output Transition Time it 50 | 4.5 - 6 12 - 15 THLE 6.0 = 5 10 = 13 20 | - 50 115 = 145 Propagation Delay Time *pLH 50 se _ . a _ a 00 20] 60 155 = 195 LE-Q, (LE-Q, Q) toHL 150] 4.5] - 20 31 - 39 6.0 | - 17 26 = 33 20/ - 42 110 = 140 Propagation Delay Time SoLH 50 so - 3 a _ a (D-9, 9) 20; - | 57 | 150 | - | 199 |" , tout 150 4.5 ~ 19 30 ~ 38 6.0 | - 16 26 = 32 20| - 55 140 = 175 toa 5014.5] - 17 28 - 35 Output Enable time Rp=1kQ a ig ifn ~ oe tom 150] 4.5) - 22 36 - 45 6.0 | - 19 31 = 38 : 20 | - 40 125 = 155 Output Disable time pe R,=1kQ 50 | 4.5 - 17 25 - 3h PH? 6.0 = 15 21 = 26 Input Capacitance Cr. ~ 5 10 - 10 Output Capacitance Cout = 10 = = = F Power Dissipation C ppt) LEOTAHCSORA = 49 = = |?P Capacitance PD TC74HC573A - $1 = = = Note(1) Cpp is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average ore ating current can be obtained by the equation: =Cpp Vec* fn +icc /8(per Latch) And the total ie when n pes. of Latch operate can be gained by the following equation: Cro(tetal)= 33+16*n (TC74HC563A ) Crp(total)=33+18 n (TC74HCS573A) HC-571