APPLICATION NOTES A V A I L A B L E AN99 * AN115 * AN120 * AN124 * AN133 * AN134 * AN135 Low Noise/Low Power/2-Wire Bus/256 Taps X9258 Quad Digital Controlled Potentiometers (XDCPTM) FEATURES DESCRIPTION * * * * * * * * The X9258 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. * * * * Four potentiometers in one package 256 resistor taps/pot-0.4% resolution 2-wire serial interface Wiper resistance, 40 typical @ V+ = 5V, V- = -5V Four nonvolatile data registers for each pot Nonvolatile storage of wiper position Standby current < 5A max (total package) Power supplies --VCC = 2.7V to 5.5V --V+ = 2.7V to 5.5V --V- = -2.7V to -5.5V 100K, 50K total pot resistance High reliability --Endurance - 100,000 data changes per bit per register --Register data retention - 100 years 24-lead SOIC, 24-lead TSSOP, 24-lead CSP (Chip Scale Package) Dual supply version of X9259 The digitally controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. BLOCK DIAGRAM Pot 0 VCC VSS R0 R1 V+ VR2 R3 WP SCL SDA A0 A1 A2 A3 VH0/RH0 Wiper Counter Register (WCR) VL0/RL0 R0 R1 R2 R3 Wiper Counter Register (WCR) Resistor Array Pot 2 VL2/RL2 VW0/RW0 Interface and Control Circuitry VW2/RW2 8 VW1/RW1 Data R0 R1 R2 R3 REV 1.1.7 2/4/03 VH2/RH2 Wiper Counter Register (WCR) Resistor Array Pot 1 VW3/RW3 VH1/RH1 R0 R1 VL1/RL1 R2 R3 www.xicor.com Wiper Counter Register (WCR) Resistor Array Pot 3 VH3/RH3 VL3/RL3 Characteristics subject to change without notice. 1 of 22 X9258 PIN DESCRIPTIONS PIN CONFIGURATION Host Interface Pins SOIC/TSSOP SERIAL CLOCK (SCL) The SCL input is used to clock data into and out of the X9258. SERIAL DATA (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. NC 1 24 A3 A0 VW3/RW3 2 23 SCL 3 22 VL2/RL2 VH3/RH3 4 21 VH2/RH2 VL3/RL3 5 20 VW2/RW2 V+ 6 19 V- X9258 VCC 7 18 VSS VL0/RL0 8 17 VW1/RW1 VH0/RH0 9 16 VH1/RH1 VW0/RW0 10 15 VL1/RL1 A2 11 14 A1 WP 12 13 SDA DEVICE ADDRESS (A0-A3) The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9258. A maximum of 16 devices may occupy the 2-wire serial bus. CSP 1 A 2 3 4 RW0 A2 A1 RL1 RL0 WP SDA RW1 VCC RH0 RH1 VSS V+ RH3 RH2 V- RL3 NC A3 RW2 RW3 A0 SCL RL2 B Potentiometer Pins VH/RH (VH0/RH0-VH3/RH3), VL/RL (VL0/RL0-VL3/RL3) The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. C D E VW/RW (VW0/RW0-VW3/RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. F Top View-Bumps Down Hardware Write Protect Input (WP) The WP pin when low prevents nonvolatile writes to the Data Registers. Analog Supplies V+, VThe Analog Supplies V+, V- are the supply voltages for the DCP analog section. REV 1.1.7 2/4/03 www.xicor.com Characteristics subject to change without notice. 2 of 22 X9258 Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. PIN NAMES Symbol Description SCL Serial Clock SDA Serial Data A0-A3 Device Address VH0/RH0-VH3/RH3, VL0/RL0-VL3/RL3 Potentiometer Pins (terminal equivalent) VW0/RW0-VW3/RW3 Potentiometers Pins (wiper equivalent) WP Hardware Write Protection V+,V- Analog Supplies VCC System Supply Voltage VSS System Ground NC No Connection (Allowed) PRINCIPLES OF OPERATION The X9258 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the DCP potentiometers. Serial Interface--2-Wire The X9258 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9258 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9258 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9258 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. REV 1.1.7 2/4/03 Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9258 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9258 will respond with a final acknowledge. Array Description The X9258 is comprised of four resistor arrays. Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The 8 bits of the WCR are decoded to select, and enable, one of 256 switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the WCR. These data registers and the WCR can be read and written by the host system. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9258 this is fixed as 0101[B]. www.xicor.com Characteristics subject to change without notice. 3 of 22 X9258 Figure 1. Slave Address ACK Polling Sequence Device Type Identifier 0 1 0 Nonvolatile Write Command Completed EnterACK Polling 1 A3 A2 A1 A0 Issue START Device Address The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0-A3 inputs. The X9258 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9258 to respond with an acknowledge. The A0-A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Acknowledge Polling The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms nonvolatile write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9258 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9258 is still busy with the write operation no ACK will be returned. If the X9258 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. REV 1.1.7 2/4/03 Issue Slave Address ACK Returned? Issue STOP No Yes Further Operation? No Yes Issue Instruction Issue STOP Proceed Proceed Instruction Structure The next byte sent to the X9258 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the two pots and when applicable they point to one of four associated registers. The format is shown below in Figure 2. www.xicor.com Characteristics subject to change without notice. 4 of 22 X9258 Figure 2. Instruction Byte Format RAM. The response of the wiper to this action will be delayed tWRL. A transfer from the Wiper Counter Register (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all of the potentiometers and one of their associated registers. Register Select I3 I2 I1 I0 R1 R0 P1 P0 Wiper Counter Register Select Instructions Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9258; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: Read Wiper Counter Register (read the current wiper position of the selected pot), Write Wiper Counter Register (change current wiper position of the selected pot), Read Data Register (read the contents of the selected nonvolatile register) and Write Data Register (write a new value to the selected data register). The sequence of operations is shown in Figure 4. The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last bits (P1, P0) select which one of the four potentiometers is to be affected by the instruction. Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the Wiper Counter Register and one of the data registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static Figure 3. Two-Byte Instruction Sequence SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 The Increment/Decrement command is different from the other commands. Once the command is issued and the X9258 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one REV 1.1.7 2/4/03 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K S T O P resistor segment towards the VH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. www.xicor.com Characteristics subject to change without notice. 5 of 22 X9258 Table 1. Instruction Set Instruction Set Instruction I3 I2 I1 I0 R1 R0 P1 P0 Operation Read Wiper Counter Register 1 0 0 1 0 0 1/0 1/0 Read the contents of the Wiper Counter Register pointed to by P1-P0 Write Wiper Counter Register 1 0 1 0 0 0 1/0 1/0 Write new value to the Wiper Counter Register pointed to by P1-P0 Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Read the contents of the Data Register pointed to by P1-P0 and R1-R0 Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 Write new value to the Data Register pointed to by P1-P0 and R1-R0 XFR Data Register to Wiper Counter Register 1 1 0 1 1/0 1/0 1/0 1/0 Transfer the contents of the Data Register pointed to by P1-P0 and R1-R0 to its associated Wiper Counter Register XFR Wiper Counter Register to Data Register 1 1 1 0 1/0 1/0 1/0 1/0 Transfer the contents of the Wiper Counter Register pointed to by P1-P0 to the Data Register pointed to by R1-R0 Global XFR Data Registers to Wiper Counter Registers 0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed to by R1-R0 of all four pots to their respective Wiper Counter Registers Global XFR Wiper Counter Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by R1-R0 of all four pots Increment/Decrement Wiper Counter Register 0 0 1 0 0 0 1/0 1/0 Enable Increment/decrement of the Control Latch pointed to by P1-P0 Note: (1) 1/0 = data is one or zero Figure 4. Three-Byte Instruction Sequence SCL SDA S T A R T 0 REV 1.1.7 2/4/03 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K www.xicor.com D7 D6 D5 D4 D3 D2 D1 D0 Characteristics subject to change without notice. A C K S T O P 6 of 22 X9258 Figure 5. Increment/Decrement Instruction Sequence F SCL SDA S T A R T 0 1 0 1 A3 A2 A1 A0 A C K I3 I2 I1 I0 R1 R0 P1 P0 A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P Figure 6. Increment/Decrement Timing Limits INC/DEC CMD Issued tWRID SCL SDA Voltage Out VW/RW Figure 7. Acknowledge Response from Receiver SCL from Master 1 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge START REV 1.1.7 2/4/03 www.xicor.com Characteristics subject to change without notice. 7 of 22 X9258 Figure 8. Detailed Potentiometer Block Diagram Detailed Operation Serial Data Path VH/RH Serial BUS Input From Interface Circuitry Register 0 8 Register 2 8 Parallel BUS Input Wiper Counter Register (WCR) Register 3 D e c o d e INC/DEC Logic If WCR = 00[H] then VW/RW = VL/RL If WCR = FF[H] then VW/RW = VH/RH C o u n t e r Register 1 UP/DN Modified SCL UP/DN CLK VL/RL VW/RW All DCP potentiometers share the serial interface and share a common architecture. Each potentiometer has a Wiper Counter Register and four Data Registers. A detailed discussion of the register organization and array operation follows. The WCR is a volatile register; that is, its contents are lost when the X9258 is powered-down. Although the register is automatically loaded with the value in R0 upon power-up, it should be noted this may be different from the value present at power-down. Wiper Counter Register The X9258 contains four Wiper Counter Registers, one for each DCP potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents of its data register zero (R0) upon power-up. Data Registers Each potentiometer has four nonvolatile Data Registers. These can be read or written directly by the host and data can be transferred between any of the four Data Registers and the WCR. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. REV 1.1.7 2/4/03 If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. www.xicor.com Characteristics subject to change without notice. 8 of 22 X9258 REGISTER DESCRIPTIONS Wiper Counter Register, (8-Bit), Volatile WP7 Data Registers, (8-Bit), Nonvolatile WP7 WP6 WP5 WP4 WP3 WP2 WP1 NV NV NV NV NV NV (MSB) NV WP0 NV (LSB) Four 8-bit Data Registers for each DCP. (sixteen 8-bit registers in total). - {D7~D0}: These bits are for general purpose not volatile data storage or for storage of up to four different wiper values. The contents of Data Register 0 are automatically moved to the wiper counter register on power-up. V WP6 WP5 WP4 WP3 WP2 WP1 V V V V V V (MSB) WP0 V (LSB) One 8-bit Wiper Counter Register for each DCP. (Four 8-bit registers in total.) - {D7~D0}: These bits specify the wiper position of the respective DCP. The Wiper Counter Register is loaded on power-up by the value in Data Register 0. The contents of the WCR can be loaded from any of the other Data Register or directly. The contents of the WCR can be saved in a DR. Instruction Format Notes: (1) (2) (3) (4) (5) "MACK"/"SACK": stands for the acknowledge sent by the master/slave. "A3 ~ A0": stands for the device addresses sent by the master. "X": indicates that it is a "0" for testing purpose but physically it is a "don't care" condition. "I": stands for the increment operation, SDA held high during active SCL phase (high). "D": stands for the decrement operation, SDA held low during active SCL phase (high). Read Wiper Counter Register (WCR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T instruction WCR S opcode addresses A C P P K 1 0 0 1 0 0 1 0 wiper position S (sent by slave on SDA) A C W W W W W W W W K P P P P P P P P 7 6 5 4 3 2 1 0 M A C K S T O P Data Byte S (sent by master on SDA) A C W W W W W W W W K P P P P P P P P 7 6 5 4 3 2 1 0 S A C K S T O P Write Wiper Counter Register (WCR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T instruction WCR S opcode addresses A C P P K 1 0 1 0 0 0 1 0 Read Data Register (DR) device S device type T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T REV 1.1.7 2/4/03 instruction DR and WCR S opcode addresses A C R R P P K 1 0 1 1 1 0 1 0 Data Byte S (sent by slave on SDA) A C W W W W W W W W K P P P P P P P P 7 6 5 4 3 2 1 0 www.xicor.com M A C K S T O P Characteristics subject to change without notice. 9 of 22 X9258 Write Data Register (WR) S device type device instruction DR and WCR S T identifier addresses opcode addresses A A C R R P P R 0 1 0 1 A A A A 1 1 0 0 3 2 1 0 K 1 0 1 0 T Data Byte S (sent by master on SDA) A C W W W W W W W W K P P P P P P P P 7 6 5 4 3 2 1 0 S A C K S T HIGH-VOLTAGE O WRITE CYCLE P XFR Data Register (DR) to Wiper Counter Register (WCR) S device type device instruction DR and WCR S T identifier addresses opcode addresses A A C R R P P R 0 1 0 1 A A A A 1 1 0 1 3 2 1 0 K 1 0 1 0 T S A C K S T O P XFR Wiper Counter Register (WCR) to Data Register (DR) device S device type addresses T identifier A R 0 1 0 1 A A A A 3 2 1 0 T instruction DR and WCR S opcode addresses A C R R P P 1 1 1 0 K 1 0 1 0 S A C K S T O P HIGH-VOLTAGE WRITE CYCLE Increment/Decrement Wiper Counter Register (WCR) device S device type T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T instruction S opcode A C K 0 0 1 0 WCR addresses 0 0 P 1 increment/decrement S (sent by master on SDA) A C P I/ I/ I/ I/ . . . . 0 K D D D D S T O P Global XFR Data Register (DR) to Wiper Counter Register (WCR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T instruction DR S opcode addresses A C R R K 0 0 0 1 1 0 0 0 S A C K S T O P Global XFR Wiper Counter Register (WCR) to Data Register (DR) S device type device T identifier addresses A R 0 1 0 1 A A A A 3 2 1 0 T REV 1.1.7 2/4/03 instruction DR S opcode addresses A C R R 1 0 0 0 0 0 K 1 0 S A C K S T O P HIGH-VOLTAGE WRITE CYCLE www.xicor.com Characteristics subject to change without notice. 10 of 22 X9258 SYMBOL TABLE REV 1.1.7 2/4/03 INPUTS 120 OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don't Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance RMIN = 100 Resistance (K) WAVEFORM Guidelines for Calculating Typical Values of Bus Pull-Up Resistors 80 VCC MAX =1.8K IOL MIN RMAX = tR CBUS Max. Resistance 60 40 20 0 Min. Resistance 0 20 40 60 80 100 120 Bus Capacitance (pF) www.xicor.com Characteristics subject to change without notice. 11 of 22 X9258 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias ....................-65C to +135C Storage temperature .........................-65C to +150C Voltage on SDA, SCL or any address input with respect to VSS ..................................-1V to +7V Voltage on V+ (referenced to VSS)......................... 10V Voltage on V- (referenced to VSS)......................... -10V (V+) - (V-).............................................................. 12V Any VH/RH ............................................................... V+ Any VL/RL ................................................................. VLead temperature (soldering, 10 seconds)........ 300C IW (10 seconds)................................................ 15mA Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Device Supply Voltage (VCC) Limits Commercial 0C +70C X9258 5V 10% Industrial -40C +85C X9258-2.7 2.7V to 5.5V ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol Max. Unit End to end resistance tolerance 20 % Power rating 50 mW 25C, each pot IW Wiper current 7.5 mA Wiper current = 1mA RW Wiper resistance 150 250 IW = 1mA @ V+ = 3V, V- = -3V RW Wiper resistance 40 100 IW = 1mA @ V+ = 5V, V- = -5V V+ Voltage on V+ Pin V VVTERM Parameter Voltage on V- Pin Min. X9258 +4.5 +5.5 X9258-2.7 +2.7 +5.5 X9258 -5.5 -4.5 X9258 -2.7 -5.5 -2.7 V- V+ Voltage on any VH/RH or VL/RL pin Noise Resolution (4) Absolute Relative Typ. 0.6 % REV 1.1.7 2/4/03 MI(3) Vw(n)(actual)-Vw(n)(expected) 0.6 MI(3) Vw(n + 1)-[Vw(n) + MI] ppm/C 20 10/10/25 www.xicor.com Ref: 1kHz 1 300 Ratiometric Temperature Coefficient CH/CL/CW Potentiometer Capacitance V dBV linearity (2) Temperature coefficient of RTOTAL V -120 linearity (1) Test Conditions ppm/C pF See Circuit #3 Characteristics subject to change without notice. 12 of 22 X9258 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Typ. Max. Unit 1 Test Conditions ICC1 VCC supply current (Nonvolatile Write) ICC2 VCC supply current (move wiper, write, read) ISB VCC current (standby) 5 A SCL = SDA = VCC, Addr. = VSS ILI Input leakage current 10 A VIN = VSS to VCC ILO Output leakage current 10 A VOUT = VSS to VCC VIH Input HIGH voltage VCC x 0.7 VCC + 0.1 V VIL Input LOW voltage -0.5 VCC x 0.3 V VOL Output LOW voltage 0.4 V 100 mA fSCL = 400kHz, SDA = Open, Other Inputs = VSS A fSCL = 400kHz, SDA = Open, Other Inputs = VSS IOL = 3mA Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/255 or (VH/RH--VL/RL)/255, single pot (4) Max. = all four arrays cascaded together, Typical = individual array resolutions. ENDURANCE AND DATA RETENTION Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 years CAPACITANCE Symbol (5) (5) CI/O CIN Test Max. Unit Test Conditions Input/output capacitance (SDA) 8 pF VI/O = 0V Input capacitance (A0, A1, A2, A3, and SCL) 6 pF VIN = 0V Min. Max. Unit POWER-UP TIMING Symbol Parameter (6) Power-up to initiation of read operation 1 ms (6) Power-up to initiation of write operation 5 ms 50 V/msec tPUR tPUW (7) tR VCC VCC Power up ramp 0.2 POWER UP AND DOWN REQUIREMENT The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their final value. The VCC ramp rate spec is always in effect. Notes: (5) This parameter is periodically sampled and not 100% tested. (6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. (7) Sample tested only. REV 1.1.7 2/4/03 www.xicor.com Characteristics subject to change without notice. 13 of 22 X9258 A.C. TEST CONDITIONS Test Circuit #3 SPICE Macro Model Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 Macro Model RTOTAL RH CH EQUIVALENT A.C. LOAD CIRCUIT 5V 2.7V CW 10pF 1533 RL CL 10pF 25pF RW SDA Output 100pF 100pF AC TIMING (Over recommended operating condition) Symbol Parameter fSCL Clock frequency Min. Max. Unit 400 kHz tCYC Clock cycle time 2500 ns tHIGH Clock high time 600 ns tLOW Clock low time 1300 ns tSU:STA Start setup time 600 ns tHD:STA Start hold time 600 ns tSU:STO Stop setup time 600 ns tSU:DAT SDA data input setup time 100 ns tHD:DAT SDA data input hold time 30 ns tR SCL and SDA rise time 300 ns tF SCL and SDA fall time 300 ns tAA SCL low to SDA data output valid time 900 ns tDH SDA data output hold time 50 ns Noise suppression time constant at SCL and SDA inputs 50 ns 1300 ns TI tBUF Bus free rime (prior to any transmission) tSU:WPA WP, A0, A1, A2 and A3 setup time 0 ns tHD:WPA WP, A0, A1, A2 and A3 hold time 0 ns HIGH-VOLTAGE WRITE CYCLE TIMING Symbol Parameter Typ. Max. Unit tWR High-voltage write cycle time (store instructions) 5 10 ms REV 1.1.7 2/4/03 www.xicor.com Characteristics subject to change without notice. 14 of 22 X9258 DCP TIMING Symbol tWRPO Parameter Min. Max. Unit Wiper response time after the third (last) power supply is stable 10 s tWRL Wiper response time after instruction issued (all load instructions) 10 s tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 10 s Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. TIMING DIAGRAMS 2-WIRE INTERFACE START and STOP Timing (START) (STOP) tF tR SCL tSU:STA tHD:STA tSU:STO tR tF SDA Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tDH tAA REV 1.1.7 2/4/03 www.xicor.com Characteristics subject to change without notice. 15 of 22 X9258 DCP Timing (for All Load Instructions) (STOP) SCL LSB SDA tWRL VWx DCP Timing (for Increment/Decrement Instruction) SCL SDA Wiper Register Address Inc/Dec Inc/Dec tWRID VWx Write Protect and Device Address Pins Timing (START) (STOP) SCL ... (Any Instruction) ... SDA ... tSU:WPA tHD:WPA WP A0, A1 A2, A3 REV 1.1.7 2/4/03 www.xicor.com Characteristics subject to change without notice. 16 of 22 X9258 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers +VR VR VW/RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Noninverting Amplifier VS Voltage Regulator + VO - VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 Comparator with Hysteresis R2 VS VS - + VO 100K - VO + } } TL072 R1 R2 10K 10K +12V REV 1.1.7 2/4/03 10K VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) -12V www.xicor.com Characteristics subject to change without notice. 17 of 22 X9258 Application Circuits (continued) Attenuator Filter C VS + R2 R1 VS VO - - R VO + R3 R4 R2 All RS = 10k R1 GO = 1 + R2/R1 fc = 1/(2pRC) VO = G VS -1/2 G +1/2 R1 R2 } } Inverting Amplifier Equivalent L-R Circuit VS R2 C1 - VS VO + + - R1 ZIN VO = G VS G = - R2/R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C R2 - + R1 - } RA + } RB frequency R1, R2, C amplitude RA, RB REV 1.1.7 2/4/03 www.xicor.com Characteristics subject to change without notice. 18 of 22 X9258 PACKAGING INFORMATION 24-Bump Chip Scale Package (CSP B24) Package Outline Drawing a 9258UA YWW I Lot# f j m d A4 A3 A2 A1 B4 B3 B2 B1 C4 C3 C2 C1 D4 D3 D2 D1 E4 E3 E2 E1 F4 F3 F2 F1 l Top View (Sample Marking) b e k Bottom View (Bumped Side) Side View e c Side View Package Dimensions Package Width Package Length Package Height Body Thickness Ball Height Ball Diameter Ball Pitch - Width Ball Pitch - Length Ball to Edge Spacing - Width Ball to Edge Spacing - Length REV 1.1.7 2/4/03 Ball Matrix: Symbol a b c d e f j k l m Min 2.771 4.549 0.644 0.444 0.200 0.300 0.626 1.015 Millimeters Nominal 2.801 4.579 0.677 0.457 0.220 0.320 0.5 0.5 0.651 1.040 Max 2.831 4.609 0.710 0.470 0.240 0.340 4 RL1 3 2 A A1 A2 1 RW0 B RW1 SDA WP RL0 RH0 VCC C VSS RH1 D V- RH2 RH3 V+ E RW2 A3 NC RL3 F RL2 SCL A0 RW3 0.676 1.065 www.xicor.com Characteristics subject to change without notice. 19 of 22 X9258 PACKAGING INFORMATION 24-Lead Plastic, TSSOP, Package Code V24 .026 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .303 (7.70) .311 (7.90) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.06) .005 (.15) .010 (.25) Gage Plane 0-8 (4.16) (7.72) Seating Plane .020 (.50) .030 (.75) (1.78) Detail A (20X) (0.42) (0.65) .031 (.80) .041 (1.05) ALL MEASUREMENTS ARE TYPICAL See Detail "A" NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.1.7 2/4/03 www.xicor.com Characteristics subject to change without notice. 20 of 22 X9258 PACKAGING INFORMATION 24-Lead Plastic Small Outline Gull Wing Package Type S 0.290 (7.37) 0.393 (10.00) 0.299 (7.60) 0.420 (10.65) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7 0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30) 0.050 (1.27) 0.050" Typical 0.010 (0.25) X 45 0.020 (0.50) 0.050" Typical 0 - 8 0.009 (0.22) 0.013 (0.33) 0.420" 0.015 (0.40) 0.050 (1.27) FOOTPRINT 0.030" Typical 24 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.1.7 2/4/03 www.xicor.com Characteristics subject to change without notice. 21 of 22 X9258 Ordering Information X9258 Y P T V VCC Limits Blank = 5V 10% -2.7 = 2.7 to 5.5V Device Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C Package S24 = 24-Lead SOIC V24 = 24-Lead TSSOP B24 = 24-Lead CSP Potentiometer Organization T = 100K U= 50K S & V Package Marking Line #1 Line #2 Line #3 Line #4 (Blank) (Part Number) (Date Code) (*) (Blank) LIMITED WARRANTY = F 2.7V 0 to 70C G 2.7V -40 to +85C I 5V -40 to +85C (c)Xicor, Inc. 2003 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.1.7 2/4/03 www.xicor.com Characteristics subject to change without notice. 22 of 22