Enpirion® Power Evaluation Board User Guide
EN5312QI PowerSoC
Enp irion EN5 312Q I family of DCDC
C onver ter M odule Evaluation Boar d
Introduction
Thank you for c hoosing Altera Enpirion power produc ts!
You are evaluating a new class of DCDC converter product, a complet e power syst em on
silicon:
• T he EN5312QI is a complet e module including magnet ics and requir ing only
cer amic input and output capacit ors.
• T he evaluation board is designed t o offer a wide range of engineer ing evaluat ion
capabilities. T his includes t he base configur at ion of a 0805 4.7uF input capacitor
and a 0805 10uF out put capacit or.
• Pads ar e available t o add up to one addit ional input capacit or and up t o t wo
additional out put capacit ors to allow for evaluat ion of performance over a wid e
r ange of input/ output capacit or combinations.
• Pads are available to populate an external divider if desired.
• E asy jumper s are provided f or t he f ollowing signals:
o Enable
o VS0-VS2 output voltage select
• Numerous test points are provi ded as well as cl ip leads for input and out put
connections
• T he board comes with input decoupling a nd reverse polarity prot ect ion t o protect
the de vice from common setup misha ps.
Quick Start Guide
Figur e 1 shows a t op view of t he evaluat ion boar d.
STEP 1: Se t the “ENA” jumper t o t he Dis able Posit ion.
CAUTION: the signal pins , E NA, V S 0, VS 1, and VS2 must
be connect ed to a “high” or a “low ”. If left floating the st at e
is indeterminate.
ST E P 2: S et t he out put voltage select pins f or t he desir ed out put volt age setti ng. Refer to
t he section on out put voltage select to det er mine t he set t ing.
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Enpirion® Power Evaluation Board User Guide
EN5312QI PowerSoC
CAUTION: the external divider is not populated. Choosing this option will force
t he device to 100% duty cycle.
ST E P 3: Connect Power S upply t o the input power connect ors, VIN (+) and GND (-) a s
indic ated in Figure 1.
CAUTION: be mindful of t he polarit y. E ven though the evaluat ion board comes
with re verse polarity protec tion diode s, it is ra re ly a good ide a to re verse the input
polarity.
STEP 4: Conne ct the loa d to the output conne ctors VOUT (+) and GN D (-), as i ndi cated i n
Figure 1.
STEP 5: P owe r up the boa rd a nd move the ENA jumper to the ena ble d position. The
EN5312Q is now powered up.
Figure 1. Evaluation Board Layout.
Output Voltage
Select
Output
Enable
Decoupling Cap
(to
decouple supply cables)
Reverse polarity
protec t io n di o de s
C
IN
C
OUT
GND (-)
V
OUT
(+)
080 5 4. 7uF
080 5 10 uF
V
IN
(+)
GND (-)
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Enpirion® Power Evaluation Board User Guide
EN5312QI PowerSoC
Output Voltage Select
VS2
VS1
VS0
VOUT
0
0
0
3.3V
0
0
1
2.5V
0
1
0
1.8V
0
1
1
1.5V
1
0
0
1.25V
1
0
1
1.2V
1
1
0
0.8V
1
1
1
Us er S el ectabl e
T he EN5312QI ut ilizes a 3 pin out put volt age select scheme. T he output volt age is
pr ogrammed by set ting t he VS x jumpers t o eit her a logic “1” or a logic “0” as described
in t he Quick St art section
T able 1 shows t he t rut h t able f or VOUT selectio n . T h ere are seven preset out put volt age
levels which can be chosen via t he VSx jumper s.
CAUTION: t he st andard evaluat ion boar d configurat ion does not populat e t he
ext ernal divider . Select ing t he ext ernal divider opt ion without populating t he
exte rna l divide r w ill re sult in unpredicta ble be havior but c an re sult in the device
going into 100% duty cycle and delivering t he input rail voltage to t he out put .
CAUTION: All signal pins mus t be connect ed to eit her a logic “1”, jumper t o
t he left , or t o a logic “0”, jumper to the right . L eaving t he jumper open will result
in an indeterminate state.
Test Recommend atio ns
Recommendations
T o guarantee measurement accur acy, the following precautions should be observed:
1. Make all input and output voltage measurements at the board using t he t est
points provided. This will eliminate voltage drop across the line and load
cables that can produce false readings.
2. Measure input and out put current wit h ser ies ammeters or accurate shunt
resistors. This is especially important when measuring efficiency.
3. Use a bala nced impeda nce probe tip to mea sure s witc hing signals to avoid
noise coupling into the probe ground le ad.
Tab le 1. Outp ut Voltage Select Truth Tab le
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Enpirion® Power Evaluation Board User Guide
EN5312QI PowerSoC
Using The External Voltage Divider
T he EN5312Q-E evaluat ion board is designed t o provide a great deal of flexibil i t y in
evaluat ing t he per formance of t he Altera Enpiri on DCDC modul e.
Pre-t inned pads are provided to place 0402 sized 1% resistors on t he board t o implement
an ext ernal resist or divider t o choose an out put voltage other than one of t he seven pr e-set
voltages available on t he VID.
VIN
VSense
Vin
VS1
VS2
VS0
EN5312
10µF
4.7uF
VOUT
V
out
GND
ENABLE
R1
R2
V
FB
Figure 2. External divider s chematic.
Figure 3 demonstrates t he placement of the R1 and R2 resist ors.
T he output volt age is selected by t he f ollowing formula:
( )
2
1
16.0 R
R
OUT VV +=
R1 mus t be chosen as 200KΩ to mainta in loop gain. Then R2 is given as:
Ω
−
=6.0
102.1 5
2OUT
Vx
R
The external voltage divider option is chosen by set t ing t he jumpers VS0, VS1, and VS2
t o a logic “high”.
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Enpirion® Power Evaluation Board User Guide
EN5312QI PowerSoC
Figure 3. Pla cemen t of external divider resist ors
Dynamically Adjustable Output
T he EN5312QI is designed to allow f or dynamic switching bet ween t he predefined
volt age levels by t oggling t he VID pins. T he inter -voltage sle w rate is optimized to
prevent excess undershoot or overshoot as the output voltage levels transition. The slew
rate i s 1mV/uS.
This feature can be tested by connecting the VSx jumper center pins to logic driver to
t oggle bet ween the various VOUT states.
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Enpirion® Power Evaluation Board User Guide
EN5312QI PowerSoC
Input and Output Capacitors
The input capacitance requirement is 4.7 uF. Altera recommends t hat a low E S R ML CC
capacit or be used. T he EN5312Q-E is populat ed wit h a 4.7uF 0805 capacit or. T here are
pre-t inned pads t hat allows for additional 0805 capacitors t o experiment wit h input filt er
performance.
The output capacitance requirement is a minimum of 10uF. T he cont rol loop is designed
to be sta ble with up to 60uF of total output capa citanc e. The eva lua tion board c omes
populated with a single 10uF 0805 capacitor.
T he board has pre-t inned pads for up to 2 additional out put capacit or s with either 0805 or
1206 footprint.
C apacitance above t he 10uF minimum can be added if t he t ransient performance is not
suf ficient using t he 10uF. Altera recomme nds a low ES R ML CC type capacit or be used.
NOTE: Capa citors must be X5R or X7R die le ctric formulations.
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Enpirion® Power Evaluation Board User Guide
EN5312QI PowerSoC
Contact Information
Alt er a Corporat ion
101 Innova tion Drive
San Jose, CA 95134
P hone: 408-544-7000
http://www.altera.com
© 2013 Alter a Corporation—Confidential. All rights res erved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY,
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tr ademar ks or ser vice mar ks ar e the pr oper ty of their r espective hol de r s as descr ibed at
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in accor dance w ith Al ter a' s standar d w ar r anty , but r eser ves the r ight to make changes to any pr oducts and ser vices at any
time w ithout noti ce. Al ter a assumes no r esponsibility or lia bi l i ty ar ising out of the applica ti on or use of any infor ma ti on ,
pr oduct, or ser vice descr ibed her ein excep t as expr essly agr eed t o in wr iting by Alter a. Alter a custome r s ar e advised to
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