RFD16N05LSM Product Preview MOSFET - Power, N-Channel, Logic Level 50 V, 16 A, 47 mW These are N-Channel logic level power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use with logic level (5 V) driving sources in applications such as programmable controllers, switching regulators, switching converters, motor relay drivers and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate biases in the 3 V to 5 V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. Formerly developmental type TA09871. www.onsemi.com D G S D Features * * * * * * * * * * * 16 A, 50 V rDS(ON) = 0.047 W UIS SOA Rating Curve (Single Pulse) Design Optimized for 5 V Gate Drives Can be Driven Directly from CMOS, NMOS, TTL Circuits SOA is Power Dissipation Limited Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Majority Carrier Device Related Literature TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" G S DPAK TO-252 CASE 369AS MARKING DIAGRAM $Y&Z&3&K RFD16N 05LSM &Y &Z &3 &K RFD16N05LSM = ON Semiconductor Logo = Assembly Plant Code = Numeric Date Code = Lot Code = Specific Device Code ORDERING INFORMATION (c) Semiconductor Components Industries, LLC, 2003 May, 2019 - Rev. 2 1 Part Number Package Brand RFD16N05LSM9A TO-252AA RFD16N05LSM Publication Order Number: RFD16N05LSM/D RFD16N05LSM MAXIMUM RATINGS Rating Drain to Source Voltage (Note 1) Drain to Gate Voltage (RGS 20 kW) (Note 1) Symbol RFD16N05LSM9A Units VDS 50 V VDGR 50 V ID 16 A Continuous Drain Current Pulsed Drain Current (Note 3) IDM 45 A Gate to Source Voltage VGS 10 V Maximum Power Dissipation PD 60 W 0.48 W/C TJ, TSTG -55 to 150 C TL 300 C Tpkg 260 C Derate Above 25C Operating and Storage Temperature Maximum Temperature for Soldering Leads at 0.063 in (1.6 mm) from Case for 10 s Package Body for 10 s, See Techbrief 334 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. TJ = 25C to 125C. ELECTRICAL SPECIFICATIONS (TC = 25C unless otherwise specified) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250 mA, VGS = 0 V, Figure 10 50 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250 mA, Figure 9 1 - 2 V VDS = 40 V, VGS = 0 V - - 1 mA - - 50 mA VGS = 10 V, VDS = 0 V - - 100 nA ID = 16 A, VGS = 5 V - - 0.047 W ID = 16 A, VGS = 4 V - - 0.056 W VDD = 25 V, ID = 8 A, VGS = 5 V, RGS = 12.5 W Figures 15, 16 - - 60 ns - 14 - ns Zero Gate Voltage Drain Current IDSS TC = Gate to Source Leakage Current Drain to Source On Resistance (Note 2) IGSS rDS(ON) Turn-On Time t(ON) Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tr - 30 - ns td(OFF) - 42 - ns tf - 14 - ns t(OFF) - - - ns - - 80 nC - - 45 nC Total Gate Charge Qg(TOT) VGS = 0 V to 10 V Gate Charge at 5 V Qg(5) VGS = 0 V to 5 V Qg(TH) VGS = 0 V to 1 V Threshold Gate Charge 150C VDD = 40 V, ID = 16 A, RL = 2.5 Figures 17, 18 - - 3 nC Thermal Resistance Junction to Case RqJC - - 2.083 C/W Thermal Resistance Junction to Ambient RqJA - - 100 C/W SOURCE TO DRAIN DIODE SPECIFICATIONS PARAMETER SYMBOL Source to Drain Diode Voltage VSD Diode Reverse Recovery Time trr TEST CONDITIONS ISD = 16 A ISD = 16 A, dISD/dt = 100 A/ms 2. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. www.onsemi.com 2 MIN TYP MAX UNITS - - 1.5 V - - 125 ns RFD16N05LSM TYPICAL PERFORMANCE CURVES (Unless Otherwise Specified) 20 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 5 0 0 102 25 50 75 100 125 75 100 125 150 TC, CASE TEMPERATURE (C) Figure 1. Normalized Power Dissipation vs Case Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 102 IAS, AVALANCHE CURRENT (A) TC = 25C TJ = MAX RATED ID MAX CONTINUOUS DC 1 Idm Starting TJ = 25C Starting TJ = 150C 10 If R = 0 tAV = (L)(IAS)/(1.3 RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS x R)/(1.3 RATED BVDSS - VDD) +1] 1 0.1 1 102 10 0.01 0.10 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms) Figure 3. Forward Bias Safe Operating Area Figure 4. Unclamped Inductive Switching SOA (Single Pulse UIS SOA) VGS = 10 V 30 TC = 25C PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX. VGS = 4 V VGS = 5 V VGS = 3 V 15 VGS = 2 V 0 0 50 TC, CASE TEMPERATURE (C) OPERATION IN THIS AREA LIMITED BY rDS(ON) 45 25 150 1.5 3.0 4.5 6.0 7.5 IDS(ON), DRAIN TO SOURCE ON CURRENT (A) ID, DRAIN CURRENT (A) 10 0.2 0 IDS, DRAIN TO SOURCE CURRENT (A) 15 45 VDS = 15 V PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 30 15 0 0 1.5 3.0 4.5 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Saturation Characteristics Figure 6. Transfer Characteristics www.onsemi.com 3 6.0 RFD16N05LSM TYPICAL PERFORMANCE CURVES (Unless Otherwise Specified) (continued) ID = 16 V VDS = 15 V 1.3 2.5 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX. 1.1 1.5 1.0 0.9 1.0 0.8 0.7 0.5 0.6 5 4 1.3 0 -50 7 50 100 150 TJ, JUNCTION TEMPERATURE (C) Figure 7. Drain to Source on Resitance vs Gate Voltageand Drain Current Figure 8. Normalized Drain to Source on Resistance vs. Junction Temperature 1.4 ID = 250 mA VGS = VDS 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 0 VGS, GATE TO SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.4 6 0 50 100 150 200 ID = 250 mA 1.2 1.0 0.8 0.6 0 -50 200 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 9. Normalized Gate Threshold vs Junction Temperature Figure 10. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 50 2000 VGS = 0 V f = 1 MHz 1600 VDS, DRAIN TO SOURCE VOLTAGE (V) NORMALIZED GATE THRESHOLD VOLTAGE PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX. 2.0 1.2 0.5 C, CAPACITANCE (pF) ID = 16 A NORMALIZED DRAIN TO SOURCE ON RESISTANCE NORMALIZED DRAIN TO SOURCEON RESISTANCE 1.4 CISS 1200 CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 800 COSS 400 CRSS 0 RL = 3.125 W, VGS = 5 V IG(REF) = 0.60 mA PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS VDD = BVDSS VDD = BVDSS VDD = 0.75 BVDSS VDD = 0.50 BVDSS VDD = 0.25 BVDSS 37.5 25 GATE SOURCE VOLTAGE 12.5 DRAIN TO SOURCE VOLTAGE 0 0 5 10 15 20 0 25 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 11. Capacitance vs Drain to Source Voltage 20 IG(REF) IG(ACT) t, TIME (ms) 80 IG(REF) IG(ACT) Figure 12. Normalized Switching Waveforms for Constant Gate Current www.onsemi.com 4 RFD16N05LSM TEST CIRCUITS AND WAVEFORMS VDS BV DSS tP VDS L IAS VARY t P TO OBTAIN RG REQUIRED PEAK I AS VDD + - VGS VDD DUT tP 0V 0 IAS t AV 0.01 W Figure 13. Unclamped Energy Test Circuit Figure 14. Unclamped Energy Waveforms t ON t OFF t d(ON) VDS RG 90% 10% 0 VDD tf 90% RL + t d(OFF) tr 10% - 90% DUT VGS 0 VGS Figure 15. Switching Time Test Circuit 50% PULSE WIDTH Figure 16. Resistive Switching Waveforms VDS (ISOL ATED SUPPLY) CURRENT REGULATOR 50% 10% VDD Qg(TOT) 12V BAT TERY 0.2 mF 50 kW SAME TYPE AS DUT Qgd Qgs 0.3 mF VDS D IG(RE F) 0 DUT G 0 IG(REF) S IG CURRENT SAMPLING RESISTOR VGS VDS ID CURRENT SAMPLING RESISTOR 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms www.onsemi.com 5 RFD16N05LSM PSPICE ELECTRICAL MODEL .SUBCKT RFD16N05L 2 1 3 ; REV 4/8/92 Ca 12 8 3.33e-9 Cb 15 14 3.11e-9 Cin 6 8 1.21e-9 Dbody 7 5 DBDMOD Dbreak 5 11 DBKMOD Dplcap 10 5 DPLCAPMOD Ebreak 11 7 17 18 70.9 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evto 20 6 18 8 1 IT 8 17 1 Lgate 1 9 1.38e-9 Ldrain 2 5 1.0e-12 Lsource 3 7 1.0e-9 Mos1 16 6 8 8 MOSMOD M = 0.99 Mos2 16 21 8 8 MOSMOD M = 0.01 Rin 6 8 1e9 Rbreak 17 18 RBKMOD 1 Rdrain 5 16 RDSMOD 27.38e-3 Rgate 9 20 2.98 Rsource 8 7 RDSMOD 0.614e-3 Rvto 18 19 RVTOMOD 1 S1a S1b S2a S2b 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD Vbat 8 19 DC 1 Vto 21 6 0.448 .MODEL DBDMOD D (IS = 1.34e-13 RS = 1.21e-2 TRS1 = 1.64e-3 TRS2 = 2.59e-6 +CJO = 1.13e-9 TT = 4.14e-8) .MODEL DBKMOD D (RS = 8.82e-2 TRS1 = -2.01e-3 TRS2 = 7.32e-10) .MODEL DPLCAPMOD D (CJO = 0.522e-9 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 2.054 KP = 24.73 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 1.01e-3 TC2 = 5.21e-8) .MODEL RDSMOD RES (TC1 = 3.66e-3 TC2 = 1.46e-5) .MODEL RVTOMOD RES (TC1 = -1.81e-3 TC2 = 1.41e-6) .MODEL S1AMOD VSWITCH(RON = 1e-5 ROFF = 0.1 VON = -4.25 VOFF = -2.25) .MODEL S1BMOD VSWITCH(RON = 1e-5 ROFF = 0.1 VON = -2.25 VOFF = -4.25) .MODEL S2AMOD VSWITCH(RON = 1e-5 ROFF = 0.1 VON = -0.65 VOFF = 4.35) .MODEL S2BMOD VSWITCH(RON = 1e-5 ROFF = 0.1 VON = 4.35 VOFF = -0.65) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. www.onsemi.com 6 RFD16N05LSM DPLCAP 5 10 DRAIN 2 LDRAIN RSCL1 + 51 5 ESCL 51 50 RSCL2 - ESG + GATE 1 LGATE 9 20 RGATE 6 8 RDRAIN VTO EVTO + 18 - 8 16 + 21 6 S1B S2B 13 + EGS MOS2 + DBODY - RSOURCE 7 LSOURCE 3 SOURCE S2A 14 13 13 8 CA 17 EBREAK 18 CIN 8 S1A 11 MOS1 RIN 12 DBREAK 6 8 - 15 17 RBREAK 18 RVTO CB + EDS - 5 8 IT 14 19 + Figure 19. www.onsemi.com 7 VBAT MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK3 (TO-252 3 LD) CASE 369AS ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13810G DPAK3 (TO-252 3 LD) DATE 30 SEP 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped "CONTROLLED COPY" in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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