© Semiconductor Components Industries, LLC, 2003
May, 2019 Rev. 2
1Publication Order Number:
RFD16N05LSM/D
RFD16N05LSM
Product Preview
MOSFET - Power,
N-Channel, Logic Level
50 V, 16 A, 47 mW
These are NChannel logic level power MOSFETs manufactured
using the MegaFET process. This process, which uses feature sizes
approaching those of LSI integrated circuits gives optimum utilization
of silicon, resulting in outstanding performance. They were designed
for use with logic level (5 V) driving sources in applications such as
programmable controllers, switching regulators, switching converters,
motor relay drivers and emitter switches for bipolar transistors. This
performance is accomplished through a special gate oxide design
which provides full rated conductance at gate biases in the 3 V to 5 V
range, thereby facilitating true onoff power control directly from
logic circuit supply voltages.
Formerly developmental type TA09871.
Features
16 A, 50 V
rDS(ON) = 0.047 W
UIS SOA Rating Curve (Single Pulse)
Design Optimized for 5 V Gate Drives
Can be Driven Directly from CMOS, NMOS, TTL Circuits
SOA is Power Dissipation Limited
Nanosecond Switching Speeds
Linear Transfer Characteristics
High Input Impedance
Majority Carrier Device
Related Literature
TB334 “Guidelines for Soldering Surface Mount Components to
PC Boards”
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MARKING DIAGRAM
Part Number Package Brand
ORDERING INFORMATION
RFD16N05LSM9A TO252AA RFD16N05LSM
&Y = ON Semiconductor Logo
&Z = Assembly Plant Code
&3 = Numeric Date Code
&K = Lot Code
RFD16N05LSM = Specific Device Code
D
S
G
DPAK
TO252
CASE 369AS
G
S
D
$Y&Z&3&K
RFD16N
05LSM
RFD16N05LSM
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2
MAXIMUM RATINGS
Rating Symbol RFD16N05LSM9A Units
Drain to Source Voltage (Note 1) VDS 50 V
Drain to Gate Voltage (RGS 20 kW) (Note 1) VDGR 50 V
Continuous Drain Current ID16 A
Pulsed Drain Current (Note 3) IDM 45 A
Gate to Source Voltage VGS ±10 V
Maximum Power Dissipation PD60 W
Derate Above 25°C 0.48 W/°C
Operating and Storage Temperature TJ, TSTG 55 to 150 °C
Maximum Temperature for Soldering
Leads at 0.063 in (1.6 mm) from Case for 10 s TL300 °C
Package Body for 10 s, See Techbrief 334 Tpkg 260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. TJ = 25°C to 125°C.
ELECTRICAL SPECIFICATIONS (TC = 25°C unless otherwise specified)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250 mA, VGS = 0 V, Figure 10 50 - - V
Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250 mA, Figure 9 12 V
Zero Gate Voltage Drain Current IDSS VDS = 40 V, VGS = 0 V 1mA
TC = 150°C 50 mA
Gate to Source Leakage Current IGSS VGS = ±10 V, VDS = 0 V 100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 16 A, VGS = 5 V 0.047 W
ID = 16 A, VGS = 4 V 0.056 W
TurnOn Time t(ON) VDD = 25 V, ID = 8 A, VGS = 5 V,
RGS = 12.5 W
Figures 15, 16
60 ns
TurnOn Delay Time td(ON) 14 ns
Rise Time tr30 ns
TurnOff Delay Time td(OFF) 42 ns
Fall Time tf14 ns
TurnOff Time t(OFF) ns
Total Gate Charge Qg(TOT) VGS = 0 V to 10 V VDD = 40 V,
ID = 16 A,
RL = 2.5 Ω
Figures 17, 18
80 nC
Gate Charge at 5 V Qg(5) VGS = 0 V to 5 V 45 nC
Threshold Gate Charge Qg(TH) VGS = 0 V to 1 V 3 nC
Thermal Resistance Junction to Case RqJC 2.083 °C/W
Thermal Resistance Junction to Ambient RqJA 100 °C/W
SOURCE TO DRAIN DIODE SPECIFICATIONS
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 16 A - - 1.5 V
Diode Reverse Recovery Time trr ISD = 16 A, dISD/dt = 100 A/ms- - 125 ns
2. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature.
RFD16N05LSM
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3
TYPICAL PERFORMANCE CURVES (Unless Otherwise Specified)
Figure 1. Normalized Power Dissipation vs
Case Temperature
Figure 2. Maximum Continuous Drain Current
vs Case Temperature
Figure 3. Forward Bias Safe Operating Area Figure 4. Unclamped Inductive Switching SOA
(Single Pulse UIS SOA)
Figure 5. Saturation Characteristics Figure 6. Transfer Characteristics
TC, CASE TEMPERATURE (°C)
POWER DISSIPATION MULTIPLIER
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
IDS, DRAIN TO SOURCE CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
IDS(ON), DRAIN TO SOURCE ON CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
1.2
1.0
0.8
0.6
0.4
0.2
0
0 25 50 75 100 125 150
TC, CASE TEMPERATURE (°C)
0
25 50 75 100 125 150
5
10
15
20
0.1
11010
2
1
102102
10
1
0.01 0.10 1 10
0
0 1.5 3.0 4.5 6.0 7.5
15
30
45
0
15
30
45
0 1.5 3.0 4.5 6.0
TC = 25°C
TJ = MAX RATED
ID MAX CONTINUOUS
OPERATION IN THIS AREA
LIMITED BY rDS(ON)
DC
Idm
If R = 0
tAV = (L)(IAS)/(1.3 RATED BVDSS VDD)
If R 0
tAV = (L/R)ln[(IAS ×R)/(1.3 RATED BVDSS VDD) +1]
Starting TJ = 150°C
Starting TJ = 25°C
VGS = 10 V
VGS = 5 V
VGS = 3 V
VGS = 2 V
TC = 25°C
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX.
VGS = 4 V VDS = 15 V
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
RFD16N05LSM
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4
TYPICAL PERFORMANCE CURVES (Unless Otherwise Specified) (continued)
Figure 7. Drain to Source on Resitance vs
Gate Voltageand Drain Current
Figure 8. Normalized Drain to Source on
Resistance vs. Junction Temperature
Figure 9. Normalized Gate Threshold vs
Junction Temperature
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 11. Capacitance vs Drain to Source
Voltage
Figure 12. Normalized Switching Waveforms
for Constant Gate Current
VGS, GATE TO SOURCE VOLTAGE (V)
NORMALIZED DRAIN TO SOURCEON
RESISTANCE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
NORMALIZED GATE THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VDS, DRAIN TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
t, TIME (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
0.5
4
TJ, JUNCTION TEMPERATURE (°C)
0
50
0.6
50
0
50
0
0
0
0
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
5 6 7 0 50 100 150 200
0.5
1.0
1.5
2.0
2.5
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
0 50 100 150 200
0.6
0.8
1.0
1.2
1.4
0 50 100 150 200
400
800
1200
1600
2000
5 10152025
12.5
25
37.5
50
20
IG(REF)
IG(ACT)
80
IG(REF)
IG(ACT)
ID = 16 V
VDS = 15 V
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX.
ID = 16 A
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX.
ID = 250 mA
VGS = VDS
ID = 250 mA
VGS = 0 V
f = 1 MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
CISS
CISS
COSS
CRSS
RL = 3.125 W, VGS = 5 V
IG(REF) = 0.60 mA
PLATEAU VOLTAGES IN DESCENDING ORDER:
VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
GATE
SOURCE
VOLTAGE
VDD = BVDSS VDD = BVDSS
DRAIN TO SOURCE VOLTAGE
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5
TEST CIRCUITS AND WAVEFORMS
Figure 13. Unclamped Energy Test Circuit Figure 14. Unclamped Energy Waveforms
Figure 15. Switching Time Test Circuit Figure 16. Resistive Switching Waveforms
Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms
tP
VGS
0.01 W
L
IAS
+
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0 V
VGS
RL
RG
DUT
+
VDD
0.3 mF
12V
BAT TERY 50 kW
VDS
S
DUT
D
G
IG(RE F)
0
(ISOL ATED
VDS
0.2 mF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT
VDD
VDS
BVDSS
tP
IAS
tAV
0
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
IG(REF)
0
RFD16N05LSM
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6
PSPICE ELECTRICAL MODEL
.SUBCKT RFD16N05L 2 1 3 ; REV 4/8/92
Ca 12 8 3.33e-9
Cb 15 14 3.11e-9
Cin 6 8 1.21e-9
Dbody 7 5 DBDMOD
Dbreak 5 11 DBKMOD
Dplcap 10 5 DPLCAPMOD
Ebreak 11 7 17 18 70.9
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evto 20 6 18 8 1
IT 8 17 1
Lgate 1 9 1.38e-9
Ldrain 2 5 1.0e-12
Lsource 3 7 1.0e-9
Mos1 16 6 8 8 MOSMOD M = 0.99
Mos2 16 21 8 8 MOSMOD M = 0.01
Rin 6 8 1e9
Rbreak 17 18 RBKMOD 1
Rdrain 5 16 RDSMOD 27.38e-3
Rgate 9 20 2.98
Rsource 8 7 RDSMOD 0.614e-3
Rvto 18 19 RVTOMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 8 19 DC 1
Vto 21 6 0.448
.MODEL DBDMOD D (IS = 1.34e-13 RS = 1.21e-2 TRS1 = 1.64e-3 TRS2 = 2.59e-6 +CJO = 1.13e-9
TT = 4.14e-8)
.MODEL DBKMOD D (RS = 8.82e-2 TRS1 = -2.01e-3 TRS2 = 7.32e-10)
.MODEL DPLCAPMOD D (CJO = 0.522e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 2.054 KP = 24.73 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 1.01e-3 TC2 = 5.21e-8)
.MODEL RDSMOD RES (TC1 = 3.66e-3 TC2 = 1.46e-5)
.MODEL RVTOMOD RES (TC1 = -1.81e-3 TC2 = 1.41e-6)
.MODEL S1AMOD VSWITCH(RON = 1e-5 ROFF = 0.1 VON = -4.25 VOFF = -2.25)
.MODEL S1BMOD VSWITCH(RON = 1e-5 ROFF = 0.1 VON = -2.25 VOFF = -4.25)
.MODEL S2AMOD VSWITCH(RON = 1e-5 ROFF = 0.1 VON = -0.65 VOFF = 4.35)
.MODEL S2BMOD VSWITCH(RON = 1e-5 ROFF = 0.1 VON = 4.35 VOFF = -0.65)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE SubCircuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
RFD16N05LSM
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7
Figure 19.
EVTO
+
13
CA CB
EGS EDS
RIN CIN
MOS1
MOS2
DBREAK
EBREAK
DBODY
LDRAIN
DRAIN
RSOURCE LSOURCE
SOURCE
RBREAK
RVTO
VBAT
IT
VTO
DPLCAP
6
10
5
16
21
8
14
73
17 18
19
2
+
+
+
RDRAIN
ESCL
RSCL1
RSCL2 51
50
+
S1A S2A
S2BS1B
12 15
13
8
14
13
6
8
+
5
8
18
8
RGATE
GATE
LGATE
209
1
ESG
+
6
811 +
17
18
5
51
DPAK3 (TO252 3 LD)
CASE 369AS
ISSUE O
DATE 30 SEP 2016
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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DPAK3 (TO252 3 LD)
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