Publication Order Number:
MMFT2955E/D
Semiconductor Components Industries, LLC, 2000
November, 2000 – Rev. 5 1
MMFT2955E
Preferred Device
Power MOSFET
1 Amp, 60 Volts
P–Channel SOT–223
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. This new energy efficient device
also offers a drain–to–source diode with a fast recovery time.
Designed for low voltage, high speed switching applications in power
supplies, converters and PWM motor controls, these devices are
particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients. The device is
housed in the SOT–223 package which is designed for medium power
surface mount applications.
•Silicon Gate for Fast Switching Speeds
•The SOT–223 Package can be Soldered Using Wave or Reflow. The
Formed Leads Absorb Thermal Stress During Soldering, Eliminating
the Possibility of Damage to the Die
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain–to–Source Voltage VDS 60
Vdc
Gate–to–Source Voltage – Continuous VGS ±15 Vdc
Drain Current – Continuous
Drain Current – Pulsed ID
IDM 1.2
4.8 Adc
Total Power Dissipation @ TA = 25°C
Derate above 25°CPD
(Note 1.) 0.8
6.4 Watts
mW/°C
Operating and Storage Temperature
Range TJ, Tstg –65 to
150 °C
Single Pulse Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = 25 V, VGS = 10 V, Peak
IL= 1.2 A, L = 0.2 mH, RG = 25 Ω)
EAS 108 mJ
THERMAL CHARACTERISTICS
Thermal Resistance –
Junction–to–Ambient (surface mounted) RθJA 156 °C/W
Maximum Temperature for Soldering
Purposes,
Time in Solder Bath TL260
10
°C
Sec
1. Power rating when mounted on FR–4 glass epoxy printed circuit board using
recommended footprint.
1 AMPERE
60 VOLTS
RDS(on) = 300 m
Device Package Shipping
ORDERING INFORMATION
MMFT2955ET1 SOT–223 1000 Tape & Reel
MMFT2955ET3 SOT–223 1000 Tape & Reel
D
S
G
123
4
P–Channel
TO–261AA
CASE 318E
STYLE 3
http://onsemi.com
LWW
MARKING
DIAGRAM
2955E
L = Location Code
WW = Work Week
PIN ASSIGNMENT
Preferred devices are recommended choices for future use
and best overall value.
321
4
Gate Drain Source
Drain
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2
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage, (VGS = 0, ID = 250 µA) V(BR)DSS 60 – – Vdc
Zero Gate Voltage Drain Current,
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS –
––
–1.0
50
µAdc
Gate–Body Leakage Current,
(VGS = 15 V, VDS = 0) IGSS – – 100 nAdc
ON CHARACTERISTICS
Gate Threshold Voltage, (VDS = VGS, ID = 1 mA) VGS(th) 2.0 – 4.5 Vdc
Static Drain–to–Source On–Resistance, (VGS = 10 V, ID = 0.6 A) RDS(on) – – 0.3 Ohms
Drain–to–Source On–Voltage, (VGS = 10 V, ID = 1.2 A) VDS(on) – – 0.48 Vdc
Forward Transconductance, (VDS = 15 V, ID = 0.6 A) gFS – 7.5 – mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS
=
20 V,
Ciss – 460 –
Output Capacitance
(VDS
=
20
V
,
VGS = 0,
f1MH)
Coss – 210 – pF
Reverse Transfer Capacitance
GS
f = 1 MHz) Crss – 84 –
SWITCHING CHARACTERISTICS (Note 2.)
Turn–On Delay Time td(on) – 18 –
Rise Time (VDD = 25 V, ID = 1.6 A
VGS =10VR
G= 50 ohms
tr– 29 –
ns
Turn–Of f Delay Time VGS = 10 V, RG = 50 ohms,
RGS = 25 ohms) td(off) – 44 – ns
Fall Time
RGS
25
ohms)
tf– 32 –
Total Gate Charge
(VDS
=
48 V, ID
=
1.2 A,
Qg– 18 –
Gate–Source Charge
(VDS
=
48
V
,
ID
=
1
.
2
A
,
VGS = 10 Vdc)
SFi 15d16
Qgs – 2.8 – nC
Gate–Drain Charge
GS )
See Figures 15 and 16 Qgd – 7.5 –
SOURCE DRAIN DIODE CHARACTERISTICS (Note 3.)
Forward On–Voltage IS = 1.2 A, VGS = 0 VSD – 1.0 – Vdc
Forward Turn–On Time IS = 1.2 A, VGS = 0,
dlS/dt = 400 A/µs
ton Limited by stray inductance
Reverse Recovery Time dlS/dt = 400 A/µs,
VR = 30 V trr – 90 – ns
2. Switching characteristics are independent of operating junction temperature.
3. Pulse Test: Pulse Width ≤300 µs, Duty Cycle ≤2%.
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TYPICAL ELECTRICAL CHARACTERISTICS
RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)
RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 1. On Region Characteristics Figure 2. Gate–Threshold Voltage Variation
With Temperature
Figure 3. Transfer Characteristics Figure 4. On–Resistance versus Drain Current
Figure 5. On–Resistance versus
Gate–to–Source Voltage Figure 6. On–Resistance versus
Junction Temperature
10
8
6
4
2
01086420
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
20 V
15 V
10 V 8 V
7 V
6 V
5 V
VGS = 4 V
VGS(th), GATE THRESHOLD VOLTS (NORMALIZE
D
1.1
-50
TJ, JUNCTION TEMPERATURE (°C)
0.7
0.8
0.9
1
0 50 100 150
VDS = VGS
ID = 1 mA
8
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
6
4
2
01086420
VDS = 10 V
-55°C
25°C
100°C
-55°C25°C
100°C
-55°C
ID, DRAIN CURRENT (AMPS)
0.6
0
0.5
0.4
0.3
0.2
0.1
02468
VGS = 10 V
100°C
25°C
-55°C
0.5
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
4
0.4
0.2
0.1
0
0.3
710131619
TJ = 25°C
ID = 1.2 A
0.5
TJ, JUNCTION TEMPERATURE (°C)
0.4
0.2
0.1
0
0.3
-50 0 50 100 150
VGS = 10 V
ID = 1.2 A
1.2
TJ = 25°C
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FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of linear
systems. The curves are based on a ambient temperature of
25°C and a maximum junction temperature of 150°C.
Limitations for repetitive pulses at various ambient
temperatures can be determined by using the thermal
response curves. ON Semiconductor Application Note,
AN569, “Transient Thermal Resistance–General Data and
Its Use” provides detailed instructions.
SWITCHING SAFE OPERATING AREA
The switching safe operating area (SOA) is the boundary
that the load line may traverse without incurring damage to
the MOSFET. The fundamental limits are the peak current,
IDM and the breakdown voltage, BVDSS. The switching
SOA is applicable for both turn–on and turn–off of the
devices for switching times less than one microsecond.
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
D
I , DRAIN CURRENT (AMPS)
1
0.1
0.01
0.1 10 100
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
10
1 s
DC
500 ms
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
100 ms
20ms
VGS = 20 V
SINGLE PULSE
TA = 25°C
Figure 8. Thermal Response
1.0
0.1
0.001
1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00
r(t), EFFECTIVE THERMAL RESISTANCE
t, TIME (s)
0.1
0.01
0.2
0.02
0.01
D = 0.5
SINGLE PULSE
(NORMALIZED)
0.05 RθJA(t) = r(t) RθJA
RθJA = 156°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TA = P(pk) RθJA(t)
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
1.0E+01
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated
source–d rai n curre nt v e rs us r e –a pplied drain voltage when the source–drain diode has undergone forward bias. The curve shows
the limitations of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to
those of Figure 9 are present. Full or half–bridge PWM DC motor controllers are common applications requiring CSOA data.
Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher
values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device,
package, and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse
blocking.
VDS(pk) is the peak drain–to–source voltage that the device must sustain during commutation; IFM is the maximum forward
source–drain diode current just prior to the onset of commutation.
VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only a second order effect on CSOA.
Stray inductances in ON Semiconductor’s test circuit are assumed to be practical minimums. d VDS/dt i n e xcess o f 1 0 V /ns
was attained with dIS/dt of 400 A/µs.
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RG
t
VDS
L
IL
VDD
Figure 9. Commutating Waveforms
tP
BVDSS
VDD
IL(t)
t, (TIME)
Figure 10. Commutating Safe Operating
Area (CSOA)
15 V
VGS
0
90%
IFM dlS/dt
IS
10% trr
tfrr
0.25 IRM
IRM
ton
VDS VfVdsL
VR
VDS(pk)
MAX. CSOA
STRESS AREA
Figure 11. Commutating Safe Operating Area
Test Circuit
S
I , SOURCE CURRENT (AMPS)
Figure 12. Unclamped Inductive Switching
Test Circuit
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
+
-
+
-
Figure 13. Unclamped Inductive Switching
Waveforms
VR
VGS
IFM
20 V
RGS DUT
ISLi
VR = 80% OF RATED VDSS
VdsL = Vf + Li ⋅ dlS/dt
6
5
4
3
2
1
080706050403020100
dIS/dt ≤400 A/µs
VDS
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Figure 14. Capacitance Variation with Voltage
SAME
DEVICETYPE
AS DUT
Vin
+18V VDD
10V 100k
0.1µF
FERRITE
BEAD DUT
100
2N3904
2N3904
47k
15V
100k
Vin = 15 Vpk; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10%.
1mA
47k
1000
800
200
400
600
0
Figure 15. Gate Charge versus Gate–To–Source Voltage
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Ciss
Figure 16. Gate Charge Test Circuit
1200
1400
1600
1800
Crss
Coss
Ciss
Coss
Crss
VGS
15 10 5 0 5 10 15 20
VDS
Qg, TOTAL GATE CHARGE (nC)
0
10
3 7.5 13 20
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
9
8
7
6
5
4
3
2
1
0
TJ = 25°C
VDS = 48 V
ID = 1.2 A
VGS VDS
TJ = 25°C
f = 1 MHz
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INFORMATION FOR USING THE SOT–223 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.079
2.0
0.15
3.8
0.248
6.3
0.079
2.0
0.059
1.5
0.059
1.5
0.059
1.5
0.091
2.3
0.091
2.3
mm
inches
SOT–223 POWER DISSIPATION
The power dissipation of the SOT–223 is a function of
the drain pad size. This can vary from the minimum pad
size for soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data
sheet for the SOT–223 package, PD can be calculated as
follows:
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 800 milliwatts.
PD = 150°C – 25°C
156°C/W = 800 milliwatts
The 156°C/W for the SOT–223 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 800
milliwatts. There are other alternatives to achieving higher
power dissipation from the SOT–223 package. One is to
increase the area of the drain pad. By increasing the area of
the drain pad, the power dissipation can be increased.
Although one can almost double the power dissipation with
this method, one will be giving up area on the printed
circuit board which can defeat the purpose of using surface
mount technology. A graph of RθJA versus drain pad area is
shown in Figure 17.
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8
0.8 Watts
1.25 Watts* 1.5 Watts
A, Area (square inches)
0.0 0.2 0.4 0.6 0.8 1.0
160
140
120
100
80
Figure 17. Thermal Resistance versus Drain Pad
Area for the SOT–223 Package (Typical)
Board Material = 0.0625″
G-10/FR-4, 2 oz Copper
TA = 25°C
*Mounted on the DPAK footprint
R , Thermal Resistance, Junction
to Ambient (C/W)
θ
JA
°
Another alternative would be to use a ceramic substrate
or an aluminum core board such as Thermal Clad. Using
a board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. A
solder stencil is required to screen the optimum amount of
solder paste onto the footprint. The stencil is made of brass
or stainless steel with a typical thickness of 0.008 inches.
The stencil opening size for the SOT–223 package should
be the same as the pad size on the printed circuit board, i.e.,
a 1:1 registration.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•Always preheat the device.
•The delta temperature between the preheat and
soldering should be 100°C or less.*
•When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
•The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
•When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
•After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied
during cooling
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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9
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 18 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177–189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 2
VENT
“SOAK”
STEP 3
HEATING
ZONES 2 & 5
“RAMP”
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
STEP 5
HEATING
ZONES 4 & 7
“SPIKE”
STEP 6
VENT STEP 7
COOLING
200°C
150°C
100°C
5°C
TIME (3 TO 7 MINUTES TOTAL) TMAX
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
205° TO 219°C
PEAK AT
SOLDER
JOINT
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
100°C
150°C160°C
170°C
140°C
Figure 18. Typical Solder Heating Profile
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PACKAGE DIMENSIONS
STYLE 3:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
H
S
F
A
B
D
G
L
4
123
0.08 (0003)
C
MK
J
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.249 0.263 6.30 6.70
INCHES
B0.130 0.145 3.30 3.70
C0.060 0.068 1.50 1.75
D0.024 0.035 0.60 0.89
F0.115 0.126 2.90 3.20
G0.087 0.094 2.20 2.40
H0.0008 0.0040 0.020 0.100
J0.009 0.014 0.24 0.35
K0.060 0.078 1.50 2.00
L0.033 0.041 0.85 1.05
M0 10 0 10
S0.264 0.287 6.70 7.30
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SOT–223 (TO–261)
CASE 318E–04
ISSUE K
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Notes
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12
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
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Phone: 81–3–5740–2700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
MMFT2955E/D
Thermal Clad is a registered trademark of the Bergquist Company.
NORTH AMERICA Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
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