NCP1075P065G - ON Semiconductor - Datasheet.Directory

March, 2018 − Rev. 9 1Publication Order Number:

NCP1070/D

NCP1070, NCP1071,

NCP1072, NCP1075,

NCP1076, NCP1077

High-Voltage Switcher for

Low Power Offline SMPS

The NCP107x products integrate a fixed frequency current mode

controller with a 700 V MOSFET. Available in a PDIP−7 or SOT−223

package, the NCP107x offer a high level of integration, including

soft−start, frequency−jittering, short−circuit protection, skip−cycle, a

maximum peak current set point, ramp compensation, and a Dynamic

Self−Supply (eliminating the need for an auxiliary winding).

Unlike other monolithic solutions, the NCP107x is quiet by nature:

during nominal load operation, the part switches at one of the available

frequencies (65, 100 or 130 kHz). When the output power demand

diminishes, the IC automatically enters frequency foldback mode and

provides excellent efficiency at light loads. When the power demand

reduces further, it enters into a skip mode to reduce the standby

consumption down to a no load condition.

Protection features include: a timer to detect an overload or a

short−circuit event, Overvoltage Protection with auto−recovery and

AC input line voltage detection.

For improved standby performance, the connection of an auxiliary

winding stops the DSS operation and helps to reduce input power

consumption below 50 mW at high line.

Features

•Built−in 700 V MOSFET with RDS(on) of 4.7 W (NCP1076/77) /

11 W (NCP1072/75) / 22 W (NCP1070/71)

•Large Creepage Distance Between High−voltage Pins

•Current−Mode Fixed Frequency Operation – 65 / 100 / 130 kHz

•Peak Current: NCP1070/72 with 250 mA, NCP1071 with 350 mA,

NCP1075 with 450 mA, NCP1076 with 650 mA and NCP1077 with

800 mA

•Fixed Ramp Compensation

•Skip−Cycle Operation at Low Peak Currents Only: No Acoustic

Noise!

•Dynamic Self−Supply: No Need for an Auxiliary

Winding

•Internal 1 ms Soft−Start

•Auto−Recovery Output Short Circuit Protection with

T imer−Based Detection

•Auto−Recovery Overvoltage Protection with Auxiliary

Winding Operation

•Frequency Jittering for Better EMI Signature, Including

Frequency Foldback Mode

•No Load Input Consumption < 50 mW

•Frequency Foldback to Improve Efficiency at Light

Load

•Internal Temperature Shutdown

•These are Pb−Free Devices

Typical Applications

•Auxiliary / Standby Isolated Power Supplies White

Goods / Smart Meter / E−Meter

SOT−223

ST SUFFIX

CASE 318E

MARKING

DIAGRAMS

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PDIP−7

P SUFFIX

CASE 626A

Z = 1 for Std product; V for Automotive

x = Current Limit (0, 1, 2, 5, 6 or 7)

y = Oscillator Frequency

= A (65 kHz), B (100 kHz), C (130 kHz)

yyy = 065, 100, 130

f = OFF phase in fault mode

= P (420 ms), B (210 ms)

A = Assembly Location

WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G or G= Pb−Free Package

AYW

z07xyG

P107xfyyy

AWL

YYWWG

See detailed ordering and shipping information on page 28 o

this data sheet.

ORDERING INFORMATION

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

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PIN CONNECTIONS

Figure 1. Pin Connections

(Top View)

SOT−223

VCC 1

VCC

(Top View)

PDIP−7

GND

DRAIN

GND

INDICATIVE MAXIMUM OUTPUT POWER

RDS(on) − IIPK 230 Vac 85−265 Vac

NCP1070 / 1071 22 W − 350 mA 14 W 7.75 W

NCP1072 / 1075 11 W − 450 mA 19 W 10 W

NCP1076 / 1077 4.7 W − 800 mA 25 W 15 W

NOTE: Informative values only, with Tamb = 50°C, FSW = 65 kHz, Self supply via Auxiliary winding and circuit mounted on minimum

copper area as recommended.

QUICK SELECTION TABLE

NCP1070 NCP1071 NCP1072 NCP1075 NCP1076 NCP1077

RDS(on) (W)22 11 4.7

Ipeak (mA) 250 350 250 450 650 800

Freq (kHz) 65 100 130 65 100 130 65 100 130* 65 100 130 65 100 130 65 100 130

*130 kHz on demand only

Figure 2. Typical Application Example

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

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PIN FUNCTION DESCRIPTION

Pin N5Pin Name Function Pin Description

1 VCC Powers the internal circuitry This pin is connected to an external capacitor. The VCC includes an

active shunt which serves as an auto−recovery over voltage protection.

2 NC

3 GND The IC Ground

4 FB Feedback signal input By connecting an opto−coupler to this pin, the peak current set point is

adjusted accordingly to the output power demand.

5 Drain Drain connection The internal drain MOSFET connection

6This un−connected pin ensures adequate creepage distance

7 GND The IC Ground

8 GND The IC Ground

Vcc

Management

UVLO

Reset

Vdd

Drain

Vcc

GND

UVLO

−

OSC

Jittering

SKIP

IFBskip

line

detection

trecovery

SCP

OFF

SKIP = ”1” −−> shut

down some blocks to

reduce consumption

LEB

−

Soft

Start

Reset

−

Vclamp

−

80−us

filter

Vcc OVP

DRV

DRV 200 ns

to CS setpoint

Ipk(0)

−

Ipflag

IFBfault

IOVP

TSD

OFF UVLO

LineOK

Reset SS as recovering from

SCP, TSD, Vcc OVP, or UVLO

IFB

freeze

Sawtooth

Ramp

compensation

Foldback

FB(up)

FB(REF)

SCP

Figure 3. Simplified Internal Circuit Architecture

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

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MAXIMUM RATINGS TABLE

Symbol Rating Value Unit

VCC Power Supply Voltage on all pins, except Pin 5(Drain) −0.3 to 10 V

BVdss Drain voltage −0.3 to 700 V

IDS(PK) Drain current peak during transformer saturation (TJ = 150°C, Note 3):

NCP1070/71:

NCP1072/75:

NCP1076/77:

Drain current peak during transformer saturation (TJ = 25°C, Note 3):

NCP1070/71:

NCP1072/75:

NCP1076/77:

480

870

2200

850

1500

3900

I_VCC Maximum Current into Pin 1 when Activating the 8.2 V Active Clamp 15 mA

RqJ−A P Suffix, Case 626A 0.36 Sq. Inch 77 °C/W

Junction−to−Air, 2.0 oz Printed Circuit Copper Clad 1.0 Sq. Inch 60

RqJ−A ST Suffix, Plastic Package Case 318E 0.36 Sq. Inch 74 °C/W

Junction−to−Air, 2.0 oz Printed Circuit Copper Clad 1.0 Sq. Inch 55

TJMAX Maximum Junction Temperature 150 °C

Storage Temperature Range −60 to +150 °C

ESD Capability, Human Body Model (All pins except HV) 2 kV

ESD Capability, Machine Model 200 V

ESD Capability, Charged Device Model 1 kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

1. This device series contains ESD protection and exceeds the following tests:

Human Body Model 2000 V per JEDEC JESD22−A114−F

Machine Model Method 200 V per JEDEC JESD22−A115−A

Charged Device Model 1000 V per JEDEC JESD22−C101E

2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78

3. Maximum drain current IDS(PK) is obtained when the transformer saturates. It should not be mixed with short pulses that can be seen at turn

on. Figure 4 below provides spike limits the device can tolerate.

Figure 4. Spike Limits

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

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ELECTRICAL CHARACTERISTICS

(For all NCP107X products except NCP1072P100BG: For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 8 V

unless otherwise noted)

(For NCP1072P100BG: For typical values TJ = 25°C, for min/max values TJ = −55°C (Note 7) to +125°C, VCC = 8 V unless otherw ise noted)

Symbol Rating Pin Min Typ Max Unit

SUPPLY SECTION AND VCC MANAGEMENT

VCC(on) VCC increasing level at which the switcher starts operation

NCP1070/71/72/75

NCP1076/77 1

17.8

7.7

8.2

8.1 8.6

8.5

VCC(min) VCC decreasing level at which the HV current source restarts 1 6.5 6.8 7.2 V

VCC(off) VCC decreasing level at which the switcher stops operation (UVLO) 1 6.1 6.3 6.6 V

VCC(reset) VCC voltage at which the internal latch is reset (guaranteed by design) 1 4 V

VCC(clamp) Offset voltage above VCC(on) at which the internal clamp activates

NCP1070/71

NCP1072/75

NCP1076/77

110

130

170

190

300

ICC1 Internal IC consumption, Mosfet switching

NCP1070/71/72/75

NCP1076/77 1

−

0.7

1.0 1.0

1.3

ICCskip Internal IC consumption, FB is 0 V (No switching on MOSFET) 1 360 mA

POWER SWITCH CIRCUIT

RDS(on) Power Switch Circuit on−state resistance (Id = 50 mA)

NCP1070/71

TJ = 25°C

TJ = 125°C

NCP1072/75

TJ = 25°C

TJ = 125°C

NCP1076/77

TJ = 25°C

TJ = 125°C

−

4.7

8.7

6.9

10.75

BVDSS Power Switch Circuit & Startup breakdown voltage

(ID(off) = 120 mA, TJ = 25°C) 5 700 V

IDSS(off) Power Switch & Startup breakdown voltage off−state leakage current

TJ = 125°C (Vds = 700 V) 5 85 mA

ton

toff

Switching characteristics (RL=50 W, VDS set for Idrain = 0.7 x Ilim)

T urn−on time (90% − 10%)

T urn−off time (10% − 90%) 5

520

INTERNAL START−UP CURRENT SOURCE

Istart1 High−voltage current source, V = VCC(on) − 200 mV

NCP1070/71/76/77

NCP1072/75

55.2

9.2

12.2

Istart2 High−voltage current source, VCC = 0 V 5 0.5 mA

VCCTH VCC Transient level for Istart1 to Istart2 toggling point 1 − 2.2 − V

CURRENT COMPARATOR

IIPK Maximum internal current setpoint at 50% duty cycle

FB pin open, Tj = 25°C

NCP1070

NCP1071

NCP1072

NCP1075

NCP1076

NCP1077

−

250

350

250

450

650

800

−

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. The final switch current is: IIPK(0) / (Vin/LP + Sa) x V in/LP + V in/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP

the primary inductor in a flyback, and tprop the propagation delay.

5. NCP1072 130 kHz on demand only.

6. Oscillator frequency is measured with disabled jittering.

7. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

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ELECTRICAL CHARACTERISTICS

(For all NCP107X products except NCP1072P100BG: For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 8 V

unless otherwise noted)

(For NCP1072P100BG: For typical values TJ = 25°C, for min/max values TJ = −55°C (Note 7) to +125°C, VCC = 8 V unless otherw ise noted)

Symbol UnitMaxTypMinPinRating

CURRENT COMPARATOR

IIPK(0) Maximum internal current setpoint at beginning of switching cycle

FB pin open, Tj = 25°C

NCP1070

NCP1071

NCP1072

NCP1075

NCP1076

NCP1077

273

382

254

467

689

846

304

425

282

508

765

940

334

467

310

549

841

1034

IIPKSW Final switch current with a primary slope of 200 mA/ms,

FSW =65 kHz (Note 4)

NCP1070

NCP1071

NCP1072

NCP1075

NCP1076

NCP1077

−

314

427

296

510

732

881

−

IIPKSW Final switch current with a primary slope of 200 mA/ms,

FSW =100 kHz (Note 4)

NCP1070

NCP1071

NCP1072

NCP1075

NCP1076

NCP1077

−

309

415

293

500

706

845

−

IIPKSW Final switch current with a primary slope of 200 mA/ms,

FSW =130 kHz

NCP1070

NCP1071

NCP1072 (Note 5)

NCP1075

NCP1076

NCP1077

−

303

407

291

493

684

814

−

TSS Soft−start duration (guaranteed by design) − − 1 − ms

TLEB Leading Edge Blanking Duration − − 200 − ns

Tprop Propagation delay from current detection to drain OFF state − − 100 − ns

INTERNAL OSCILLATOR

fOSC Oscillation frequency, 65 kHz version, Tj = 25°C (Note 6) − 59 65 71 kHz

fOSC Oscillation frequency, 100 kHz version, Tj = 25°C (Note 6) − 90 100 110 kHz

fOSC Oscillation frequency, 130 kHz version, Tj = 25°C (Note 5 et 6) −117 130 143 kHz

fjitter Frequency jittering in percentage of fOSC − − ±6 − %

fswing Jittering swing frequency − − 300 − Hz

Dmax Maximum duty−cycle

NCP1070/71/72/75 except NCP1072P100BG

NCP1076/77/72B & NCP1072P100BG

−

−62

65 68

FEEDBACK SECTION

IFBfault FB current for which Fault is detected 4−35 mA

IFB100% FB current for which internal current set−point is 100% (IIPK(0)) 4 −44 mA

IFBFreeze FB current for which internal current set−point is IFreeze 4 − −90 −mA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. The final switch current is: IIPK(0) / (Vin/LP + Sa) x V in/LP + V in/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP

the primary inductor in a flyback, and tprop the propagation delay.

5. NCP1072 130 kHz on demand only.

6. Oscillator frequency is measured with disabled jittering.

7. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

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ELECTRICAL CHARACTERISTICS

(For all NCP107X products except NCP1072P100BG: For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 8 V

unless otherwise noted)

(For NCP1072P100BG: For typical values TJ = 25°C, for min/max values TJ = −55°C (Note 7) to +125°C, VCC = 8 V unless otherw ise noted)

Symbol UnitMaxTypMinPinRating

FEEDBACK SECTION

VFB(REF) Equivalent pull−up voltage in linear regulation range

(Guaranteed by design) 4 3.3 V

RFB(up) Equivalent feedback resistor in linear regulation range

(Guaranteed by design) 4 19.5 kW

FREQUENCY FOLDBACK & SKIP

IFBfold Start of frequency foldback feedback level 4 − −68 −mA

IFBfold(end) End of frequency foldback feedback level, Fsw = Fmin 4 − −100 −mA

Fmin The frequency below which skip−cycle occurs − 21 25 29 kHz

IFBskip The feedback level to enter skip mode 4 − −120 −mA

IFreeze Internal minimum current setpoint (IFB = IFBFreeze)

NCP1070

NCP1071

NCP1072

NCP1075

NCP1076

NCP1077

−−

−

123

168

228

280

−

RAMP COMPENSATION

Sa(65) The internal ramp compensation @ 65 kHz

NCP1070

NCP1071

NCP1072

NCP1075

NCP1076

NCP1077

−

4.2

7.5

−

mA/ms

Sa(100) The internal ramp compensation @ 100 kHz

NCP1070

NCP1071

NCP1072

NCP1075

NCP1076

NCP1077

−

6.5

11.5

−

mA/ms

Sa(130) The internal ramp compensation @ 130 kHz

NCP1070

NCP1071

NCP1072 (Note 5)

NCP1075

NCP1076

NCP1077

− −

−

8.4

−

PROTECTIONS

tSCP Fault validation further to error flag assertion − 40 53 − ms

trecovery OFF phase in fault mode

NCP1070/1/2/5/6/7

NCP1072P100BG −

−−

−420

210 −

−

IOVP VCC clamp current at which the switcher stops pulsing

NCP1070/71

NCP1072/75/76/77

6.2

8.7

8.5 11.2

tOVP The filter of VCC OVP comparator − − 80 − ms

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. The final switch current is: IIPK(0) / (Vin/LP + Sa) x V in/LP + V in/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP

the primary inductor in a flyback, and tprop the propagation delay.

5. NCP1072 130 kHz on demand only.

6. Oscillator frequency is measured with disabled jittering.

7. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

www.onsemi.com

ELECTRICAL CHARACTERISTICS

(For all NCP107X products except NCP1072P100BG: For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, VCC = 8 V

unless otherwise noted)

(For NCP1072P100BG: For typical values TJ = 25°C, for min/max values TJ = −55°C (Note 7) to +125°C, VCC = 8 V unless otherw ise noted)

Symbol UnitMaxTypMinPinRating

PROTECTIONS

VHV(EN) The drain pin voltage above which allows MOSFET operate, which is

detected after TSD, UVLO, SCP, or VCC OVP mode. 5 72 91 110 V

TEMPERATURE MANAGEMENT

TSD Temperature shutdown (Guaranteed by design) − 150 °C

Hysteresis in shutdown (Guaranteed by design) − 50 °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. The final switch current is: IIPK(0) / (Vin/LP + Sa) x V in/LP + V in/LP x tprop, with Sa the built−in slope compensation, Vin the input voltage, LP

the primary inductor in a flyback, and tprop the propagation delay.

5. NCP1072 130 kHz on demand only.

6. Oscillator frequency is measured with disabled jittering.

7. For coldest temperature, QA sampling at −40°C in production and −55°C specification is Guaranteed by Characterization.

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

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TYPICAL CHARACTERISTICS

Figure 5. VCC(on) vs. Temperature Figure 6. VCC(min) vs. Temperature

Figure 7. VCC(off) vs. Temperature Figure 8. VCC(clamp) vs. Temperature

Figure 9. ICC1 vs. Temperature Figure 10. RDS(on) vs. Temperature

8.4

8.3

8.2

8.1

8.0

7.9

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

VCC(on) (V)

7.0

6.9

6.8

6.7

6.6

6.5

−50 −25 0 25 50 75 100 125

VCC(min) (V)

TEMPERATURE (°C)

6.6

−50 −25 0 25 50 75 100 125

VCC(off) (V)

TEMPERATURE (°C)

6.5

6.4

6.3

6.2

6.1

240

220

200

180

160

140

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

VCC(clamp) (V)

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

ICC1 (mA)

0.80

0.75

0.70

0.65

0.60

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

RDS(on) (W)

35 NCP1070/71

NCP1072/75

NCP1076/77

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TYPICAL CHARACTERISTICS

Figure 11. IDSS(off) vs. Temperature Figure 12. Istart1 vs. Temperature

Figure 13. Istart2 vs. Temperature Figure 14. IIPK(0) vs. Temperature

Figure 15. F

OSC

vs. Temperature Figure 16. D

(max)

vs. Temperature

100

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

DSS(off)

(

50 −50 −25 0 25 50 75 100 12

Istart1 (mA)

−50 −25 0 25 50 75 100 125

0.6

0.5

0.4

0.3

0.2

0.1

TEMPERATURE (°C)

start2

(mA)

TEMPERATURE (°C)

1000

IIPK(0) (mA)

−50 −25 0 25 50 75 100 12

900

700

600

500

400

300

200

−50 −25 0 25 50 75 100 125

110

100

TEMPERATURE (°C)

OSC

(kHz)

−50 −25 0 25 50 75 100 12

TEMPERATURE (°C)

Dmax (%)

110

NCP1075

NCP1072

100 kHz

65 kHz

NCP1076

NCP1077

NCP1071

NCP1070

800

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

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TYPICAL CHARACTERISTICS

Figure 17. Fmin vs. Temperature Figure 18. tSCP vs. Temperature

Figure 19. trecovery vs. Temperature Figure 20. IOVP vs. Temperature

Figure 21. VHV(EN) vs. Temperature

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

Fmin (kHz)

21 −50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

tSCP (ms)

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

510

trecovery (ms)

490

470

450

430

410

390

370

350 −50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

IOVP (mA)

9.5

9.0

8.5

8.0

7.5

7.0

−50 −25 0 25 50 75 100 125

TEMPERATURE (°C)

110

VHV(EN) (V)

105

100

Figure 22. Drain Current Peak during Transformer

Saturation vs. Junction Temperature

TJ, JUNCTION TEMPERATURE (°C)

1251007550250−25−50

IDS(PK) (A)

150

NCP1076/77

NCP1072/75

NCP1070/71

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

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TYPICAL CHARACTERISTICS

Figure 23. Breakdown Voltage vs. Temperature

TEMPERATURE (°C)

1006040200−20−40

0.925

0.950

0.975

1.025

1.050

1.100

BVDSS/BVDSS (25°C)(−)

125

1.000

1.075

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

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APPLICATION INFORMATION

Introduction

The NCP107x offers a complete current−mode control

solution. The component integrates everything needed to

build a rugged and low−cost Switch−Mode Power Supply

(SMPS) featuring low standby power. The Quick Selection

Table on page 2 details the differences between references,

mainly peak current setpoints and operating frequency.

•Current−mode operation: the controller uses

current−mode control architecture.

•700 V Power MOSFET: Due to ON Semiconductor

Very High Voltage Integrated Circuit technology, the

circuit hosts a high*voltage power MOSFET featuring

a 22/11/4.7 W RDS(on) – TJ = 25°C. This value lets the

designer build a power supply up to respectively

7.75 W, 10 W and 15 W operated on universal mains.

An internal current source delivers the startup current,

necessary to crank the power supply.

•Dynamic Self−Supply: Due to the internal high voltage

current source, this device could be used in the

application without the auxiliary winding to provide

supply voltage.

•Short circuit protection: by permanently monitoring the

feedback line activity, the IC is able to detect the

presence of a short−circuit, immediately reducing the

output power for a total system protection. A tSCP timer

is started as soon as the feedback current is below

threshold, IFB(fault), which indicates the maximum peak

current. If at the end of this timer the fault is still

present, then the device enters a safe, auto−recovery

burst mode, affected by a fixed timer recurrence,

trecovery. Once the short has disappeared, the controller

resumes and goes back to normal operation.

•Built−in VCC Over Voltage Protection: when the

auxiliary winding is used to bias the VCC pin (no DSS),

an internal active clamp connected between VCC and

ground limits the supply dynamics to VCC(clamp). In

case the current injected in this clamp exceeds a level

of 6.0 mA (minimum), the controller immediately stops

switching and waits a full timer period (trecovery) before

attempting to restart. If the fault is gone, the controller

resumes operation. If the fault is still there, e.g. a

broken opto−coupler, the controller protects the load

through a safe burst mode.

•Line detection: An internal comparator monitors the

drain voltage as recovering from one of the following

situations:

♦Short Circuit Protection,

♦VCC OVP is confirmed,

♦UVLO

♦TSD

If the drain voltage is lower than the internal threshold

(VHV(EN)), the internal power switch is inhibited. This

avoids operating at too low ac input. This is also called

brown−in function in some fields.

•Frequency jittering: an internal low−frequency

modulation signal varies the pace at which the

oscillator frequency is modulated. This helps spreading

out energy in conducted noise analysis. To improve the

EMI signature at low power levels, the jittering remains

active in frequency foldback mode.

•Soft−Start: a 1 ms soft−start ensures a smooth startup

sequence, reducing output overshoots.

•Frequency foldback capability: a continuous flow of

pulses is not compatible with no−load/light−load

standby power requirements. To excel in this domain,

the controller observes the feedback current

information and when it reaches a level of IFBfold, the

oscillator then starts to reduce its switching frequency

as the feedback current continues to increase (the power

demand continues to reduce). It can go down to 25 kHz

(typical) reached for a feedback level of IFBfold(end)

(100 mA roughly). At this point, if the power continues

to drop, the controller enters classical skip−cycle mode.

•Skip: if SMPS naturally exhibits a good efficiency at

nominal load, they begin to be less efficient when the

output power demand diminishes. By skipping

un−needed switching cycles, the NCP107x drastically

reduces the power wasted during light load conditions.

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APPLICATION INFORMATION

Startup Sequence

When the power supply is first powered from the mains

outlet, the internal current source is biased and charges up

the VCC capacitor from the drain pin. Once the voltage on

this VCC capacitor reaches the VCC(on) level, the current

source turns off and pulses are delivered by the output stage:

the circuit is awake and activates the power MOSFET if the

bulk voltage is above VHV(EN) level. Figure 24 details the

simplified internal circuitry.

VCC(on)

VCC(min)

Istart1

Vbulk

CVCC

Rlimit

ICC1

Vclamp

Iclamp

Iclamp > IOVP

--> OVP fault

Drain

Figure 24. The Internal Arrangement of the Start−up Circuitry

Being loaded by the circuit consumption, the voltage on

the V CC capacitor goes down. When VCC is below VCC(min)

level, it activates the internal current source to bring VCC

toward VCC(on) level and stops again: a cycle takes place

whose low frequency depends on the VCC capacitor and the

IC consumption. A 1.4 V ripple takes place on the VCC pin

whose average value equals (VCC(on) + VCC(min))/2.

Figure 25 portrays a typical operation of the DSS.

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Figure 25. The Charge/Discharge Cycle Over a 1 mF VCC Capacitor

As one can see, even if there is auxiliary winding to

provide energy for VCC, it happens that the device is still

biased by DSS during start−up time or some fault mode

when the voltage on auxiliary winding is not ready yet. The

VCC capacitor shall be dimensioned to avoid VCC crosses

VCC(off) level, which stops operation. The DV between

VCC(min) and VCC(off) is 0.4 V. There is no current source to

charg e V CC capacitor when driver is on, i.e. drain voltage is

close to zero. Hence the VCC capacitor can be calculated

using

CVCC wICC1Dmax

fOSC @DV(eq. 1)

Take the NCP1072 65 kHz device as an example. CVCC

should be above

0.8m @72%

59 kHz @0.4

A margin that covers the temperature drift and the voltage

drop due to switching inside FET should be considered, an d

thus a capacitor above 0.1 mF is appropriate.

The VCC capacitor has only a supply role and its value

does not impact other parameters such as fault duration or

the frequency sweep period for instance. As one can see on

Figure 24, an internal active zener diode, protects the

switcher against lethal VCC runaways. This situation can

occur if the feedback loop optocoupler fails, for instance,

and you would like to protect the converter against an over

voltage event. In that case, the internal current increase

incurred by the VCC rapid growth triggers the over voltage

protection (OVP) circuit and immediately stops the output

pulses for trecovery duration (420 ms typically). Then a new

start−up attempt takes place to check whether the fault has

disappeared or not. The OVP paragraph gives more design

details on this particular section.

Fault Condition – Short−Circuit on VCC

In some fault situations, a short−circuit can purposely

occur between VCC and GND. In high line conditions ( V HV

= 370 VDC) the current delivered by the startup device will

seriously increase the junction temperature. For instance,

since I start1 equals 5 mA (the min corresponds to the highest

Tj), the device would dissipate 370 x 5 m = 1.85 W. To avoid

this situation, the controller includes a novel circuitry made

of two startup levels, Istart1 and Istart2. At power−up, as long

as VCC is below a 2.4 V level, the source delivers Istart2

(around 500 mA typical), then, when VCC reaches 2.4 V, the

source smoothly transitions to I start1 and delivers its nominal

value. As a result, in case of short−circuit between VCC and

GND, the power dissipation will drop to 370 x 500u =

185 mW. Figure 25 portrays this particular behavior.

The first startup period is calculated by the formula C x V

= I x t, which implies a 1m x 2.4 / 500u = 4.8 ms startup time

for the first sequence. The second sequence is obtained by

toggling the source to 8 mA with a delta V of VCC(on) –

VCCTH = 8.2 – 2.4 = 5.8 V, which finally leads to a second

startup time of 1m x 5.8 / 8m = 0.725 ms. The total startup

time becomes 4.8m + 0.725m = 5.525 ms. Please note that

this calculation is approximated by the presence of the knee

in the vicinity of the transition.

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Fault Condition – Output Short−Circuit

As soon as VCC reaches VCC(on), drive pulses are

internally enabled. If everything is correct, the auxiliary

winding increases the voltage on the VCC pin as the output

voltage rises. During the start−sequence, the controller

smoothly ramps up the peak drain current to maximum

setting, i.e. IIPK, which is reached after a typical period of

1 ms. When the output voltage is not regulated, the current

coming through FB pin is below IFBfault level (35 mA

typically), which is not only during the startup period but

also anytime an overload occurs, an internal error flag is

asserted, Ipflag, indicating that the system has reached its

maximum current limit set point. The assertion of this flag

triggers a fault counter tSCP (53 ms typically). If at counter

completion, Ipflag remains asserted, all driving pulses are

stopped and the part stays off in trecovery duration (about

420 ms). A new attempt to re−start occurs and will last 53 ms

providing the fault is still present. If the fault still af fects the

output, a safe burst mode is entered, affected by a low

duty−cycle operation (11%). When the fault disappears, the

power supply quickly resumes operation. Figure 26 depicts

this particular mode:

Figure 26. In Case of Short−Circuit or Overload, the NCP107X Protects Itself and the Power Supply Via a Low

Frequency Burst Mode. The VCC is Maintained by the Current Source and Self−supplies the Controller.

Auto−Recovery Over Voltage Protection

The particular NCP107X arrangement offers a simple

way to prevent output voltage runaway when the

optocoupler fails. As Figure 27 shows, an active zener diode

monitors and protects the VCC pin. Below its equivalent

breakdown voltage, that is to say 8.4 V typical, no current

flows in it. If the auxiliary VCC pushes too much current

inside the zener, then the controller considers an OVP

situation and stops the internal drivers. When an OVP

occurs, all switching pulses are permanently disabled. After

trecovery delay, it resumes the internal drivers. If the failure

symptom still exists, e.g. feedback opto−coupler fails, the

device keeps the auto−recovery OVP mode.

Figure 27 shows that the insertion of a resistor (Rlimit)

between the auxiliary dc level and the VCC pin is mandatory

a) not to damage the internal 8.4 V zener diode during an

overshoot for instance (absolute maximum current is

15 mA) b) t o implement the fail−safe optocoupler protection

(OVP) as o ffered by the active clamp. Please note that there

cannot be bad interaction between the clamping voltage of

the internal zener and VCC(on) since this clamping voltage is

actually built on top of VCC(on) with a fixed amount of offset

(200 mV typical). Rlimit should be carefully selected to avoid

triggering the OVP as we discussed, but also to avoid

disturbing the VCC in low / light load conditions. The below

lines detail how to evaluate the Rlimit value...

Self−supplying controllers in extremely low standby

applications of t e n p u z z l e s t h e designe r. Actually, if a SMPS

operated at nominal load can deliver an auxiliary voltage of

an arbitrary 16 V (Vnom), this voltage can drop below 10 V

(Vstby) when entering standby. This is because the

recurrence of the switching pulses expands so much that the

low frequency re−fueling rate of the VCC capacitor is not

enough to keep a proper auxiliary voltage. Figure 28

portrays a typical scope shot of a SMPS entering deep

standby (output un−loaded). Thus, care must be taken when

calculating Rlimit 1) to not trigger the VCC over current latch

(by injecting 6 mA into the active clamp – always use the

minimum value for worse case design) in normal operation

but 2) not to drop too much voltage over Rlimit when entering

standby. Otherwise, the converter will enter dynamic self

supply mode (DSS mode), which increases the power

dissipation. Based on these recommendations, we are able t o

bound Rlimit between two equations:

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Vnom *VCC(clamp)

Itrip vRlimit v

Vstby *VCC(min)

ICCskip (eq. 2)

Where:

Vnom is the auxiliary voltage at nominal load

Vstby is the auxiliary voltage when standby is entered

Itrip is the current corresponding to the nominal operation. It

thus must be selected to avoid false tripping in overshoot

conditions. Always use the minimum of the specification for

a robust design, i.e. Itrip < IOVP.

ICCskip is the controller consumption during skip mode.

This number decreases compared to normal operation since

the part in standby does almost not switch. It is around

0.36 mA for the NCP1072 65 kHz version.

VCC(min) is the level above which the auxiliary voltage must

be maintained to keep the controller away from the dynamic

self supply mode (DSS mode), which is not a problem in

itself if low standby power does not matter.

If a further improvement on standby efficiency is

concerned, it is good to obtain VCC around 8 V at no load

condition in order not to re−activate the internal clamp

circuit.

Figure 27. A More Detailed View of the NCP107x Offers Better Insight on How to Properly Wire an Auxiliary Winding

Iclamp > IOVP

Since Rlimit shall not bother the controller in standby, e.g.

keep VCC to above VCC(min) (7.2 V maximum), we

purposely select a Vnom well above this value. As explained

before, experience shows that a 40% decrease can be seen o n

auxiliary windings from nominal operation down to standby

mode. Let’s select a nominal auxiliary winding of 13 V to

offer sufficient margin regarding 7.2 V when in standby

(Rlimit also drops voltage in standby...). Plugging the values

in Equation 2 gives the limits within which Rlimit shall be

selected:

13 *8.4

6m vRlimit v8*7.2

0.36m

that is to say: 0.77 kW < Rlimit < 2.2 kW.

If we design a 65 kHz power supply delivering 12V, then

the ratio between auxiliary and power must be: 13 / 12 =

1.08. The OVP latch will activate when the clamp current

exceeds 6 mA. This will occur when Vauxiliary grows−up

to: 1. 8.4 + 0.77k x (6m + 0.8m) ≈ 13.6 V for the first

boundary (Rlimit = 0.77 kW)

2. 8.4 + 2.2k x (6m +0.8m) ≈ 23.4 V for the second

boundary (Rlimit = 2.2 kW)

Due to a 1.08 ratio between the auxiliary VCC and the

power winding, the OVP will be seen as a lower overshoot

on the real output:

1. 13.6 / 1.08 ≈ 12.6 V

2. 23.4 / 1.08 ≈ 21.7 V

As one can see, tweaking the Rlimit value will allow the

selection of a given overvoltage output level. Theoretically

predicting the auxiliary drop from nominal to standby is an

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almost impossible exercise since many parameters are

involved, including the converter time constants. Fine

tuning of Rlimit thus requires a few iterations and

experiments on a breadboard to check the auxiliary voltage

variations but also the output voltage excursion in fault.

Once properly adjusted, the fail−safe protection will

preclude any lethal voltage runaways in case a problem

would occur in the feedback loop.

Figure 28. The Burst Frequency Becomes so Low That it is Difficult to Keep an Adequate Level on the Auxiliary

VCC...

Figure 29 describes the main signal variations when the

part operates in auto−recovery OVP:

Figure 29. If the VCC Current Exceeds a Certain Threshold, an Auto−Recovery Protection is Activated

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Improving the precision in auto−recovery OVP

Given the OVP variations the internal trip current

dispersion incur, it is sometimes more interesting to explore

a different solution, improving the situation to the cost of a

minimal amount of surrounding elements. Figure 30 shows

that adding a simple zener diode on top of the limiting

resistor, offers a better precision since what matters now is

the internal VCC(on) breakdown plus the zener voltage. A

resistor in series with the zener diodes keeps the maximum

current in the VCC pin below the maximum rating of 15 mA

just before trip the OVP.

Vcc

Rlimit

Laux

Ground

Figure 30. A Simple Zener Diode Added in Parallel

Soft−Start

The NCP107X features a 1 ms soft−start which reduces

the power−on stress but also contributes to lower the output

overshoot. Figure 31 shows a typical operating waveform.

The NCP107X features a novel patented structure which

offers a better soft−start ramp, almost ignoring the start−up

pedestal inherent to traditional current−mode supplies:

VCCON

Drain current

Figure 31. The 1 ms soft−start sequence

Jittering

Frequency jittering is a method used to soften the EMI

signature by spreading the energy in the vicinity of the main

switching component. The NCP107X offers a ±6%

deviation of the nominal switching frequency. The sweep

sawtooth is internally generated and modulates the clock up

and down with a fixed frequency of 300 Hz. Figure 32

shows the relationship between the jitter ramp and the

frequency deviation. It is not possible to externally disable

the jitter.

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65kHz

68.9kHz

61.1kHz

Jitter ramp

Internal

sawtooth

adjustable

Figure 32. Modulation Effects on the Clock Signal by the Jittering Sawtooth

Line Detection

An internal comparator monitors the drain voltage as

recovering from one of the following situations:

•Short Circuit Protection,

•VCC OVP is confirmed,

•UVLO

•TSD

If the drain voltage is lower than the internal threshold

VHV(EN) (91 Vdc typically), the internal power switch is

inhibited. This avoids operating at too low ac input. This is

also called brown−in function in some fields.

Frequency Foldback

The reduction of no−load standby power associated with

the need for improving the efficiency, requires to change the

traditional fixed−frequency type of operation. This device

implements a switching frequency folback when the

feedback current passes above a certain level, IFBfold, set

around 68 mA. At this point, the oscillator enters frequency

foldback and reduces its switching frequency.

The internal peak current set−point is following the

feedback current information until its level reaches the

minimal freezing level point of IFreeze. The only way to

further reduce the transmitted power is to diminish the

operating frequency down to Fmin (25 kHz typically). This

value is reached at a feedback current level of IFBfold(end).

Below this point, if the output power continues to decrease,

the part enters skip cycle for the best noise−free performance

in no−load conditions. Figures 33 and 34 depict the adopted

scheme for the part.

Figure 33. By Observing the Current on the Feedback Pin, the Controller Reduces its Switching Frequency for an

Improved Performance at Light Load

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Figure 34. Ipk Set−point is Frozen at Lower Power Demand.

Feedback and Skip

Figure 35 depicts the relationship between feedback

voltage and current. The feedback pin operates linearly as

the absolute value of feedback current (IFB) is above 40 mA.

In this linear operating range, the dynamic resistance is

19.5 kW typically (RFB(up)) and the effective pull up voltage

is 3.3 V typically (VFB(REF)). When IFB is below 40 mA, the

FB voltage will jump to close to 4.5 V.

Figure 35. Feedback Voltage vs. Current

Figure 36 depicts the skip mode block diagram. When the

FB current information reaches IFBskip, the internal clock to

set the flip−flop is blanked and the internal consumption of

the controller is decreased. The hysteresis of internal skip

comparator is minimized to lower the ripple of the auxiliary

voltage for VCC pin and VOUT of power supply during skip

mode. It easies the design of VCC over load range.

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Figure 36. Skip Cycle Schematic

Ramp Compensation and Ipk Set−point

In order to allow the NCP107X to operate in CCM with a

duty cycle above 50%, a fixed slope compensation is

internally applied to the current−mode control.

Here we got a table of the ramp compensation, the initial

current set point, and the final current set−point of different

versions of switcher.

Fsw Sa Ipk(Duty = 50%) Ipk(0)

NCP1070

65 kHz 7 mA/ms

250 mA 304 mA

100 kHz 11 mA/ms

130 kHz 14 mA/ms

NCP1071

65 kHz 10 mA/ms

350 mA 425 mA

100 kHz 15 mA/ms

130 kHz 20 mA/ms

NCP1072

65 kHz 4.2 mA/ms

250 mA 282 mA

100 kHz 6.5 mA/ms

130 kHz 8.4 mA/ms

NCP1075

65 kHz 7.5 mA/ms

450 mA 508 mA

100 kHz 11.5 mA/ms

130 kHz 15 mA/ms

NCP1076

65 kHz 15 mA/ms

650 mA 765 mA

100 kHz 23 mA/ms

130 kHz 30 mA/ms

NCP1077

65 kHz 18 mA/ms

800 mA 940 mA

100 kHz 28 mA/ms

130 kHz 36 mA/ms

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The Figure 37 depicts the variation of IPK set−point vs. the power switcher duty ratio, which is caused by the internal ramp

compensation.

Figure 37. IPK Set−point Varies with Power Switch On Time, Which is Caused by the Ramp Compensation

Design Procedure

The design of an SMPS around a monolithic device does

not differ from that of a standard circuit using a controller

and a MOSFET. However , one needs to be aware of certain

characteristics specific of monolithic devices. Let us follow

the steps:

Vin min = 90 Vac or 127 Vdc once rectified, assuming a low

bulk ripple

Vin max = 265 Vac or 375 Vdc

Vout = 12 V

Pout = 10 W

Operating mode is CCM

h = 0.8

1. The lateral MOSFET body−diode shall never be

forward biased, either during start−up (because of

a large leakage inductance) or in normal operation

as shown by Figure 38. This condition sets the

maximum voltage that can be reflected during toff.

As a result, the Flyback voltage which is reflected

on the drain at the switch opening cannot be larger

than the input voltage. When selecting

components, you thus must adopt a turn ratio

which adheres to the following equation:

NǒVout )VfǓtVin,min (eq. 3)

2. In our case, since we operate from a 127 V DC rail

while delivering 12 V, we can select a reflected

voltage of 120 Vdc maximum. Therefore, the turn

ratio Np:Ns must be smaller than

Vreflect

Vout )Vf+120

12 )0.5 +9.6

or Np:Ns < 9.6. Here we choose N = 8 in this case.

We will see later on how it affects the calculation.

1.004M 1.011M 1.018M 1.025M 1.032M

−50.0

50.0

150

250

350

> 0 !!

Figure 38. The Drain−Source Wave Shall Always be Positive

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Figure 39. Primary Inductance Current Evolution in

CCM

ILavg

3. Lateral MOSFETs have a poorly doped

body−diode which naturally limits their ability to

sustain the avalanche. A traditional RCD clamping

network shall thus be installed to protect the

MOSFET. In some low power applications, a

simple capacitor can also be used since

Vdrain,max +Vin )NǒVout )VfǓ)Ipeak Lf

Ctot

(eq. 4)

where Lf is the leakage inductance, Ctot the total

capacitance at the drain node (which is increased by

the capacitor you will wire between drain and

source), N the NP:NS turn ratio, Vout the output

voltage, Vf the secondary diode forward drop and

finally, Ipeak the maximum peak current. Worse case

occurs when the SMPS is very close to regulation,

e.g. the Vout target is almost reached and Ipeak is still

pushed to the maximum. For this design, we have

selected our maximum voltage around 650 V (at Vin

= 375 Vdc). This voltage is given by the RCD clamp

installed from the drain to the bulk voltage. We will

see how to calculate it later on.

4. Calculate the maximum operating duty−cycle for

this flyback converter operated in CCM:

dmax +NǒVout )VfǓ

NǒVout )VfǓ)Vin,min +1

Vin,min

NǒVout)VfǓ

+0.44

(eq. 5)

5. To obtain the primary inductance, we have the

choice between two equations:

L+ǒVindǓ2

fswKPin

(eq. 6)

where

K+

DIL

ILavg

and defines the amount of ripple we want in CCM

(see Figure 39).

♦Small K: deep CCM, implying a large primary

inductance, a low bandwidth and a large

leakage inductance.

♦Large K: approaching BCM where the rms

losses are worse, but smaller inductance,

leading to a better leakage inductance.

From Equation 6, a K factor of 1 (50% ripple), gives

an inductance of:

L+(127 0.44)2

65k 1 12.75 +3.8 mH

+223 mA peak−to−peak

DIL+Vin,min @dmax

LFSW +127 0.44

3.8 65k

The peak current can be evaluated to be:

Ipeak +Iavg

DIL

2+Ipeak +98m

0.44 )

DIL

+335 mA

On IL, ILavg can also be calculated:

ILavg +Ipeak *

DIL

2+0.34 *0.112 +223 mA

6. Based on the above numbers, we can now evaluate

the conduction losses:

Id,rms +dǒIpeak 2*IpeakDIL)DIL2

+0.44ǒ0.3352*0.335 @0.223 )0.2232

+154 mA

If we take the maximum Rds(on) for a 125°C junction

temperature, i.e. 24 W, then conduction losses worse

case are:

Pcond +Id,rms 2RDS(on) +570 mW

7. Off−time and on−time switching losses can be

estimated based on the following calculations:

Poff +

IpeakǒVbulk )VclampǓtoff

2Tsw (eq. 7)

+0.335 (127 )120 @2) 10n

2 15.4m

+36 mW

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Where, assume the Vclamp is equal to two times of

reflected voltage.

Pon +

IvalleyǒVbulk )NǒVout )VfǓǓton

6Tsw

(eq. 8)

+0.111 (127 )100) 20n

6 15.4m

+5.5 mW

It is noted that the overlap of voltage and current seen

on MOSFET during turning on and off duration is

dependent on the snubber and parasitic capacitance

seen from drain pin. Therefore the toff and ton in

Equations 7 and 8 have to be modified after

measuring on the bench.

8. The theoretical total power is then 0.570 + 0.036 +

0.0055 = 611 mW

9. If the NCP107X operates at DSS mode, then the

losses caused by DSS mode should be counted as

losses of this device on the following calculation:

PDSS +ICC1 @Vin,max +1m @375 +375 mW

(eq. 9)

MOSFET protection

As in any Flyback design, it is important to limit the drain

excursion to a safe value, e.g. below the MOSFET BVdss

which is 700 V. Figure 40a, b, c present possible

implementations:

Figure 40. Different Options to Clamp the Leakage Spike

ab c

Figure 40a: the simple capacitor limits the voltage

according to The lateral MOSFET body−diode shall never

be forward biased, either during start−up (because of a large

leakage inductance) or in normal operation as shown by

Figure 38. This condition sets the maximum voltage that can

be reflected during toff. As a result, the Flyback voltage

which is reflected on the drain at the switch opening cannot

be larger than the input voltage. When selecting

components, you thus must adopt a turn ratio which adheres

to the following equation: Equation 3. This option is only

valid for low power applications, e.g. below 5 W, otherwise

chances exist to destroy the MOSFET. After evaluating the

leakage inductance, you can compute C with Equation 4.

Typical values are between 100 pF and up to 470 pF. Large

capacitors increase capacitive losses...

Figure 40b: the most standard circuitry is called the RCD

network. You calculate Rclamp and Cclamp using the

following formulae:

Rclamp +

clampǒVclamp *ǒVout )VfǓNǓ

LleakIpeak 2Fsw

(eq. 10)

Cclamp +

Vclamp

VrippleFswRclamp

(eq. 11)

Vclamp is usually selected 50−80 V above the reflected

value N x (Vout + Vf). The diode needs to be a fast one and

a MUR160 represents a good choice. One major drawback

of the RCD network lies in its dependency upon the peak

current. Worse case occurs when Ipeak and V in are maximum

and Vout is close to reach the steady−state value.

Figure 40c: this option is probably the most expensive of

all three but it offers the best protection degree. If you need

a very precise clamping level, you must implement a zener

diode or a TVS. There are little technology differences

behind a standard zener diode and a TVS. However, the die

area is far bigger for a transient suppressor than that of zener.

A 5 W zener diode like the 1N5388B will accept 180 W peak

power if it lasts less than 8.3 ms. If the peak current in the

worse case (e.g. when the PWM circuit maximum current

limit works) multiplied by the nominal zener voltage

exceeds these 180 W, then the diode will be destroyed when

the supply experiences overloads. A transient suppressor

like the P6KE200 still dissipates 5 W of continuous power

but is able to accept surges up to 600 W @ 1 ms. Select the

zener or TVS clamping level between 40 to 80 V above the

reflected output voltage when the supply is heavily loaded.

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Power Dissipation and Heatsinking

The NCP107X welcomes two dissipating terms, the DSS

current−source (when active) and the MOSFET. Thus, Ptot

= PDSS + PMOSFET. It is mandatory to properly manage the

heat generated by losses. If no precaution is taken, risks exist

to trigger the internal thermal shutdown (TSD). To help

dissipating the heat, the PCB designer must foresee large

copper areas around the package. Take the PDIP−7 package

as an example, when surrounded by a surface greater than

1.0 cm2 of 35 mm copper, it becomes possible to drop its

thermal resistance junction−to−ambient, RqJA down to

75°C/W and thus dissipate more power. The maximum

power the device can thus evacuate is:

Pmax +TJmax *Tambmax

RqJA

(eq. 12)

which gives around 930 mW for an ambient of 50°C and a

maximum junction of 120°C. If the surface is not large

enough, assuming the RqJA is 100°C/W, then the maximum

power the device can evacuate becomes 700 mW. Figure 41

gives a possible layout to help drop the thermal resistance.

Figure 41. A Possible PCB Arrangement to Reduce the Thermal Resistance Junction−to−Ambient

A 10 W NCP1075 based Flyback Converter Featuring

Low Standby Power

Figure 43 depicts a typical application showing a

NCP1075−65 kHz operating in a 10 W converter. To leave

more room for the MOSFET, it is recommended to disable

the DSS by shorting the J3. In this application, the feedback

is made via a NCP431 whose low bias current (50 mA) helps

to lower the no load standby power.

Measurements have been taken from a demonstration

board implementing the diagram in Figure 43 and the

following results were achieved with auxiliary winding to

bias the device:

100 Vac 115 V ac 230 Vac 265 Vac

No load consumption with

auxiliary winding 26 mW 28 mW 38 mW 45 mW

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

www.onsemi.com

Figure 42. Vout = 12 V

Figure 43. A 12 V – 0.85 A Universal Mains Power Supply

R_L3

MA5597−AL

10 nF

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

www.onsemi.com

ORDERING INFORMATION

Device Frequency RDS(on) (W)Ipk (mA) Package Type Shipping†

NCP1070STAT3G 65 kHz 22 250 SOT−223

(Pb−Free)

4000 / Tape & Reel

NCP1070STBT3G 100 kHz 22 250 4000 / Tape & Reel

NCP1070STCT3G 130 kHz 22 250 4000 / Tape & Reel

NCP1070P065G 65 kHz 22 250 PDIP−7

(Pb−Free)

50 Units / Rail

NCP1070P100G 100 kHz 22 250 50 Units / Rail

NCP1070P130G 130 kHz 22 250 50 Units / Rail

NCP1071STAT3G 65 kHz 22 350 SOT−223

(Pb−Free)

4000 / Tape & Reel

NCP1071STBT3G 100 kHz 22 350 4000 / Tape & Reel

NCP1071STCT3G 130 kHz 22 350 4000 / Tape & Reel

NCP1071P065G 65 kHz 22 350 PDIP−7

(Pb−Free)

50 Units / Rail

NCP1071P100G 100 kHz 22 350 50 Units / Rail

NCP1071P130G 130 kHz 22 350 50 Units / Rail

NCP1072STAT3G 65 kHz 11 250 SOT−223

(Pb−Free) 4000 / Tape & Reel

NCP1072STBT3G 100 kHz 11 250 4000 / Tape & Reel

NCP1072P065G 65 kHz 11 250 PDIP−7

(Pb−Free)

50 Units / Rail

NCP1072P100G 100 kHz 11 250 50 Units / Rail

NCP1072P100BG 100 kHz 11 250 50 Units / Rail

NCP1075STAT3G 65 kHz 11 450 SOT−223

(Pb−Free)

4000 / Tape & Reel

NCP1075STBT3G 100 kHz 11 450 4000 / Tape & Reel

NCP1075STCT3G 130 kHz 11 450 4000 / Tape & Reel

NCP1075P065G 65 kHz 11 450 PDIP−7

(Pb−Free)

50 Units / Rail

NCP1075P100G 100 kHz 11 450 50 Units / Rail

NCP1075P130G 130 kHz 11 450 50 Units / Rail

NCP1076STAT3G 65 kHz 4.7 650 SOT−223

(Pb−Free)

4000 / Tape & Reel

NCP1076STBT3G 100 kHz 4.7 650 4000 / Tape & Reel

NCP1076STCT3G 130 kHz 4.7 650 4000 / Tape & Reel

NCP1076P065G 65 kHz 4.7 650 PDIP−7

(Pb−Free)

50 Units / Rail

NCP1076P100G 100 kHz 4.7 650 50 Units / Rail

NCP1076P130G 130 kHz 4.7 650 50 Units / Rail

NCP1077STAT3G 65 kHz 4.7 800 SOT−223

(Pb−Free)

4000 / Tape & Reel

NCP1077STBT3G 100 kHz 4.7 800 4000 / Tape & Reel

NCP1077STCT3G 130 kHz 4.7 800 4000 / Tape & Reel

NCP1077P065G 65 kHz 4.7 800 PDIP−7

(Pb−Free)

50 Units / Rail

NCP1077P100G 100 kHz 4.7 800 50 Units / Rail

NCP1077P130G 130 kHz 4.7 800 50 Units / Rail

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

www.onsemi.com

PACKAGE DIMENSIONS

SOT−223 (TO−261)

CASE 318E−04

ISSUE N

123

0.08 (0003)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCH.

1.5

0.059 ǒmm

inchesǓ

SCALE 6:1

3.8

0.15

2.0

0.079

6.3

0.248

2.3

0.091 2.3

0.091

2.0

0.079

HEDIM

AMIN NOM MAX MIN

MILLIMETERS

1.50 1.63 1.75 0.060

INCHES

A1 0.02 0.06 0.10 0.001

b0.60 0.75 0.89 0.024

b1 2.90 3.06 3.20 0.115

c0.24 0.29 0.35 0.009

D6.30 6.50 6.70 0.249

E3.30 3.50 3.70 0.130

e2.20 2.30 2.40 0.087

0.85 0.94 1.05 0.033

0.064 0.068

0.002 0.004

0.030 0.035

0.121 0.126

0.012 0.014

0.256 0.263

0.138 0.145

0.091 0.094

0.037 0.041

NOM MAX

L1 1.50 1.75 2.00 0.060

6.70 7.00 7.30 0.264 0.069 0.078

0.276 0.287

HE− −

0°10°0°10°

L0.20 −−− −−− 0.008 −−− −−−

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

NCP1070, NCP1071, NCP1072, NCP1075, NCP1076, NCP1077

www.onsemi.com

PACKAGE DIMENSIONS

PDIP−7 (PDIP−8 LESS PIN 6)

CASE 626A

ISSUE C

NOTE 8

TOP VIEW

SEATING

PLANE

0.010 CA

SIDE VIEW

END VIEW

WITH LEADS CONSTRAINED

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: INCHES.

3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK -

AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.

4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH

OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE

NOT TO EXCEED 0.10 INCH.

5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM

PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR

TO DATUM C.

6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE

LEADS UNCONSTRAINED.

7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE

LEADS, WHERE THE LEADS EXIT THE BODY.

8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE

CORNERS).

NOTE 5

e/2 A2

NOTE 3

MBMNOTE 6

DIM MIN MAX

INCHES

A−−−− 0.210

A1 0.015 −−−−

b0.014 0.022

C0.008 0.014

D0.355 0.400

D1 0.005 −−−−

e0.100 BSC

E0.300 0.325

M−−−− 10

−−− 5.33

0.38 −−−

0.35 0.56

0.20 0.36

9.02 10.16

0.13 −−−

2.54 BSC

7.62 8.26

−−− 10

MIN MAX

MILLIMETERS

E1 0.240 0.280 6.10 7.11

eB −−−− 0.430 −−− 10.92

0.060 TYP 1.52 TYP

A2 0.115 0.195 2.92 4.95

L0.115 0.150 2.92 3.81

°°

NCP1070/D

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ON Semiconductor:

NCP1072P100G NCP1072STBT3G NCP1075P065G NCP1075STAT3G NCP1072STAT3G NCP1075STBT3G

NCP1075P130G NCP1075STCT3G NCP1075P100G NCP1072P065G NCP1071SOTGEVB NCP1075PSRGEVB

NCP1076DIPGEVB NCP1071P065G NCP1071P100G NCP1076STAT3G NCP1071STAT3G NCP1076P065G

NCP1076STBT3G NCP1071P130G NCP1071STBT3G NCP1076STCT3G NCP1076P100G NCP1076P130G

NCP1071STCT3G NCP1076BAP100G NCP1076BAP065G NCP1076BAP130G