6
LTC1144
and hence the efficiency, is set by the output impedance.
As frequency is decreased, the output impedance will
eventually be dominated by the 1/(f × C1) term and power
efficiency will drop.
Note also that power efficiency decreases as frequency
goes up. This is caused by internal switching losses which
occur due to some finite charge being lost on each
switching cycle. This charge loss per unit cycle, when
multiplied by the switching frequency, becomes a current
loss. At high frequency this loss becomes significant and
the power efficiency starts to decrease.
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
OSCILLATOR FREQUENCY (kHz)
0.1
POWER CONVERSION EFFICIENCY (%)
OUTPUT RESISTANCE (Ω)
100
95
90
85
80
75
70
600
500
400
300
200
100
0
1 10 100
1144 F05
V
+
= 15V, C1 = C2 = 10µF
I
L
= 20mA, T
A
= 25°C
POWER
CONVERSION
EFFICIENCY
OUTPUT
RESISTANCE
Figure 5. Power Conversion Efficiency and Output
Resistance vs Oscillator Frequency
SHDN (Pin 6)
The LTC1144 has a SHDN pin that will disable the internal
oscillator when it is pulled low. The supply current will also
drop to 8µA.
OSC (Pin 7) and Boost (Pin 1)
The switching frequency can be raised, lowered or driven
from an external source. Figure 6 shows a functional
diagram of the oscillator circuit.
By connecting the boost pin (pin 1) to V
+
, the charge and
discharge current is increased, and hence the frequency is
increased by approximately 10 times. Increasing the fre-
quency will decrease output impedance and ripple for
higher load currents.
Loading pin 7 with more capacitance will lower the fre-
quency. Using the boost (pin 1) in conjunction with exter-
nal capacitance on pin 7 allows user selection of the
frequency over a wide range.
Driving the LTC1144 from an external frequency source
can be easily achieved by driving pin 7 and leaving the
boost pin open as shown in Figure 7. The output current
from pin 7 is small, typically 4µA, so a logic gate is capable
of driving this current. The choice of using a CMOS logic
gate is best because it can operate over a wide supply
voltage range (3V to 15V) and has enough voltage swing
to drive the internal Schmitt trigger shown in Figure 6. For
5V applications, a TTL logic gate can be used by simply
adding an external pull-up resistor (see Figure 7).
Capacitor Selection
External capacitors C1 and C2 are not critical. Matching is
not required, nor do they have to be high quality or tight
tolerance. Aluminum or tantalum electrolytics are excel
lent
choices, with cost and size being the only consideration.
Figure 6. Oscillator
OSC
(7)
SCHMITT
TRIGGER
BOOST
(1)
1144 F06
9I
9I
I
I
V
+
GND
(3)
≈20pF
1
2
3
4
8
7
6
5
+
+
C1
OSC INPUT
NC
REQUIRED FOR
TTL LOGIC
C2
100k
–(V+)
V+
1144 F07
LTC1144
Figure 7. External Clocking