fax id: 1099 PRELIMINARY CY62127V Features 2.7V-3.6V operation CMOS for optimum speed/power Low active power (70 ns) 198 mW (max.) (55 mA) Low standby power (70 ns, LL version) 54 wW (max.) (15 WA) Automatic power-down when deselected Power down either with CE or BHE and BLE HIGH * Independent control of Upper and Lower Bytes Available in 44-pin TSOP II (forward) Functional Description The CY62127V is a high-performance CMOS static RAM or- ganized as 65,536 words by 16bits. This device has an auto- matic power-down feature that significantly reduces power consumption by 99% when deselected. The device enters power-down mode when CE is HIGH or when CE is LOW and both BLE and BHE are HIGH. 64K x 16 Static RAM Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O, through |/Og), is written into the location specified on the address pins (Ag through Aj5). If byte high enable (BHE) is LOW, then data from I/O pins (I/Og through |/O4) is written into the location speci- fied on the address pins (Ag through Aj4s). Reading from the device is accomplished by taking chip en- able (CE) and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O, to I/Og. If byte high enable (BHE) is LOW, then data from memory will appear on |/Og to I/O4g. See the truth table at the back of this datasheet for a complete description of read and write modes. The input/output pins (I/O, through |/O4g) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY62127V is available in standard 44-pin TSOP Type II (forward pinout) and mini-BGA packages. Logic Block Diagram Pin Configurations TSOP Il (Forward) <_<}, Top View DATA IN DRIVERS <q A,Q1 441 As Ap | As Q2 8 1 Ag A, Ao Gs Ay a | A; 04 411 OE 10 Ao M5 401 BHE Ag| a ao = 39 = Q = CEUs 1) BLE A; | 64K x 16 <x VO, 07 380 VO1g Agp-1 5 RAM Array o 1/01/03 /OoOs 870 O45 Ag > = 1024 X 1024 a 0309 361 1/044 Az | O oO EP 1/09/0146 04 (10 3817 1/043 A, Veco O11 341] Vss A, Vgs 12 83 Voc l /Os C13 321] Oj. Og O14 3100 1/0,, VO7 O15 30D O49 29 FJ I/O: COLUMN DECODER WEE 7 28 A NC. Ais O18 271 Ag Aya 019 260 Ag Ai3 20 20 Aio yo om Oo +t ne Ae ap fell PiZ Nc (22 23 NC 62127V-1 62127V-2 Cypress Semiconductor Corporation + 3901 North First Street -* SanJose + CA 95134 + 408-943-2600 February 9, 1998mes PRELIMINARY CY62127V So Pin Configurations (continued) Mini-BGA T 2 3 4 5 6 HOMO) |r OHMOMEE) | MOAMMOOQE |e HOME) | COCOOOE) | CILIEIC)QYE) |F COCOGOR: COMEIEIEIE) | 62127V-3 Selection Guide 62127V-55 62127V-70 Units Maximum Access Time 55 70 ns Maximum Operating Current 55 55 mA Maximum CMOS Standby Current Com'| Std 0.3 0.3 mA L 50 50 HA LL 15 15 HA Indl LL 30 30 HA Shaded areas contain advance information Maximum Ratings Current into Outputs (LOW) oo... ccccsceececseesseeseeteees 20 mA (Above which the useful life may be impaired. For user guide- ar MIL:STD.283, Moxhod $01 5) eee >2001V lines, not tested.) Latch-Up C , 200 mA Storage Temperature cecccccecscsseccsssssssseceen 65C to +150C Atch-Up Current ........ecccceseescececeseeesseetsneesseeesneetaas > m Ambient Temperature with Operating Range Power Applied ........ccceceeesseeeeesneesenneeeneees 55C to +125C Ambient mbien Supply Voltage on Vcc to Relative GND!"I .... -0.5V to +4.6V Range Temperature! Vee pe voltage Applied to Outputs 05V to Ven 40.5V Commercial 0C to +70C 2.7V-3.6V in Hig tate . see eetneeeeteaeeeenneeeetineetnnees 0.5V to Voc +0. Industrial 40C to 185C > 7Vo3 BV DC Input Voltagel oc ccecseeseeseeenee 0.5V to Veg +0.5V Notes: 1. Vit (min.) = -2.0V for pulse durations of less than 20 ns. 2. Ty is the instant on case temperature.PRELIMINARY CY62127V S37 CyPRESS Electrical Characteristics Over the Operating Range 62127V_-55, 70 Parameter Description Test Conditions Min. Typ./3 Max. | Unit Vou Output HIGH Voltage Veco = Min., lo =-1.0 mA 2.2 Vv VoL Output LOW Voltage Voc = Min., lop = 2.1 mA 0.4 V Vin Input HIGH Voltage 2.0 Vect Vv 0.3 Vi Input LOW Voltage!!! -0.3 0.4 V ix Input Load Current GND <V,< Voc 1 +1 HA loz Output Leakage Current | GND<V\< Voc, -1 +1 pA Output Disabled loc Voc Operating Voc = Max. 55 mA Supply Current loyt = 0 mA, Ispi Automatic CE Max. Voc, CE = Vin 2 mA Power-Down Current Vin 2 Vin or TTL Inputs Vin < ViLs f= fMaAX Ispo Automatic CE Max. Vcc, Std 0.3 mA Power-Down Current CE = Vcc 0.8, L 50 A CMOS Inputs Vin 2 Voc 0.3V, H or Vin < 0.3V, f=0 Com! LL 0.5 15 HA Ind LL 0.5 30 HA Capacitance"! Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f = 1 MHz, 9 pF Cout Output Capacitance Voc = 8.3V 9 pF AC Test Loads and Waveforms R1 10762 R1 10762 3.0V O-wwr 3.0VO | 1 soy ALL INPUT PULSES OUTPUT o1r1 OUTPUT o1+4 $ Re $ Re? 30 rT ~ 1262 rT f 1262 q GND INCLUDING = = INCLUDING = = <3ns JIG AND JIG AND SCOPE (a) SCOPE (b) 5810 Equivalent to: THEVENIN OUTPUTQ~wwO__ 1.62V EQUIVALENT 62127V-4 Notes: 3. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (Ta = 25C, Vece=3.0V). Parameters are guaranteed by design and characterization, and not 100% tested. 4. Tested initially and after any design or process changes that may affect these parameters.PRELIMINARY CY62127V Switching Characteristics Over the Operating Range 62127V-55 62127V-70 Parameter Description Min. Max. Min. Max. Unit READ CYCLE tre Read Cycle Time 55 70 ns taAA Address to Data Valid 55 70 ns toHA Data Hold from Address Change 10 10 ns tace CE LOW to Data Valid 55 70 ns tpoE OE LOW to Data Valid 25 35 ns tLZ0E OE LOW to Low 21] 5 5 ns tHz0E OE HIGH to High ZS 71 20 25 ns tLzcE CE LOW to Low Z1/] 10 10 ns tuzce CE HIGH to High Z! 7 20 25 ns tpy CE LOW to Power-Up 0 a) ns tpp CE HIGH to Power-Down 55 70 ns tpBeE Byte Enable to Data Valid 55 70 ns tLZBE Byte Enable to LOW ZI] 5 5 ns tuzBe Byte Disable to HIGH z/7] 20 25 ns WRITE CYCLE! two Write Cycle Time 55 70 ns tsce CE LOW to Write End 45 60 ns taw Address Set-Up to Write End 45 60 ns tHa Address Hold from Write End ns tsa Address Set-Up to Write Start ns tpwe WE Pulse Width 40 50 ns tsp Data Set-Up to Write End 25 30 ns tub Data Hold from Write End 0) ns tLzwe WE HIGH to Low Z!J 5 ns tuzwe WE LOW to High zZ/6.7] 25 25 ns taw Byte Enable to End of Write 45 60 ns Shaded areas contain advance information. Notes: 5. Test conditions assume signal transition time of 5ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified lo-/loy and 30pF load capacitance. 6. tHzoe: tyzce tHzwe; and tyzpe are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured +500 mV from steady-state voltage. 7. Atany given temperature and voltage condition, tyzceg is less than t_zce, tyzogis less than t_zoe; tHzwe is less than t_zwe, and tyzpe is less than t, pe, for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Refer to truth table for further conditions from BHE and BLE.eure PRELIMINARY CY62127V P PoP Se eS ae seer. TM Data Retention Characteristics (Over the Operating Range for L and LL version only) Parameter Description Conditions"! Min. | Typ | Max. | Unit Vor Voc for Data Retention 2.0 3.6 V locpR Data Retention Current L Voc=Vpr=3.0V, 0.5 50 HA 5 CE 2>Voc 0.39, Com! LL Vin > Veo - 0.3V or, 0.5 15 HA Indl LL Vin < 0.3V 0.5 30 HA tcpr! Chip Deselect to Data Retention Time 0 ns tr Operation Recovery Time tro ns Data Retention Waveform DATA RETENTION MODE Voc 3.0V Vor > 2V 3.0V tcopR >' << tp > 62127V-5 Switching Waveforms Read Cycle No.1!1911] < tac | ADDRESS * < taa | << tona > DATA OUT PREVIOUS DATA VALID KXXKX DATA VALID 62127V-6 Notes: 9. No input may exceed Voc + 0.3V. 10. Device is continuously selected. OE, CE, BHE, BLE = Vi. 11. WEis HIGH for read cycle.PRELIMINARY CY62127V Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)!'!.12.13] ADDRESS CE OE BHE, BLE "OBE tHZBE tLZBE tpoe tHZOE tLZ0E tHZcE HIGH HIGH IMPEDANCE IMPEDANCE DATA OUT DATA VALID tLZzceE = - Vec tpu - \ SUPPLY 50% 50% Nc CURRENT N ise Write Cycle No. 1 (CE Controlled)!'141 twe ADDRESS * / ex__ tsce } CE k He tsa > taw tua | GG... LLL taw TPWE > <_ tsp. rt td DATA VO DATA VALID 62127V-8 Notes: 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = V\, or BHE and BLE = Vj. 14. If CE, BHE, or go HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.PRELIMINARY CY62127V CYPRESS Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)!'3.141 two ADDRESS * xK tsce = SX LLL Va < taw <_ta-* < isn. < tpwe EAS BEALE NSS i LLL 7 \ OE LLL, | tHZ0E tsp DATA I/O DATAn VALID VA) HD 62127V-9 Write Cycle No.3 (WE Controlled, OE Low)!'3:14] ADDRESS CE WE BHE, BLE tsp DATAVO NOTE 15 DATA VALID 62127V-10 Note: 15. During this period the I/Os are in the output state and input signals should not be applied.nee PRELIMINARY CY62127V eae CE | OE | WE | BLE | BHE 1/0,-/0, 1/Oo-V/O46 Mode Power H Xx Xx Xx Xx High Z High Z Power Down Standby (Igp) L L H L L Data Out Data Out Read All bits Active (Icc) L L H L H Data Out High Z Read Lower bits only Active (Icc) L L H H L High Z Data Out Read Upper bits only Active (Icc) L xX L L L Data In Data In Write All bits Active (Icc) L X L L H Data In High Z Write Lower bits only Active (Icc) L X L H L High Z Data In Write Upper bits only Active (Icc) L H H L L High Z High Z Selected, Outputs Disabled Active (Icc) L Xx Xx H H High Z High Z Power Down Standby (lgp) Ordering Information Speed Package Operating (ns) Ordering Code Name Package Type Range 55 CY62127V-55ZC 244 44-Lead TSOP | Commercial CY62127VL-55ZC 244 44-Lead TSOP Il CY62127VLL-55ZC 244 44-Lead TSOP II CY62127VLL-55Z1 244 44-Lead TSOP II Industrial 55 CY62127V-70BAC BA48 48-ball mini Ball Grid Array (7.00 mm x 7.00 mm) Commercial CY62127VL-70BAC BA48 48-ball mini Ball Grid Array (7.00 mm x 7.00 mm) CY62127VLL-70BAC BA48 48-ball mini Ball Grid Array (7.00 mm x 7.00 mm) CY62127VLL-70BAI BA48 48-ball mini Ball Grid Array (7.00 mm x 7.00 mm) Industrial 70 CY62127V-70ZC 244 44-Lead TSOP Il Commercial CY62127VL-70ZC 244 44-Lead TSOP II CY62127VLL-70ZC 244 44-Lead TSOP II CY62127VLL-70Z1 244 44-Lead TSOP II Industrial 70 CY62127V-70BAC BA48 48-ball mini Ball Grid Array (7.00 mm x 7.00 mm) | Commercial CY62127VL-70BAG BA48 48-ball mini Ball Grid Array (7.00 mm x 7.00 mm) CY62127VLL-70BAC BA48 48-ball mini Ball Grid Array (7.00 mm x 7.00 mm) CY62127VLL-70BAI BA48 48-ball mini Ball Grid Array (7.00 mm x 7.00 mm) Industrial Shaded area contains advance information. Document #: 3800686nee PRELIMINARY CY62127V Package Diagrams 44-Pin TSOP Il 244 DIMENSION CM betel CINCH? MAX MIE LEAD COPLANAPITY 1.004 [HCHES., ; PIN 1 ID, BARARBRAARARRRAA ARR A AA 0.404 + 930 Od i ae (or) Hee EE HE Ee Se SEE EE SSS _ EJECTOR FIN TOP VIEW BOTTOM WIEW e202 (0404) 0.600 a Babe OBE) Dole) a P_ [D0S8 02560 COUs LES BASE PLANE _ g210 .o,00e2s OP -3S MPL Tat o7e0 (000d. | I 18,917 (07e93 Say. 225 Se Tees D7er: ER sears Tage Gea Ele ce eB Be Alo cokPRELIMINARY CY62127V Package Diagrams (continued) 48-Ball (7.00 mm x 7.00 mm) Mini Ball Grid Array BA48 $e 90.256)C AS 0.30+ 0.05(48X) 654321 / eoclood t+_ O OO 00 ] + 7.00+ 0.20 5.25 | O;O O1O O,O OO O}O O/O a7tmloogw>p> 7.Q0+ 0.20 | | | ORO e ROG ROMO mam C|SEATING PLANE 0.40+0.0- 0.21+0.05| be 1.100.10 Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.