MR0DL08B FEATURES Dual Supply 128K x 8 MRAM * 3.3 Volt VDD power supply with a range of 2.7V to 3.6V * I/O Voltage range supports wide +1.65 to +3.6 Volt interfaces * Fast 45 ns read/write cycle * SRAM compatible timing * Unlimited read & write endurance * Data always non-volatile for >20-years at temperature * All products meet MSL-3 moisture sensitivity level * RoHS-compliant small footprint BGA package BENEFITS * One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems for simpler, more efficient designs RoHS * Improves reliability by replacing battery-backed SRAM INTRODUCTION The MR0DL08B is a dual power supply 1,048,576-bit magnetoresistive random access memory (MRAM) device organized as 131,072 words of 8 bits. It supports I/O voltages from +1.65 to +3.6 volts. The MR0DL08B offers SRAM compatible 45ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20-years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. The MR0DL08B is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR0DL08B is available in small footprint 8 mm x 8 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. The MR0DL08B provides highly reliable data storage over a wide range of temperatures. The product is offered with commercial temperature (0 to +70 C). CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 2 2. ELECTRICAL SPECIFICATIONS................................................................. 4 3. TIMING SPECIFICATIONS.......................................................................... 8 4. ORDERING INFORMATION....................................................................... 13 5. MECHANICAL DRAWING.......................................................................... 14 6. REVISION HISTORY...................................................................................... 15 How to Reach Us.......................................................................................... 15 Copyright (c) Everspin Technologies 2018 1 MR0DL08B Rev. 1.3, 3/2018 MR0DL08B 1. DEVICE PIN ASSIGNMENT Figure 1.1 Block Diagram OUTPUT ENABLE BUFFER G A[16:0] 17 ADDRESS BUFFER OUTPUT ENABLE 7 10 ROW DECODER COLUMN DECODER CHIP ENABLE BUFFER E 8 8 OUTPUT BUFFER 8 128Kx 8 BIT MEMORY ARRAY WRITE ENABLE BUFFER W SENSE AMPS 8 FINAL WRITE DRIVERS 8 WRITE DRIVER 8 DQ[7:0] WRITE ENABLE Table 1.1 Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable DQ Data I/O VDD Power Supply VDDQ I/O Power Supply VSS Ground DC Do Not Connect NC No Connection, Ball D3, H1, H6, G2 Reserved for Future Expansion Copyright (c) Everspin Technologies 2018 2 MR0DL08B Rev. 1.2, 3/2018 MR0DL08B DEVICE PIN ASSIGNMENT Figure 1.2 Pin Diagrams for Available Packages (Top View) 1 2 3 4 5 6 DC G A A A VDD A NC DC A A E DC B DQ VDD A A NC DQ C VSS DQ NC A DQ VDDQ D VDDQ DQ DC DQ VSS E DQ3 NC NC DQ F NC NC A A W NC G NC A A A A NC H 48 Pin FBGA Table 1.2 Operating Modes E1 G1 W1 Mode VDD Current DQ[7:0]2 H X X Not selected ISB1, ISB2 Hi-Z L H H Output disabled IDDR Hi-Z L L H Byte Read IDDR DOut L X L Byte Write IDDW Din 1 H = high, L = low, X = don't care 2 Hi-Z = high impedance Copyright (c) Everspin Technologies 2018 3 MR0DL08B Rev. 1.3, 3/2018 MR0DL08B 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Table 2.1 Absolute Maximum Ratings1 Parameter Core Supply voltage2 I/O Power Supply voltage2 Symbol VDD Value Unit -0.5 to 4.0 V VDDQ -0.5 to 4.0 V VIN -0.5 to +4.0 or Voltage on any pin2 VDDQ + 0.5 V whichever is less Output current per pin IOUT 20 mA Package power dissipation 3 PD 0.600 W Temperature under bias TBIAS -10 to 85 C Storage Temperature Tstg -55 to 150 C Lead temperature during solder (3 minute max) TLead 260 C Maximum magnetic field during write Hmax_write 2000 A/m Maximum magnetic field during read or standby Hmax_read 8000 A/m 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2 All voltages are referenced to VSS. 3 Power dissipation capability depends on package characteristics and use environment. Copyright (c) Everspin Technologies 2018 4 MR0DL08B Rev. 1.2, 3/2018 MR0DL08B Electrical Specifications Table 2.2 Operating Conditions Parameter Core Power supply voltage Symbol VDD Min Typical Max 2.7 1 3.3 3.6 Unit V I/O Power supply voltage VDDQ 1.65 1 - 3.6 V Write inhibit voltage VDD VWIDD 2.3 2.5 2.7 1 V Write inhibit voltage VDDQ VWIDDQ 1.2 1.4 1.65 1 V Input high voltage (VDDQ=1.65-2.2V) VIH 1.4 - VDDQ + 0.2 2 V Input high voltage (VDDQ=2.2-2.7V) VIH 1.8 - VDDQ + 0.2 2 V Input high voltage (VDDQ=2.7-3.6V) VIH 2.2 - VDDQ + 0.2 2 V Input low voltage (VDDQ=1.65-2.2V) VIL -0.2 3 - 0.4 V Input low voltage (VDDQ=2.2-2.7V) VIL -0.2 3 - 0.6 V Input low voltage (VDDQ=2.7-3.6V) VIL -0.2 3 - 0.8 V Access Time TA 0 70 C Notes: 1. VDDQVDD. Write inhibit occurs when either VDD or VDDQ drops below its write inhibit voltage. There is a 2 ms startup time once VDD exceeds VDD(min). See Power Up and Power Down Sequencing. 2. VIH(max) = VDDQ + 0.2 V DC ; VIH(max) = VDDQ + 0.5 V AC (pulse width 20 ns) for I 20.0 mA. 3. VIL(min) = -0.2 V DC ; VIL(min) = -2.0 V AC (pulse width 20 ns) for I 20.0 mA. Copyright (c) Everspin Technologies 2018 5 MR0DL08B Rev. 1.3, 3/2018 MR0DL08B Electrical Specifications Power Up and Power Down Sequencing Initial Power Up The MRAM is protected from write operations whenever VDD is less than VWIDD. Upon power up VDD must go above 3.0V, and a 2 ms startup time must be observed before read or write operations can start. This time allows memory power supplies to stabilize. Power Loss or Brownout During power loss or brownout where VDD goes below VWIDD writes are inhibited. To return to normal operation and exit Write Inhibit, VDD must go above 3.0V, and a 2 ms startup time must be observed. Once powered up, VDD minimum can go as low as 2.7V. Chip Enable and Write Enable The E and W control signals should track VDD on power up to VDD - 0.2 V or VIH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. Figure 2.1 Power Up and Power Down Sequencing VWIDD VWIDDQ VDD / VDDQ STARTUP 2 ms READ/WRITE INHIBITED BROWNOUT or POWER LOSS NORMAL OPERATION READ/WRITE INHIBITED 2 ms RECOVER NORMAL OPERATION VIH VIH E W Copyright (c) Everspin Technologies 2018 6 MR0DL08B Rev. 1.2, 3/2018 MRD08B Electrical Specifications Table 2.3 DC Characteristics Parameter Symbol Ilkg(I) Input leakage current Min Typical Max Unit - - 1 A Output leakage current Ilkg(O) - - 1 A Output low voltage (VDDQ=1.65-2.2V@ 0.1mA) VOL - - 0.2 V Output low voltage (VDDQ=2.2-2.7V@ 0.1mA) VOL - - 0.4 V Output low voltage (VDDQ=2.7-3.6V@ 2.1 mA) VOL - - 0.4 V Output high voltage (VDDQ=1.65-2.2V@ - 0.1 mA) VOH 1.4 - - V Output high voltage (VDDQ=2.2-2.7V@ -0.1 mA) VOH 2 - - V Output high voltage (VDDQ=2.7-3.6V@ -1.0 mA) VOH 2.4 - - V Table 2.4 Power Supply Characteristics Parameter AC active supply current - read modes1 (IOUT= 0 mA, VDD= max) AC active supply current - write modes1 (VDD= max) Symbol Typical Max Unit IDDR 25 30 mA IDDW 55 65 mA IDDQ 0.50 2 mA ISB1 6 8 mA ISB2 5 7 mA AC active operating current (VDDQ = VIH= 3.6V, VIL= 0V) input transitions <2ns, no output load AC standby current (VDD= max, E = VIH) no other restrictions on other inputs CMOS standby current (E VDD - 0.2 V and VIn VSS + 0.2 V or VDDQ - 0.2 V) (VDD = max, f = 0 MHz) 1 All active current measurements are measured with one address transition per cycle and at minimum cycle time. Copyright (c) Everspin Technologies 2018 7 MR0DL08B Rev. 1.3, 3/2018 MR0DL08B 3. TIMING SPECIFICATIONS Table 3.1 Capacitance1 Parameter 1 Symbol Typical Max Unit Address input capacitance CIn - 6 pF Control input capacitance CIn - 6 pF Input/Output capacitance CI/O - 8 pF f = 1.0 MHz, VDDQ=VDDQ(typ), TA = 25 C, periodically sampled rather than 100% tested. Table 3.2 AC Measurement Conditions Parameter VDDQ=1.8 VDDQ=2.5 VDDQ=3.3 Unit Logic input timing measurement reference level 0.8 0.8 0.8 V Logic output timing measurement reference level 0.8 0.8 0.8 V 0 or 1.8 0 or 2.5 0 or 3.3 V 0.8 1.2 1.75 V Output load resistor (R1) for all other timing 13,500 16,600 1,103 Output load resistor (R2) for all other timing 10,800 15,400 1,554 Logic input pulse levels Output load voltage (VL) for low & high impedance parameters (Figure 3.1) Figure 3.1 Output Load Test Low and High ZD= 50 Output RL = 50 VL Figure 3.2 Output Load Test All Others VDDQ R1 Output 30 pF R2 Copyright (c) Everspin Technologies 2018 8 MR0DL08B Rev. 1.2, 3/2018 MR0DL08B Timing Specifications Read Mode Table 3.3 Read Cycle Timing1 Parameter Symbol Min Max Unit Read cycle time tAVAV 45 - ns Address access time tAVQV - 45 ns Enable access time2 tELQV - 45 ns Output enable access time tGLQV - 20 ns Output hold from address change tAXQX 3 - ns Enable low to output active tELQX 3 - ns Output enable low to output active3 tGLQX 0 - ns Enable high to output Hi-Z tEHQZ 0 15 ns Output enable high to output Hi-Z3 tGHQZ 0 15 ns 3 3 1 2 3 W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. Addresses valid before or at the same time E goes low. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. Figure 3.3A Read Cycle 1 t AVAV A (ADDRESS) t AXQX Q (DATA OUT) Previous Data Valid Data Valid t AVQV Note: Device is continuously selected NOTE: Device is continuously selected (E (EV VILIL, ,GV G IL). VIL) Figure 3.3B Read Cycle 2 t AVAV A (ADDRESS) t AVQV E (CHIP ENABLE) t ELQV t EHQZ t ELQX G (OUTPUT ENABLE) Q (DATA OUT) Copyright (c) Everspin Technologies 2018 t GHQZ t GLQV t GLQX Data Valid 9 MR0DL08B Rev. 1.3, 3/2018 MR0DL08B Timing Specifications Table 3.4 Write Cycle Timing 1 (W Controlled)1 Parameter Symbol Min Max Unit Write cycle time2 tAVAV 45 - ns Address set-up time tAVWL 0 - ns Address valid to end of write (G high) tAVWH 25 - ns Address valid to end of write (G low) tAVWH 25 - ns 20 - ns 20 - ns 15 - ns tWLWH Write pulse width (G high) tWLEH tWLWH Write pulse width (G low) Data valid to end of write tWLEH tDVWH Data hold time tWHDX 0 - ns tWLQZ 0 15 ns tWHQX 3 - ns tWHAX 12 - ns Write low to data Hi-Z3 Write high to output active 3 Write recovery time 1 2 3 All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given voltage or temperature, tWLQZ(max) < tWHQX(min) Figure 3.4 Write Cycle Timing 1 (W Controlled) t AVAV A (ADDRESS) t WHAX t AVWH E (CHIP ENABLE) t WLEH t WLWH W (WRITE ENABLE) t AVWL t DVWH D (DATA IN) t WHDX Data Valid t WLQZ Q (DATA OUT) Hi-Z Hi-Z t WHQX Copyright (c) Everspin Technologies 2018 10 MR0DL08B Rev. 1.2, 3/2018 MR0DL08B Timing Specifications Table 3.5 Write Cycle Timing 2 (E Controlled)1 Parameter Symbol Min Max Unit Write cycle time2 tAVAV 45 - ns Address set-up time tAVEL 0 - ns Address valid to end of write (G high) tAVEH 25 - ns Address valid to end of write (G low) tAVEH 25 - ns 20 - ns 20 - ns 15 - ns tELEH Enable to end of write (G high) tELWH tELEH Enable to end of write (G low)3 1 2 3 Data valid to end of write tELWH tDVEH Data hold time tEHDX 0 - ns Write recovery time tEHAX 12 - ns All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. Figure 3.5 Write Cycle Timing 2 (E Controlled) t AVAV A (ADDRESS) t EHAX t AVEH t ELEH E (CHIP ENABLE) t AVEL t ELWH W (WRITE ENABLE) t DVEH D (DATA IN) Data Valid Hi-Z Q (DATA OUT) Copyright (c) Everspin Technologies 2018 t EHDX 11 MR0DL08B Rev. 1.3, 3/2018 MR0DL08B Timing Specifications Table 3.6 Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled)1 Parameter Symbol Min Max Unit Write cycle time2 tAVAV 45 - ns Address set-up time tAVWL 0 - ns Address valid to end of write (G high) tAVWH 25 - ns Address valid to end of write (G low) tAVWH 25 - ns 20 - ns 15 - ns tWLWH Write pulse width 1 2 3 Data valid to end of write tWLEH tDVWH Data hold time tWHDX 0 - ns Enable recovery time tEHAX -2 - ns Write recovery time3 tWHAX 6 - ns Write to enable recovery time3 tWHEL 12 - ns All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. Table 3.6 Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled) t AVAV A (ADDRESS) t WHAX t AVWH E (CHIP ENABLE) t EHAX t WLEH W (WRITE ENABLE) t WHEL t WLWH t AVWL t DVWH t WHDX D (DATA IN) Copyright (c) Everspin Technologies 2018 12 MR0DL08B Rev. 1.2, 3/2018 MR0DL08B 4. ORDERING INFORMATION Figure 4.1 Part Numbering System MR 0 DL 08 B MA 45 R Carrier (Blank= Tray,R=Tape & Reel) Speed (45 = 45 ns) Package (MA = FBGA) Temperature Range (Blank= 0 to +70 C) Revision (B = Revision) Data Width (08 = 8-Bit) Type (DL= Dual Supply Low Voltage) Density (0 = 1Mb) Part Type (MR = Magnetoresistive RAM) Table 4.1 Available Parts Part Number Description Temperature MR0DL08BMA45 Dual Supply 128x8 MRAM 48-BGA Dual Supply 128x8 MRAM 48-BGA Tape & Reel Commercial MR0DL08BMA45R Copyright (c) Everspin Technologies 2018 13 Commercial MR0DL08B Rev. 1.3, 3/2018 MR0DL08B Mechanical Drawings Figure 5.1 FBGA TOP VIEW 0.41 0.31 0.32 0.22 SIDE VIEW BOTTOM VIEW Print Version Not To Scale 1. Dimensions in Millimeters. 2. Dimensions and tolerances per ASME Y14.5M - 1994. 3. Maximum solder ball diameter measured parallel to DATUM A 4. DATUM A, the seating plane is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. Copyright (c) Everspin Technologies 2018 14 MR0DL08B Rev. 1.2, 3/2018 MR0DL08B 6. REVISION HISTORY Revision Date Description of Change 1 Nov 19, 2013 Initial Data Sheet Release 1.1 May 19, 2015 Revised contact information. 1.2 June 11, 2015 Corrected Japan Sales Office telephone number. 1.3 March 22, 2018 Updated Contact Us table Copyright (c) Everspin Technologies 2018 15 MR0DL08B Rev. 1.3, 3/2018 HOW TO CONTACT US Home Page: Everspin Technologies, Inc. www.everspin.com Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any World Wide Information Request integrated circuit or circuits based on the information in this document. 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