4 MHz, 7 nV/√Hz, Low Offset and
Drift, High Precision Amplifiers
Data Sheet
ADA4077-1/ADA4077-2/ADA4077-4
FEATURES
Offset voltage and offset voltage drift
B grade: 25 µV and 0.25 µV/°C at VSY = ±5 V
A grade maximum offset at 25°C and maximum drift from
−40°C to +125°C
SOIC: 50 µV and 0.55 µV/°C single/dual and 0.75 µV/°C quad
MSOP: 90 µV and 1.2 µV/°C dual and 120 µV and 1.2 µV/°C
single
TSSOP: 120 µV and 1.2 µV/°C quad
MSL1 rated
Low input bias current: 1 nA maximum at TA = 25°C
Low voltage noise density: 6.9 nV/√Hz typical at f = 1000 Hz
CMRR, PSRR, and AV > 120 dB minimum
Low supply current: 400 µA per amplifier typical
Wide gain bandwidth product: 3.9 MHz at ±5 V
Dual-supply operation: ±2.5 V to ±15 V
Unity gain stable
No phase reversal
APPLICATIONS
Process control front-end amplifiers
Wireless base station control circuits
Optical network control circuits
Instrumentation
Sensors and controls: thermocouples, RTDs, strain bridges,
and shunt current measurements
Precision filters
GENERAL DESCRIPTION
The single ADA4077-1, dual ADA4077-2, and quad ADA4077-4
amplifiers feature extremely low offset voltage and drift, and low
input bias current, noise, and power consumption. Outputs are
stable with capacitive loads of more than 1000 pF with no
external compensation.
Applications for this amplifier include sensor signal conditioning
(such as thermocouples, RTDs, strain gauges), process control
front-end amplifiers, and precision diode power measurement
in optical and wireless transmission systems. The ADA4077-1,
ADA4077-2, and ADA4077-4 are useful in line powered and
portable instrumentation, precision filters, and voltage or
current measurement and level setting.
Unlike amplifiers by some competitors, the ADA4077-1/
ADA4077-2/ADA4077-4 have an MSL1 rating that is compliant
with the most stringent of assembly processes, and they are
specified over the extended industrial temperature range from
−40°C to +125°C for the most demanding operating environments.
PIN CONNECTION DIAGRAMS
NC
1
–IN
2
+IN
3
V–
4
NC
8
V+
7
OUT
6
NC
5
NC = NO CONNECT. NOT INT E RNALLY CO NNE CTED.
ADA4077-1
TOP VIEW
(No t t o Scal e)
10238-101
Figure 1. ADA4077-1, 8-Lead SOIC (and 8-Lead MSOP)
OUT A 1
–IN A 2
+IN A 3
V– 4
V+
8
OUT B
7
–IN B
6
+IN B
5
ADA4077-2
TOP VIEW
(No t t o Scal e)
10238-001
Figure 2. ADA4077-2, 8-Lead MSOP (and 8-Lead SOIC)
ADA4077-4
1
2
3
4
5
6
7
–IN A
+IN A
V+
OUT B
–IN B
+IN B
OUT A 14
13
12
11
10
9
8
–IN D
+IN D
V–
OUT C
–IN C
+IN C
OUT D
TOP VIEW
(No t t o Scal e)
10238-202
Figure 3. ADA4077-4, 14-Lead TSSOP (and 14-Lead SOIC)
The ADA4077-1 and ADA4077-2 are available in an 8-lead SOIC
package, including the B grade, and in an 8-lead MSOP (A grade
only). The ADA4077-4 is offered in a 14-lead TSSOP and a 14-lead
SOIC package.
V
OS
(µV)
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
NUMBER OF AMPLIFIERS
10
15
20
25
30
35
40
45
50
MORE
0
20
40
60
80
100
120
140
160
180
200
10238-103
V
SY
= ±5V
SOIC
Figure 4. Offset Voltage Distribution
Table 1. Evolution of Precision Devices by Generation
Op Amp First Second Third Fourth Fifth Sixth
Single OP07 OP77 OP177 OP1177 AD8677 ADA4077-1
Dual OP2177 ADA4077-2
Quad OP4177 ADA4077-4
Rev. C Document Feedback
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ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Connection Diagrams ............................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics, ±5 V .................................................. 3
Electrical Characteristics, ±15 V ................................................ 4
Absolute Maximum Ratings ....................................................... 6
Thermal Resistance ...................................................................... 6
ESD Caution...................................................................................6
Pin Configurations and Function Descriptions ............................7
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 20
Applications Information .............................................................. 21
Output Phase Reversal ............................................................... 21
Low Power Linearized RTD ...................................................... 21
Proper Board Layout .................................................................. 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 24
REVISION HISTORY
6/15—Rev. B to Rev. C
Change to Figure 63 ....................................................................... 18
1/14—Rev. A to Rev. B
Added ADA4077-1 ............................................................. Universal
Changes to Features Section............................................................ 1
Added Figure 1; Renumbered Sequentially .................................. 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 4
Added Figure 5, Figure 6, and Table 6; Renumbered
Sequentially ....................................................................................... 7
Changes to Figure 17, Figure 20, and Figure 21 ......................... 11
Changes to Figure 65 ...................................................................... 19
Added Figure 67 and Figure 68..................................................... 19
Changes to Output Phase Reversal Section and Figure 70 ....... 21
Changes to Ordering Guide .......................................................... 24
10/13—Rev. 0 to Rev. A
Added ADA4077-4 ............................................................. Universal
Changes to Features, General Description, and Figure 1 ............. 1
Deleted Figure 2; Renumbered Sequentially ................................. 1
Added Figure 2 ................................................................................... 1
Changes to Table 2 ............................................................................. 3
Changes to Table 3 ............................................................................. 4
Changes to Table 4 ............................................................................. 6
Added Figure 6, Figure 7, and Table 7; Renumbered
Sequentially ........................................................................................ 8
Changes to Typical Performance Characteristics Section ........... 9
Changes to Figure 65 ...................................................................... 20
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 23
10/12—Revision 0: Initial Version
Rev. C | Page 2 of 24
Data Sheet ADA4077-1/ADA4077-2/ADA4077-4
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS, ±5 V
VSY = ±5.0 V, VCM = 0 V, T A = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage (B Grade, 8-Lead SOIC,
ADA4077-1/ADA4077-2)
VOS 10 25 µV
A
65
µV
Offset Voltage Drift (B Grade, 8-Lead SOIC,
ADA4077-1/ADA4077-2)
ΔVOS/ΔT −40°C < TA < +125°C 0.1 0.25 µV/°C
Offset Voltage (A Grade) VOS
8-Lead SOIC (ADA4077-1/ADA4077-2) and
14-Lead SOIC (ADA4077-4)
15 50 µV
−40°C < TA < +125°C 105 µV
8-Lead MSOP (ADA4077-1) 120 µV
8-Lead MSOP (ADA4077-2) 50 90 µV
−40°C < TA < +125°C 220 µV
14-Lead TSSOP (ADA4077-4) 15 120 µV
A
220
µV
Offset Voltage Drift (A Grade) ΔVOS/ΔT −40°C < TA < +125°C
8-Lead SOIC (ADA4077-1/ADA4077-2) 0.25 0.55 µV/°C
14-Lead SOIC (ADA4077-4) 0.4 0.75 µV/°C
8-Lead MSOP (ADA4077-1/ADA4077-2) and
14-Lead TSSOP (ADA4077-4)
0.5 1.2 µV/°C
Input Bias Current IB −1 −0.4 +1 nA
−40°C < TA < +125°C −1.5 +1.5 nA
Input Offset Current IOS −0.5 +0.1 +0.5 nA
−40°C < TA < +125°C −1.0 +1.0 nA
Input Voltage Range −3.8 +3 V
Common-Mode Rejection Ratio
CMRR
CM
122
140
dB
−40°C < TA < +125°C 120 dB
Large Signal Voltage Gain AV RL = 2 kΩ, VO = −3.0 V to +3.0 V 121 130 dB
−40°C < TA < +125°C 120 dB
Input Capacitance CINCM Common mode 5 pF
Input Resistance RIN Common mode 70 GΩ
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 1 mA 4.1 V
−40°C < TA < +125°C 4 V
Output Voltage Low VOL IL = 1 mA −3.5 V
−40°C < TA < +125°C −3.2 V
Output Current IOUT VDROPOUT < 1.6 V ±10 mA
Short-Circuit Current ISC TA = 25°C 22 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = +1 0.05 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±2.5 V to ±18 V 123 128 dB
−40°C < TA < +125°C 120 dB
Supply Current per Amplifier
I
SY
O
400
450
µA
−40°C < TA < +125°C 650 µA
Rev. C | Page 3 of 24
ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 1.2 V/µs
Settling Time to 0.1% tS VIN = 1 V step, RL = 2 kΩ, AV = −1 3 µs
Gain Bandwidth Product GBP VIN = 10 mV p-p, RL = 2 kΩ, AV = +100 3.9 MHz
Unity-Gain Crossover
UGC
IN
L
V
3.9
MHz
−3 dB Closed-Loop Bandwidth −3 dB AV = +1, VIN = 10 mV p-p, RL = 2 kΩ 5.9 MHz
Phase Margin ΦM VIN = 10 mV p-p, RL = 2 kΩ, AV = +1 55 Degrees
Total Harmonic Distortion Plus Noise THD + N VIN = 1 V rms, AV = +1, RL = 2 kΩ,
f = 1 kHz
0.004 %
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.25 µV p-p
Voltage Noise Density en f = 1 Hz 13 nV/√Hz
f = 100 Hz 7 nV/√Hz
f = 1000 Hz 6.9 nV/√Hz
Current Noise Density in f = 1 kHz 0.2 pA/√Hz
MULTIPLE AMPLIFIERS CHANNEL SEPARATION CS f = 1 kHz, RL = 10 kΩ −125 dB
ELECTRICAL CHARACTERISTICS, ±15 V
VSY = ±15 V, VCM = 0 V, T A = 25°C, unless otherwise noted.
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage (B Grade, 8-Lead SOIC,
ADA4077-1/ADA4077-2)
V
OS
10
35
µV
−40°C < TA < +125°C 65 µV
Offset Voltage Drift (B Grade, 8-Lead SOIC,
ADA4077-1/ADA4077-2)
ΔVOS/ΔT −40°C < TA < +125°C 0.1 0.25 µV/°C
Offset Voltage (A Grade) VOS
8-Lead SOIC (ADA4077-1/ADA4077-2) and
14-Lead SOIC (ADA4077-4)
15
50
µV
−40°C < TA < +125°C 105 µV
8-Lead MSOP (ADA4077-1) 120 µV
8-Lead MSOP (ADA4077-2) 50 90 µV
−40°C < T
A
< +125°C
220
µV
14-Lead TSSOP (ADA4077-4) 15 120 µV
−40°C < TA < +125°C 220 µV
Offset Voltage Drift (A Grade) ΔVOS/ΔT −40°C < TA < +125°C
8-Lead SOIC (ADA4077-1/ADA4077-2) 0.2 0.55 µV/°C
14-Lead SOIC (ADA4077-4) 0.4 0.75 µV/°C
8-Lead MSOP (ADA4077-1/ADA4077-2) and
14-Lead TSSOP (ADA4077-4)
0.5
1.2
µV/°C
Input Bias Current IB −1 −0.4 +1 nA
−40°C < TA < +125°C −1.5 +1.5 nA
Input Offset Current IOS −0.5 +0.1 +0.5 nA
−40°C < T
A
< +125°C
−1.0
+1.0
nA
Input Voltage Range −13.8 +13 V
Common-Mode Rejection Ratio CMRR VCM = −13.8 V to +13 V 132 150 dB
−40°C < TA < +125°C 130 dB
Rev. C | Page 4 of 24
Data Sheet ADA4077-1/ADA4077-2/ADA4077-4
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Large Signal Voltage Gain
8-Lead SOIC and 8-Lead MSOP
(ADA4077-1/ADA4077-2)
AV RL = 2 kΩ, VO = −13.0 V to +13.0 V 125 130 dB
−40°C < TA < +125°C 120 dB
14-Lead TSSOP and 14-Lead SOIC
(ADA4077-4)
AV RL = 2 kΩ, VO = −13.0 V to +13.0 V 122 130 dB
−40°C < TA < +125°C 120 dB
Input Capacitance CINDM Differential mode 3 pF
CINCM Common mode 5 pF
Input Resistance RIN Common mode 100 GΩ
OUTPUT CHARACTERISTICS
Output Voltage High VOH IL = 1 mA 14.1 V
−40°C < TA < +125°C 14 V
Output Voltage Low
V
OL
I
L
= 1 mA
−13.5
V
−40°C < TA < +125°C −13.2 V
Output Current IOUT VDROPOUT < 1.2 V ±10 mA
Short-Circuit Current ISC TA = 25°C 22 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = +1 0.05 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ±2.5 V to ±18 V 123 128 dB
−40°C < TA < +125°C 120 dB
Supply Current per Amplifier ISY VO = 0 V 400 500 µA
−40°C < TA < +125°C 650 µA
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 2 kΩ
1.2
V/µs
Settling Time to 0.01% ts VIN = 10 V p-p, RL = 2 kΩ, AV = −1 16 µs
Settling Time to 0.1% ts VIN = 10 V p-p, RL = 2 kΩ, AV = −1 10 µs
Gain Bandwidth Product GBP VIN = 10 mV p-p, RL = 2 kΩ, AV = +100 3.6 MHz
Unity-Gain Crossover UGC VIN = 10 mV p-p, RL = 2 kΩ, AV = +1 3.9 MHz
−3 dB Closed-Loop Bandwidth −3 dB AV = +1, VIN = 10 mV p-p, RL = 2 kΩ 5.5 MHz
Phase Margin ΦM VIN = 10 mV p-p, RL = 2 kΩ, AV = +1 58 Degrees
Total Harmonic Distortion Plus Noise THD + N VIN = 1 V rms, AV = +1, RL = 2 kΩ,
f = 1 kHz
0.004 %
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.25 µV p-p
Voltage Noise Density en f = 1 Hz 13 nV/√Hz
f = 100 Hz 7 nV/√Hz
f = 1000 Hz 6.9 nV/√Hz
Current Noise Density
i
n
f = 1 kHz
0.2
pA/√Hz
MULTIPLE AMPLIFIERS CHANNEL SEPARATION CS f = 1 kHz, RL = 10 kΩ −125 dB
Rev. C | Page 5 of 24
ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage
36 V
Input Voltage ±VSY
Input Current1 ±10 mA
Differential Input Voltage ±VSY
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range
−40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature, Soldering (10 sec) 300°C
ESD Human Body Model (HBM)2 6 kV
Field Induced Charge Device Model (FICDM)3 1.25 kV
1 The input pins have clamp diodes to the power supply pins and to each
other. Limit the input current to 10 mA or less whenever input signals
exceed the power supply rail by 0.3 V.
2 ESDA/JEDEC JS-001-2011 applicable standard.
3 JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type
θ
JA
θ
JC
Unit
8-Lead MSOP 190 44 °C/W
8-Lead SOIC
158
43
°C/W
14-Lead TSSOP 240 43 °C/W
14-Lead SOIC 115 36 °C/W
ESD CAUTION
Rev. C | Page 6 of 24
Data Sheet ADA4077-1/ADA4077-2/ADA4077-4
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC
–IN
+IN
V–
NC
V+
OUT
NC
NC = NO CONNECT. NOT INT E RNALLY CO NNE CTED.
ADA4077-1
TOP VIEW
(No t t o Scal e)
10238-205
1
2
3
4
8
7
6
5
Figure 5. ADA4077-1 Pin Configuration, 8-Lead MSOP (RM-8)
NC
1
–IN
2
+IN
3
V–
4
NC
8
V+
7
OUT
6
NC
5
NC = NO CONNECT. NOT INT E RNALLY CO NNE CTED.
ADA4077-1
TOP VIEW
(No t t o Scal e)
10238-105
Figure 6. ADA4077-1 Pin Configuration, 8-Lead SOIC (R-8)
Table 6. ADA4077-1 Pin Function Descriptions, 8-Lead MSOP and 8-Lead SOIC
Pin No. Mnemonic Description
1, 5, 8 NC No Connect. Not internally connected.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4
V−
Negative Supply Voltage.
6 OUT Output.
7 V+ Positive Supply Voltage.
Rev. C | Page 7 of 24
ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet
OUT A
1
–IN A
2
+IN A
3
V–
4
V+
8
OUT B
7
–IN B
6
+IN B
5
ADA4077-2
TOP VIEW
(No t t o Scal e)
10238-004
Figure 7. ADA4077-2 Pin Configuration, 8-Lead MSOP
OUT A 1
–IN A 2
+IN A 3
V– 4
V+
8
OUT B
7
–IN B
6
+IN B
5
ADA4077-2
TOP VIEW
(Not to S cale)
10238-005
Figure 8. ADA4077-2 Pin Configuration, 8-Lead SOIC
Table 7. ADA4077-2 Pin Function Descriptions, 8-Lead MSOP and 8-Lead SOIC
Pin No. Mnemonic Description
1 OUT A Output Channel A.
2 −IN A Inverting Input Channel A.
3 +IN A Noninverting Input Channel A.
4 V− Negative Supply Voltage.
5
+IN B
Noninverting Input Channel B.
6 −IN B Inverting Input Channel B.
7 OUT B Output Channel B.
8 V+ Positive Supply Voltage.
Rev. C | Page 8 of 24
Data Sheet ADA4077-1/ADA4077-2/ADA4077-4
ADA4077-4
1
2
3
4
5
6
7
–IN A
+IN A
V+
OUT B
–IN B
+IN B
OUT A
14
13
12
11
10
9
8
–IN D
+IN D
V–
OUT C
–IN C
+IN C
OUT D
TOP VIEW
(No t t o Scal e)
10238-206
Figure 9. ADA4077-4 Pin Configuration, 14-Lead TSSOP
OUT A 1
–IN A 2
+IN A 3
V+ 4
OUT D
14
–IN D
13
+IN D
12
V–
11
+IN B 5+I N C
10
–IN B 6–IN C
9
OUT B 7OUT C
8
ADA4077-4
TOP VIEW
(No t t o Scal e)
10238-207
Figure 10. ADA4077-4 Pin Configuration, 14-Lead SOIC
Table 8. ADA4077-4 Pin Function Descriptions, 14-Lead TSSOP and 14-Lead SOIC
Pin No.
Mnemonic
Description
1 OUT A Output Channel A.
2
−IN A
Negative Input Channel A.
3 +IN A Positive Input Channel A.
4 V+ Positive Supply Voltage.
5 +IN B Positive Input Channel B.
6 −IN B Negative Input Channel B.
7 OUT B Output Channel B.
8 OUT C Output Channel C.
9 −IN C Negative Input Channel C.
10 +IN C Positive Input Channel C.
11 V− Negative Supply Voltage.
12 +IN D Positive Input Channel D.
13
−IN D
Negative Input Channel D.
14 OUT D Output Channel D.
Rev. C | Page 9 of 24
ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
20
40
V
OS
(µV)
60
80
100
120
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
NUMBER OF AMPLIFIERS
10
15
20
25
30
35
40
45
50
MORE
10238-006
V
SY
= ±5V
MSOP
Figure 11. ADA4077-2 Offset Voltage (VOS) Distribution, VSY = ±5 V
V
OS
(µV)
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
NUMBER OF AMPLIFIERS
10
15
20
25
30
35
40
45
50
MORE
0
20
40
60
80
100
120
140
160
180
200
10238-144
V
SY
= ±5V
SOIC
Figure 12. Offset Voltage (VOS) Distribution, VSY = ±5 V
–10
–5
0
5
10
15
20
–50 –25 025 50 75 100 125
V
OS
(µV)
TEMPERATURE (°C)
10238-210
V
SY
= ±5V
Figure 13. Offset Voltage (VOS) vs. Temperature, VSY = ±5 V
0
20
40
60
80
100
120
140
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
30
35
40
45
50
MORE
V
OS
(µV)
NUMBER OF AMPLIFIERS
10238-003
V
SY
= ±15V
MSOP
Figure 14. ADA4077-2 Offset Voltage (VOS) Distribution, VSY = ±15 V
V
OS
(µV)
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
NUMBER OF AMPLIFIERS
10
15
20
25
30
35
40
45
50
MORE
0
20
40
60
80
100
120
140
160
180
200
10238-009
V
SY
= ±15V
SOIC
Figure 15. Offset Voltage (VOS) Distribution, VSY = ±15 V
–15
–10
–5
0
5
10
15
–50 –25 025 50 75 100 125
V
OS
(µV)
TEMPERATURE (°C)
10238-213
V
SY
= ±15V
Figure 16. Offset Voltage (VOS) vs. Temperature, VSY = ±15 V
Rev. C | Page 10 of 24
Data Sheet ADA4077-1/ADA4077-2/ADA4077-4
TCV
OS
(µV/°C)
NUMBER OF AMPLIFIERS
10238-130
0
5
10
15
20
25
30
35
40
45
50
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
V
SY
= ±15V, ±5V
TSSOP AND MSOP, A GRADE
Figure 17. TCVOS (TSSOP and MSOP, A Grade)
10
–10 035
V
OS
(µV)
V
SY
(V)
10238-134
–5
0
5
510 15 20 25 30
Figure 18. Offset Voltage (VOS) vs. Voltage Supplies (VSY)
100
80
60
40
20
0
–20
–40
–60
–80
–100
–20 –15 –10 –5 02015105
V
OS
(µV)
V
CM
(V)
10238-112
AVERAGE –3σ
AVERAGE
AVERAGE +3σ
V
SY
= ±15V
Figure 19. Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = ±15 V
0
10
20
30
40
50
60
70
TCV
OS
(µV/°C)
NUMBER O F AMPLIFIERS
10238-008
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
V
SY
= ±15V, ±5V
SOIC, A GRADE
Figure 20. TCVOS (SOIC, A Grade)
0
20
40
60
80
100
120
140
TCV
OS
(µV/°C)
NUMBER OF AMPLIFIERS
10238-308
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
V
SY
= ±15V, ±5V
SOIC, B GRADE
Figure 21. TCVOS (SOIC, B Grade)
0
0.2
0.4
0.6
02 4 6810 12 14 16 18 20 22 24 26 28 30 32 34 36 38
I
SY
(mA)
V
SY
(V)
+25°C
–40°C
+85°C
+125°C
10238-218
V
O
= 0V
Figure 22. Supply Current per Amplifier (ISY) vs. Power Supply Voltage (VSY)
Rev. C | Page 11 of 24
ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet
–6
–4
–2
0
2
4
6
–50 050 100–25 25
TEMPERATURE (°C)
OUTPUT VOLTAGE SW I NG (V)
75 125
V
OH
V
OL
10238-021
V
SY
= ±5V
Figure 23. Output Voltage Swing vs. Temperature, VSY = ±5 V
350
0
NUMBER OF AM P LIFI ERS
INPUT BI AS CURRE NT (n A)
10238-013
50
100
150
200
250
300
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
MORE
V
SY
= ±5V
Figure 24. Input Bias Current, VSY = ±5 V
–0.7
–0.6
–0.5
–0.4
–0.3
I
B
(n A)
–0.2
–0.1
0
–50 050 100–25 TEMPERATURE ( °C)
25 75 125
+I
B
–I
B
10238-014
V
SY
= ±5V
Figure 25. Input Bias Current (IB) vs. Temperature, VSY = ±5 V
–50 050 100
–25 25
TEMPERATURE (°C)
OUTPUT VOLTAGE SWING (V)
75 125
V
OH
V
OL
13.2
13.4
13.6
13.8
14.0
14.2
14.4
10238-140
V
SY
= ±15V
Figure 26. Output Voltage Swing vs. Temperature, VSY = ±15 V
400
0
NUMBER OF AM P LIFI ERS
INPUT BI AS CURRE NT (n A)
10238-016
50
100
150
200
250
300
350
–1
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
MORE
V
SY
= ±15V
Figure 27. Input Bias Current, VSY = ±15 V
–0.7
–0.6
–0.5
–0.4
–0.3
I
B
(n A)
–0.2
–0.1
0
–50 050 100–25 TEMPERATURE ( °C)
25 75 125
+I
B
–I
B
10238-017
V
SY
= ±15V
Figure 28. Input Bias Current (IB) vs. Temperature, VSY = ±15 V
Rev. C | Page 12 of 24
Data Sheet ADA4077-1/ADA4077-2/ADA4077-4
0.1
1
10
0.001 0.01 0.1 110 100
OUTPUT DROPOUT VOLTAGE (V
OL
– V–) (V)
SINK CURRE NT (mA)
+25°C
–40°C
+85°C
+125°C
10238-222
V
SY
= ±5V
Figure 29. Output Dropout Voltage vs. Sink Current, VSY = ±5 V
0.1
1
10
0.001 0.01 0.1 110 100
OUTPUT DROPOUT VOLTAGE (V
DD
– V+) (V)
SOURCE CURRE NT (mA)
+25°C
–40°C
+85°C
+125°C
10238-226
V
SY
= ±5V
Figure 30. Output Dropout Voltage vs. Source Current, VSY = ±5 V
–150
–100
–50
0
50
100
150
–150
–100
–50
0
50
100
150
10k 100k 1M 10M 100M
PHASE M ARGI N ( Degrees)
GAI N (dB)
FREQUENCY (Hz)
GAIN WITH CL= 0pF
GAIN WITH CL = 100pF
GAIN WITH CL = 200pF
PHASE WI TH CL= 0pF
PHASE WI TH CL = 100pF
PHASE WI TH CL = 200pF
10238-227
VSY = ±5V
AV = –1
RL = 2kΩ
Figure 31. Open-Loop Gain and Phase vs. Frequency, VSY = ±5 V
0.1
1
10
0.001 0.01 0.1 110 100
OUTPUT DROPOUT VOLTAGE (V
OL
– V–) (V)
SINK CURRE NT (mA)
+25°C
–40°C
+85°C
+125°C
10238-225
V
SY
= ±15V
Figure 32. Output Dropout Voltage vs. Sink Current, VSY = ±15 V
0.1
1
10
0.001 0.01 0.1 110 100
OUTPUT DROPOUT VOLTAGE (V
DD
– V+) (V)
SOURCE CURRE NT (mA)
+25°C
–40°C
+85°C
+125°C
10238-229
V
SY
= ±15V
Figure 33. Output Dropout Voltage vs. Source Current, VSY = ±15 V
–150
–100
–50
0
50
100
150
–150
–100
–50
0
50
100
150
10k 100k 1M 10M 100M
PHASE M ARGI N ( Degrees)
GAI N (dB)
FREQUENCY (Hz)
10238-230
V
SY
= ±15V
A
V
= –1
R
L
= 2kΩ
GAIN WITH C
L
= 0pF
GAIN WITH C
L
= 100pF
GAIN WITH C
L
= 200pF
PHASE WI TH C
L
= 0pF
PHASE WI TH C
L
= 100pF
PHASE WI TH C
L
= 200pF
Figure 34. Open-Loop Gain and Phase vs. Frequency, VSY = ±15 V
Rev. C | Page 13 of 24
ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet
124
125
126
127
128
129
130
131
132
133
–50 050 100–25 25
PSRR ( dB)
TEMPERATURE (°C) 75 125
10238-035
V
SY
= ±5V TO ±15V
Figure 35. PSRR vs. Temperature, VSY = ±5 V to ±15 V
–20
0
20
40
60
80
100
120
100 1k 10k 100k 1M 10M
PSRR ( dB)
FREQUENCY (Hz)
PSRR–
PSRR+
V
SY
= ±5V
10238-034
Figure 36. PSRR vs. Frequency, VSY = ±5 V
141
142
143
144
145
146
147
148
149
150
151
152
–50 050
–25 25
TEMPERATURE (°C)
CMRR (dB)
75 100 125
10238-030
V
SY
= ±5V
Figure 37. CMRR vs. Temperature, VSY = ±5 V
CMRR (dB)
0
20
40
60
80
100
120
140
100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
V
SY
= ±15V
V
SY
= ±5V
10238-029
Figure 38. CMRR vs. Frequency, VSY = ±5 V and VSY = ±15 V
–20
0
20
40
60
80
100
120
100 1k 10k 100k 1M 10M
PSRR ( dB)
FREQUENCY (Hz)
PSRR–
PSRR+
V
SY
= ±15V
10238-037
Figure 39. PSRR vs. Frequency, VSY = ±15 V
153
154
155
156
157
158
159
–50 050–25 25
TEMPERATURE (°C)
CMRR (dB)
75 100 125
10238-033
V
SY
= ±15V
Figure 40. CMRR vs. Temperature, VSY = ±15 V
Rev. C | Page 14 of 24
Data Sheet ADA4077-1/ADA4077-2/ADA4077-4
Rev. C | Page 15 of 24
50
–50
1k 10k 100k 100M10M1M
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
–40
–30
–20
–10
0
10
20
30
40
G = 1
G = 10
G = 100
10238-028
VSY = ±5V
Figure 41. Closed-Loop Gain vs. Frequency, VSY = ±5 V
0.001
0.01
0.1
1
10
100
1k
100 1k 10k 100k 1M 10M
Z
OUT
(Ω)
FREQUENCY (Hz)
A
V
= +100
V
SY
= ±5V
A
V
= +10
A
V
= +1
10238-036
Figure 42. Output Impedance (ZOUT) vs. Frequency, VSY = ±5 V
TIME (100µs/DIV)
0V
VOLTAGE (0.2V/DIV)
V
SY
= ±5V
V
IN
= 1V p-p
A
V
= +1
R
L
= 2kΩ
C
L
= 300pF
10238-040
Figure 43. Large Signal Transient Response, VSY = ±5 V
50
–50
1k 10k 100k 100M10M1M
CLOSED-LOOP GAIN (dB)
FREQUENCY (Hz)
–40
–30
–20
–10
0
10
20
30
40
G = 1
G = 10
G = 100
10238-031
V
SY
= ±15V
Figure 44. Closed-Loop Gain vs. Frequency, VSY = ±15 V
0.001
0.01
0.1
1
10
100
1k
100 1k 10k 100k 1M 10M
Z
OUT
(Ω)
FREQUENCY (Hz)
A
V
= +100
V
SY
= ±15V
A
V
= +10
A
V
= +1
10238-039
Figure 45. Output Impedance (ZOUT) vs. Frequency, VSY = ±15 V
TIME (100µs/DIV)
VOL
T
AGE (1V/DIV)
V
SY
= ±15V
V
IN
= 4V p-p
A
V
= +1
R
L
= 2kΩ
C
L
= 300pF
10238-043
0V
Figure 46. Large Signal Transient Response, VSY = ±15 V
ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
–0.2 –0.1 00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VOLTAGE (V)
TIME (ms)
10238-344
VSY = ±5V
VIN = 100mV p-p
AV = +1
LOAD = 2kΩ||1000pF
Figure 47. Small Signal Transient Response, VSY = ±5 V
TIME ( 10µ s/DI V )
0.5
0
–0.5
INPUT VOLTAGE (V)
–1
1
3
5
OUTPUT VOLTAGE (V)
V
SY
= ±5V
A
V
= –100
V
IN
= 200mV
R
L
= 10kΩ
INPUT
OUTPUT
10238-046
Figure 48. Positive Overload Recovery, VSY = ±5 V
TIME ( 10µ s/DI V )
0.5
0
–0.5
INP UT VOLTAGE (V)
–5
–3
–1
1
OUTPUT VOLTAGE (V)
V
SY
= ±5V
A
V
= –100
V
IN
= 200mV
R
L
= 10kΩ
INPUT
OUTPUT
10238-047
Figure 49. Negative Overload Recovery, VSY = ±5 V
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
–0.2 –0.1 00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
VOLTAGE (V)
TIME (ms)
10238-247
VSY = ±15V
VIN = 100mV p-p
AV = +1
LOAD = 2kΩ||1000pF
Figure 50. Small Signal Transient Response, VSY = ±15 V
–5
0
5
10
15
20
25
30
35
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
–10 010 20 30 40 50 60 70 9080
OUTPUT (V)
INPUT (V)
TIME (µs)
VSY = ±15V
VIN = 200mV p-p
AV = –100
LOAD = 10kΩ
10238-248
Figure 51. Positive Overload Recovery, VSY = ±15 V
TIME ( 10µ s/DI V )
0.5
0
–0.5
INPUT VOLTAGE (V)
–15
–10
–5
0
OUTPUT VOLTAGE (V)
V
SY
= ±15V
A
V
= –100
V
IN
= 200mV
R
L
= 10kΩ
INPUT
OUTPUT
10238-051
Figure 52. Negative Overload Recovery, VSY = ±15 V
Rev. C | Page 16 of 24
Data Sheet ADA4077-1/ADA4077-2/ADA4077-4
0
5
10
15
20
25
30
35
40
1p 10p 100p 1n 10n
OVERSHOOT (%)
LOAD CAPACITANCE ( F)
OS+
OS–
V
SY
= ±5V
R
L
= 2kΩ
10238-250
Figure 53. Small Signal Overshoot vs. Load Capacitance, VSY = ±5 V
–0.03
–0.02
–0.01
0
0.01
0.02
0.03
0.04
0.05
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
OUTPUT (V)
INPUT (V)
TIME (1µs/DIV)
VSY = ±5V
VIN = 1V p-p
RL = 2kΩ
10238-251
Figure 54. Positive 0.1% Settling Time, VSY = ±5 V
–0.03
–0.02
–0.01
0
0.01
0.02
0.03
0.04
0.05
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
OUTPUT (V)
INPUT (V)
10238-252
V
SY
= ±5V
V
IN
= 1V p-p
R
L
= 2kΩ
TIME (1µs/DIV)
Figure 55. Negative 0.1% Settling Time, VSY = ±5 V
0
5
10
15
20
25
30
35
40
1p 10p 100p 1n 10n
OVERSHOOT (%)
LOAD CAPACITANCE ( F)
OS+
OS–
V
SY
= ±15V
R
L
= 2kΩ
10238-253
Figure 56. Small Signal Overshoot vs. Load Capacitance, VSY = ±15 V
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
–30
–25
–20
–15
–10
–5
0
5
10
OUTPUT (V)
INPUT (V)
V
SY
= ±15V
V
IN
= 10V p - p
R
L
= 2kΩ
10238-254
TIME (1µs/DIV)
Figure 57. Positive 0.1% Settling Time, VSY = ±15 V
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
–30
–25
–20
–15
–10
–5
0
5
10
OUTPUT (V)
INPUT (V)
V
SY
= ±15V
V
IN
= 10V p - p
R
L
= 2kΩ
10238-255
TIME (1µs/DIV)
Figure 58. Negative 0.1% Settling Time, VSY = ±15 V
Rev. C | Page 17 of 24
ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet
1k
100
10
110 10M
1M
100k
10k
1k
100
VOLTAGE NOISE DENSITY (nV/√Hz)
FRE Q UE NCY ( Hz )
V
SY
= ±15V
V
SY
= ±5V
A
V
= +1
10238-053
Figure 59. Voltage Noise Density vs. Frequency, VSY = ±5 V and VSY = ±15 V
10238-155
0.0001
0.001
0.01
0.1
1
10 100 1k 10k 100k
THD + NOI S E ( %)
FREQUENCY (Hz)
BANDWIDTH = 80kHz
BANDWIDTH = 500kHz
V
SY
= ±5V
Figure 60. THD + N vs. Frequency, VSY = ±5 V
TIME (1s/DIV)
INPUT VOLTAG E ( 50nV/ DIV)
V
SY
= ±5V
10238-054
Figure 61. 0.1 Hz to 10 Hz Noise, VSY = ±5 V
100
003.0
VOLTAGE NOISE CORNER (nV/√Hz)
FRE Q UE NCY ( Hz )
10238-153
10
20
30
40
50
60
70
80
90
0.5 1.0 1.5 2.0 2.5
VSY = ±5V
VSY = ±15V
Figure 62. Voltage Noise Corner vs. Frequency, VSY = ±15 V and VSY = ±5 V
10238-158
10 100 1k 10k 100k
THD + NOI S E ( %)
FREQUENCY (Hz)
BANDWIDTH = 80kHz
BANDWIDTH = 500kHz
0.0001
0.001
0.01
0.1
1
10
100
V
SY
= ±15V
Figure 63. THD + N vs. Frequency, VSY = ±15 V
TIME (1s/DIV)
INPUT VOLTAG E ( 50nV/ DIV)
V
SY
= ±15V
10238-058
Figure 64. 0.1 Hz to 10 Hz Noise, VSY = ±15 V
Rev. C | Page 18 of 24
Data Sheet ADA4077-1/ADA4077-2/ADA4077-4
–1000
–900
–800
–700
–600
–500
–400
–300
–200
–100
0
100
200
–20
–
15 –10
–
50 5 10 15 20
I
B
(p A)
V
CM
(V)
MEAN
MEAN +3σ
MEAN –3σ
V
SY
= ±15V
–15V ≤ V
CM
≤ +15V
T
A
= 25° C
10238-219
Figure 65. Input Bias Current (IB) vs. Common-Mode Voltage (VCM)
0
–160
–140
–120
–100
–80
–60
–40
–20
100 100k10k1k 1M
CHANNEL S E P ARATI ON (d B)
FRE Q UE NCY ( Hz )
10238-244
V
SY
= ±15V
V
IN
= 10V p - p
A
V
= +1
R
L
= 10kΩ
2kΩ
–
+
VIN CH A
VCC
VEE
–
+
2kΩ
10kΩ
1kΩ
CH B,
CH C,
CH D
VCC
VEE
Figure 66. Channel Separation, VSY = ±15 V
0.1
1
10
100
110 100 1k 10k 100k
CURRENT NO ISE DE NS IT Y (pA/√Hz)
FREQUENCY (Hz)
V
SY
= ±15V
10238-267
Figure 67. Current Noise Density, VSY = ±15 V
0.1
1
10
100
110 100 1k 10k 100k
CURRENT NO ISE DE NS IT Y (pA/√Hz)
FREQUENCY (Hz)
V
SY
= ±5V
10238-268
Figure 68. Current Noise Density, VSY = ±5 V
Rev. C | Page 19 of 24
ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet
THEORY OF OPERATION
The ADA4077-1, ADA4077-2, and ADA4077-4 are the sixth
generation of the Analog Devices, Inc., industry-standard OP07
amplifier family. The ADA4077-1, ADA4077-2, and ADA4077-4
are high precision, low noise operational amplifiers with a
combination of extremely low offset voltage and very low input
bias currents. Unlike JFET amplifiers, the low bias and offset
currents are relatively insensitive to ambient temperatures, even
up to 125°C.
The Analog Devices proprietary process technology and linear
design expertise have produced a high voltage amplifier with
superior performance to the OP07, OP77, OP177, and OP1177
in tiny, 8-lead SOIC and 8-lead MSOP packages (ADA4077-1
and ADA4077-2) and 14-lead TSSOP and 14-lead SOIC packages
(ADA4077-4). Despite their small size, the ADA4077-1,
ADA4077-2, and ADA4077-4 offer numerous improvements,
including low wideband noise, wide bandwidth, lower offset and
offset drift, lower input bias current, and complete freedom from
phase inversion.
The ADA4077-1, ADA4077-2, and ADA4077-4 have a specified
operating temperature range of −40°C to +125°C with an MSL1
rating, which is as wide as any similar device in a plastic surface-
mount package. This MSL1 rating is increasingly important as
printed circuit board (PCB) and overall system sizes continue to
shrink, causing internal system temperatures to rise.
In the ADA4077-1, ADA4077-2, and the ADA4077-4, the power
consumption is reduced by a factor of four compared to the OP177,
and the bandwidth and slew rate are both increased by a factor
of six. The low power dissipation and very stable performance
vs. temperature also reduce warmup drift errors to insignificant
levels.
Inputs are protected internally from overvoltage conditions
referenced to either supply rail. Like any high performance
amplifier, maximum performance is achieved by following
appropriate circuit and PCB guidelines.
Rev. C | Page 20 of 24
Data Sheet ADA4077-1/ADA4077-2/ADA4077-4
APPLICATIONS INFORMATION
OUTPUT PHASE REVERSAL
Phase reversal is defined as a change of polarity in the amplifier
transfer function. Many operational amplifiers exhibit phase
reversal when the voltage applied to the input is greater than the
maximum common-mode voltage. In some instances, this phase
reversal can cause permanent damage to the amplifier. In feedback
loops, it can result in system lockups or equipment damage. The
ADA4077-1, ADA4077-2, and the ADA4077-4 are immune to
phase reversal problems even at input voltages beyond the
power supply settings.
2
CH1 5.00V CH2 5.00V M10.0ms A CH1 300mV
1
T 0.000%
10238-063
Figure 69. No Phase Reversal
LOW POWER LINEARIZED RTD
A common application for a single element varying bridge is a
resistance temperature detector (RTD) thermometer amplifier, as
shown in Figure 70. The excitation is delivered to the bridge by a
2.5 V reference applied at the top of the bridge.
RTDs can have a thermal resistance as high as 0.5°C to 0.8°C per
mW. To minimize errors due to resistor drift, keep the current
low through each leg of the bridge. In this circuit, the amplifier
supply current flows through the bridge. However, at a maximum
supply current of 500 µA for the ADA4077-2, the RTD dissipates
less than 0.1 mW of power, even at the highest resistance.
Therefore, errors due to power dissipation in the bridge
are kept under 0.1°C.
Calibration of the bridge is made at the minimum value of the
temperature to be measured by adjusting RP until the output is
zero.
To calibrate the output span, set the full-scale and linearity
potentiometers to midpoint, and apply a 500°C temperature to
the sensor, or substitute the equivalent 500°C RTD resistance.
Adjust the full-scale potentiometer for a 5 V output. Finally,
apply 250°C or the equivalent RTD resistance, and adjust the
linearity potentiometer for 2.5 V output. The circuit achieves
higher than ±0.5°C accuracy after adjustment.
200Ω
500Ω
FULL- S CALE ADJ
4.37kΩ
100Ω
100Ω 20Ω
R
P
,
ZERO ADJ
4.12kΩ
4.12kΩ
5kΩ
LINEARITY
ADJ
49.9kΩ
ADR4525
+15V
0.1µF
V+
100Ω
RTD
1/2
ADA4077-2
7
6
5
1/2
ADA4077-2
1
8
2
34
V–
V
OUT
0.1µF
10238-064
Figure 70. Low Power Linearized RTD Circuit
PROPER BOARD LAYOUT
The ADA4077-1, ADA4077-2, and ADA4077-4 are high precision
devices. To ensure optimum performance at the PCB level, care
must be taken in the design of the board layout.
To avoid leakage currents, maintain a clean and moisture free
board surface. Coating the surface creates a barrier to moisture
accumulation, and reduces parasitic resistance on the board.
Keeping supply traces short and properly bypassing the power
supplies minimizes the power supply disturbances caused by
the output current variation, such as when driving an ac signal
into a heavy load. Connect bypass capacitors as closely as possible
to the device supply pins. Stray capacitances are a concern at the
outputs and the inputs of the amplifier. It is recommended that
the signal traces be kept at least 5 mm from supply lines to
minimize coupling.
A variation in temperature across the PCB can cause a mismatch
in the Seebeck voltages at solder joints and other points where
dissimilar metals are in contact, resulting in thermal voltage errors.
To minimize these thermocouple effects, orient resistors so that
heat sources warm both ends equally. Ensure, where possible, that
input signal paths contain matching numbers and types of
components, to match the number and type of thermocouple
junctions. For example, dummy components such as zero value
resistors can be used to match real resistors in the opposite input
path. Place matching components in close proximity to each other,
and orient them in the same manner. Ensure that leads are of equal
length so that thermal conduction is in equilibrium. Keep heat
sources on the PCB as far away from amplifier input circuitry as
is practical.
The use of a ground plane is highly recommended. A ground
plane reduces EMI noise and maintains a constant temperature
across the circuit board.
Rev. C | Page 21 of 24
ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet
OUTLINE DIMENSIONS
COM PLI ANT TO JEDEC S TANDARDS M O-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 M AX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° M AX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 71. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 72. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. C | Page 22 of 24
Data Sheet ADA4077-1/ADA4077-2/ADA4077-4
COM PLI ANT TO JEDEC S TANDARDS M O-153-AB- 1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 73. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
CONTROLLING DIMENSIONSARE IN M IL LIM E TERS; INCH DI M E NS IONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REF ERE NCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDE C S TANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 ( 0.2441)
5.80 ( 0.2283)
4.00 ( 0.1575)
3.80 ( 0.1496)
8.75 ( 0.3445)
8.55 ( 0.3366)
1.27 ( 0.0500)
BSC
SEATING
PLANE
0.25 ( 0.0098)
0.10 ( 0.0039)
0.51 ( 0.0201)
0.31 ( 0.0122)
1.75 ( 0.0689)
1.35 ( 0.0531)
0.50 ( 0.0197)
0.25 ( 0.0098)
1.27 ( 0.0500)
0.40 ( 0.0157)
0.25 ( 0.0098)
0.17 ( 0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 74. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
Rev. C | Page 23 of 24
ADA4077-1/ADA4077-2/ADA4077-4 Data Sheet
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
Branding
ADA4077-1ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A35
ADA4077-1ARMZ-R7
−40°C to +125°C
8-Lead Mini Small Outline Package [MSOP]
RM-8
A35
ADA4077-1ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A35
ADA4077-1ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4077-1ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4077-1ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4077-1BRZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4077-1BRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4077-1BRZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4077-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2X
ADA4077-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2X
ADA4077-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A2X
ADA4077-2ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4077-2ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4077-2ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4077-2BRZ
−40°C to +125°C
8-Lead Standard Small Outline Package [SOIC_N]
R-8
ADA4077-2BRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4077-2BRZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4077-4ARUZ
−40°C to +125°C
14-Lead Thin Shrink Small Outline Package [TSSOP]
RU-14
ADA4077-4ARUZ-R7 −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADA4077-4ARUZ-RL −40°C to +125°C 14-Lead Thin Shrink Small Outline Package [TSSOP] RU-14
ADA4077-4ARZ −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADA4077-4ARZ-R7 −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADA4077-4ARZ-RL −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
1 Z = RoHS Compliant Part.
Rev. C | Page 24 of 24
©2012–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10238-0-6/15(C)
www.analog.com/ADA4077-1/ADA4077-2/ADA4077-4
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1ARMZ ADA4077-1ARZ ADA4077-1ARMZ-R7 ADA4077-1ARMZ-RL ADA4077-1BRZ-R7 ADA4077-1ARZ-R7
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4ARUZ-R7 ADA4077-4ARZ-R7