GA10JT12-263
Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 11
Normally – OFF Silicon Carbide
Junction Transistor
Features
Package
• 175 °C Maximum Operating Temperature
• Gate Oxide Free SiC Switch
• Optional Gate Return Pin
• Exceptional Safe Operating Area
• Excellent Gain Linearity
• Temperature Independent Switching Performance
• Low Output Capacitance
• Positive Temperature Coefficient of RDS,ON
• Suitable for Connecting an Anti-parallel Diode
7L D2PAK (TO-263-7L)
Advantages
Applications
• Compatible with Si MOSFET/IGBT Gate Drive ICs
• > 20 µs Short-Circuit Withstand Capability
• Lowest-in-class Conduction Losses
• High Circuit Efficiency
• Minimal Input Signal Distortion
• High Amplifier Bandwidth
• Down Hole Oil Drilling, Geothermal Instrumentation
• Hybrid Electric Vehicles (HEV)
• Solar Inverters
• Switched-Mode Power Supply (SMPS)
• Power Factor Correction (PFC)
• Induction Heating
• Uninterruptible Power Supply (UPS)
•
Motor Drives
Table of Conte nts
Section I: Absolute Ma ximum Rating s .......................................................................................................... 1
Section II: Static Electrical Characteristics ................................................................................................... 2
Section III: D ynamic Electrical Char acteristics ............................................................................................ 2
Section IV: Figures .......................................................................................................................................... 3
Section V: Driving the GA10JT12-263 ........................................................................................................... 7
Section VI: Packag e Di mensions ................................................................................................................. 11
Section VII: SPICE Model Parameters ......................................................................................................... 12
Section I: Absolute Maximum Ratings
Parameter
Symbol
Conditions
Value
Unit
Notes
Drain – Source Voltage
VDS
V
GS
= 0 V
1200
V
Continuous Drain Current
ID
TC = 25°C
25
A
Fig. 17
Continuous Drain Current
ID
T
C
= 150°C
10
A
Fig. 17
Continuous Gate Current I
G
1.3 A
Continuous Gate Return Current IGR 1.3 A
Turn-Off Safe Operating Area RBSOA TVJ = 175 oC,
Clamped Inductive Load
I
D,max
= 10
@ VDS ≤ VDSmax A Fig. 19
Short Circuit Safe Operating Area SCSOA
T
VJ
= 175 oC, I
G
= 1 A, V
DS
= 800 V,
Non Repetitive
>20 µs
Reverse Gate – Source Voltage
VSG
30
V
Reverse Drain – Source Voltage
VSD
25
V
Power Dissipation Ptot TC = 25 °C / 150 °C, tp > 100 ms 170 / 22 W Fig. 16
Storage Temperature Tstg -55 to 175 °C
1
G
TAB
Drain
2
GR
3
S
4
S
5
S
6
S
7
S
Drain
(TAB)
Source
(Pin 3, 4, 5, 6, 7)
Gate
(Pin 1)
Gate Return
(Pin 2)
VDS = 1200 V
RDS(ON) = 100 mΩ
ID (@ 25°C) = 25 A
ID (@ 150°C) = 10 A
hFE (@ 25°C) = 80
Please note: The Source and Gate Return
pins are not exchangeable. Their exchange
might lead to malfunction.
GA10JT12-263
Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 2 of 11
Section II: Static Electrical Characteristics
A: On State
B: Off State
C: Thermal
Section III: Dynamic Electrical Characteristics
A: Capacitance and Gate Charge
B: Switching1
1 – All times are relative to the Drain-Source Voltage VDS
Parameter Symbol Conditions
Value
Unit Notes
Min.
Typical
Max.
Drain – Source On Resistance RDS(ON) ID = 10 A, Tj = 2 5 ° C
ID = 10 A, Tj = 150 °C
ID = 10 A, Tj = 175 °C
100
155
175
mΩ Fig. 5
Gate – Source Saturation Voltage VGS,SAT ID = 10 A, ID/IG = 40, Tj = 25 °C
ID = 10 A, ID/IG = 30, Tj = 175 °C
3.50
3.27
V Fig. 7
DC Current Gain hFE VDS = 8 V, ID = 10 A, Tj = 25 °C
VDS = 8 V, ID = 10 A, Tj = 125 °C
VDS = 8 V, ID = 10 A, Tj = 175 °C
80
52
46
– Fig. 4
Drain Leakage Current IDSS VDS = 1200 V, VGS = 0 V, T j = 25 °C
VDS = 1200 V, VGS = 0 V, Tj = 150 °C
VDS = 1200 V, VGS = 0 V, Tj = 175 °C
0.1
0.1
0.2
μA Fig. 8
Gate Leakage Current
ISG
V
SG
= 20 V, T
j
= 25 °C
20
nA
Thermal resistance, junction - case RthJC
0.88
°C/W Fig. 20
Parameter Symbol Conditions
Value
Unit Notes
Min.
Typical
Max.
Input Capacitance
Ciss
VGS = 0 V, VDS = 800 V, f = 1 MHz
1275
pF
Fig. 9
Reverse Transfer/Output Capacitance
Crss/Coss
V
DS
= 800 V,
f
= 1 MHz
30
pF
Fig. 9
Output Capacitance Stored Energy
EOSS
VGS = 0 V, VDS = 800 V, f = 1 MHz
12
µJ
Fig. 10
Effective Output Capacitance,
time related
Coss,tr ID = constant, VGS = 0 V, V DS = 0…800 V 54 pF
Effective Output Capacitance,
energy related Coss,er VGS = 0 V, VDS = 0…800 V 38 pF
Gate-Source Charge
Q
GS
VGS = -5…3 V
11
nC
Gate-Drain Charge
QGD
V
GS
= 0 V, V
DS
= 0…800 V
56
nC
Gate Charge - Total
QG
67
nC
Internal Gate Resistance – ON
RG(INT-ON)
V
GS
> 2.5 V, V
DS
= 0 V, T
j
= 175 ºC
0.19
Ω
Turn On Delay Time
td(on)
Tj = 25 º C, VDS = 800 V,
ID = 10 A, Resistive Load
Refer to Section V for additional
driving information.
10
ns
Fall Time, V
DS
t
f
10
ns
Fig. 11, 13
Turn Off Delay Time
t
d(off)
22
ns
Rise Time, VDS
tr
10
ns
Fig. 12, 14
Turn On Delay Time
td(on)
Tj = 175 ºC, VDS = 800 V,
ID = 10 A, Resistive Load
10
ns
Fall Time, VDS
tf
10
ns
Fig. 11
Turn Off Delay Time
td(off)
35
ns
Rise Time, VDS tr 10 ns Fig. 12
Turn-On Energy Per Pulse
E
on
Tj = 25 º C, VDS = 800 V,
ID = 10 A, Inductive Load
Refer to Section V.
140
µJ
Fig. 11, 13
Turn-Off Energy Per Pulse
Eoff
10
µJ
Fig. 12, 14
Total Switching Energy
Etot
150
µJ
Turn-On Energy Per Pulse
Eon
Tj = 175 ºC, VDS = 800 V,
ID = 10 A, Inductive Load
140
µJ
Fig. 11
Turn-Off Energy Per Pulse
Eoff
100
µJ
Fig. 12
Total Switching Energy
Etot
150
µJ
GA10JT12-263
Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 3 of 11
Section IV: Figures
A: Static Characteristics
Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 150 °C
Figure 3: Typical Output Characteristics at 175 °C Figure 4: DC Current Gain vs. Drain Current
Figure 5: On-Resistance vs. Gate Current Figure 6: On-Resistance vs. Temper a ture
GA10JT12-263
Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 4 of 11
Figure 7: Typical Gate – Source Saturation Voltage Figure 8: Typical Blocking Characteristics
B: Dynamic Cha racteristi cs
Figure 9: Input, Output, and Reverse Transfer Capacitance Figure 10: Energy Stored in Output Capacitance
Figure 11: Typical Switching Times and T ur n On Energy
Losses vs. Temperature
Figure 12: Typical Switching Times and Turn O ff Energy
Losses vs. Temperature
GA10JT12-263
Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 5 of 11
Figure 13: Typical Switching Times and T ur n On Energy
Losses vs. Drain Current
Figure 14: Typical Switching Times and Turn O ff Energy
Losses vs. Drain Current
C: Current and Power Derating
Figure 15: Typical Hard Switched Device Power Loss vs.
Switching Fr eq uen cy
2
Figure 16: Power Derating Curve
Figure 17: Drain Current Derating vs. Temperature Figure 18: Forward Bias Safe Operating Area at Tc= 25 oC
2 – Representative values based on device conduction and switching loss. Actual losses will depend on gate drive conditions, device load, and circuit topology.
GA10JT12-263
Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 6 of 11
Figure 19: Turn-Off Safe Operating Area Figure 20: Trans ient Thermal Impedance
.
GA10JT12-263
Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 7 of 11
Section V: Driving the GA10JT12-263
Drive Topology Gate Drive Power
Consumption Switching
Frequency Application Emphasis Availability
TTL Logic
High
Low
Wide Temperature Range
Coming Soon
Constant Current Medium Medium Wide Temperature Range Coming Soon
High Speed – Boost Capacitor
Medium
High
Fast Switching
Production
High Speed – Boost Inductor
Low
High
Ultra Fast Switching
Coming Soon
Proportional
Lowest
High
Wide Drain Current Range
Coming Soon
Pulsed Power Medium N/A Pulse Power Coming Soon
A: Static TTL Logic Driving
The GA10JT12-263 may be driven with direct (5 V) TTL logic and current amplific ation. The amplified current level of the supply must m eet or
exceed the steady state gate current (IG,steady) required to operate the GA10JT12-263. Minimum IG,steady is dependent on the anticipated drain
current ID through the SJT and th e DC current gain h FE, it may be calc ulated from the following equation. An ac curate value of the h FE may be
read from Figure 4. An optional resis tor RG may be used in se ries with the gat e pin t o trim I G,steady, also an opti onal cap acitor CG ma y be added
in parallel with RG to facilitate faster SJT switching if desired, further details on these options are given in the following section.
,
(,)1.5
Figure 21: TTL Gate Drive Schematic
B: High Speed Driving
The SJT is a current controlled transi stor which requires a pos itive gate current for turn-on and to remain i n on-state. An ideal ized gate current
waveform for ultra-fast switching of the SJT while maintaining l ow gate drive losses is shown in Figure 22, it features a positive current peak
during turn-on, a negative current peak during turn-off, and continuous gate current during on-state.
Figure 22: An idealized gate current waveform for fast switching of an SJT.
An SJT is rapidly switched from its blocking state to on-state when the necessary gate charge, QG, for turn-on is supplied by a burst of high
gate current, IG,on, until the SJT gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged.
=, 1
+
TTL
Gate Signal
5 / 0 V
TTL i/p
5 V
D
S
G
GR
CG
RG
IG,steady
GA10JT12-263
Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 8 of 11
Ideally, IG,on should terminate when the drain v oltage falls to its on-state value i n order to avoid unnecessary drive l osses during the steady on-
state. In practice, the rise time of the I G,on pulse is affected by the parasiti c inductances, Lpar in the device pack age and drive circuit. A voltage
developed across the parasitic i nductance in the source path, Ls, c an de-bias the gate-s ource junction, when high d rain currents begi n to flow
through the device. The voltage applied to the gate pin should be maintained high enough, above the VGS,sat (see Figure 7) level to counter
these effects.
A high negative peak current, -IG,off is recommend ed at the s tart of the turn -off t ransi tion, i n orde r to r apidl y s weep out the inj ected c arriers from
the gate, and achieve rapid turn-off. Turn off can be achieved with VGS = 0 V, however a negative gate voltage VGS may be used in order to
speed up the turn-off transition.
Gate Return Pin
The optional gate return (GR) pin allows for a reduction of source path inductive and resistive coupling in the gate driver connection to the
GA10JT12-263. Drain currents th rough the source pin during trans ient and steady state operation in duce an undesirable source vol tage in all
power transistors due to unavoidable source pin inductance and resistance. This voltage can negatively affect gate driving performance,
however the gate return pin all ows for dec oupling f rom these sou rce current path effec ts which resul ts in faster s witching and higher ef fic iency
gate driving.
B:1: High Speed, Low Loss Drive with Boost Capacitor, GA03IDDJT30-FR4
The GA10JT12-263 may be driven using a High S peed, Low Loss Drive with Boo st Capacitor topol ogy in which multiple v oltage levels, a gate
resistor, and a gate capacitor are used to provide fast switching current peaks at turn-on and turn-off and a continuous gate current while in
on-state. A 3 kV isolated evaluation gate drive board (GA03IDDJT30-FR4) utilizing this topology is commercially available for high and low-
side driving, its datasheet provides additional details about this drive topology.
Figure 23: Topolog y of the GA03IDDJT30-FR4 Two Voltage Source gate driver.
The GA03IDDJT30-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective
gate resistance3 of RG = 3.75 Ω. It may be necessary for the user to reduce RG1 and RG2 under high drain current conditions for safe
operation of the GA10JT12-263. The steady state c urrent supplied to the gate pin of the GA10JT12-263 with on-board R G = 3.75 Ω, is shown
in Figure 24. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 25.
For the GA10JT12-263, RG must be reduced for ID ≥ ~11 A for safe operation with the GA03IDDJT30-FR4.
For operation at ID ≥ ~11 A, RG may be calculated from the following equati on, which contains the DC current gain h FE (Figure 4) and the gate-
source saturation voltage VGS,sat (Figure 7).
, =4.7 , (,)
1.5 0.6
IG
CG2
Gate
Signal
VGH
D1
R4
R1 U1
VGL
VEE
U2
VGL
VEE
VGL
U3
VGH
U4
VEE
C2
C1
VEE
U5
VGL
VEE
U6
CG1
RG1
RG2
R2
R3
C5
C3
C4
C8
C6 C9
C10
+12 V
+12 V
VCC High
VCC High RTN
VCC Low
VCC Low RTN
Signal
Signal RTN
Gate
Source
Voltage Isolation Barrier
GA03IDDJT30-FR4
Gate Driver Board
D
S
G
GR
GA10JT12-263
Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 9 of 11
Figure 24: Typical steady state gate current supplied by the
GA03IDDJT30-FR4 board for the GA10JT12-263 with the on
board resistance of 3.75 Ω
Figure 25: Maximum gate resistance for safe operation of
the GA10JT12-263 at different drain currents using the
GA03IDDJT30-FR4 board.
B:2: High Speed, Low Loss Drive with Boost Inductor
A High Speed, Low-Loss Driver with Boos t Induct or i s al so c apable of driv ing the G A10JT12-263 at hi gh-speed. It uti l iz es a gate dri ve i nductor
instead of a capacitor to provide the high-current gate current pulses IG,on and IG,off. During operation, inductor L is charged to a specified IG,on
current value then made to discharge IL into the SJT gate pin using logic control of S1, S2, S3, and S4, as shown in Figure 26. After turn on,
while the device remains on the neces sary steady state gate c urrent IG,steady is supplied from source VCC through R G. Please refer to the artic le
“A current-source concept for fast and efficient driving of silicon carbide transistors” by Dr. Jacek Rąbkowski for additional information on this
driving topology.4
Figure 26: Simplified Inductive Pulsed Drive Topology
3 – RG = (1/RG1 +1/RG2)-1. Driver is pre-installe d wi th RG1 = R G2 = 7.5 Ω
4 – Archives of Electrical Engineering. Volume 62, Issue 2, Pages 333–343, ISSN (Print) 0004-0746, DOI: 10.2478/aee-2013-0026, June 2013
L
RG
VEE
VCC
VCC
VEE
S1
S2
S3
S4
D
S
G
GR
GA10JT12-263
Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 10 of 11
C: Proportional Gate Current Driving
For applications in which the GA10JT12-263 will operate over a wide range of drain current condi tions, it may be beneficial to drive the device
using a proportional gate drive topology to optimize gate drive power consumption. A proportional gate driver relies on instantaneous drain
current ID feedback to vary the steady state gate current IG,steady supplied to the GA10JT12-263
C:1: Voltage Controlled Proportional Driver
The voltage controlled proportional driver relies on a gate drive IC to detect the GA10JT12-263 drain-source voltage VDS during on-state to
sense ID. The gate drive IC will then increase or decrease IG,steady in response to ID. This allows IG,steady, and thus the gate drive power
consumption, to be reduced whi le ID is relatively low or for IG,steady to increase when is ID hi gher. A high voltage diode connected between the
drain and sense protects the IC from high-vol tage when the driver and GA10JT12-263 are in off-state. A simpl ified version of this topology is
shown in Figure 27, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/
Figure 27: Simplified Voltage Controlled Proportional Driver
C:2: Current Controlled Proportional Driver
The current controlled proportional driver relies on a low-los s transformer in the dr ain or source path to provide feed back I D of the GA10JT12-
263 during on-state to supply IG,steady into the dev ice gate. IG,steady will then increase or decrease in response to ID at a fixed forced current gain
which is set be the turns ratio of the transformer, hforce = ID / IG = N2 / N1. GA10JT12-263 is i nitiall y turned-on using a gate current puls e suppli ed
into an RC drive circuit to allow ID current to begin flowing. This topology allows IG,steady, and thus the gate drive power consumption, to be
reduced while ID is relatively low or for IG,steady to increase when is ID higher. A simplified version of this topology is shown in Figure 28,
additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/.
Figure 28: Simplified Current Controlled Proportional Driver
Proportional
Gate Current
Driver
Gate Signal
I
G,steady
HV Diode
Sense
Signal Output
D
S
G
GR
N
2
N
2
N
1
N
3
Gate Signal
D
S
G
GR
GA10JT12-263
Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 11 of 11
Section VI: Package Dimensions
TO-263-7L PACKAGE OUTLINE
NOTE
1. CONTROLLED DIMENSION IS INCH. DI ME NSIO N IN BRACK E T IS MILLI ME TE R.
2. DIMENSIONS DO NOT INCLUDE END FLAS H, MOLD FLASH, MATERIAL PROTRUSIONS
Revision History
Date Revision Comments Supersedes
2015/06/05 0 Initial release
2015/11/20 1 Updated Electrical Characteristics
Published by
GeneSiC Semiconductor, Inc.
43670 Trade Center Place Suite 155
Dulles, VA 20166
GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice.
GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any
intellectual property rights is granted by this document.
Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft
navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal
injury and/or property damage.
0.171 (4.343)
0.181 (4.597)
0.045 (1.143)
0.055 (1.397)
0.000 (0.000)
0.012 (0.305)
SEATING PLANE
<D>
0.090 (2.286)
0.110 (2.794)
0.010 (0.254)
GATE PLANE
0°- 8°
0.013 (0.330)
0.017 (0.432)
0.400 (10.160)
0.420 (10.668)
0.055 (1.397) REF.
0.075 (1.905)
0.045 (1.143)
0.055 (1.397)
0.351 (8.915)
0.361 (9.169)
0.575 (14.605)
0.625 (15.875)
18°- 22° REF.
0.400 (10.160)
0.300 (7.620)
0.256 (6.502)
0.065 (1.651)
0.125 (3.175)
0.304
(7.722)
GA10JT12-263
XXXXXX Lot code
0.050
(1.27)
0.024
(0.60)
GA10JT12-263
Nov 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 1
Section VII: SPICE Model Parameters
This is a secure document. Please copy this code from the SPICE model PDF file on our website
(http://www.genesicsemi.com/images/products_sic/sjt/GA10JT12-263_SPICE.pdf) into LTSPICE
(version 4) software for simulation of the GA10JT12-263.
* MODEL OF GeneSiC Semiconductor Inc.
*
* $Revision: 2.0 $
* $Date: 20-NOV-2015 $
*
* GeneSiC Semiconductor Inc.
* 43670 Trade Center Place Ste. 155
* Dulles, VA 20166
*
* COPYRIGHT (C) 2015 GeneSiC Semiconductor Inc.
* ALL RIGHTS RESERVED
*
* These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY
* OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE."
* Models accurate up to 2 times rated drain current.
*
.model GA10JT12 NPN
+ IS 9.833E-48
+ ISE 1.073E-26
+ EG 3.23
+ BF 87
+ BR 0.55
+ IKF 5000
+ NF 1
+ NE 2
+ RB 4.67
+ IRB 0.001
+ RBM 0.16
+ RE 0.005
+ RC 0.08
+ CJC 229.9E-12
+ VJC 3.22
+ MJC 0.492
+ CJE 1244E-9
+ VJE 2.86
+ MJE 0.465
+ XTI 3
+ XTB -1.35
+ TRC1 7E-3
+ VCEO 1200
+ ICRATING 10
+ MFG GeneSiC_Semiconductor
*
* End of GA10JT12 SPICE Model
