ATmega103-6AX - Atmel Corporation

Features

•Utilizes the AVR® RISC Architecture

•AVR – High-performance and Low-power RISC Architecture

–121 Powerful Instructions – Most Single Clock Cycle Execution

–32 x 8 General Purpose Working Registers + Peripheral Control Registers

–Up to 6 MIPS Throughput at 6 MHz

•Data and Nonvolatile Program Memory

–128K Bytes of In-System Programmable Flash

Endurance: 1,000 Write/Erase Cycles

–4K Bytes Internal SRAM

–4K Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

–Programming Lock for Flash Program and EEPROM Data Security

–SPI Interface for In-System Programming

•Peripheral Features

–On-chip Analog Comparator

–Programmable Watchdog Timer with On-chip Oscillator

–Programmable Serial UART

–Master/Slave SPI Serial Interface

–Real Time Counter (RTC) with Separate Oscillator

–Two 8-bit Timer/Counters with Separate Prescaler and PWM

–Expanded 16-bit Timer/Counter System, with Separate Prescaler, Compare,

Capture Modes and Dual 8-, 9-, or 10-bit PWM

–Programmable Watchdog Timer with On-chip Oscillator

–8-channel, 10-bit ADC

•Special Microcontroller Features

–Low-power Idle, Power Save and Power-down Modes

–Software Selectable Clock Frequency

–External and Internal Interrupt Sources

•Specifications

–Low-power, High-speed CMOS Process Technology

–Fully Static Operation

•Power Consumption at 4 MHz, 3V, 25°C

–Active: 5.5 mA

–Idle Mode: 1.6 mA

–Power-down Mode: < 1 µA

•I/O and Packages

–32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines

–64-lead TQFP

•Operating Voltages

–2.7 - 3.6V (ATmega103L)

–4.0 - 5.5V (ATmega103)

•Speed Grades

–0 - 4 MHz (ATmega103L)

–0 - 6 MHz (ATmega103)

Rev. 0945E–01/00

8-bit

Microcontroller

with 128K Bytes

In-System

Programmable

Flash

ATmega103

ATmega103L

Preliminary

ATmega103/103L

Pin Configuration

TQFP

Description

The ATmega103(L) is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing power-

ful instructions in a single clock cycle, the ATmega103(L) achieves throughputs approaching 1 MIPS per MHz allowing the

system designer to optimize power consumption versus processing speed.

The AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 general purpose

working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code

efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega103(L) provides the following features: 128K bytes of in-system programmable Flash, 4K bytes EEPROM, 4K

bytes SRAM, 32 general purpose I/O lines, 8 input lines, 8 output lines, 32 general purpose working registers, real time

counter (RTC), 4 flexible timer/counters with compare modes and PWM, UART, programmable watchdog timer with inter-

nal oscillator, an SPI serial port and three software selectable power saving modes. The Idle mode stops the CPU while

allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power-down mode saves

the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In

Power Save mode, the timer oscillator continues to run, allowing the user to maintain a timer base while the rest of the

device is sleeping.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The on-chip ISP Flash allows the

program memory to be reprogrammed in-system through a serial interface or by a conventional nonvolatile memory

programmer. By combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the Atmel

ATmega103(L) is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded

control applications.

The ATmega103(L) AVR is supported with a full suite of program and system development tools including: C compilers,

macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

PC0 (A8)

VCC

GND

(ADC0) PF0

(ADC7) PF7

(ADC1) PF1

(ADC2) PF2

(ADC3) PF3

(ADC4) PF4

(ADC5) PF5

(ADC6) PF6

AREF

AGND

AVCC

6464

(PDI/RXD) PE0

(PDO/TXD) PE1

PEN

(AC+) PE2

(AC-) PE3

(INT4) PE4

(INT5) PE5

(INT6) PE6

(INT7) PE7

(SS) PB0

(SCK) PB1

(MOSI) PB2

(MISO) PB3

(OC0/PWM0) PB4

PB7 (OC2/PWM2)

TOSC2

(OC1B/PWM1B) PB6

TOSC1

(OC1A/PWM1A) PB5

PC1 (A9)

PD7 (T2)

PC2 (A10)

PC3 (A11)

PC4 (A12)

PC5 (A13)

PC6 (A14)

PC7 (A15)

PA7 (AD7)

ALE

PA6 (AD6)

PA5 (AD5)

PA4 (AD4)

PA3 (AD3)

(AD0) PA0

(AD1) PA1

(AD2) PA2

PD6 (T1)

PD5

PD4 (IC1)

PD3 (INT3)

PD2 (INT2)

PD1 (INT1)

PD0 (INT0)

XTAL1

XTAL2

RESET

GND

VCC

ATmega103/103L

INDEX CORNER

ATmega103/103L

Block Diagram

Figure 1. The ATmega103(L) Block Diagram

PROGRAM

COUNTER

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTE

DATA DIR.

REG. PORTA

DATA DIR.

REG. PORTD

DATA REGISTER

PORTB

DATA REGISTER

PORTE

DATA REGISTER

PORTA

DATA REGISTER

PORTC

DATA REGISTER

PORTD

PROGRAMMING

LOGIC

TIMING AND

CONTROL

OSCILLATOR

INTERRUPT

UNIT

EEPROM

SPI UART

STATUS

ALU

PORTB DRIVER/BUFFERSPORTE DRIVER/BUFFERS

PORTA DRIVER/BUFFERS

PORTF BUFFERS

ANALOG MUX ADC

PORTD DRIVER/BUFFERS

PORTC DRIVERS

PB0 - PB7PE0 - PE7

PA0 - PA7PF0 - PF7

RESET

VCC

AGND

GND

AREF

TOSC2

TOSC1

XTAL1

CONTROL

LINES

ANALOG

COMPARATOR

PD0 - PD7

PC0 - PC7

PEN

ALE

8-BIT DATA BUS

AVCC

ATmega103/103L

Pin Descriptions

VCC

Supply voltage

GND

Ground

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A

output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are

externally pulled low, they will source current if the internal pull-up resistors are activated.

Port A serves as Multiplexed Address/Data bus when using external SRAM.

The port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs,

Port B pins that are externally pulled low, will source current if the pull-up resistors are activated.

Port B also serves the functions of various special features.

The port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C (PC7..PC0)

Port C is an 8-bit output port. The Port C output buffers can sink 20 mA.

Port C also serves as Address output when using external SRAM.

Since Port C is an output only port, the port C pins are not tri-stated when a reset condition becomes active.

Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs,

Port D pins that are externally pulled low will source current if the pull-up resistors are activated.

Port D also serves the functions of various special features.

The port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output buffers can sink 20 mA. As inputs,

Port E pins that are externally pulled low will source current if the pull-up resistors are activated.

Port E also serves the functions of various special features.

The port E pins are tri-stated when a reset condition becomes active, even if the clock is not running

Port F (PF7..PF0)

Port F is an 8-bit input port. Port F also serves as the analog inputs for the ADC.

RESET

Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate

a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

ATmega103/103L

XTAL2

Output from the inverting oscillator amplifier.

TOSC1

Input to the inverting Timer/Counter oscillator amplifier.

TOSC2

Output from the inverting Timer/Counter oscillator amplifier.

External SRAM write strobe

External SRAM read strobe

ALE

ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the low-

order address (8 bits) into an address latch during the first access cycle, and the AD0-7 pins are used for data during the

second access cycle.

AVCC

Supply voltage for Port F, including ADC. The pin must be connected to VCC when not used for the ADC. See “ADC Noise

Canceling Techniques” on page 71 for details when using the ADC.

AREF

This is the analog reference input for the ADC converter. For ADC operations, a voltage in the range AGND to AVCC must

be applied to this pin.

AGND

If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to

GND.

PEN

This is a programming enable pin for the serial programming mode. By holding this pin low during a power-on reset, the

device will enter the serial programming mode. PEN has no function during normal operation.

ATmega103/103L

Clock Options

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-

chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used.

Figure 2. Oscillator Connections

Note: When using the MCU Oscillator as a clock for an external device, an HC buffer should be connected as indicated in the figure.

External Clock

To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in

Figure 3.

Figure 3. External Clock Drive Configuration

Timer Oscillator

For the Timer Oscillator pins, TOSC1 and TOSC2, the crystal is connected directly between the pins. No external capaci-

tors are needed. The oscillator is optimized for use with a 32,768 Hz watch crystal. An external clock signal applied to this

pin goes through the same amplifier having a bandwidth of 256 kHz. The external clock signal should therefore be in the

range 0 Hz - 256 kHz.

XTAL2

XTAL1

GND

MAX 1 HC BUFFER

XTAL2

XTAL1

GND

EXTERNAL

OSCILLATOR

SIGNAL

ATmega103/103L

Architectural Overview

Figure 4. The ATmega103(L) AVR RISC Architecture

The AVR uses a Harvard architecture concept – with separate memories and buses for program and data. The program

memory is accesses with a single level pipeline. While one instruction is being executed, the next instruction is pre-fetched

from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is

in-system programmable Flash memory. With a few exceptions, AVR instructions have a single 16-bit word format,

meaning that every program memory address contains a single 16-bit instruction.

During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is

effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and

the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are

executed). The 16-bit stack pointer SP is read/write accessible in the I/O space.

The 4000 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR

architecture.

64K x 16

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registers

ALU

Status

and Test

4K x 8

EEPROM

Peripherals

Data Bus 8-bit

AVR ATmega103(L) Architecture

4K x 8

Data

SRAM

Direct Addressing

Indirect Addressing

ATmega103/103L

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status

register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the

program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the

interrupt vector address, the higher the priority.

The memory spaces in the AVR architecture are all linear and regular memory maps.

General Purpose Register File

Figure 5 shows the structure of the 32 general purpose working registers in the CPU.

Figure 5. AVR CPU General Purpose Working Registers

All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only

exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a

register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the regis-

ters in the register file – R16..R31. The general SBC, SUB, CP, AND and OR and all other operations between two

registers or on a single register apply to the entire register file.

As shown in Figure 5, each register is also assigned a data memory address, mapping them directly into the first 32

locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization

provides great flexibility in access of the registers, as the X-, Y- and Z-registers can be set to index any register in the file.

The 4K bytes of SRAM available for general data are implemented as addresses $0060 to $0FFF.

7 0 Addr.

R0 $00

R1 $01

R2 $02

. . .

R13 $0D

General R14 $0E

Purpose R15 $0F

Working R16 $10

Registers R17 $11

. . .

R26 $1A X-register low byte

R27 $1B X-register high byte

R28 $1C Y-register low byte

R29 $1D Y-register high byte

R30 $1E Z-register low byte

R31 $1F Z-register high byte

ATmega103/103L

X-register, Y-register and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are address pointers

for indirect addressing of the SRAM. The three indirect address registers X, Y and Z are defined as:

Figure 6. X-, Y- and Z-registers

In the different addressing modes these address registers have functions as fixed displacement, automatic increment and

decrement (see the descriptions for the different instructions).

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a

single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into

three main categories – arithmetic, logical and bit-functions.

ISP Flash Program Memory

The ATmega103(L) contains 128K bytes on-chip In-system Programmable Flash memory for program storage. Since all

instructions are single or double 16-bit words, the Flash is organized as 64K x 16. The Flash memory has an endurance of

at least 1000 write/erase cycles.

Constant tables can be allocated in the entire program memory space (see the LPM – Load Program Memory and ELPM

Extended Load Program Memory instruction descriptions).

SRAM Data Memory

The ATmega103(L) supports two different configurations for the SRAM data memory as listed in the following table:

Note: When using 64K of external SRAM, 60K will be available.

15 0

X-register 7 0 7 0

R27 ($1B) R26 ($1A)

15 0

Y-register 7 0 7 0

R29 ($1D) R28 ($1C)

15 0

Z-register 7 0 7 0

R31 ($1F) R30 ($1E)

Table 1. Memory Configurations

Configuration Internal SRAM Data Memory External SRAM Data Memory

A 4000 None

B 4000 up to 64K

ATmega103/103L

Figure 7. Memory Configurations

32 Registers

64 I/O Registers

Internal SRAM

(4000 x 8)

$0000 - $001F

$0020 - $005F

$0000

$7FFF/$FFFF

$0FFF

$0060

Data MemoryProgram Memory

Program Flash

(32K/64K x 16)

Memory Configuration A

$0000 - $001F

$0020 - $005F

$0000

$7FFF/

$FFFF

$1000

$0FFF

$FFFF

$0060

Program Memory

Program Flash

(32K/64K x 16)

Memory Configuration B

32 Registers

64 I/O Registers

Internal SRAM

(4000 x 8)

Data Memory

External SRAM

(0 - 64K x 8)

ATmega103/103L

The 4096 first Data Memory locations address both the Register file, the I/O Memory and the internal data SRAM. The first

96 locations address the register file and I/O memory, and the next 4000 locations address the internal data SRAM.

An optional external data SRAM can be used with the ATmega103(L). This SRAM will occupy an area in the remaining

address locations in the 64K address space. This area starts at the address following the internal SRAM. If a 64K external

SRAM is used, 4K of the external memory is lost as the addresses are occupied by internal memory.

When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data

SRAM is accessed using the same instructions as for the internal data memory access. When the internal data memories

are accessed, the read and write strobe pins (RD and WR) are inactive during the whole access cycle. External SRAM

operation is enabled by setting the SRE bit in the MCUCR register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means

that the commands LD, ST, LDS, STS, PUSH and POP take one additional clock cycle. If the stack is placed in external

SRAM, interrupts, subroutine calls and returns take two clock cycles extra because the two-byte program counter is

pushed and popped. When external SRAM interface is used with wait state, two additional clock cycles is used per byte.

This has the following effect: Data transfer instructions take two extra clock cycles, whereas interrupt, subroutine calls and

returns will need four clock cycles more than specified in the “Instruction Set Summary” on page 122.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with

Pre-decrement and Indirect with Post-increment. In the register file, registers R26 to R31 feature the indirect addressing

pointer registers.

The Indirect with Displacement mode features a 63 address locations reach from the base address given by the Y- or

Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,

Y and Z are decremented and incremented.

The entire data address space including the 32 general purpose working registers and the 64 I/O registers are all accessi-

ble through all these addressing modes. See the next section for a detailed description of the different addressing modes.

Program and Data Addressing Modes

The ATmega103(L) AVR RISC microcontroller supports powerful and efficient addressing modes for access to the

program memory (Flash) and data memory (SRAM, Register File and I/O Memory). This section describes the different

addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction

word. To simplify, not all figures show the exact location of the addressing bits.

Figure 8. Direct Single Register Addressing

The operand is contained in register d (Rd).

OP d

ATmega103/103L

Figure 9. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

I/O Direct

Figure 10. I/O Direct Addressing

Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.

OP dr

0459

I/O MEMORY

OP P

ATmega103/103L

Data Direct

Figure 11. Direct Data Addressing

A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source

Data Indirect with Displacement

Figure 12. Data Indirect with Displacement

Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction

word.

OP Rr/Rd

15 0

16 LSBs

$0000

$FFFF

20 19

Data Space

$0000

$FFFF

Y- OR Z-REGISTER

OP an

05610

ATmega103/103L

Data Indirect

Figure 13. Data Indirect Addressing

Operand address is the contents of the X-, Y- or the Z-register.

Data Indirect with Pre-decrement

Figure 14. Data Indirect Addressing with Pre-decrement

The X-, Y- or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-,

Y- or the Z-register.

Data Space

$0000

$FFFF

X-, Y- OR Z-REGISTER

015

Data Space

$0000

$FFFF

X-, Y- OR Z-REGISTER

015

-1

ATmega103/103L

Data Indirect with Post-increment

Figure 15. Data Indirect Addressing with Post-increment

The X-, Y- or the Z-register is incremented after the operation. Operand address is the content of the X-, Y- or the Z-register

prior to incrementing.

Constant Addressing Using the LPM and ELPM Instructions

Figure 16. Code Memory Constant Addressing

Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 32K), LSB selects low

byte if cleared (LSB = 0) or high byte if set (LSB = 1). If ELPM is used, LSB of the RAM Page Z register – RAMPZ – is used

to select low or high memory page (RAMPZ0 = 0: Low Page, RAMPZ0 = 1: High Page).

Data Space

$0000

$FFFF

X-, Y- OR Z-REGISTER

015

PROGRAM MEMORY

$0000

$7FFF/$FFFF

0115

Z-REGISTER

ATmega103/103L

Direct Program Address, JMP and CALL

Figure 17. Direct Program Memory Addressing

Program execution continues at the address immediate in the instruction words.

Indirect Program Addressing, IJMP and ICALL

Figure 18. Indirect Program Memory Addressing

Program execution continues at address contained by the Z-register (i.e. the PC is loaded with the contents of the

Z-register).

21 20

15 0

16 LSBs

PROGRAM MEMORY $0000

$7FFF/$FFFF

PROGRAM MEMORY

$0000

$7FFF/$FFFF

015

Z-REGISTER

ATmega103/103L

Relative Program Addressing, RJMP and RCALL

Figure 19. Relative Program Memory Addressing

Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.

EEPROM Data Memory

The EEPROM memory is organized as a separate data space, in which single bytes can be read and written. The

EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is

described on page 52 specifying the EEPROM address register, the EEPROM data register, and the EEPROM control

Memory Access Times and Instruction Execution Timing

This section describes the general access timing concepts for instruction execution and internal memory access.

The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal

clock division is used.

Figure 20 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the

fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding

unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 20. The Parallel Instruction Fetches and Instruction Executions

15 1112

OP k

PROGRAM MEMORY $0000

$7FFF/$FFFF

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

ATmega103/103L

Figure 21 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register

operands is executed, and the result is stored back to the destination register.

Figure 21. Single Cycle ALU Operation

The internal data SRAM access is performed in two System Clock cycles as described in Figure 22.

Figure 22. On-chip Data SRAM Access Cycles

See “Interface to External SRAM” on page 72 for a description of the access to the external SRAM.

System Clock Ø

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

System Clock Ø

Data

Address Address

T1 T2 T3 T4

Prev. Address

Read Write

ATmega103/103L

I/O Memory

The I/O space definition of the ATmega103(L) is shown in the following table:

Table 2. ATmega103(L) I/O Space

I/O Address (SRAM Address) Name Function

$3F ($5F) SREG Status REGister

$3E ($5E) SPH Stack Pointer High

$3D ($5D) SPL Stack Pointer Low

$3C ($5C) XDIV XTAL Divide Control Register

$3B ($5B) RAMPZ RAM Page Z Select Register

$3A ($5A) EICR External Interrupt Control Register

$39 ($59) EIMSK External Interrupt MaSK register

$38 ($58) EIFR External Interrupt Flag Register

$37 ($57) TIMSK Timer/Counter Interrupt MaSK register

$36 ($56) TIFR Timer/Counter Interrupt Flag register

$35 ($55) MCUCR MCU General Control Register

$34 ($54) MCUSR MCU Status Register

$33 ($53) TCCR0 Timer/Counter0 Control Register

$32 ($52) TCNT0 Timer/Counter0 (8-bit)

$31 ($51) OCR0 Timer/Counter0 Output Compare Register

$30 ($50) ASSR Asynchronous Mode Status Register

$2F ($4F) TCCR1A Timer/Counter1 Control Register A

$2E ($4E) TCCR1B Timer/Counter1 Control Register B

$2D ($4D) TCNT1H Timer/Counter1 High Byte

$2C ($4C) TCNT1L Timer/Counter1 Low Byte

$2B ($4B) OCR1AH Timer/Counter1 Output Compare Register A High Byte

$2A ($4A) OCR1AL Timer/Counter1 Output Compare Register A Low Byte

$29 ($49) OCR1BH Timer/Counter1 Output Compare Register B High Byte

$28 ($48) OCR1BL Timer/Counter1 Output Compare Register B Low Byte

$27 ($47) ICR1H Timer/Counter1 Input Capture Register High Byte

$26 ($46) ICR1L Timer/Counter1 Input Capture Register Low Byte

$25 ($45) TCCR2 Timer/Counter2 Control Register

$24 ($44) TCNT2 Timer/Counter2 (8-bit)

$23 ($43) OCR2 Timer/Counter2 Output Compare Register

$21 ($41) WDTCR Watchdog Timer Control Register

$1F ($3F) EEARH EEPROM Address Register High

$1E ($3E) EEARL EERPOM Address Register Low

$1D ($3D) EEDR EEPROM Data Register

$1C ($3C) EECR EEPROM Control Register

ATmega103/103L

Note: Reserved and unused locations are not shown in the table.

All the different ATmega103(L) I/Os and peripherals are placed in the I/O space. The different I/O locations are directly

accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O

space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In

these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the “Instruction

Set Summary” on page 122 for more details. When using the I/O specific instructions IN, OUT, the I/O register address

$00 - $3F are used. When addressing I/O registers as SRAM, $20 must be added to this address. All I/O register

addresses throughout this document are shown with the SRAM address in parentheses.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on

all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions

work with registers $00 to $1F only.

$1B ($3B) PORTA Data Register, Port A

$1A ($3A) DDRA Data Direction Register, Port A

$19 ($39) PINA Input Pins, Port A

$18 ($38) PORTB Data Register, Port B

$17 ($37) DDRB Data Direction Register, Port B

$16 ($36) PINB Input Pins, Port B

$15 ($35) PORTC Data Register, Port C

$12 ($32) PORTD Data Register, Port D

$11 ($31) DDRD Data Direction Register, Port D

$10 ($30) PIND Input Pins, Port D

$0F ($2F) SPDR SPI I/O Data Register

$0E ($2E) SPSR SPI Status Register

$0D ($2D) SPCR SPI Control Register

$0C ($2C) UDR UART I/O Data Register

$0B ($2B) USR UART Status Register

$0A ($2A) UCR UART Control Register

$09 ($29) UBRR UART Baud Rate Register

$08 ($28) ACSR Analog Comparator Control and Status Register

$07 ($27) ADMUX ADC Multiplexer Select Register

$06 ($26) ADCSR ADC Control and Status Register

$05 ($25) ADCH ADC Data Register High

$04 ($24) ADCL ADC Data Register Low

$03 ($23) PORTE Data Register, Port E

$02 ($22) DDRE Data Direction Register, Port E

$01 ($21) PINE Input Pins, Port E

$00 ($20) PINF Input Pins, Port F

Table 2. ATmega103(L) I/O Space (Continued)

I/O Address (SRAM Address) Name Function

ATmega103/103L

The different I/O and peripherals control registers are explained in the following sections.

Status Register – SREG

The AVR status register – SREG – at I/O space location $3F ($5F) is defined as:

•Bit 7 - I: Global Interrupt Enable

The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is

then performed in separate control registers. If the global interrupt enable register is cleared (zero), none of the interrupts

are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has

occurred, and is set by the RETI instruction to enable subsequent interrupts.

•Bit 6 - T: Bit Copy Storage

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. A

bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a

•Bit 5 - H: Half Carry Flag

The half carry flag H indicates a half carry in some arithmetic operations. See the instruction set description on page 122

for detailed information.

•Bit 4 - S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the instruc-

tion set description on page 122 for detailed information.

•Bit 3 - V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetics. See the instruction set description on

page 122 for detailed information.

•Bit 2 - N: Negative Flag

The negative flag N indicates a negative result from an arithmetical or logical operation. See the Instruction set description

on page 122 for detailed information.

•Bit 1 - Z: Zero Flag

The zero flag Z indicates a zero result from an arithmetical or logical operation. See the instruction set description on

page 122 for detailed information.

•Bit 0 - C: Carry Flag

The carry flag C indicates a carry in an arithmetical or logical operation. See the instruction set description on page 122 for

detailed information.

Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from

an interrupt routine. This must be handled by software.

Stack Pointer – SP

The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and

$3D ($5D). As the ATmega103(L) supports up to 64K bytes memory, all 16 bits are used.

Bit 76543210

$3F ($5F) I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 151413121110 9 8

$3E ($5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

00000000

ATmega103/103L

The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack

space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are

enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed

onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with

subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP

instruction, and it is incremented by two when an address is popped from the Stack with return from subroutine RET or

return from interrupt RETI.

RAM Page Z Select Register – RAMPZ

The RAMPZ register is normally used to select which 64K RAM Page is accessed by the Z pointer. As the ATmega103(L)

does not support more than 64K of SRAM memory, this register is used only to select which page in the program memory

is accessed when the ELPM instruction is used. The different settings of the RAMPZ0 bit have the following effects:

Note that LPM is not affected by the RAMPZ setting.

MCU Control Register – MCUCR

The MCU Control Register contains control bits for general MCU functions.

•Bit 7 - SRE: External SRAM Enable

When the SRE bit is set (one), the external data SRAM is enabled, and the pin functions AD0-7 (Port A), and A8-15 (Port

C) are activated as the alternate pin functions. Then the SRE bit overrides any pin direction settings in the respective data

direction registers. When the SRE bit is cleared (zero), the external data SRAM is disabled, and the normal pin and data

direction settings are used.

•Bit 6 - SRW: External SRAM Wait State

When the SRW bit is set (one), a one cycle wait state is inserted in the external data SRAM access cycle. When the SRW

bit is cleared (zero), the external data SRAM access is executed with a three-cycle scheme. See Figure 51 on page 73 and

Figure 52 on page 74.

•Bit 5 - SE: Sleep Enable

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the

MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just

before the execution of the SLEEP instruction.

Bit 7654321 0

$3B ($5B) - - - - - - - RAMPZ0 RAMPZ

Read/WriteRRRRRRRR/W

Initial value0000000 0

RAMPZ0 = 0: Program memory address $0000 - $7FFF (lower 64K bytes) is accessed by ELPM

RAMPZ0 = 1: Program memory address $8000 - $FFFF (higher 64K bytes) is accessed by ELPM

Bit 7654321 0

$35 ($55) SRE SRW SE SM1 SM0 - - - MCUCR

Read/Write R/W R/W R/W R/W R/W R R R

Initial value0000000 0

ATmega103/103L

•Bits 4,3 - SM1/SM0: Sleep Mode Select Bits 1 and 0

This bit selects between the three available sleep modes as shown in the following table:

•Bits 2..0 - Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always read zero.

XTAL Divide Control Register – XDIV

The XTAL Divide Control Register is used to divide the XTAL clock frequency by a number in the range 1 - 129. This fea-

ture can be used to decrease power consumption when the requirement for processing power is low.

•Bit 7 - XDIVEN: XTAL Divide Enable

When the XDIVEN bit is set (one), the clock frequency of the CPU and all peripherals is divided by the factor defined by the

setting of XDIV6 - XDIV0. This bit can be set and cleared run-time to vary the clock frequency as suitable to the application.

•Bits 6..0 - XDIV6..XDIV0: XTAL Divide Select Bits 6 - 0

These bits define the division factor that applies when the XDIVEN bit is set (one). If the value of these bits is denoted d,

the following formula defines the resulting CPU clock frequency fclk:

The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is set to one, the value written simulta-

neously into XDIV6..XDIV0 is taken as the division factor. When XDIVEN is cleared to zero, the value written

simultaneously into XDIV6..XDIV0 is rejected. As the divider divides the master clock input to the MCU, the speed of all

peripherals is reduced when a division factor is used.

Table 3. Sleep Mode Select

SM1 SM0 Sleep Mode

0 0 Idle Mode

01Reserved

10Power-down

11Power Save

Bit 7 654321 0

$3C ($5C) XDIVEN XDIV6 XDIV5 XDIV4 XDIV3 XDIV2 XDIV1 XDIV0 XDIV

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value0 000000 0

fCLK

XTAL

129 d–

-------------------=

ATmega103/103L

Reset and Interrupt Handling

The ATmega103(L) provides 23 different interrupt sources. These interrupts and the separate reset vector each have a

separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be set

(one) together with the I-bit in the status register in order to enable the interrupt.

The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The

complete list of vectors is shown in Table 4. The list also determines the priority levels of the different interrupts. The lower

the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt

Request 0, etc.

Table 4. Reset and Interrupt Vectors

Vector No. Program Address Source Interrupt Definition

1 $0000 RESET Hardware Pin, Power-on Reset and Watchdog Reset

2 $0002 INT0 External Interrupt Request 0

3 $0004 INT1 External Interrupt Request 1

4 $0006 INT2 External Interrupt Request 2

5 $0008 INT3 External Interrupt Request 3

6 $000A INT4 External Interrupt Request 4

7 $000C INT5 External Interrupt Request 5

8 $000E INT6 External Interrupt Request 6

9 $0010 INT7 External Interrupt Request 7

10 $0012 TIMER2 COMP Timer/Counter2 Compare Match

11 $0014 TIMER2 OVF Timer/Counter2 Overflow

12 $0016 TIMER1 CAPT Timer/Counter1 Capture Event

13 $0018 TIMER1 COMPA Timer/Counter1 Compare Match A

14 $001A TIMER1 COMPB Timer/Counter1 Compare Match B

15 $001C TIMER1 OVF Timer/Counter1 Overflow

16 $001E TIMER0 COMP Timer/Counter0 Compare Match

17 $0020 TIMER0 OVF Timer/Counter0 Overflow

18 $0022 SPI, STC SPI Serial Transfer Complete

19 $0024 UART, RX UART, Rx Complete

20 $0026 UART, UDRE UART Data Register Empty

21 $0028 UART, TX UART, Tx Complete

22 $002A ADC ADC Conversion Complete

23 $002C EE READY EEPROM Ready

24 $002E ANALOG COMP Analog Comparator

ATmega103/103L

The most typical program setup for the Reset and Interrupt Vector Addresses are:

Address Labels Code Comments

$0000 jmp RESET ; Reset Handler

$0002 jmp EXT_INT0 ; IRQ0 Handler

$0004 jmp EXT_INT1 ; IRQ1 Handler

$0006 jmp EXT_INT2 ; IRQ2 Handler

$0008 jmp EXT_INT3 ; IRQ3 Handler

$000A jmp EXT_INT4 ; IRQ4 Handler

$000C jmp EXT_INT5 ; IRQ5 Handler

$000E jmp EXT_INT6 ; IRQ6 Handler

$0010 jmp EXT_INT7 ; IRQ7 Handler

$0012 jmp TIM2_COMP ; Timer2 Compare Handler

$0014 jmp TIM2_OVF ; Timer2 Overflow Handler

$0016 jmp TIM1_CAPT ; Timer1 Capture Handler

$0018 jmp TIM1_COMPA ; Timer1 CompareA Handler

$001A jmp TIM1_COMPB ; Timer1 CompareB Handler

$001C jmp TIM1_OVF ; Timer1 Overflow Handler

$001E jmp TIM0_COMP ; Timer0 Compare Handler

$0020 jmp TIM0_OVF ; Timer0 Overflow Handler

$0022 jmp SPI_STC ; SPI Transfer Complete Handler

$0024 jmp UART_RXC ; UART RX Complete Handler

$0026 jmp UART_DRE ; UDR Empty Handler

$0028 jmp UART_TXC ; UART TX Complete Handler

$002A jmp ADC ; ADC Conversion Complete Handler

$002C jmp EE_RDY ; EEPROM Ready Handler

$002E jmp ANA_COMP ; Analog Comparator Handler

;

$0030 MAIN: ldi r16, high(RAMEND); Main program start

$0031 out SPH,r16

$0032 ldi r16, low(RAMEND)

$0033 out SPL,r16

$0034 <instr> xxx

... ... ... ...

Reset Sources

The ATmega103(L) has three sources of reset:

•Power-on Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (VPOT).

•External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns.

•Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.

During reset, all I/O registers except the MCU Status register are then set to their initial values, and the program starts exe-

cution from address $0000. The instruction placed in address $0000 must be a JMP – absolute jump instruction to the reset

handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program

code can be placed at these locations. The circuit diagram in Figure 23 shows the reset logic. Table 5 defines the timing

and electrical parameters of the reset circuitry.

ATmega103/103L

Figure 23. Reset Logic

Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling).

Table 5. Reset Characteristics (VCC = 5V)

Symbol Parameter Condition Min Typ Max Units

VPOT(1) Power-on Reset Threshold (rising) 1.0 1.4 1.8 V

Power-on Reset Threshold (falling) 0.4 0.6 0.8 V

VRST RESET Pin Threshold Voltage VCC/2 V

TTOUT Reset Delay Time-out Period

SUT = 00 5 CPU cycles

SUT = 01

SUT = 10

SUT = 11

0.4

3.2

12.8

0.5

4.0

16.0

0.6

4.8

19.2

Power-on Reset

Circuit

Reset Circuit

Watchdog

Timer

On-chip

RC Oscillator

Delay Unit

RINTERNAL

RESET

POR

VCC

XTAL1

RESET

PEN D Q

100-500K

10-50K

COUNTER RESET

SUT0

SUT1

Q8 Q11 Q13

14-stage Ripple Counter

ATmega103/103L

Power-on Reset

A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As shown in Figure 23, an internal timer

clocked from the Watchdog timer oscillator prevents the MCU from starting until after a certain period after VCC has

reached the Power-on Threshold voltage – VPOT, regardless of the VCC rise time (see Figure 24). The Fuse bits SUT1 and

SUT0 is used to select start-up time as indicated in Table 5. A “0” in the table indicates that the fuse is programmed.

The user can select the start-up time according to typical oscillator start-up time. The number of WDT oscillator cycles used

for each time-out except for SUT = 00 is shown in Table 6. The frequency of the watchdog oscillator is voltage dependent

as shown in “Typical Characteristics” on page 110.

The setting SUT 1/0 = 00 starts the MCU after 5 CPU clock cycles, and can be used when an external clock signal is

applied to the XTAL1 pin. This setting does not use the WDT oscillator, and enables very fast start-up from the sleep

modes power-down or power save if the clock signal is present during sleep. For details, refer to the programming specifi-

cation starting on page 92.

If the built-in start-up delay is sufficient, RESET can be connected to VCC directly or via an external pull-up resistor. By hold-

ing the pin low for a period after VCC has been applied, the Power-on Reset period can be extended. Refer to Figure 25 for

a timing example on this.

Figure 24. MCU Start-up, RESET Tied to VCC.

Table 6. Number of Watchdog Oscillator Cycles

SUT 1/0 Time-out at VCC = 5V Number of WDT cycles

01 0.5 ms 512

10 4.0 ms 4K

11 16.0 ms 16K

VCC

RESET

TIME-OUT

INTERNAL

RESET

tTOUT

VPOT

VRST

ATmega103/103L

Figure 25. MCU Start-up, RESET Controlled Externally

External Reset

An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even

if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the

Reset Threshold Voltage (VRST) on its positive edge, the delay timer starts the MCU after the Time-out period tTOUT has

expired.

Figure 26. External Reset During Operation

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this

pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 51 for details on operation of the Watchdog.

VCC

RESET

TIME-OUT

INTERNAL

RESET

tTOUT

VPOT

VRST

VCC

RESET

TIME-OUT

INTERNAL

RESET

tTOUT

VRST

ATmega103/103L

Figure 27. Watchdog Reset during Operation

MCU Status Register – MCUSR

The MCU Status Register provides information on which reset source caused an MCU reset.

•Bits 7..2 - Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always read as zero.

•Bit 1 - EXTRF: External Reset Flag

After a power-on reset, this bit is undefined (X). It will be set by an external reset. A watchdog reset will leave this bit

unchanged.

•Bit 0 - PORF: Power-on Reset Flag

This bit is set by a power-on reset. A watchdog reset or an external reset will leave this bit unchanged.

To summarize, the following table shows the value of these two bits after the three modes of reset:

To make use of these bits to identify a reset condition, the user software should clear both the PORF and EXTRF bits as

early as possible in the program. Checking the PORF and EXTRF values is done before the bits are cleared. If the bit is

cleared before an external or watchdog reset occurs, the source of reset can be found by using the following truth table:

Bit 7 654321 0

$34 ($54) - - - - - - EXTRF PORF MCUSR

Read/WriteR RRRRRR/WR/W

Initial value 0 0 0 0 0 0 See bit description

Table 7. PORF and EXTRF Values after Reset

Reset Source EXTRF PORF

Power-on Reset undefined 1

External Reset 1 unchanged

Watchdog Reset unchanged unchanged

Table 8. Reset Source Identification

Reset Source EXTRF PORF

Watchdog Reset 0 0

Power-on Reset 0 1

External Reset 1 0

Power-on Reset 1 1

VCC

RESET

TIME-OUT

INTERNAL

RESET

WDT

TIME-OUT

1 XTAL Cycle

TOUT

ATmega103/103L

Interrupt Handling

The ATmega103(L) has two dedicated 8-bit Interrupt Mask control registers; EIMSK – External Interrupt Mask register and

TIMSK – Timer/Counter Interrupt Mask register. In addition, other enable and mask bits can be found in the peripheral

control registers.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user soft-

ware can set (one) the I-bit to enable nested interrupts. The I-bit is set (one) when a Return from Interrupt instruction (RETI)

is executed.

When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hard-

ware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a

logic one to the flag bit position(s) to be cleared.

If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set

and remembered until the interrupt is enabled, or the flag is cleared by software.

If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt

flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority.

Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is

active.

Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from

an interrupt routine. This must be handled by software.

External Interrupt Mask Register – EIMSK

•Bits 7..4 - INT7 - INT4: External Interrupt Request 7-4 Enable

When an INT7- INT4 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin

interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Register (EICR) defines whether the

external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt

request even if the pin is enabled as an output. This provides a way of generating a software interrupt.

•Bits 3..0 - INT3 - INT0: External Interrupt Request 3-0 Enable

When an INT3 - INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin

interrupt is enabled. The external interrupts are always low level triggered interrupts. Activity on any of these pins will trig-

ger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt.

When enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low.

External Interrupt Flag Register – EIFR

•Bits 7..4 - INTF7 - INTF4: External Interrupt 7-4 Flags

When an event on the INT7 - INT4 pins triggers an interrupt request, the corresponding interrupt flag, INTF7 - INTF4

becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7 - INT4 in EIMSK, are set (one), the

MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag is

cleared by writing a logical one to it.

•Bits 3..0 - Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always read as zero.

Bit 7654 3 2 10

$39 ($59) INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 EIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

Bit 7654 3 2 10

$38 ($58) INTF7 INTF6 INTF5 INTF4 - - - - EIFR

Read/Write R/W R/W R/W R/W R R R R

Initial value 0 0 0 0 0 0 0 0

ATmega103/103L

External Interrupt Control Register – EICR

•Bits 7..0 - ISCX1, ISCX0: External Interrupt 7-4 Sense Control Bits

The External Interrupts 7 - 4 are activated by the external pins INT7 - INT4 if the SREG I-flag and the corresponding inter-

rupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in the

following table:

The value on the INTX pin is sampled before detecting edges. If edge interrupt is selected, pulses that last longer than one

CPU clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU

clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the

low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level

triggered interrupt will generate an interrupt request as long as the pin is held low.

Timer/Counter Interrupt Mask Register – TIMSK

•Bit 7 - OCIE2: Timer/Counter2 Output Compare Interrupt Enable

When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match inter-

rupt is enabled. The corresponding interrupt (at vector $0012) is executed if a Compare match in Timer/Counter2 occurs,

i.e. when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

•Bit 6 - TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is

enabled. The corresponding interrupt (at vector $0014) is executed if an overflow in Timer/Counter2 occurs, i.e., when the

TOV2 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).

•Bit 5 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event

Interrupt is enabled. The corresponding interrupt (at vector $0016) is executed if a capture-triggering event occurs on pin

29, PD4(IC1), i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register.

•Bit 4 - OCE1A: Timer/Counter1 Output CompareA Match Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match

interrupt is enabled. The corresponding interrupt (at vector $0018) is executed if a CompareA match in Timer/Counter1

occurs, i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register.

Bit 7654 3 2 1 0

$3A ($5A) ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 EICR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

Table 9. Interrupt Sense Control

ISCX1 ISCX0 Description

0 0 The low level of INTX generates an interrupt request.

01Reserved

1 0 The falling edge of INTX generates an interrupt request.

1 1 The rising edge of INTX generates an interrupt request.

Bit 7 6 5 4 3 2 1 0

$37 ($57) OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 TIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

ATmega103/103L

•Bit 3 - OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match

interrupt is enabled. The corresponding interrupt (at vector $001A) is executed if a CompareB match in Timer/Counter1

occurs, i.e., when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register.

•Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is

enabled. The corresponding interrupt (at vector $001C) is executed if an overflow in Timer/Counter1 occurs, i.e., when the

TOV1 bit is set in the Timer/Counter Interrupt Flag Register.

•Bit 1 - OCIE0: Timer/Counter0 Output Compare Interrupt Enable

When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match inter-

rupt is enabled. The corresponding interrupt (at vector $001E) is executed if a Compare match in Timer/Counter0 occurs,

i.e., when the OCF0 bit is set in the Timer/Counter Interrupt Flag Register.

•Bit 0 - TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is

enabled. The corresponding interrupt (at vector $0020) is executed if an overflow in Timer/Counter0 occurs, i.e., when the

TOV0 bit is set in the Timer/Counter Interrupt Flag Register.

Timer/Counter Interrupt Flag Register – TIFR

•Bit 7 - OCF2: Output Compare Flag 2:

The OCF2 bit is set (one) when compare match occurs between Timer/Counter2 and the data in OCR2 – Output Compare

is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE2 (Timer/Counter2 Compare Interrupt

Enable), and the OCF2 are set (one), the Timer/Counter2 Output Compare Interrupt is executed.

•Bit 6 - TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the I-bit in

SREG, and TOIE2 (Timer/Counter1 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow

Interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 advances from $00.

•Bit 5 - ICF1: Input Capture Flag 1

The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the

input capture register – ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector.

Alternatively, ICF1 is cleared by writing a logic one to the flag. When the SREG I-bit, and TICIE1 (Timer/Counter1 Input

Capture Interrupt Enable), and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.

•Bit 4 - OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A – Output

Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-

tively, OCF1A is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1A (Timer/Counter1 Compare

Interrupt Enable), and the OCF1A are set (one), the Timer/Counter1 CompareA match Interrupt is executed.

•Bit 3 - OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B – Output

Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alterna-

tively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare

match Interrupt Enable), and the OCF1B are set (one), the Timer/Counter1 CompareB match Interrupt is executed.

Bit 7 6 5 4 3 2 1 0

$36 ($56) OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 TIFR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

ATmega103/103L

•Bit 2 - TOV1: Timer/Counter1 Overflow Flag

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in

SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow

Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 advances from $0000.

•Bit 1 - OCF0: Output Compare Flag 0

The OCF0 bit is set (one) when compare match occurs between Timer/Counter0 and the data in OCR0 – Output Compare

is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE0 (Timer/Counter2 Compare Interrupt

Enable), and the OCF0 are set (one), the Timer/Counter0 Output Compare Interrupt is executed.

•Bit 0 - TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG

I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow inter-

rupt is executed. In PWM mode, this bit is set when Timer/Counter0 advances from $00.

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. 4 clock cycles after the

interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this 4

clock cycle period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2.

The vector is normally a jump to the interrupt routine, and this jump takes 3 clock cycles. If an interrupt occurs during exe-

cution of a multi-cycle instruction, this instruction is completed before the interrupt is served.

A return from an interrupt handling routine (same as for a subroutine call routine) takes 4 clock cycles. During these 4 clock

cycles, the Program Counter (2 bytes) is popped back from the Stack, and the Stack Pointer is incremented by 2. When the

AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending

interrupt is served.

Sleep Modes

To enter any of the three sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed.

The SM1 and SM0 bits in the MCUCR register select which sleep mode (Idle, Power-down, or Power Save) will be acti-

vated by the SLEEP instruction, see Table 3 on page 23.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the register file, SRAM, and I/O memory are unal-

tered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset vector

Idle Mode

When the SM1/SM0 bits are set to 00, the SLEEP instruction makes the MCU enter the Idle Mode, stopping the CPU but

allowing SPI, UART, Analog Comparator, ADC, Timer/Counters, Watchdog and the interrupt system to continue operating.

This enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and

UART Receive Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the analog compara-

tor can be powered down by setting the ACD-bit in the Analog Comparator Control and Status register (ACSR). This will

reduce power consumption in Idle Mode. When the MCU wakes up from Idle mode, the CPU starts program execution

immediately.

ATmega103/103L

Power-down Mode

When the SM1/SM0 bits are set to 10, the SLEEP instruction makes the MCU enter the Power-down Mode. In this mode,

the external oscillator is stopped, while the external interrupts and the Watchdog (if enabled) continue operating. Only an

external reset, a watchdog reset (if enabled), or an external level interrupt can wake up the MCU.

Note that if a level triggered interrupt is used for wake-up from Power-down Mode, the changed level must be held for some

time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the watch-

dog oscillator clock, and if the input has the required level during this time, the MCU will wake up. The period of the

watchdog oscillator is 1 µs (nominal) at 5.0V and 25C. The frequency of the watchdog oscillator is voltage dependent as

shown in “Typical Characteristics” on page 110.

When waking up from Power-down Mode, there is a delay from the wake-up condition occurs until the wake-up becomes

effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by

the same SUT fuses that define the reset time-out period. The wake-up period is equal to the clock reset period, as shown

in Table 5 on page 26.

If the wake-up condition disappears before the MCU wakes up and starts to execute, e.g. a low level on is not held long

enough, the interrupt causing the wake-up will not be executed.

Power Save Mode

When the SM1/SM0 bits are 11, the SLEEP instruction makes the MCU enter the Power Save Mode. This mode is identical

to Power-down, with one exception:

If Timer/Counter0 is clocked asynchronously, i.e. the AS0 bit in ASSR is set, Timer/Counter0 will run during sleep. In addi-

tion to the Power-down wake-up sources, the device can also wake up from either Timer Overflow or Output Compare

event from Timer/Counter0 if the corresponding Timer/Counter0 interrupt enable bits are set in TIMSK. To ensure that the

part executes the Interrupt routine when waking up, also set the global interrupt enable bit in SREG.

When waking up from Power Save Mode by an external interrupt, 2 instruction cycles are executed before the interrupt

flags are updated. When waking up by the asynchronous timer, 3 instruction cycles are executed before the flags are

updated. During these cycles, the processor executes instructions, but the interrupt condition is not readable, and the

interrupt routine has not started yet. If the asynchronous timer is not clocked asynchronously, Power-down Mode is recom-

mended instead of Power Save Mode because the contents of the registers in the asynchronous timer should be

considered undefined after wake-up in Power Save Mode if ASX is 0.

Timer/Counters

The ATmega103(L) provides three general purpose Timer/Counters – two 8-bit T/Cs and one 16-bit T/C. Timer/Counter0

can optionally be asynchronously clocked from an external oscillator. This oscillator is optimized for use with a 32.768 kHz

crystal, enabling use of Timer/Counter0 as a Real Time Clock (RTC). Timer/Counter0 has its own prescaler.

Timer/Counters 1 and 2 have individual prescaling selection from the same 10-bit prescaling timer. These Timer/Counters

can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers

the counting.

ATmega103/103L

Timer/Counter Prescalers

Figure 28. Prescaler for Timer/Counter1 and Timer/Counter2

For Timer/Counters 1 and 2, the four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024 where CK is

the CPU clock. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. For

Timer/Counters 1 and 2, added selections as CK, external source and stop, can be selected as clock sources.

Figure 29. The Timer/Counter0 Prescaler

10-BIT T/C PRESCALER

TIMER/COUNTER2 CLOCK SOURCE

TCK2

TIMER/COUNTER1 CLOCK SOURCE

TCK1

CS20 CS10

CS21 CS11

CS22 CS12

CK/8

CK/256

CK/1024

CK/64

10-BIT T/C PRESCALER

TIMER/COUNTER0 CLOCK SOURCE

PCK0

CK PCK0

TOSC1

AS0

CS00

CS01

CS02

PCK0/8

PCK0/64

PCK0/128

PCK0/1024

PCK0/256

PCK0/32

ATmega103/103L

The clock source for Timer/Counter0 prescaler is named PCK0. PCK0 is by default connected to the main system clock

CK. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. By setting the

AS0 bit in ASSR, Timer/Counter 0 prescaler is asynchronously clocked from the TOSC1 pin. This enables use of

Timer/Counter0 as a Real Time Clock (RTC). A crystal can be connected between the TOSC1 and TOSC2 pins to serve as

an independent clock source for Timer/Counter0. This oscillator is optimized for use with a 32.768 kHz crystal.

8-bit Timer/Counters T/C0 and T/C2

Figure 30 shows the block diagram for Timer/Counter0.

Figure 30. Timer/Counter0 Block Diagram

8-BIT DATA BUS

8-BIT ASYNCH T/C0 DATA BUS

ASYNCH. STATUS

TIMER INT. FLAG

TIMER/COUNTER0

(TCNT0)

SYNCH UNIT

8-BIT COMPARATOR

OUTPUT COMPARE

REGISTER0 (OCR0)

TIMER INT. MASK

T/C CLK SOURCE

UP/DOWN

T/C CLEAR

CONTROL

LOGIC

OCF0

TOV0

TOV1

OCF2A

OCF2B

ICF1

TOV2

OCF2

OCF0

TOV0

OCIE0

TOIE0

TOIE1

OCIE1A

OCIE1B

TICIE1

TOIE2

OCIE2

OCR0UB

TC0UB

ICR0UB

PCK0

TCK0

T/C0 OVER-

FLOW IRQ

T/C0 COMPARE

MATCH IRQ

T/C0 CONTROL

CS02

COM01

PWM0

AS0

CS01

COM00

CS00

CTC0

ATmega103/103L

Figure 31. Timer/Counter2 Block Diagram

Note: Figure 31 shows the block diagram for Timer/Counter2.

The 8-bit Timer/Counter0 can select clock source from PCK0 or prescaled PCK0. The 8-bit Timer/Counter2 can select

clock source from CK, prescaled CK, or an external pin. Both Timer/Counters can be stopped as described in the specifica-

tion for the Timer/Counter Control Registers – TCCR0 and TCCR2.

The different status flags (overflow, compare match and capture event) are found in the Timer/Counter Interrupt Flag

enable/disable settings are found in the Timer/Counter Interrupt Mask Register (TIMSK).

When Timer/Counter2 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To

assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one

internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock.

The 8-bit Timer/Counters feature a high resolution and a high accuracy usage with the lower prescaling opportunities. Sim-

ilarly, the high prescaling opportunities make these units useful for lower speed functions or exact timing functions with

infrequent actions.

Both Timer/Counters support two Output Compare functions using the Output Compare Registers – OCR0 and OCR2 – as

the data source to be compared to the Timer/Counter contents. The Output Compare functions include optional clearing of

the counter on compare match, and action on the Output Compare Pins – PB4(OC0/PWM0) and PB7(OC2/PWM2) – on

compare match.

Timer/Counter0 and 2 can also be used as 8-bit Pulse Width Modulators. In this mode the Timer/Counter and the output

compare register serve as a glitch-free, stand-alone PWM with centered pulses. Refer to page 40 for a detailed description

on this function.

8-BIT DATA BUS

T/C2 CONTROL

TIMER INT. FLAG

TIMER/COUNTER2

(TCNT2)

8-BIT COMPARATOR

OUTPUT COMPARE

REGISTER2 (OCR2)

TIMER INT. MASK

T/C CLK SOURCE

UP/DOWN

T/C CLEAR

CONTROL

LOGIC

CS22

COM21

PWM2

OCF0

TOV0

TOV1

OCF2A

OCF2B

ICF1

TOV2

OCF2 OCF2

TOV2

OCIE0

TOIE0

TOIE1

OCIE1A

OCIE1B

TICIE1

TOIE2

OCIE2

CS21

COM20

CS20

CTC2

T/C2 OVER-

FLOW IRQ

T/C2 COMPARE

MATCH IRQ

ATmega103/103L

Timer/Counter0 Control Register – TCCR0

Timer/Counter2 Control Register – TCCR2

•Bit 7 - Res: Reserved Bit

This bit is a reserved bit in the ATmega103(L) and always reads as zero.

•Bit 6 - PWM0/PWM2: Pulse Width Modulator Enable

When set (one) this bit enables PWM mode for Timer/Counter0 or Timer/Counter2. This mode is described on page 40.

•Bits 5,4 - COM01, COM00/COM21, COM20: Compare Output Mode, Bits 1 and 0

The COMn1 and COMn0 control bits determine any output pin action following a compare match in Timer/Counter2.

Any output pin actions affect pins PB4(OC0/PWM0) or PB7(OC2/PWM2). Since this is an alternative function to an I/O

port, the corresponding direction control bit must be set (one) to control an output pin. The control configuration is shown in

Table 10.

Note: n = 0 or 2

In PWM mode, these bits have a different function. Refer to Table 13 for a detailed description.

•Bit 3 - CTC0/CTC2: Clear Timer/Counter on Compare Match

When the CTC0 or CTC2 control bit is set (one), the Timer/Counter is reset to $00 in the CPU clock cycle after a compare

match. If the control bit is cleared, the Timer continues counting and is unaffected by a compare match. Since the compare

match is detected in the CPU clock cycle following the match, this function will behave differently when a prescaling higher

than 1 is used for the timer. When a prescaling of 1 is used, and the compare register is set to C, the timer will count as fol-

lows if CTC0/2 is set:

... | C-2 | C-1 | C | 0 | 1 | ...

When the prescaler is set to divide by 8, the timer will count like this:

... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0, 0 | 1, 1, 1, ...

In PWM mode, this bit has no effect.

•Bits 2,1,0 - CS02, CS01, CS00/CS22, CS21, CS20: Clock Select Bits 2,1 and 0

The Clock Select2 bits 2,1 and 0 define the prescaling source of the Timer/Counter.

Bit 7 6 5 4 3 2 1 0

33 ($53) - PWM0 COM01 COM00 CTC0 CS02 CS01 CS00 TCCR0

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

$25 ($45) - PWM2 COM21 COM20 CTC2 CS22 CS21 CS20 TCCR2

Read/Write R R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

Table 10. Compare Mode Select

COMn1 COMn0 Description

0 0 Timer/Counter disconnected from output pin OCn/PWMn

0 1 Toggle the OCn/PWMn output line.

1 0 Clear the OCn/PWMn output line (to zero).

1 1 Set the OCn/PWMn output line (to one).

ATmega103/103L

The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK

CPU clock. If the external pin modes are used for Timer/Counter2, transitions on PD7/(T2) will clock the counter even if the

pin is configured as an output. This feature can give the user SW control of the counting.

Timer/Counter0 – TCNT0

Timer/Counter2 – TCNT2

These 8-bit registers contains the value of the Timer/Counters.

Both Timer/Counters are realized as up or up/down (in PWM mode) counters with read and write access. If the

Timer/Counter is written to and a clock source is selected, it continues counting in the timer clock cycle after it is preset with

the written value.

Table 11. Timer/Counter0 Prescale Select

CS02 CS01 CS00 Description

0 0 0 Timer/Counter0 is stopped.

001PCK0

010PCK0/8

011PCK0/32

100PCK0/64

1 0 1 PCK0/128

1 1 0 PCK0/256

1 1 1 PCK0/1024

Table 12. Timer/Counter2 Prescale Select

CS22 CS21 CS20 Description

0 0 0 Timer/Counter2 is stopped.

001CK

010CK/8

011CK/64

100CK/256

1 0 1 CK/1024

1 1 0 External Pin PD7(T2), falling edge

1 1 1 External Pin PD7(T2), rising edge

Bit 76543210

$32 ($42) MSB LSB TCNT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

$24 ($44) MSB LSB TCNT2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

ATmega103/103L

Timer/Counter0 Output Compare Register – OCR0

Timer/Counter2 Output Compare Register – OCR2

The output compare registers are 8-bit read/write registers.

The Timer/Counter Output Compare Registers contain the data to be continuously compared with the Timer/Counter.

Actions on compare matches are specified in TCCR0 and TCCR2. A compare match does only occur if the Timer/Counter

counts to the OCR value. A software write that sets the Timer/Counter and Output Compare Register to the same value

does not generate a compare match.

A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event.

Timer/Counter 0 and 2 in PWM Mode

When the PWM mode is selected, the Timer/Counter and the Output Compare Register – OCR0 or OCR2 form an 8-bit,

free-running, glitch-free and phase correct PWM with outputs on the PB4(OC0/PWM0) or PB7(OC2/PWM2) pin. The

Timer/Counter acts as an up/down counter, counting up from $00 to $FF, where it turns and counts down again to zero

before the cycle is repeated. When the counter value matches the contents of the Output Compare register, the

PB4(OC0/PWM0) or PB7(OC2/PWM2) pin is set or cleared according to the settings of the COM01/COM00 or

COM21/COM20 bits in the Timer/Counter Control Registers TCCR0 and TCCR2. Refer to Table 13 for details.

Note: n = 0 or 2

Note that in PWM mode, the Output Compare register is transferred to a temporary location when written. The value is

latched when the Timer/Counter reaches $FF. This prevents the occurrence of odd-length PWM pulses (glitches) in the

event of an unsynchronized OCR0 or OCR2 write. See Figure 32 for an example.

Bit 76543210

$31 ($51) MSB LSB OCR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

$23 ($43) MSB LSB OCR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Table 13. Compare Mode Select in PWM Mode

COMn1 COMn0 Effect on Compare/PWM Pin

0 0 Not connected

0 1 Not connected

Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted

PWM).

1 1 Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM).

ATmega103/103L

Figure 32. Effects on Unsynchronized OCR Latching

During the time between the write and the latch operation, a read from OCR0 or OCR2 will read the contents of the tempo-

rary location. This means that the most recently written value always will read out of OCR0/2

When the OCR register (not the temporary register) is updated to $00 or $FF, the PWM output changes to low or high

immediately according to the settings of COM21/COM20 or COM11/COM10. This is shown in Table 14.

Note: n = 0 or 2

In PWM mode, the Timer Overflow Flag, TOV0 or TOV2, is set when the counter advances from $00. Timer Overflow

Interrupt0 and 2 operates exactly as in normal Timer/Counter mode, i.e. it is executed when TOV0 or TOV2 is set provided

that Timer Overflow Interrupt and global interrupts are enabled. This does also apply to the Timer Output Compare flags

and interrupts.

The frequency of the PWM will be Timer Clock Frequency divided by 510.

Asynchronous Status Register – ASSR

•Bit 7..4 - Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always reads as zero.

•Bit 3 - AS0: Asynchronous Timer/Counter0

When set(one) Timer/Counter0 is clocked from the TOSC1 pin. When cleared (zero) Timer/Counter0 is clocked from the

internal system clock, CK. When the value of this bit is changed the contents of TCNT0 might get corrupted.

•Bit 2 - TCN0UB: Timer/Counter0 Update Busy

When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set (one). When TCNT0 has been

updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that

TCNT0 is ready to be updated with a new value.

Table 14. PWM Outputs OCRn = $00 or $FF

COMn1 COMn0 OCRn Output PWMn

1 0 $00 L

10$FF H

1 1 $00 H

11$FF L

Bit 76543 2 1 0

$30 ($50) - - - - AS0 TCN0UB OCR0UB TCR0UB ASSR

Read/Write R R R R R/W R R R

Initial value 0 0 0 0 0 0 0 0

Counter Value

Compare Valu

PWM Output

Synchronized OCR Latch

Counter Value

Compare Valu

PWM Output

Unsynchronized OCR Latch Glitch

Compare Value changes

ATmega103/103L

•Bit 1 - OCR0UB: Output Compare Register0 Update Busy

When Timer/Counter0 operates asynchronously and OCR0 is written, this bit becomes set (one). When OCR0 has been

updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that

OCR0 is ready to be updated with a new value.

•Bit 0 - TCR0UB: Timer/Counter Control Register0 Update Busy

When Timer/Counter0 operates asynchronously and TCCR0 is written, this bit becomes set (one). When TCCR0 has been

updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that

TCCR0 is ready to be updated with a new value.

If a write is performed to any of the three Timer/Counter0 registers while its update busy flag is set (one), the updated value

might get corrupted and cause an unintentional interrupt to occur.

When reading TCNT0, OCR0 and TCCR0, there is a difference in result. When reading TCNT0, the actual timer value is

read. When reading OCR0 or TCCR0, the value in the temporary storage register is read.

Asynchronous Operation of Timer/Counter0

When Timer/Counter0 operates synchronously, all operations and timing are identical to Timer/Counter2. During asynchro-

nous operation, however, some considerations must be taken.

•WARNING: When switching between asynchronous and synchronous clocking of Timer/Counter0, the timer registers,

TCNT0, OCR0 and TCCR0 might get corrupted. Safe procedure for switching clock source:

1. Disable the timer 0 interrupts OCIE0 and TOIE0.

2. Select clock source by setting ASO as appropriate.

3. Write new values to TCNT0, OCR0 and TCCR0.

4. If switching to asynchronous operation: Wait for TCNT0UB, OCR0UB and TCR0UB to be cleared.

5. Enable interrupts if needed.

•The oscillator is optimized for use with a 32,768 Hz watch crystal. An external clock signal applied to this pin goes

through the same amplifier having a bandwidth of 256 kHz. The external clock signal should therefore be in the interval

0 Hz - 256 kHz. The frequency of the clock signal applied to the TOSC1 pin must be lower than one fourth of the CPU

main clock frequency. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is

enabled.

•When writing to one of the registers TCNT0, OCR0, or TCCR0, the value is transferred to a temporary register, and

latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary

register, which means that e.g. writing to TCNT0 does not disturb an OCR0 write in progress. To detect that a transfer to

the destination register has taken place, a Asynchronous Status Register – ASSR has been implemented.

•When entering Power Save mode after having written to TCNT0, OCR0 or TCCR0, the user must wait until the written

the changes have had any effect. This is extremely important if the output compare0 interrupt is used to wake up the

device; Output compare is disabled during write to OCR0 or TCNT0. If the write cycle is not finished (i.e. the user goes to

sleep before the OCR0UB bit returns to zero), the device will never get a compare match and the MCU will not wake up.

•If Timer/Counter0 is used to wake up the device from Power Save mode, precautions must be taken if the user wants to

re-enter Power Save mode; The interrupt logic needs one TOSC1 cycle to get reset. If the time between wake up and re-

entering Power Save mode is less than one TOSC1 cycle, the interrupt will not occur and the device will fail to wake up. If

the user is in doubt whether the time before re-entering Power Save is sufficient, the following algorithm can be used to

ensure that one TOSC1 cycle has elapsed:

1. Write a value to TCCR0, TCNT0 or OCR0

2. Wait until the corresponding Update Busy flag in ASSR returns to zero.

3. Enter Power Save mode

ATmega103/103L

•When asynchronous operation is selected, the 32 kHz oscillator for Timer/Counter0 is always running, except in power-

down mode. After a power up reset or wake-up from power-down, the user should be aware of the fact that this oscillator

might take as long as one second to stabilize. The user is advised to wait for at least one second before using

Timer/Counter0 after power-up or wake-up from power-down. The content of all Timer/Counter0 registers must be

considered lost after a wake-up from power-down due to the unstable clock signal upon start-up, no matter whether the

oscillator is in use or a clock signal is applied to the TOSC pin.

•Description of wake-up from power save mode when the timer is clocked asynchronously: When the interrupt condition is

met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at

least one before the processor can read the counter value. To execute the corresponding Timer/Counter0 interrupt

routine, the global interrupt bit in SREG must have been set. Otherwise, the part will still wake up from power-down, but

continues to execute the sleep command. The interrupt flags are updated 3 processor cycles after the processor clock

has started. During these cycles, the processor executes instructions, but the interrupt condition is not readable, and the

interrupt routine has not started yet.

•During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes three

processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the

timer value causing the setting of the interrupt flag. The output compare pin is changed on the timer clock, and is not

synchronized to the processor clock.

16-bit Timer/Counter1

Figure 33 shows the block diagram for Timer/Counter1.

The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped

as described in the specification for the Timer/Counter1 Control Register (TCCR1B). The different status flags (overflow,

compare match and capture event) are found in the Timer/Counter Interrupt Flag Register (TIFR). Control signals are found

in the Timer/Counter1 Control Registers – TCCR1A and TCCR1B. The interrupt enable/disable settings for Timer/Counter1

are found in the Timer/Counter Interrupt Mask Register (TIMSK).

When Timer/Counter1 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To

assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one

internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock.

The 16-bit Timer/Counter1 features both a high resolution and a high accuracy usage with the lower prescaling opportuni-

ties. Similarly, the high prescaling opportunities makes the Timer/Counter1 useful for lower speed functions or exact timing

functions with infrequent actions.

The Timer/Counter1 supports two Output Compare functions using the Output Compare Register 1 A and B – OCR1A and

OCR1B – as the data sources to be compared to the Timer/Counter1 contents. The Output Compare functions include

optional clearing of the counter on compareA match, and actions on the Output Compare pins on both compare matches.

ATmega103/103L

Figure 33. Timer/Counter1 Block Diagram

Timer/Counter1 can also be used as a 8-, 9- or 10-bit Pulse Width Modulator. In this mode the counter and the

OCR1A/OCR1B registers serve as a dual glitch-free stand-alone PWM with centered pulses. Refer to page 49 for a

detailed description on this function.

The Input Capture function of Timer/Counter1 provides a capture of the Timer/Counter1 contents to the Input Capture

are defined by the Timer/Counter1 Control Register (TCCR1B). In addition, the Analog Comparator can be set to trigger

the Input Capture. Refer to “Analog Comparator” on page 65 for details on this. The ICP pin logic is shown in Figure 34.

Figure 34. ICP Pin Schematic Diagram

8-BIT DATA BUS

T/C1 CONTROL

T/C1 INPUT CAPTURE REGISTER (ICR1)

16-BIT COMPARATOR 16-BIT COMPARATOR

TIMER/COUNTER1 OUTPUT COMPARE REGISTER A TIMER/COUNTER1 OUTPUT COMPARE REGISTER B

TIMER/COUNTER1 (TCNT1)

TIMER INT. FLAG

15 15

CONTROL

LOGIC

COM1A1

COM1B1

CS12

TOV1

OCF0

TOV0

OCF1A

OCF1B

ICF1

COM1A0

COM1B0

CS11

CTC1

PWM11

PWM10

ICES1

ICNC1

CS10

T/C1 COMPARE

MATCHA IRQ

T/C1 COMPARE

MATCHB IRQ

T/C1 INPUT

CAPTURE IRQ

T/C1 OVER-

FLOW IRQ

CAPTURE

TRIGGER

T/C CLOCK SOURCE

T/C CLEAR

UP/DOWN

TIMER INT. MASK

OCIE0

TOIE0

TOIE1

OCIE1A

OCIE1B

TICIE1

TOIE2

TOV2

OCIE2

OCF2

ATmega103/103L

If the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over four samples,

and all four must be equal to activate the capture flag.

Timer/Counter1 Control Register A – TCCR1A

•Bits 7..6 - COM1A1, COM1A0: Compare Output Mode1A, Bits 1 and 0

The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1.

Any output pin actions affect pin OC1A – Output CompareA pin 1. This is an alternative function to an I/O port, and the cor-

responding direction control bit must be set (one) to control an output pin. The control configuration is shown in Table 15.

•Bits 5..4 - COM1B1, COM1B0: Compare Output Mode1B, Bits 1 and 0

The COM1B1 and COM1B0 control bits determine any output pin action following a compare match in Timer/Counter1.

Any output pin actions affect pin OC1B – Output CompareB. Since this is an alternative function to an I/O port, the corre-

sponding direction control bit must be set (one) to control an output pin. The following control configuration is given:

Note: X = A or B.

In PWM mode, these bits have a different function. Refer to Table 16 for a detailed description.

•Bits 3..2 - Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always read as zero.

•Bits 1..0 - PWM11, PWM10: Pulse Width Modulator Select Bits

These bits select PWM operation of Timer/Counter1 as specified in Table 18 on page 49. This mode is described on

page 49.

Bit 7 6 5 4 3 2 1 0

$2F ($4F) COM1A1 COM1A0 COM1B1 COM1B0 - - PWM11 PWM10 TCCR1A

Read/Write R/W R/W R/W R/W R R R/W R/W

Initial value 0 0 0 0 0 0 0 0

Table 15. Compare1 Mode Select

COM1X1 COM1X0 Description

0 0 Timer/Counter1 disconnected from output pin OC1X

0 1 Toggle the OC1X output line.

1 0 Clear the OC1X output line (to zero).

1 1 Set the OC1X output line (to one).

Table 16. PWM Mode Select

PWM11 PWM10 Description

0 0 PWM operation of Timer/Counter1 is disabled.

0 1 Timer/Counter1 is an 8-bit PWM

1 0 Timer/Counter1 is a 9-bit PWM

1 1 Timer/Counter1 is a 10-bit PWM

ATmega103/103L

Timer/Counter1 Control Register B – TCCR1B

•Bit 7 - ICNC1: Input Capture1 Noise Canceler (4 CKs)

When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is trig-

gered at the first rising/falling edge sampled on the input capture pin PD4(IC1) as specified. When the ICNC1 bit is set

(one), four successive samples are measures on PD4(IC1), and all samples must be high/low according to the input cap-

ture trigger specification in the ICES1 bit. The actual sampling frequency is XTAL clock frequency.

•Bit 6 - ICES1: Input Capture1 Edge Select

While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register (ICR1) on

the falling edge of the input capture pin – PD4(IC1). While the ICES1 bit is set (one), the Timer/Counter1 contents are

transferred to the Input Capture Register on the rising edge of the input capture pin – PD4(IC1).

•Bits 5, 4 - Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always read zero.

•Bit 3 - CTC1: Clear Timer/Counter1 on Compare Match

When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If

the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. Since the com-

pare match is detected in the CPU clock cycle following the match, this function will behave differently when a prescaling

higher than 1 is used for the timer. When a prescaling of 1 is used, and the compareA register is set to C, the timer will

count as follows if CTC1 is set:

... | C-2 | C-1 | C | 0 | 1 | ...

When the prescaler is set to divide by 8, the timer will count like this:

... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0, 0 | ...

In PWM mode, this bit has no effect.

•Bits 2,1,0 - CS12, CS11, CS10: Clock Select1, Bit 2,1 and 0

The lock Select1 bits 2,1 and 0 define the prescaling source of Timer/Counter1.

The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK

CPU clock. If the external pin modes are used for Timer/Counter1, transitions on PD6/(T1) will clock the counter even if the

pin is configured as an output. This feature can give the user SW control of the counting.

Bit 7 6 5 4 3 2 1 0

$2E ($4E) ICNC1 ICES1 - - CTC1 CS12 CS11 CS10 TCCR1B

Read/Write R/W R/W R R R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

Table 17. Clock1 Prescale Select

CS12 CS11 CS10 Description

0 0 0 Stop, the Timer/Counter1 is stopped.

001CK

010CK/8

011CK/64

100CK/256

101CK/1024

1 1 0 External Pin T1, falling edge

1 1 1 External Pin T1, rising edge

ATmega103/103L

Timer/Counter1 – TCNT1H and TCNT1L

This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes

are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit tem-

porary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B and ICR1. If the main

program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access

from the main program (and from interrupt routines if interrupts are allowed from within interrupt routines).

•TCNT1 Timer/Counter1 Write:

When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP register. Next, when the CPU

writes the low byte TCNT1L, this byte of data is combined with the byte data in the TEMP register, and all 16 bits are

written to the TCNT1 Timer/Counter1 register simultaneously. Consequently, the high byte TCNT1H must be accessed

first for a full 16-bit register write operation. When using Timer/Counter1 as an 8-bit timer, it is sufficient to write the low

byte only.

•TCNT1 Timer/Counter1 Read:

When the CPU reads the low byte TCNT1L, the data of TCNT1L is sent to the CPU and the data of the high byte

TCNT1H is placed in the TEMP register. When the CPU reads the data in the high byte TCNT1H, the CPU receives the

data in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for a full 16-bit register read

operation. When using Timer/Counter1 as an 8-bit timer, it is sufficient to read the low byte only.

The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1

is written to and a clock source is selected, the Timer/Counter1 continues counting in the clock cycle after it is preset with

the written value.

Bit 151413121110 9 8

$2D ($4D) MSB TCNT1H

$2C ($4C) LSB TCNT1L

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

00000000

ATmega103/103L

Timer/Counter1 Output Compare Register – OCR1AH and OCR1AL

Timer/Counter1 Output Compare Register – OCR1BH and OCR1BL

The output compare registers are 16-bit read/write registers.

The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1.

Actions on compare matches are specified in the Timer/Counter1 Control and Status register. A compare match does only

occur if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same

value does not generate a compare match.

A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event.

Since the Output Compare Registers – OCR1A and OCR1B – are 16-bit registers, a temporary register TEMP is used

when OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte,

OCR1AH or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or

OCR1BL, the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or

OCR1BH must be written first for a full 16-bit register write operation.

The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform

access to registers using TEMP, interrupts must be disabled during access from the main program.

Timer/Counter1 Input Capture Register – ICR1H and ICR1L

The input capture register is a 16-bit read-only register.

When the rising or falling edge (according to the input capture edge setting (ICES1)) of the signal at the input capture pin –

PD4(IC1) – is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register (ICR1). At the

same time, the input capture flag (ICF1) is set (one).

Bit 151413121110 9 8

$2B MSB OCR1AH

$2A LSB OCR1AL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

00000000

Bit 151413121110 9 8

$29 MSB OCR1BH

$28 LSB OCR1BL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

00000000

Bit 151413121110 9 8

$27 ($37) MSB ICR1H

$26 ($36) LSB ICR1L

76543210

Read/WriteRRRRRRRR

RRRRRRRR

Initial value00000000

00000000

ATmega103/103L

Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register TEMP is used when ICR1 is read to

ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and

the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the

CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit reg-

ister read operation.

The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and also interrupt

routines perform access to registers using TEMP, interrupts must be disabled during access from the main program.

Timer/Counter1 in PWM Mode

When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1A (OCR1A) and the Output Compare

Register1B (OCR1B), form a dual 8-, 9- or 10-bit, free-running, glitch-free and phase correct PWM with outputs on the

PB5(OC1A) and PB6(OC1B) pins. Timer/Counter1 acts as an up/down counter, counting up from $0000 to TOP (see Table

16), where it turns and counts down again to zero before the cycle is repeated. When the counter value matches the con-

tents of the 10 least significant bits of OCR1A or OCR1B, the PB5(OC1A)/PB6(OC1B) pins are set or cleared according to

the settings of the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register TCCR1A. Refer to

Table 19 for details.

Note: X = A or B

Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written, are transferred to a temporary loca-

tion. They are latched when Timer/Counter1 reaches the value TOP. This prevents the occurrence of odd-length PWM

pulses (glitches) in the event of an unsynchronized OCR1A/OCR1B write. See Figure 35 for an example.

Table 18. Timer TOP Values and PWM Frequency

PWM Resolution Timer TOP value Frequency

8-bit $00FF (255) fTCK1/510

9-bit $01FF (511) fTCK1/1022

10-bit $03FF (1023) fTCK1/2046

Table 19. Compare1 Mode Select in PWM Mode

COM1X1 COM1X0 Effect on OCX1

0 0 Not connected

0 1 Not connected

1 0 Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM).

1 1 Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM).

ATmega103/103L

Figure 35. Effects on Unsynchronized OCR1 Latching

During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the

temporary location. This means that the most recently written value always will read out of OCR1A/B.

When the OCR1A/OCR1B contains $0000 or TOP, the output OC1A/OC1B is updated to low or high on the next compare

match according to the settings of COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 20.

Note: If the compare register contains the TOP value and the prescaler is not in use (CS12..CS10 = 001), the PWM output will not

produce any pulse at all, because the up-counting and down-counting value is reached simultaneously. When the prescaler is in

use (CS12..CS10 ≠001 or 000), the PWM output goes active when the counter reaches the TOP value, but the down-counting

compare match is not interpreted to be reached before the next time the counter reaches the TOP value, making a one-period

PWM pulse.

Note: X = A or B

In PWM mode, the Timer Overflow Flag1, TOV1, is set when the counter advances from $0000. Timer Overflow Interrupt1

operates exactly as in normal Timer/Counter mode, i.e. it is executed when TOV1 is set provided that Timer Overflow

Interrupt1 and global interrupts are enabled. This does also apply to the Timer Output Compare1 flags and interrupts.

Table 20. PWM Outputs OCR1X = $0000 or TOP

COM1X1 COM1X0 OCR1X Output OC1X

1 0 $0000 L

10TOP H

1 1 $0000 H

11TOP L

Counter Value

Compare V

alue

PWM Output OC1X

Synchronized OCR1X Latch

Counter Value

Compare Value

PWM Output OC1X

Unsynchronized OCR1X Latch Glitch

Compare Value changes

Note: X = A or B

Compare Value changes

ATmega103/103L

Watchdog Timer

The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the Watchdog Timer prescaler, the

Watchdog reset interval can be adjusted as shown in Table 21. See characterization data for typical values at other VCC

levels. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. From the Watchdog is reset, eight different

clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog

reset, the ATmega103(L) resets and executes from the reset vector. For timing details on the Watchdog reset, refer to

page 28.

To prevent unintentional disabling of the watchdog, a special turn-off procedure must be followed when the watchdog is

disabled. Refer to the description of the Watchdog Timer Control Register for details.

Figure 36. Watchdog Timer

Watchdog Timer Control Register – WDTCR

•Bits 7..5 - Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and will always read as zero.

•Bit 4 - WDTOE: Watchdog Turn Off Enable

This bit must be set (one) when the WDE bit is cleared, Otherwise, the watchdog will not be disabled. Once set, hardware

will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a watchdog disable procedure.

•Bit 3 - WDE: Watchdog Enable

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function

is disabled. WDE can only be cleared if the WDTOE bit is set (one). To disable an enabled watchdog timer, the following

procedure must be followed:

1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be written to WDE even though

it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog.

•Bits 2..0 - WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0

The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The

different prescaling values and their corresponding Time-out Periods are shown in Table 21.

Bit 765 43210

$21 ($41) - - - WDTOE WDE WDP2 WDP1 WDP0 WDTCR

Read/Write R R R R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

1 MHz at V

= 5V

350 kHz at V

= 3V

Oscillator

ATmega103/103L

Note: The frequency of the watchdog oscillator is voltage dependent as shown in the Electrical Characteristics section.

The WDR – Watchdog Reset – instruction should always be executed before the Watchdog Timer is enabled. This ensures that

the reset period will be in accordance with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without

reset, the watchdog timer may not start counting from zero.

EEPROM Read/Write Access

The EEPROM access registers are accessible in the I/O space.

The write access time is in the range of 2.5 - 4ms, depending on the VCC voltages. A self-timing function lets the user soft-

ware detect when the next byte can be written. A special EEPROM Ready interrupt can be set to trigger when the

EEPROM is ready to accept new data.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of

the EEPROM control register for details on this.

When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When it is

read, the CPU is halted for 4 clock cycles.

EEPROM Address Register – EEARH, EEARL

The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the 4K-byte EEPROM space.

The EEPROM data bytes are addressed linearly between 0 and 4095.

Table 21. Watchdog Timer Prescale Select

WDP2 WDP1 WDP0

Number of WDT Oscillator

Cycles

Typical Time-out

at Vcc = 3.0V

Typical Time-out

at Vcc = 5.0V

0 0 0 16K cycles 47 ms 15 ms

0 0 1 32K cycles 94 ms 30 ms

0 1 0 64K cycles 0.19 s 60 ms

0 1 1 128K cycles 0.38 s 0.12 s

1 0 0 256K cycles 0.75 s 0,24 s

1 0 1 512K cycles 1.5 s 0.49 s

1 1 0 1,024K cycles 3.0 s 0.97 s

1 1 1 2,048K cycles 6.0 s 1.9 s

Bit 15141312 11 10 9 8

$1F ($3F) - - - - EEAR11 EEAR10 EEAR9 EEAR8 EEARH

$1E ($3E) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

7654 3 2 10

Read/Write R R R R R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

0000 0 0 00

ATmega103/103L

EEPROM Data Register – EEDR

•Bits 7..0 - EEDR7..0: EEPROM Data:

For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given

by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the

address given by EEAR.

EEPROM Control Register – EECR

•Bits 7..4 - Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and will always be read as zero.

•Bit 3 - EERIE: EEPROM Ready Interrupt Enable

When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the inter-

rupt is disabled. The EEPROM Ready interrupt constantly generates an interrupt request when EEWE is cleared (zero).

•Bit 2 - EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one)

setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect.

When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description

of the EEWE bit for a EEPROM write procedure.

•Bit 1 - EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up,

the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written

to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the

EEPROM (the order of steps 2 and 3 is unessential):

1. Wait until EEWE becomes zero.

2. Write new EEPROM address to EEAR (optional).

3. Write new EEPROM data to EEDR (optional).

4. Write a logical one to the EEMWE bit in EECR.

5. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will

time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR and EEDR reg-

ister will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag

cleared during the four last steps to avoid these problems.

When the write access time (typically 2.5 ms at VCC = 5V or 4 ms at VCC = 2.7V) has elapsed, the EEWE bit is cleared

(zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has

been set, the CPU is halted for two cycles before the next instruction is executed.

•Bit 0 - EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the

EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the

EEDR register. The EEPROM read access takes one instruction there is no need to poll the EERE bit. When EERE has

been set, the CPU is halted for four cycles before the next instruction is executed.

Bit 76543210

$1D ($3D) MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543 2 10

$1C ($3C) - - - - EERIE EEMWE EEWE EERE EECR

Read/Write R R R R R/W R/W R/W R/W

Initial value 0 0 0 0 0 0 0 0

ATmega103/103L

The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or

address is written to the EEPROM I/O registers, the write operation will be interrupted, and the result is undefined.

Prevent EEPROM Corruption

During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the

EEPROM to operate properly. These issues are the same as for board level systems using the EEPROM, and the same

design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence

to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incor-

rectly, if the supply voltage for executing instructions is too low.

EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This is best done by an

external low VCC Reset Protection circuit, often referred to as a Brown-out Detector (BOD). Please refer to

”Application Note AVR 180” for design considerations regarding power-on reset and low voltage detection.

2. Keep the AVR core in Power-down Sleep Mode during periods of low VCC. This will prevent the CPU from attempting

to decode and execute instructions, effectively protecting the EEPROM registers from unintentional writes.

3. Store constants in Flash memory if the ability to change memory contents from software is not required. Flash

memory can not be updated by the CPU, and will not be subject to corruption.

Serial Peripheral Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega103(L) and periph-

eral devices or between several AVR devices. The ATmega103(L) SPI features include the following:

•Full-duplex, 3-wire Synchronous Data Transfer

•Master or Slave Operation

•LSB First or MSB First Data Transfer

•Four Programmable Bit Rates

•End of Transmission Interrupt Flag

•Write Collision Flag Protection

•Wake-up from Idle Mode (Slave Mode Only)

ATmega103/103L

Figure 37. SPI Block Diagram

The interconnection between master and slave CPUs with SPI is shown in Figure 38. The PB1(SCK) pin is the clock output

in the master mode and is the clock input in the slave mode. Writing to the SPI data register of the master CPU starts the

SPI clock generator, and the data written shifts out of the PB2(MOSI) pin and into the PB2 (MOSI) pin of the slave CPU.

After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI interrupt enable

bit (SPIE) in the SPCR register is set, an interrupt is requested. The Slave Select input, PB0(SS), is set low to select an

individual slave SPI device. The two shift registers in the Master and the Slave can be considered as one distributed 16-bit

circular shift register. This is shown in Figure 38. When data is shifted from the master to the slave, data is also shifted in

the opposite direction, simultaneously. This means that during one shift cycle, data in the master and the slave are

interchanged.

ATmega103/103L

Figure 38. SPI Master-slave Interconnection

The system is single buffered in the transmit direction and double buffered in the receive direction. This means that charac-

ters to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving

data, however, a received byte must be read from the SPI Data Register before the next byte has been completely shifted

in. Otherwise, the first byte is lost.

When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins is overridden according to the following

table:

Note: See “Alternate Functions of Port B” on page 78 for a detailed description and how to define the direction of the user defined SPI

pins.

SS Pin Functionality

When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is

configured as an output, the pin is a general output pin which does not affect the SPI system. If SS is configured as an

input, it must be hold high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is

configured as master with the SS pin defined as an input, the SPI system interprets this as another master selecting the

SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the SPI becoming a slave, the

MOSI and SCK pins become inputs.

2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled and the I-bit in SREG is set, the interrupt routine will

be executed.

Thus, when interrupt-driven SPI transmittal is used in master mode, and there exists a possibility that SS is driven low, the

interrupt should always check that the MSTR bit is still set. Once the MSTR bit has been cleared by a slave select, it must

be set by the user to re-enable SPI master mode.

When the SPI is configured as a slave, the SS pin is always input. When SS is held low, the SPI is activated and MISO

becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and

the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin

is brought high. If the SS pin is brought high during a transmission, the SPI will stop sending and receiving immediately and

both data received and data sent must be considered as lost.

Table 22. SPI Pin Overrides

PIN Direction, Master SPI Direction, Slave SPI

MOSI User Defined Input

MISO Input User Defined

SCK User Defined Input

SS User Defined Input

MASTER

MISO

SPI

CLOCK GENERATOR

SLAVE

MISO

MOSI MOSI

SCK SCK

SS SS

VCC

MSB LSB MSB LSB

8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER

ATmega103/103L

Data Modes

There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits

CPHA and CPOL. The SPI data transfer formats are shown in Figure 39 and Figure 40.

Figure 39. SPI Transfer Format with CPHA = 0 and DORD = 0

Figure 40. SPI Transfer Format with CPHA = 1 and DORD = 0

SPI Control Register – SPCR

•Bit 7 - SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled.

•Bit 6 - SPE: SPI Enable

When the SPE bit is set (one), the SPI is enabled and SS, MOSI, MISO and SCK are connected to pins PB0, PB1, PB2 and

PB3.

•Bit 5 - DORD: Data Order

When the DORD bit is set (one), the LSB of the data word is transmitted first.

When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.

Bit 76543210

$0D ($2D) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

MSB 6 5 4 3 2 1 LSB

1 2 3 4 5 6 7 8

MSB

6 5 4 3 2 1 LSB

SCK CYCLE #

(FOR REFERENCE)

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

(FROM MASTER)

MISO

(FROM SLAVE)

SS (TO SLAVE)

* Not defined but normally MSB of character just received.

SAMPLE

SCK CYCLE #

(FOR REFERENCE)

SCK (CPOL=0)

SCK (CPOL=1)

MOSI

(FROM MASTER)

MISO

(FROM SLAVE)

SS (TO SLAVE)

* Not defined but normally LSB of previously-transmitted character.

MSB LSB

LSBMSB

SAMPLE

ATmega103/103L

•Bit 4 - MSTR: Master/Slave Select

This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input

and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to

set MSTR to re-enable SPI master mode.

•Bit 3 - CPOL: Clock Polarity

When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 39

and Figure 40 for additional information.

•Bit 2 - CPHA: Clock Phase

Refer to Figure 39 or Figure 40 for the functionality of this bit.

•Bits 1,0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The

relationship between SCK and the CPU Clock frequency fcl is shown in the following table:

Note: Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled.

SPI Status Register – SPSR

•Bit 7 - SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and

global interrupts are enabled. SPIF is cleared by hardware when executing the corresponding interrupt handling vector.

Alternatively, the SPIF bit is cleared by first reading the SPI status register with SPIF set (one), then accessing the SPI

Data Register (SPDR).

•Bit 6 - WCOL: Write Collision Flag

The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are

cleared (zero) by first reading the SPI Status Register with WCOL set (one), and then accessing the SPI Data Register.

•Bit 5..0 - Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and will always read as zero.

SPI Data Register – SPDR

The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register.

Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.

Table 23. Relationship between SCK and the Oscillator Frequency

SPR1 SPR0 SCK Frequency

fcl/4

fcl/16

fcl/64

fcl/128

Bit 76543210

$0E SPIF WCOL - - - - - - SPSR

Read/WriteRRRRRRRR

Initial value00000000

Bit 76543210

$0F ($2F) MSB LSB SPDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value XXXXXXXXUndefined

ATmega103/103L

UART

The ATmega103(L) features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and

Transmitter (UART). The main features are:

•Baud rate generator that can generate a large number of baud rates (bps)

•High baud rates at low XTAL frequencies

•8 or 9 bits data

•Noise filtering

•Overrun detection

•Framing Error detection

•False Start Bit detection

•Three separate interrupts on TX Complete, TX Data Register Empty and RX Complete

Data Transmission

A block schematic of the UART transmitter is shown in Figure 41.

Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register, UDR. Data is transferred

from UDR to the Transmit Shift register when:

•A new character has been written to UDR after the stop bit from the previous character has been shifted out. The shift

•A new character has been written to UDR before the stop bit from the previous character has been shifted out. The shift

If the 10(11)-bit Transmit Shift register is empty, data is transferred from UDR to the shift register. At this time the UDRE

(UART Data Register Empty) bit in the UART Status Register, USR, is set. When this bit is set (one), the UART is ready to

receive the next character. Writing to UDR clears UDRE. At the same time as the data is transferred from UDR to the

10(11)-bit shift register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word is

selected (the CHR9 bit in the UART Control Register, UCR is set), the TXB8 bit in UCR is transferred to bit 9 in the

Transmit Shift register.

ATmega103/103L

Figure 41. UART Transmitter

On the Baud Rate clock following the transfer operation to the shift register, the start bit is shifted out on the TXD pin, fol-

lowed by the data, LSB first. When the stop bit has been shifted out, the shift register is loaded if any new data has been

written to the UDR during the transmission. During loading, UDRE is set. If there is no new data in the UDR register to send

when the stop bit is shifted out, the UDRE flag will remain set. In this case, after the stop bit has been present on TXD for

one bit length, the TX Complete Flag, TXC, in USR is set.

The TXEN bit in UCR enables the UART transmitter when set (one). When this bit is cleared (zero), the PE1 pin can be

used for general I/O. When TXEN is set, the UART Transmitter will be connected to PE1, which is forced to be an output

pin regardless of the setting of the DDE1 bit in DDRE.

DATA BUS

UART I/O DATA

10(11)-BIT TX

SHIFT REGISTER

UART CONTROL

CONTROL LOGIC

UART STATUS

BAUD RATE

GENERATOR

XTAL

TXB8

RXB8

TXEN

CHR9

RXEN

TXC

TXCIE

RXCIE

UDRIE

UDRE

RXC

UDRE

/16

UDRE

IRQ

TXC

IRQ

SHIFT ENABLE

STORE UDR

IDLE

BAUD

BAUD x 16

PIN CONTROL

LOGIC

TXD

ATmega103/103L

Data Reception

Figure 42. UART Receiver

The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle,

one single sample of logical zero will be interpreted as the falling edge of a start bit, and the start bit detection sequence is

initiated. Let sample 1 denote the first zero-sample. Following the 1-to-0 transition, the receiver samples the RXD pin at

sample 8, 9, and 10. If two or more of these three samples are found to be logical ones, the start bit is rejected as a noise

spike and the receiver starts looking for the next 1-to-0 transition.

If however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also

sampled at samples 8, 9, and 10. The logical value found in at least two of the three samples is taken as the bit value.

All bits are shifted into the transmitter shift register as they are sampled. Sampling of an incoming character is shown in

Figure 43.

Figure 43. Sampling Received Data

DATA BUS

UART I/O DATA

10(11)-BIT RX

SHIFT REGISTER

UART CONTROL

DATA RECOVERY

LOGIC

UART STATUS

BAUD RATE

GENERATOR

XTAL

RXB8

TXB8

TXEN

CHR9

RXEN

TXC

TXCIE

RXCIE

UDRIE

UDRE

RXC

DOR

RXC

IRQ

/16

BAUD X 16 BAUD

STORE UDR

PIN CONTROL

LOGIC

RXD

START BIT D0 D1 D2 D3 D4 D5 D6 D7 STOP BIT

RXD

RECEIVER

SAMPLING

ATmega103/103L

When the stop bit enters the receiver, the majority of the three samples must be one to accept the stop bit. If two or more

samples are logical zeros, the Framing Error (FE) flag in the UART Status Register (USR) is set when the received byte is

transferred to UDR. Before reading the UDR register, the user should always check the FE bit to detect Framing Errors. FE

is cleared when UDR is read.

Whether or not a valid stop bit is detected at the end of a character reception cycle, the data is transferred to UDR and the

RXC flag in USR is set. UDR is in fact two physically separate registers, one for transmitted data and one for received data.

When UDR is read, the Receive Data register is accessed, and when UDR is written, the Transmit Data register is

accessed. If 9-bit data word is selected (the CHR9 bit in the UART Control Register, UCR is set), the RXB8 bit in UCR is

loaded with bit 9 in the Transmit Shift register when data is transferred to UDR.

If, after having received a character, the UDR register has not been accessed since the last receive, the OverRun (OR) flag

in USR is set. This means that the new data transferred to the shift register could not be transferred to UDR and is lost. The

OR bit is buffered, and is available when the valid data byte in UDR has been read. The user should always check the OR

after reading from the UDR register in order to detect any overruns if the baud rate is high or CPU load is high.

When the RXEN bit in the UCR register is cleared (zero), the receiver is disabled. This means that the PE0 pin can be used

as a general I/O pin. When RXEN is set, the UART Receiver will be connected to PE0, which is forced to be an input pin

regardless of the setting of the DDE0 bit in DDRE. When PE0 is forced to input by the UART, the PORTE0 bit can still be

used to control the pull-up resistor on the pin.

When the CHR9 bit in the UCR register is set, transmitted and received characters are 9 bits long plus start and stop bits.

The 9th data bit to be transmitted is the TXB8 bit in UCR register. This bit must be set to the wanted value before a trans-

mission is initated by writing to the UDR register.

UART Control

UART I/O Data Register – UDR

The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register,

the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read.

UART Status Register – USR

The USR register is a read-only register providing information on the UART Status.

•Bit 7 - RXC: UART Receive Complete

This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set regard-

less of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be

executed when RXC is set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART

Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the

interrupt routine terminates.

•Bit 6 - TXC: UART Transmit Complete

This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and

no new data has been written to the UDR. This flag is especially useful in half-duplex communications interfaces, where a

transmitting application must enter receive mode and free the communications bus immediately after completing the

transmission.

Bit 76543210

$0C ($2C) MSB LSB UDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

$0B ($2B) RXC TXC UDRE FE OR –––USR

Read/Write R R/W R R R R R R

Initial value00100000

ATmega103/103L

When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is

cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared

(zero) by writing a logical one to the bit.

•Bit 5 - UDRE: UART Data Register Empty

This bit is set (one) when a character written to UDR is transferred to the Transmit Shift register. Setting of this bit indicates

that the transmitter is ready to receive a new character for transmission.

When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set. UDRE is

cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine

must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates.

UDRE is set (one) during reset to indicate that the transmitter is ready.

•Bit 4 - FE: Framing Error

This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero.

The FE bit is cleared when the stop bit of received data is one.

•Bit 3 - OR: OverRun

This bit is set if an overrun condition is detected, i.e. when a character already present in the UDR register is not read

before the next character is transferred from the Receiver Shift register. The OR bit is buffered, which means that it is will

be set once the valid data still in UDRE is read.

The OR bit is cleared (zero) when data is received and transferred to UDR.

•Bits 2..0 - Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and will always read as zero.

UART Control Register – UCR

•Bit 7 - RXCIE: RX Complete Interrupt Enable

When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete interrupt routine to be executed

provided that global interrupts are enabled.

•Bit 6 - TXCIE: TX Complete Interrupt Enable

When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete interrupt routine to be executed

provided that global interrupts are enabled.

•Bit 5 - UDRIE: UART Data Register Empty Interrupt Enable

When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty interrupt routine to be

executed provided that global interrupts are enabled.

•Bit 4 - RXEN: Receiver Enable

This bit enables the UART receiver when set (one). When the receiver is disabled, the TXC, OR and FE status flags cannot

become set. If these flags are set, turning off RXEN does not cause them to be cleared.

•Bit 3 - TXEN: Transmitter Enable

This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the

transmitter is not disabled before the character in the shift register plus any following character in UDR has been com-

pletely transmitted.

•Bit 2 - CHR9: 9-bit Characters

When this bit is set (one) transmitted and received characters are 9 bits long plus start and stop bits. The 9th bit is read and

written by using the RXB8 and TXB8 bits in UCR, respectively. The 9th data bit can be used as an extra stop bit or a parity

bit.

•Bit 1 - RXB8: Receive Data Bit 8

When CHR9 is set (one), RXB8 is the 9th data bit of the received character.

Bit 76543210

$0A ($2A) RXCIE TXCIE UDRIE RXEN TXEN CHR9 RXB8 TXB8 UCR

Read/Write R/W R/W R/W R/W R/W R/W R W

Initial value00000010

ATmega103/103L

•Bit 0 - TXB8: Transmit Data Bit 8

When CHR9 is set (one), TXB8 is the 9th data bit in the character to be transmitted.

Baud Rate Generator

The baud rate generator is a frequency divider which generates baud rates according to the following equation:

•BAUD = baud rate

•fCK = CPU clock frequency

•UBRR = contents of the UART baud rate register, UBRR (0 - 255)

For standard crystal frequencies, the most commonly used baud rates can be generated by using the UBRR settings in

Table 24. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. UBRR

values which yield an actual baud rate differing less than 2% from the target baud rate, are bolded in the table. However,

using baud rates that have more than 1% error is not recommended. High error ratings give less noise resistance.

Table 24. UBRR Settings at Various CPU Frequencies

BAUD fCK

16 UBRR 1+()

--------------------------------------=

Baud Rate 1MHz %Error 1.8432 MHz %Error 2MHz %Error 2.4576 MHz %Error

2400 UBRR= 25 0.2 UBRR= 47 0.0 UBRR= 51 0.2 UBRR= 63 0.0

4800 UBRR= 12 0.2 UBRR= 23 0.0 UBRR= 25 0.2 UBRR= 31 0.0

9600 UBRR= 6 7.5 UBRR= 11 0.0 UBRR= 12 0.2 UBRR= 15 0.0

14400 UBRR= 3 7.8 UBRR= 70.0

UBRR= 8 3.7 UBRR= 10 3.1

19200 UBRR= 2 7.8 UBRR= 50.0

UBRR= 6 7.5 UBRR= 70.0

28800 UBRR= 1 7.8 UBRR= 30.0

UBRR= 3 7.8 UBRR= 4 6.3

38400 UBRR= 1 22.9 UBRR= 20.0

UBRR= 2 7.8 UBRR= 30.0

57600 UBRR= 0 7.8 UBRR= 10.0

UBRR= 1 7.8 UBRR= 2 12.5

76800 UBRR= 0 22.9 UBRR= 1 33.3 UBRR= 1 22.9 UBRR= 10.0

115200 UBRR= 0 84.3 UBRR= 00.0

UBRR= 0 7.8 UBRR= 0 25.0

Baud Rate 3.2768 MHz %Error 3.6864 MHz %Error 4MHz %Error 4.608 MHz %Error

2400 UBRR= 84 0.4 UBRR= 95 0.0 UBRR= 103 0.2 UBRR= 119 0.0

4800 UBRR= 42 0.8 UBRR= 47 0.0 UBRR= 51 0.2 UBRR= 59 0.0

9600 UBRR= 20 1.6 UBRR= 23 0.0 UBRR= 25 0.2 UBRR= 29 0.0

14400 UBRR= 13 1.6 UBRR= 15 0.0 UBRR= 16 2.1 UBRR= 19 0.0

19200 UBRR= 10 3.1 UBRR= 11 0.0 UBRR= 12 0.2 UBRR= 14 0.0

28800 UBRR= 61.6

UBRR= 70.0

UBRR= 8 3.7 UBRR= 90.0

38400 UBRR= 4 6.3 UBRR= 50.0

UBRR= 6 7.5 UBRR= 7 6.7

57600 UBRR= 3 12.5 UBRR= 30.0

UBRR= 3 7.8 UBRR= 40.0

76800 UBRR= 2 12.5 UBRR= 20.0

UBRR= 2 7.8 UBRR= 3 6.7

115200 UBRR= 1 12.5 UBRR= 10.0

UBRR= 1 7.8 UBRR= 2 20.0

Baud Rate 7.3728 MHz %Error 8MHz %Error 9.216 MHz %Error 11.059 MHz %Error

2400 UBRR= 191 0.0 UBRR= 207 0.2 UBRR= 239 0.0 UBRR= 287 -

4800 UBRR= 95 0.0 UBRR= 103 0.2 UBRR= 119 0.0 UBRR= 143 0.0

9600 UBRR= 47 0.0 UBRR= 51 0.2 UBRR= 59 0.0 UBRR= 71 0.0

14400 UBRR= 31 0.0 UBRR= 34 0.8 UBRR= 39 0.0 UBRR= 47 0.0

19200 UBRR= 23 0.0 UBRR= 25 0.2 UBRR= 29 0.0 UBRR= 35 0.0

28800 UBRR= 15 0.0 UBRR= 16 2.1 UBRR= 19 0.0 UBRR= 23 0.0

38400 UBRR= 11 0.0 UBRR= 12 0.2 UBRR= 14 0.0 UBRR= 17 0.0

57600 UBRR= 70.0

UBRR= 8 3.7 UBRR= 90.0

UBRR= 11 0.0

76800 UBRR= 50.0

UBRR= 6 7.5 UBRR= 7 6.7 UBRR= 80.0

115200 UBRR= 30.0

UBRR= 3 7.8 UBRR= 40.0

UBRR= 50.0

ATmega103/103L

UART Baud Rate Register – UBRR

The UBRR is an 8-bit read/write register which specifies the UART Baud Rate according to the description on the previous

page.

Analog Comparator

The analog comparator compares the input values on the positive input PE2 (AC+) and negative input PE3 (AC-). When

the voltage on the positive input PE2 (AC+) is higher than the voltage on the negative input PE3 (AC-), the Analog Compar-

ator Output, ACO is set (one). The output of the comparator can be set to trigger the Timer/Counter1 Input Capture

function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can

select Interrupt triggering on comparator output rise, fall, or toggle. A block diagram of the comparator and its surrounding

logic is shown in Figure 44.

Figure 44. Analog Comparator Block Diagram

Analog Comparator Control and Status Register – ACSR

•Bit 7 - ACD: Analog Comparator Disable

When this bit is set (one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the

analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD bit, the Analog

Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is

changed.

•Bit 6 - Res: Reserved Bit

This bit is a reserved bit in the ATmega103(L) and will always read as zero.

•Bit 5 - ACO: Analog Comparator Output

ACO is directly connected to the comparator output.

Bit 76543210

$09 ($29) MSB LSB UBRR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

$08 ($28) ACD - ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR

Read/Write R/W R R R/W R/W R/W R/W R/W

Initial value 0 0 X 0 0 0 0 0

PE2

(AC+)

PE3

(AC-)

ACO

ACI

INTERRUPT

SELECT

ACIS1 ACIS0

ACIE

ACIC

ANALOG

COMPARATOR

IRQ

TO T/C1 CAPTURE

TRIGGER MUX

VCC

ACD

ATmega103/103L

•Bit 4 - ACI: Analog Comparator Interrupt Flag

This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog

Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by

hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to

the flag. Observe however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared

if it has become set before the operation.

•Bit 3 - ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated.

When cleared (zero), the interrupt is disabled.

•Bit 2 - ACIC: Analog Comparator Input Capture Enable

When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the analog comparator.

The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize

the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When cleared (zero), no con-

nection between the analog comparator and the Input Capture function is given. To make the comparator trigger the

Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one).

•Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are

shown in Table 25.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable

bit in the ACSR register. Otherwise an interrupt can occur when the bits are changed.

Caution: Using the SBI or CBI instruction on other bits than ACI in this register will write a one back into ACI if it is read as

set, thus clearing the flag.

Analog-to-digital Converter

Feature list:

•10-bit resolution

•±2 LSB absolute accuracy

•0.5 LSB integral non-linearity

•70 - 280 µs conversion time

•Up to 14 kSPS

•8 multiplexed input channels

•Interrupt on ADC conversion complete

•Sleep mode noise canceler

The ATmega103(L) features a 10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Multi-

plexer which allows each pin of Port F to be used as an input for the ADC. The ADC contains a Sample and Hold Amplifier

which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC

is shown in Figure 45.

The ADC has two separate analog supply voltage pins, AVCC and AGND. AGND must be connected to GND, and the volt-

age on AVCC must not differ more than ± 0.3 V from VCC. See the section “ADC Noise Canceling Techniques” on page 71

on how to connect these pins.

Table 25. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle

01Reserved

1 0 Comparator Interrupt on Falling Output Edge

1 1 Comparator Interrupt on Rising Output Edge

ATmega103/103L

An external reference voltage must be applied to the AREF pin. This voltage must be in the range AGND - AVCC.

Figure 45. Analog-to-digital Converter Block Schematic

Operation

The ADC operates in Single Conversion mode, and each conversion will have to be initiated by the user.

The ADC is enabled by writing a logical one to the ADC Enable bit, ADEN in ADCSR. The first conversion that is started

after enabling the ADC, will be preceded by a dummy conversion to initialize the ADC. To the user, the only difference will

be that this conversion takes 13 more ADC clock pulses than a normal conversion (see Figure 48).

A conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit will stay high as long as the

conversion is in progress and be set to zero by hardware when the conversion is completed. If a different data channel is

selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel

change.

As the ADC generates a 10-bit result, two data registers, ADCH and ADCL, must be read to get the result when the conver-

sion is complete. Special data protection logic is used to ensure that the contents of the data registers belong to the same

result when they are read. This mechanism works as follows:

When reading data, ADCL must be read first. Once ADCL is read, ADC access to data registers is blocked. This means

that if ADCL has been read, and a conversion completes before ADCH is read, none of the registers are updated and the

result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL registers is re-enabled.

The ADC has its own interrupt, ADIF, which can be triggered when a conversion completes. When ADC access to the data

registers is prohibited between reading of ADCL and ADCH, the interrupt will trigger even if the result is lost.

ADC CONVERSION

COMPLETE IRQ

8-BIT DATA BUS

ADC MULTIPLEXER

SELECT (ADMUX)

ADC CTRL & STATUS

ADC DATA REGISTER

(ADCH/ADCL)

MUX2

ADIE ADIE

ADSC

ADEN

ADIF ADIF

MUX1

MUX0

ADPS0

ADPS1

ADPS2

CHANNEL

MUX

CONVERSION LOGIC10-BIT DAC

SAMPLE & HOLD

COMPARATOR

Analog

Inputs

External

Reference

Voltage

ATmega103/103L

Prescaling

Figure 46. ADC Prescaler

The ADC contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. The ADC accepts

input clock frequencies in the range 50 - 200 kHz. Applying a higher input frequency will result in a poorer accuracy, see

“ADC DC Characteristics” on page 72.

The ADPS0 - ADPS2 bits in ADCSR are used to generate a proper ADC clock input frequency from any XTAL frequency

above 100 kHz. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSR.

The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.

When initiating a conversion by setting the ADSC bit in ADCSR, the conversion starts at the following falling edge of the

ADC clock cycle. The actual sample-and-hold takes place one ADC clock cycle after the start of the conversion. The result

is ready and written to the ADC Result Register after 13 cycles. The ADC needs 2 more clock cycles before a new conver-

sion can be started. If ADSC is set high in this period, the ADC will start the new conversion immediately. For a summary of

conversion times, see Table 26.

Figure 47. ADC Timing Diagram, First Conversion

7-BIT ADC PRESCALER

ADC CLOCK SOURCE

ADPS0

ADPS1

ADPS2

CK/128

CK/2

CK/4

CK/8

CK/16

CK/32

CK/64

Reset

ADEN

MSB of result

LSB of result

ADC clock

ADSC

Hold strobe

ADIF

ADCH

ADCL

Cycle number

ADEN

1212

13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2

Dummy Conversion Actual Conversion Second

Conversion

ATmega103/103L

Figure 48. ADC Timing Diagram

ADC Noise Canceler Function

The ADC features a noise canceler that enables conversion during idle mode to reduce noise induced from the CPU core.

To make use of this feature, the following procedure should be used:

1. Turn off the ADC by clearing ADEN.

2. Turn on the ADC and simultaneously start a conversion by setting ADEN and ADSC. This starts a dummy

conversion that will be followed by a valid conversion.

3. Within 14 ADC clock cycles, enter idle mode.

4. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the MCU and

execute the ADC conversion complete interrupt routine.

ADC Multiplexer Select Register – ADMUX

•Bits 7..3 - Res: Reserved Bits

These bits are reserved bits in the ATmega103(L) and always read as zero.

•Bits 2..0 - MUX2..MUX0: Analog Channel Select Bits 2-0

The value of these three bits selects which analog input 7-0 is connected to the ADC.

Table 26. ADC Conversion Time

Condition

Sample Cycle

Number

Result Ready

(cycle number)

Total Conversion

Time (cycles)

Total Conversion

Time (µs)

1st Conversion 14 26 28 140 - 560

Single Conversion 1 13 15 75 - 300

Bit 76543210

$07 ($27) - - - - - MUX2 MUX1 MUX0 ADMUX

Read/Write R R R R R R/W R/W R/W

Initial value00000000

12 3 4 5 6 7 8 910 11 12 13

MSB of result

LSB of result

ADC clock

ADSC

Hold strobe

ADIF

ADCH

ADCL

Cycle number 14 15 12

One Conversion Next Conversion

ATmega103/103L

ADC Control and Status Register – ADCSR

•Bit 7 - ADEN: ADC Enable

Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while

a conversion is in progress, will terminate this conversion.

•Bit 6 - ADSC: ADC Start Conversion

A logical “1” must be written to this bit to start each conversion. The first time ADSC has been written after the ADC has

been enabled, or if ADSC is written at the same time as the ADC is enabled, a dummy conversion will precede the initiated

conversion. This dummy conversion performs initialization of the ADC.

ADSC remains high during the conversion. ADSC goes low after the conversion is complete, but before the result is written

to the ADC Data registers. This allows a new conversion to be initiated before the current conversion is complete. The new

conversion will then start immediately after the current conversion completes. When a dummy conversion precedes a real

conversion, ADSC will stay high until the real conversion completes.

Writing a zero to this bit has no effect.

•Bit 5 - Res: Reserved Bit

This bit is reserved in the ATmega103(L). Warning: When writing ADCSR, a logical “0” must be written to this bit.

•Bit 4 - ADIF: ADC Interrupt Flag

This bit is set (one) when an ADC conversion is complete and the the result is written to the ADC Data registers are

updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set (one). ADIF is

cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a

logical one to the flag. Beware that if doing a read-modify-write on ADCSR, a pending interrupt can be disabled. This also

applies if the SBI and CBI instructions are used.

•Bit 3 - ADIE: ADC Interrupt Enable

When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Interrupt is activated.

•Bits 2..0 - ADPS2..ADPS0: ADC Prescaler Select Bits

These bits determine the division factor between the XTAL frequency and the input clock to the ADC.

Bit 76543210

$06 ($26) ADEN ADSC - ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSR

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial value00000000

Table 27. ADC Prescaler Selections

ADPS2 ADPS1 ADPS0 Division Factor

000 Invalid

001 2

010 4

011 8

100 16

101 32

110 64

111 128

ATmega103/103L

ADC Data Register – ADCL and ADCH

When an ADC conversion is complete, the result is found in these two registers. It is essential that both registers are read,

and that ADCL is read before ADCH.

ADC Noise Canceling Techniques

Digital circuitry inside and outside the ATmega103(L) generates EMI which might affect the accuracy of analog measure-

ments. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques:

1. The analog part of the ATmega103(L) and all analog components in the application should have a separate analog

ground plane on the PCB. This ground plane is connected to the digital ground plane via a single point on the PCB.

2. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and

keep them well away from high-speed switching digital tracks.

3. The AVCC pin on the ATmega103(L) should have its own decoupling capacitor as shown in Figure 49.

4. Use the ADC noise canceler function to reduce induced noise from the CPU.

5. If some Port F pins are used as digital inputs, it is essential that these do not switch while a conversion is in

progress.

Figure 49. ADC Power Connections

Bit 151413121110 9 8

$05 ($25) - - - - - - ADC9 ADC8 ADCH

$04 ($24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL

76543210

Read/WriteRRRRRRRR

RRRRRRRR

Initial value00000000

00000000

VCC

GND

10nF

Analog Ground Plane

ATmega103(L)

(ADC0) PF0

(ADC7) PF7

(ADC1) PF1

(ADC2) PF2

(ADC3) PF3

(ADC4) PF4

(ADC5) PF5

(ADC6) PF6

AREF

AGND

AVCC

6161

6262

6363

6464

PEN

(AD0) PA0

ATmega103/103L

ADC DC Characteristics

Notes: 1. Minimum for AVCC is 2.7V.

2. Maximum for AVCC is 6.0V.

Interface to External SRAM

The interface to the SRAM consists of:

•Port A: multiplexed low-order address bus and data bus

•Port C: high-order address bus

•The ALE-pin: address latch enable

•The RD and WR-pin: read and write strobes

The external data SRAM is enabled by setting the SRE – External SRAM enable bit of the MCUCR – MCU control register,

and will override the setting of the data direction register DDRA. When the SRE bit is cleared (zero), the external data

SRAM is disabled, and the normal pin and data direction settings are used. When SRE is cleared (zero), the address space

above the internal SRAM boundary is not mapped into the internal SRAM, as in AVR parts not having interface to the

external SRAM.

When ALE goes from high to low, there is a valid address on Port A. ALE is low during a data transfer. RD and WR are

active when accessing the external SRAM only.

When the external SRAM is enabled, the ALE signal may have short pulses when accessing the internal RAM, but the ALE

signal is stable when accessing the external SRAM.

Figure 50 sketches how to connect an external SRAM to the AVR using 8 latches which are transparent when G is high.

TA = -40°C to 85°C

Symbol Parameter Condition Min Typ Max Units

Resolution 10 Bits

Absolute accuracy VREF = 4V, VCC = 4V

ADC clock = 200 kHz 12LSB

Absolute accuracy VREF = 4V, VCC = 4V

ADC clock = 1 MHz 4LSB

Absolute accuracy VREF = 4V, VCC = 4V

ADC clock = 2 MHz 16 LSB

Integral Non-linearity VREF > 2V 0.5 LSB

Differential Non-linearity VREF > 2V 0.5 LSB

Zero Error (Offset) 1 LSB

Conversion Time 70 280 µs

Clock Frequency 50 200 kHz

AVCC Analog Supply Voltage VCC - 0.3(1) VCC + 0.3(2) V

VREF Reference Voltage AGND AVCC V

RREF Reference Input Resistance 6 10 13 kΩ

RAIN Analog Input Resistance 100 MΩ

ATmega103/103L

Default, the external SRAM access is a three-cycle scheme as depicted in Figure 51. When one extra wait state is needed

in the access cycle, set the SRW bit (one) in the MCUCR register. The resulting access scheme is shown in Figure 52. In

both cases, note that Port A is data bus in one cycle only. As soon as the data access finishes, Port A becomes a low-order

address bus again.

Note: If a read is followed by a write, or opposite, there is no extra insertion of wait states in between. The user may insert a NOP

between consecutive read and write operations to the external RAM, because such short time for releasing the bus is difficult to

obtain without making bus contention.

For details in the timing for the SRAM interface, please refer to Figure 78, Table 45, Table 46, Table 47, and Table 48 in

section “DC Characteristics” on page 105.

Figure 50. External SRAM Connected to the AVR

Figure 51. External SRAM Access Cycle without Wait States

D[7:0]

A[7:0]

A[15:8]

SRAM

Port A

ALE

Port C

AVR

System Clock Ø

ALE

Data / Address [7..0]

Address [15..8]

Address

T1 T2 T3

Prev. Address

Data

Writ

Address

ATmega103/103L

Figure 52. External SRAM Access Cycle with Wait State

I/O Ports

All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction

of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instruc-

tions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if

configured as input).

Port A

Port A is an 8-bit bi-directional I/O port with internal pull-ups.

Three I/O memory address locations are allocated for Port A, one each for the Data Register – PORTA, $1B($3B), Data

Direction Register – DDRA, $1A($3A) and the Port A Input Pins – PINA, $19($39). The Port A Input Pins address is read

only, while the Data Register and the Data Direction Register are read/write.

All port pins have individually selectable pull-up resistors. The Port A output buffers can sink 20mA and thus drive LED

displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the

internal pull-up resistors are activated.

The Port A pins have alternate functions related to the optional external data SRAM. Port A can be configured to be the

multiplexed low-order address/data bus during accesses to the byte.

When Port A is set to the alternate function by the SRE (External SRAM Enable) bit in the MCUCR (MCU Control Register),

the alternate settings override the data direction register.

System Clock Ø

ALE

Data / Address [7..0]

Address [15..8]

Address

T1 T2 T3 T4

Prev. Address

Data

Writ

Addr.

ATmega103/103L

Port A Data Register – PORTA

Port A Data Direction Register – DDRA

Port A Input Pins Address – PINA

The Port A Input Pins address (PINA) is not a register, and this address enables access to the physical value on each

Port A pin. When reading PORTA the Port A Data Latch is read, and when reading PINA, the logical values present on the

pins are read.

Port A as General Digital I/O

All 8 pins in Port A have equal functionality when used as digital I/O pins.

PAn, General I/O pin: The DDAn bit in the DDRA register selects the direction of this pin, if DDAn is set (one), PAn is con-

figured as an output pin. If DDAn is cleared (zero), PAn is configured as an input pin. If PORTAn is set (one) when the pin

configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, PORTAn has to be

cleared (zero) or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes

active, even if the clock is not running.

Note: n: 7,6...0, pin number

Port A Schematics

Note that all port pins are synchronized. The synchronization latch is, however, not shown in the figure.

Bit 76543210

$1B ($3B) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

$1A ($3A) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

$19 ($39) PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA

Read/WriteRRRRRRRR

Initial value N/A N/A N/A N/A N/A N/A N/A N/A

Table 28. DDAn Effects on Port A Pins

DDAn PORTAn I/O Pull-up Comment

0 0 Input No Tri-state (high-Z)

0 1 Input Yes PAn will source current if ext. pulled low.

1 0 Output No Push-pull Zero Output

1 1 Output No Push-pull One Output

ATmega103/103L

Figure 53. Port A Schematic Diagrams (Pins PA0 - PA7)

Port B

Port B is an 8-bit bi-directional I/O port with internal pull-ups.

Three I/O memory address locations are allocated for Port B, one each for the Data Register – PORTB, $18($38), Data

Direction Register – DDRB, $17($37) and the Port B Input Pins – PINB, $16($36). The Port B Input Pins address is read

only, while the Data Register and the Data Direction Register are read/write.

All port pins have individually selectable pull-up resistors. The Port B output buffers can sink 20mA and thus drive LED dis-

plays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current if the

internal pull-up resistors are activated.

DATA BUS

RESET

MOS

PULL-

PAn

WP:

WD:

RL:

RP:

RD:

SRE:

WRITE PORTA

WRITE DDRA

READ PORTA LATCH

READ PORTA PIN

READ DDRA

EXT. SRAM ENABLE

ADDRESS

DATA

WRITE

READ

0-7

DDAn

PORTAn

SRE

ATmega103/103L

The Port B pins with alternate functions are shown in the following table:

When the pins are used for the alternate function the DDRB and PORTB register have to be set according to the alternate

function description.

Port B Data Register – PORTB

Port B Data Direction Register – DDRB

Port B Input Pins Address – PINB

The Port B Input Pins address (PINB) is not a register, and this address enables access to the physical value on each

Port B pin. When reading PORTB, the Port B Data Latch is read, and when reading PINB, the logical values present on the

pins are read.

Port B as General Digital I/O

All 8 pins in port B have equal functionality when used as digital I/O pins.

PBn, General I/O pin: The DDBn bit in the DDRB register selects the direction of this pin, if DDBn is set (one), PBn is con-

figured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) when the pin

configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTBn has to be

cleared (zero) or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes

active, even if the clock is not running.

Table 29. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB0 SS (SPI Slave Select input)

PB1 SCK (SPI Bus Serial Clock)

PB2 MOSI (SPI Bus Master Output/Slave Input)

PB3 MISO (SPI Bus Master Input/Slave Output)

PB4 OC0/PWM0 (Output Compare and PWM Output for Timer/Counter0)

PB5 OC1A/PWM1A (Output Compare and PWM Output A for Timer/Counter1)

PB6 OC1B/PWM1B (Output Compare and PWM Output B for Timer/Counter1)

PB7 OC2/PWM2 (Output Compare and PWM Output for Timer/Counter2)

Bit 76543210

$18 ($38) PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

$17 ($37) DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

$16 ($36) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB

Read/WriteRRRRRRRR

Initial value N/A N/A N/A N/A N/A N/A N/A N/A

ATmega103/103L

Note: n: 7,6...0, pin number

Alternate Functions of Port B

The alternate pin configuration is as follows:

•OC2/PWM2, Bit 7

OC2/PWM2, Output Compare output for Timer/Counter2 or PWM output when Timer/Counter2 is in PWM Mode. The pin

has to be configured as an output to serve this function.

•OC1B/PWM1B, Bit 6

OC1B/PWM1B, Output Compare output B for Timer/Counter1 or PWM output B when Timer/Counter1 is in PWM Mode.

The pin has to be configured as an output to serve this function.

•OC1A/PWM1A, Bit 5

OC1A/PWM1A, Output Compare output A for Timer/Counter1 or PWM output A when Timer/Counter1 is in PWM Mode.

The pin has to be configured as an output to serve this function.

•OC0/PWM0, Bit 4

OC0/PWM0, Output Compare output for Timer/Counter0 or PWM output when Timer/Counter0 is in PWM Mode. The pin

has to be configured as an output to serve this function.

•MISO - Port B, Bit 3

MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured

as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled

by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit. See the description of

the SPI port for further details.

•MOSI - Port B, Bit 2

MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured

as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is con-

trolled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit. See the

description of the SPI port for further details.

•SCK - Port B, Bit 1

SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured

as an input regardless of the setting of DDB1. When the SPI is enabled as a master, the data direction of this pin is con-

trolled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit. See the

description of the SPI port for further details.

•SS - Port B, Bit 0

SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting

of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-

tion of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the

PORTB0 bit. See the description of the SPI port for further details.

Table 30. DDBn Effects on Port B Pins

DDBn PORTBn I/O Pull-up Comment

0 0 Input No Tri-state (high-Z)

0 1 Input Yes PBn will source current if ext. pulled low

1 0 Output No Push-pull Zero Output

1 1 Output No Push-pull One Output

ATmega103/103L

Port B Schematics

Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures.

Figure 54. Port B Schematic Diagram (Pin PB0)

Figure 55. Port B Schematic Diagram (Pin PB1)

ATmega103/103L

Figure 56. Port B Schematic Diagram (Pin PB2)

Figure 57. Port B Schematic Diagram (Pin PB3)

ATmega103/103L

Figure 58. Port B Schematic Diagram (Pin PB4)

Figure 59. Port B Schematic Diagram (Pins PB5 and PB6)

DATA BUS

RESET

MOS

PULL-

PB4

WP:

WD:

RL:

RP:

RD:

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

DDB4

PORTB4

COMP. MATCH 0

COM01

OUTPUT

MODE SELECT

DATA BUS

RESET

MOS

PULL-

PBn

WP:

WD:

RL:

RP:

RD:

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

5, 6

A, B

DDBn

PORTBn

COMP. MATCH 1X

COM1X0

COM1X1

OUTPUT

MODE SELECT

ATmega103/103L

Figure 60. Port B Schematic Diagram (Pin PB7)

Port C

PORT C is an 8-bit output port.

The Port C pins have alternate functions related to the optional external data SRAM. When using the device with external

SRAM, Port C outputs the high-order address byte during accesses to external data memory. When a reset condition

becomes active, the port pins are not tri-stated, but the pins will assume their initial value after two stable clock cycles.

The Port C Data Register – PORTC

Bit 76543210

$15 ($35) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

DATA BUS

RESET

MOS

PULL-

PB7

WP:

WD:

RL:

RP:

RD:

WRITE PORTB

WRITE DDRB

READ PORTB LATCH

READ PORTB PIN

READ DDRB

DDB7

PORTB7

COMP. MATCH 2

COM20

COM21

OUTPUT

MODE SELECT

ATmega103/103L

Port C Schematics

Figure 61. Port C Schematic Diagram (Pins PC0 - PC7)

Port D

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors.

Three I/O memory address locations are allocated for the Port D, one each for the Data Register – PORTD, $12($32), Data

Direction Register – DDRD, $11($31) and the Port D Input Pins – PIND, $10($30). The Port D Input Pins address is read

only, while the Data Register and the Data Direction Register are read/write.

The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-

up resistors are activated.

Some Port D pins have alternate functions as shown in the following table:

When the pins are used for the alternate function the DDRD and PORTD register has to be set according to the alternate

function description.

Port D Data Register – PORTD

Table 31. Port D Pins Alternate Functions

Port Pin Alternate Function

PD0 INT0 (External Interrupt0 Input)

PD1 INT1 (External Interrupt1 Input)

PD2 INT2 (External Interrupt2 Input)

PD3 INT3 (External Interrupt3 Input)

PD4 IC1 (Timer/Counter1 Input Capture Trigger)

PD6 T1 (Timer/Counter1 Clock Input)

PD7 T2 (Timer/Counter2 Clock Input)

Bit 76543210

$12 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

DATA B

RESET

PCn R

WP:

RL:

SRE:

WRITE PORTC

READ PORTC LATCH

SRAM ADDRESS

EXTERNAL SRAM ENABLE

0-7

PORTCn

SRE

ATmega103/103L

Port D Data Direction Register – DDRD

Port D Input Pins Address – PIND

The Port D Input Pins address (PIND) is not a register, and this address enables access to the physical value on each

Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the

pins are read.

Port D as General Digital I/O

PDn, General I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is con-

figured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PDn is set (one) when configured

as an input pin the MOS pull-up resistor is activated. To switch the pull-up resistor off the PDn has to be cleared (zero) or

the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes active, even if

the clock is not running.

Note: n: 7,6...0, pin number

Alternate Functions of Port D

INT0..INT3 - Port D, Bits 0..3

External Interrupt sources 0 - 3. The PD0 - PD3 pins can serve as external active low interrupt sources to the MCU. The

internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and

how to enable the sources.

IC1 - Port D, Bit 4

IC1 – Input Capture pin for Timer/Counter1. When a positive or negative (selectable) edge is applied to this pin, the con-

tents of Timer/Counter1 is transferred to the Timer/Counter1 Input Capture Register. The pin has to be configured as an

input to serve this function. See the Timer/Counter1 description on how to operate this function. The internal pull up MOS

resistor can be activated as described above.

T1 - Port D, Bit 6

T1, Timer/Counter1 counter source. See the timer description for further details.

T2 - Port D, Bit 7

T2, Timer/Counter2 counter source. See the timer description for further details.

Bit 76543210

$11 DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

$10 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND

Read/WriteRRRRRRRR

Initial value N/A N/A N/A N/A N/A N/A N/A N/A

Table 32. DDDn Bits on Port D Pins

DDDn PORTDn I/O Pull-up Comment

0 0 Input No Tri-state (high-Z)

0 1 Input Yes PDn will source current if ext. pulled low.

1 0 Output No Push-pull Zero Output

1 1 Output No Push-pull One Output

ATmega103/103L

Port D Schematics

Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures.

Figure 62. Port D Schematic Diagram (Pins PD0, PD1, PD2 and PD3)

Figure 63. Port D Schematic Diagram (Pin PD4)

DATA B

RESET

MOS

PULL-

PDn

WP:

WD:

RL:

RP:

RD:

WRITE PORTD

WRITE DDRD

READ PORTD LATCH

READ PORTD PIN

READ DDRD

0, 1, 2, 3

DDDn

PORTDn

INTn

DATA BUS

RESET

MOS

PULL-

PD4

WP:

WD:

RL:

RP:

RD:

ACIC:

ACO:

WRITE PORTD

WRITE DDRD

READ PORTD LATCH

READ PORTD PIN

READ DDRD

COMPARATOR IC ENABLE

COMPARATOR OUTPUT

DDD4

PORTD4

NOISE CANCELER EDGE SELECT ICF1

ICNC1 ICES1

ACIC

ACO

ATmega103/103L

Figure 64. Port D Schematic Diagram (Pin PD5)

Figure 65. Port D Schematic Diagram (Pins PD6 and PD7)

DATA B

RESET

MOS

PULL-

PD5

WP:

WD:

RL:

RP:

RD:

WRITE PORTD

WRITE DDRD

READ PORTD LATCH

READ PORTD PIN

READ DDRD

DDD5

PORTD5

DATA BUS

RESET

MOS

PULL-

PDn

WP:

WD:

RL:

RP:

RD:

WRITE PORTD

WRITE DDRD

READ PORTD LATCH

READ PORTD PIN

READ DDRD

6, 7

1, 2

DDDn

PORTDn

SENSE CONTROL TIMERm CLOCK

SOURCE MUX

CSm2 CSm0

CSm1

ATmega103/103L

Port E

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors.

Three I/O memory address locations are allocated for the Port E, one each for the Data Register – PORTE, $03($23), Data

Direction Register – DDRE, $02($22) and the Port E Input Pins – PINE, $01($21). The Port E Input Pins address is read

only, while the Data Register and the Data Direction Register are read/write.

The Port E output buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source current if the

pull-up resistors are activated.

All Port E pins have alternate functions as shown in the following table:

When the pins are used for the alternate function the DDRE and PORTE register has to be set according to the alternate

function description.

Port E Data Register – PORTE

Port E Data Direction Register – DDRE

Port E Input Pins Address – PINE

The Port E Input Pins address (PINE) is not a register, and this address enables access to the physical value on each

Port E pin. When reading PORTE, the Port E Data Latch is read, and when reading PINE, the logical values present on the

pins are read.

Table 33. Port E Pins Alternate Functions

Port Pin Alternate Function

PE0 PDI/RXD (Programming Data Input or UART Receive Pin)

PE1 PDO/TXD (Programming Data Output or UART Transmit Pin)

PE2 AC+ (Analog Comparator Positive Input)

PE3 AC- (Analog Comparator Negative Input)

PE4 INT4 (External Interrupt4 Input)

PE5 INT5 (External Interrupt5 Input)

PE6 INT6 (External Interrupt6 Input)

PE7 INT7 (External Interrupt7 Input)

Bit 76543210

$03 ($23) PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 PORTE

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

$02 ($22) DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 DDRE

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

$01 ($21) PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 PINE

Read/WriteRRRRRRRR

Initial value N/A N/A N/A N/A N/A N/A N/A N/A

ATmega103/103L

Port E as General Digital I/O

PEn, General I/O pin: The DDEn bit in the DDRE register selects the direction of this pin. If DDEn is set (one), PEn is con-

figured as an output pin. If DDEn is cleared (zero), PEn is configured as an input pin. If PEn is set (one) when configured as

an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off the PEn has to be cleared (zero) or the

pin has to be configured as an output pin.The port pins are tri-stated when a reset condition becomes active, even if the

clock is not running.

Note: n: 7,6...0, pin number

Alternate Functions of Port E

PDI/RXD - Port E, Bit 0

PDI, Serial Programming Data Input. During Serial Program downloading, this pin is used as data input line for the

ATmega103(L).

RXD, UART Receive Pin. Receive Data (Data input pin for the UART). When the UART receiver is enabled this pin is con-

figured as an input regardless of the value of DDRD0. When the UART forces this pin to be an input, a logical one in

PORTD0 will turn on the internal pull-up.

PDO/TXD - Port E, Bit 1

PDO, Serial Programming Data Output. During Serial Program downloading, this pin is used as data output line for the

ATmega103(L).

TXD, UART Transmit Pin.

AC+ - Port E, Bit 2

AC+ – Analog Comparator Positive Input. This pin is directly connected to the positive input of the analog comparator.

AC- - Port E, Bit 3

AC- – Analog Comparator Negative Input. This pin is directly connected to the negative input of the analog comparator.

INT4..INT7 - Port E, Bit 4-7

INT4..INT7 – External Interrupt sources 4 - 7: The PE4 - PE7 pins can serve as external interrupt sources to the MCU.

Interrupts can be triggered by low level or positive or negative edge on these pins. The internal pull-up MOS resistors can

be activated as described above. See the interrupt description for further details, and how to enable the sources.

Port E Schematics

Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures.

Table 34. DDEn Bits on Port E Pins

DDEn PORTEn I/O Pull-up Comment

0 0 Input No Tri-state (high-Z)

0 1 Input Yes PDn will source current if ext. pulled low.

1 0 Output No Push-pull Zero Output

1 1 Output No Push-pull One Output

ATmega103/103L

Figure 66. Port E Schematic Diagram (Pin PE0)

Figure 67. Port E Schematic Diagram (Pin PE1)

ATmega103/103L

Figure 68. Port E Schematic Diagram (Pin PE2)

Figure 69. Port E Schematic Diagram (Pin PE3)

DATA BUS

RESET

MOS

PULL-

PE2

AC+

TO COMPARATOR

WP:

WD:

RL:

RP:

RD:

WRITE PORTE

WRITE DDRE

READ PORTE LATCH

READ PORTE PIN

READ DDRE

DDE2

PORTE2

DATA BUS

RESET

MOS

PULL-

PE3

AC-

TO COMPARATOR

WP:

WD:

RL:

RP:

RD:

WRITE PORTE

WRITE DDRE

READ PORTE LATCH

READ PORTE PIN

READ DDRE

DDE3

PORTE3

ATmega103/103L

Figure 70. Port E Schematic Diagram (Pins PE4, PE5, PE6 and PE7)

Port F

Port F is an 8-bit input port.

One I/O memory location is allocated for Port F, the Port F Input Pins – PINF, $00 ($20).

All Port F pins are connected to the analog multiplexer which further is connected to the A/D converter. The digital input

function of Port F can be used together with the A/D converter, allowing the user to use some pins of Port F and digital

inputs and other as analog inputs, at the same time.

Port F Input Pins Address – PINF

The Port F Input Pins address (PINF) is not a register, and this address enables access to the physical value on each

Port F pin.

Bit 76543210

$00 ($20) PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 PINF

Read/WriteRRRRRRRR

Initial value N/A N/A N/A N/A N/A N/A N/A N/A

DATA B

RESET

MOS

PULL-

PEn

WP:

WD:

RL:

RP:

RD:

WRITE PORTE

WRITE DDRE

READ PORTE LATCH

READ PORTE PIN

READ DDRE

4, 5, 6, 7

DDEn

PORTEn

SENSE CONTROL INTn

ISCn1 ISCn0

ATmega103/103L

Figure 71. Port F Schematic Diagram (Pins PF7 - PF0)

Memory Programming

Program and Data Memory Lock Bits

The ATmega103(L) MCU provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to

obtain the additional features listed in Table 35. The Lock bits can only be erased to “1” with the Chip Erase command.

Note: 1. In Parallel mode, programming of the Fuse bits are also disabled. Program the Fuse bits before programming the Lock bits.

Fuse Bits

The ATmega103(L) has four Fuse bits, SPIEN, SUT1..0, and EESAVE.

•When the SPIEN Fuse is programmed (“0”), Serial Program and Data Downloading is enabled. Default value is

programmed (“0”). The SPIEN Fuse is not accessible in serial programming mode.

•When EESAVE is programmed, the EEPROM memory is preserved through the Chip Erase cycle. Default value is

unprogrammed (“1”). The EESAVE Fuse bit can not be programmed if any of the Lock bits are programmed.

•SUT1..0 Fuses: Determine the MCU start-up time. See Table 5 on page 26 for further details. Default value is

unprogrammed (“11”), which gives a nominal start up time of 16 ms.

The status of the Fuse bits is not affected by Chip Erase.

Table 35. Lock Bit Protection Modes

Memory Lock Bits Protection Type

Mode LB1 LB2

1 1 1 No memory lock features enabled.

2 0 1 Further programming of the Flash and EEPROM is disabled.(1)

3 0 0 Same as mode 2, and verify is also disabled.

DATA B

PFn

AINn

TO ADC MUX

RP:

READ PORTF PIN

0 - 7

ATmega103/103L

Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial

and parallel mode. The three bytes reside in a separate address space.

For the ATmega103 they are:

1. $000: $1E (indicates manufactured by Atmel)

2. $001: $97 (indicates 128K bytes Flash memory)

3. $002: $01 (indicates ATmega103 when signature byte $001 is $97)

Programming the Flash and EEPROM

Atmel’s ATmega103(L) offers 128K bytes of in-system reprogrammable Flash memory and 4K bytes of EEPROM Data

memory.

The ATmega103(L) is shipped with the on-chip Flash Program and EEPROM Data memory arrays in the erased state (i.e.

contents = $FF) and ready to be programmed. This device supports a parallel programming mode and a serial program-

ming mode. The +12V supplied to the RESET pin in parallel programming mode is used for programming enable only, and

no current of significance is drawn by this pin. The serial programming mode provides a convenient way to download pro-

gram and data into the ATmega103(L) inside the user’s system.

The Flash Program memory array on the ATmega103(L) is organized as 512 pages of 256 bytes each. When programming

the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simulta-

neously in either programming mode.

The EEPROM Data memory array on the ATmega103(L) is programmed byte-by-byte in either programming mode. An

auto-erase cycle is provided within the self-timed EEPROM write instruction in the serial programming mode.

During programming, the supply voltage must be in accordance with Table 36.

Parallel Programming

This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Lock bits and

Fuse bits in the ATmega103(L). Pulses are assumed to be at least 500 ns unless otherwise noted.

Signal Names

In this section, some pins of the ATmega103(L) are referenced by signal names describing their function during parallel

programming (see Figure 72 and Table 37). Pins not described in Table 37 are referenced by pin names.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in

Table 38.

When pulsing WR or OE, the command loaded determines the action executed. The command is a byte where the different

bits are assigned functions as shown in Table 39.

Table 36. Supply Voltage during Programming

Part Serial Programming Parallel Programming

ATmega103 4.0 - 5.0V 4.0 - 5.0V

ATmega103L 3.2 - 3.6V 3.2 - 5.0V

ATmega103/103L

Figure 72. Parallel Programming

Table 37. Pin Name Mapping

Signal Name in Programming Mode Pin Name I/O Function

RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command

OE PD2 I Output Enable (Active low)

WR PD3 I Write Pulse (Active low)

BS1 PD4 I Byte Select 1 (“0” selects low byte, “1” selects high byte)

XA0 PD5 I XTAL Action Bit 0

XA1 PD6 I XTAL Action Bit 1

BS2 PD7 I Byte Select 2 (Always low)

PAGEL PA0 I Program Memory Page Load

DATA PB7-0 I/O Bidirectional Data Bus (Output when OE is low)

Table 38. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 Is Pulsed

0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1)

0 1 Load Data (High or low data byte for Flash determined by BS1)

1 0 Load Command

1 1 No Action, Idle

ATmega103(L)

VCC

+5V

PA0

GND

XTAL1

PD1

PD2

PD3

PD4

PD5

PD6

PAGEL

RDY/BSY

BS1

XA0

XA1

PB7 - PB0 DATA

RESET+12V

PD7

ATmega103/103L

Enter Programming Mode

The following algorithm puts the device in parallel programming mode:

1. Apply supply voltage according to Table 36, between VCC and GND.

2. Set RESET and BS1 pins to “0” and wait at least 100 ns.

3. Apply 11.5 - 12.5V to RESET. Any activity on BS1 within 100 ns after +12V has been applied to RESET will cause

the device to fail entering programming mode.

Chip Erase

The Chip Erase will erase the Flash and EEPROM memories, and Lock bits. The Lock bits are not reset until the program

memory has been completely erased. The Fuse bits are not changed. A chip erase must be performed before the Flash or

EEPROM is reprogrammed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a tWLWH_CE wide negative pulse to execute Chip Erase. See Table 40 for tWLWH_CE value. Chip Erase does not

generate any activity on the RDY/BSY pin.

Table 39. Command Byte Bit Coding

Command Byte Command Executed

1000 0000 Chip Erase

0100 0000 Write Fuse Bits

0010 0000 Write Lock Bits

0001 0000 Write Flash

0001 0001 Write EEPROM

0000 1000 Read Signature Bytes

0000 0100 Read Lock and Fuse Bits

0000 0010 Read Flash

0000 0011 Read EEPROM

Table 40. Minimum WR Pulse Width for Chip Erase

Symbol 3.2V 3.6V 4.0V 5.0V

tWLWH_CE 56 ms 43 ms 35 ms 22 ms

ATmega103/103L

Programming the Flash

The Flash is organized as 512 pages of 256 bytes each. When programming the Flash, the program data is latched into a

page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes

how to program the entire Flash memory:

A: Load Command “Write Flash”.

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS1 to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B: Load Address Low Byte.

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “0”. This selects low address.

3. Set DATA = Address low byte ($00 - $FF)

4. Give XTAL1 a positive pulse. This loads the address low byte.

C: Load Data Low Byte.

1. Set BS1 to “0”. This selects low data.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data low byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the data byte.

D: Latch Data Low Byte.

Give PAGEL a positive pulse. This latches the data low byte.

(See Figure 73 for signal waveforms.)

E: Load Data High Byte.

1. Set BS1 to “1”. This selects high data.

2. Set XA1, XA0 to “01”. This enables data loading.

3. Set DATA = Data high byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the data high byte.

F: Latch Data High Byte.

Give PAGEL a positive pulse. This latches the data high byte.

G: Repeat B through F 128 times to fill the page buffer.

H: Load Address High Byte.

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS1 to “1”. This selects high address.

3. Set DATA = Address high byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the address high byte.

I: Program Page.

1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low.

2. Wait until RDY/BSY goes high.

(See Figure 74 for signal waveforms.)

J: End Page Programming.

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set DATA = “0000 0000”. This is the command for No Operation.

3. Give XTAL1 a positive pulse. This loads the command and the internal write signals are reset.

ATmega103/103L

K: Repeat A through J 512 times or until all data has been programmed.

Figure 73. Programming the Flash Waveforms

Figure 74. Programming the Flash Waveforms (Continued)

$10 ADDR. LOW ADDR. HIGH DATA LOWDATA

XA1

XA2

BS1

XTAL1

RDY/BSY

RESET

+12V

BS2

PAGEL

DATA HIGH

DATA

XA1

XA0

BS1

XTAL1

RDY/BSY

RESET +12V

BS2

PAGEL

ATmega103/103L

Programming the EEPROM

The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 96 for

details on Command, Address and Data loading):

1. A: Load Command “0001 0001”.

2. H: Load Address High Byte ($00 - $0F).

3. B: Load Address Low Byte ($00 - $FF).

4. E: Load Data Low Byte ($00 - $FF).

L: Write Data Low Byte.

1. Set BS to “0”. This selects low data.

2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low.

3. Wait until RDY/BSY goes high to program the next byte.

(See Figure 75 for signal waveforms.)

The loaded command and address are retained in the device during programming. For efficient programming, the following

should be considered:

•The command needs only be loaded once when writing or reading multiple memory locations.

•Address high byte needs only be loaded before programming a new 256-word page in the EEPROM.

•Skip writing the data value $FF that is the contents of the entire EEPROM after a chip erase.

These considerations also apply to Flash, EEPROM and Signature bytes reading.

Figure 75. Programming the EEPROM Waveforms

$11 ADDR. HIGH ADDR. LOW DATA LOWDATA

XA1

XA2

BS1

XTAL1

RDY/BSY

RESET

+12V

BS2

PAGEL

ATmega103/103L

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 96 for details on Com-

mand and Address loading):

1. A: Load Command “0000 0010”.

2. H: Load Address High Byte ($00 - $FF).

3. B: Load Address Low Byte ($00 - $FF).

4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.

5. Set BS to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 96 for details on

Command and Address loading):

1. A: Load Command “0000 0011”.

2. H: Load Address High Byte ($00 - $0F).

3. B: Load Address ($00 - $FF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.

5. Set OE to “1”.

Programming the Fuse Bits

The algorithm for programming the Fuse bits is as follows (refer to “Programming the Flash” on page 96 for details on Com-

mand and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

Bit 5 = SPIEN Fuse bit

Bit 3 = EESAVE Fuse bit

Bit 2 = always “1”

Bit 1 = SUT1 Fuse bit

Bit 0 = SUT0 Fuse bit

Bit 7, 6,4,2 = “1”. These bits are reserved and should be left unprogrammed (“1”).

3. Give WR a tWLWH_PFB wide negative pulse to execute the programming. tWLWH_PFB is found in Table 41. Programming

the Fuse bits does not generate any activity on the RDY/BSY pin.

Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 96 for details on Com-

mand and Data loading):

1. A: Load Command “0010 0000”.

2. D: Load Data Low Byte. Bit n = “0” programs the Lock bit.

Bit 2 = Lock Bit2

Bit 1 = Lock Bit1

Bit 7-3,0 = “1”. These bits are reserved and should be left unprogrammed (“1”).

3. L: Write Data Low Byte.

The Lock bits can only be cleared by executing Chip Erase.

ATmega103/103L

100

Reading the Fuse and Lock Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 96 for details on

Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, and BS to “0”. The status of the Fuse bits can now be read at DATA (“0” means programmed).

Bit 5 = SPIEN Fuse bit

Bit 3 = EESAVE Fuse bit

Bit 1 = SUT1 Fuse bit

Bit 0 = SUT0 Fuse bit

Set OE to “0”, and BS to “1”. The status of the Lock bits can now be read at DATA (“0” means programmed).

Bit 2 = Lock Bit2

Bit 1 = Lock Bit1

3. Set OE to “1”.

Reading the Signature Bytes

The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 96 for details on

Command and Address loading):

1. A: Load Command “0000 1000”.

2. C: Load Address Low Byte ($00 - $02).

Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA.

3. Set OE to “1”.

Parallel Programming Characteristics

Figure 76. Parallel Programming Timing

Data & Contol

(DATA, XA0/1, BS1)

DATA

Write

Read

XTAL1 t

XHXL

WLWH

DVXH

XLOL

OLDV

XLDX

PLWL

WHRL

WLRH

RDY/BSY

PAGEL t

PHPL

PLBX

BVXH

XLWL

RHBX

OHDZ

BVWL

ATmega103/103L

101

Table 41. Parallel Programming Characteristics

TA = 25°C ± 10%, VCC = 5V ± 10%

Notes: 1. Use tWLWH_CE for Chip Erase and tWLWH_PFB for programming the fuse bits.

2. If tWLWH is held longer than tWLRH, no RDY/BSY pulse will be seen.

Symbol Parameter Min Typ Max Units

VPP Programming Enable Voltage 11.5 12.5 V

IPP Programming Enable Current 250 µA

tDVXH Data and Control Valid before XTAL1 High 67 ns

tXHXL XTAL1 Pulse Width High 67 ns

tXLDX Data and Control Hold after XTAL1 Low 67 ns

tXLWL XTAL1 Low to WR Low 67 ns

tBVXH BS1 Valid before XTAL1 High 67 ns

tPHPL PAGEL Pulse Width High 67 ns

tPLBX BS1 Hold after PAGEL Low 67 ns

tPLWL PAGEL Low to WR Low 67 ns

tBVWL BS1 Valid to WR Low 67 ns

tRHBX BS1 Hold after RDY/BSY High 67 ns

tWLWH WR Pulse Width Low(1) 67 ns

tWHRL WR High to RDY/BSY Low(2) 20 ns

tWLRH WR Low to RDY/BSY High(2) 0.5 0.7 0.9 ms

tXLOL XTAL1 Low to OE Low 67 ns

tOLDV OE Low to DATA Valid 20 ns

tOHDZ OE High to DATA Tri-stated 20 ns

tWLWH_CE WR Pulse Width Low for Chip Erase 5 10 15 ms

tWLWH_PFB WR Pulse Width Low for Progr. the Fuse Bits 1.0 1.5 1.8 ms

ATmega103/103L

102

Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial interface while RESET is pulled to GND,

or when PEN is low during Power-on Reset. The serial interface consists of pins SCK, RXD/PDI (input) and TXD/PDO (out-

put). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase

instructions can be executed.

For the EEPROM, an auto-erase cycle is provided within the self-timed write instruction and there is no need to first exe-

cute the Chip Erase instruction. The Chip Erase instruction turns the content of every memory location in both the Program

and EEPROM arrays into $FF.

The Program and EEPROM memory arrays have separate address spaces: $0000 to $FFFF for Program memory and

$0000 to $0FFF for EEPROM memory.

Either an external clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The

minimum low and high periods for the serial clock (SCK) input are defined as follows:

Low: > 2 XTAL1 clock cycles

High: > 2 XTAL1 clock cycles

Serial Programming Algorithm

When writing serial data to the ATmega103(L), data is sampled by the ATmega 103/103L on the rising edge of SCK. When

reading data from the ATmega103(L), data is clocked on the falling edge of SCK. See Figure 77 on page 105 for an expla-

nation. To program and verify the ATmega103(L) in the serial programming mode, the following sequence is recommended

(See 4-byte instruction formats in Table 44.):

1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. The RESET signal

must be kept low during the complete serial programming session. If a crystal is not connected across pins XTAL1

and XTAL2, apply a clock signal to the XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is

held low during power-up. In this case, RESET must be given a positive pulse of at least two XTAL1 cycles duration

after SCK has been set to “0”.

As an alternative to using the RESET signal, PEN can be held low during Power-on Reset while SCK is set to “0”. In

this case, only the PEN value at Power-on Reset is important. If a crystal is not connected across pins XTAL1 and

XTAL2, apply a clock signal to the XTAL1 pin. If the programmer cannot guarantee that SCK is held low during power-

up, the PEN method cannot be used.The device must be powered down in order to commence normal operation when

using this method.

2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin

PE0(PDI/RXD).

3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the

second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Whether the

echo is correct or not, all 4 bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a

positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is

no functional device connected.

4. If a chip erase is performed (must be done to erase the Flash), wait at least (2 x tWD_FLASH), give RESET a positive

pulse of at least two XTAL1 cycles duration after SCK has been set to “0”, and start over from step 2.

5. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the

7 LSB of the address and data together with the Load Program Memory Page instruction. The Program Memory

Page is stored by loading the Write Program Memory Page instruction with the 9 MSB of the address. The next

page can be written after tWD_FLASH, i.e. writing 256 bytes takes tWD_FLASH. Accessing the serial programming inter-

face before the Flash write operation completes can result in incorrect programming.

6. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appro-

priate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If

polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (Please refer to Table 42.)

7. Any memory location can be verified by using the Read instruction which returns the content at the selected

address at serial output PE1(PDO/TXD).

ATmega103/103L

103

8. At the end of the programming session, RESET can be set high to commence normal operation.

9. Power-off sequence (if needed): Set XTAL1 to “0” (if a crystal is not used). Set RESET to “1”. Turn VCC power off.

Table 42 shows the actual delays used in this section.

Please note: The MISO pin is not high-Z during serial programming.

Data Polling for the EEPROM

When a new EEPROM byte has been written and is being programmed into the EEPROM, reading the address location

being programmed will first give the value P1 (please refer to Table 43) until the auto-erase is finished, and then the

value P2.

At the time the device is ready for a new EEPROM byte, the programmed value will read correctly. This is used to deter-

mine when the next byte can be written. This will not work for the values P1 and P2, so when programming these values,

the user will have to wait for at least the prescribed time tWD_EEPROM (please refer to Table 42) before programming the next

byte. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF can

be skipped. This does not apply if the EEPROM is reprogrammed without chip erasing the device.

Data polling is not implemented for the Flash!

Note: See Errata sheet for latest information.

Table 42. Minimum Wait Delay before Writing the Next Flash or EEPROM Location

Symbol 3.2V 3.6V 4.0V 5.0V

tWD_FLASH 56 ms 43 ms 35 ms 22 ms

tWD_EEPROM 9 ms 7 ms 6 ms 4 ms

Table 43. Read Back Value during EEPROM Polling

Part/Revision P1 P2

TBD TBD TBD

ATmega103/103L

104

Note: a = address high bits

b = address low bits

H = 0 – Low byte, 1 – High byte

o = data out

i = data in

x = don’t care

1 = Lock Bit 1

2 = Lock Bit 2

3 = SUT0 Fuse

4 = SUT1 Fuse

5 = SPIEN Fuse

6 = EESAVE Fuse

Table 44. Serial Programming Instruction Set

Instruction

Instruction Format

OperationByte 1 Byte 2 Byte 3 Byte 4

Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming while

RESET is low.

Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.

Read Program Memory 0010 H000 aaaa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from

Program memory at word address a:b.

Load Program Memory Page 0100 H000 xxxx xxxx xbbb bbbb iiii iiii Write H (high or low) data i to Program

Memory Page at word address b.

Write Program Memory Page 0100 1100 aaaa aaaa bxxx xxxx xxxx xxxx Write Program Memory Page at

address a:b.

Read EEPROM Memory 1010 0000 xxxx aaaa bbbb bbbb oooo oooo Read data o from EEPROM memory

at address a:b.

Write EEPROM Memory 1100 0000 xxxx aaaa bbbb bbbb iiii iiii Write data i to EEPROM memory at

address a:b.

Read Lock Bits 0101 1000 xxxx xxxx xxxx xxxx xxxx x21xRead Lock bits. “0” = programmed,

“1” = unprogrammed.

Write Lock Bits 1010 1100 1111 1211 xxxx xxxx xxxx xxxx Write Lock bits. Set bits 1,2 = “0” to

program Lock bits.

Read Fuse Bits 0101 0000 xxxx xxxx xxxx xxxx xx5x 6143 Read Fuse bits. “0” = programmed,

“1” = unprogrammed.

Write Fuse Bits 1010 1100 1011 6143 xxxx xxxx xxxx xxxx Write Fuse bits. Set bit 6,4,3 = “0” to

program, “1” to unprogram.

Read Signature Byte 0011 0000 xxxx xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b.

ATmega103/103L

105

Figure 77. Serial Programming Waveforms

Electrical Characteristics

Absolute Maximum Ratings*

Operating Temperature.................................. -40°C to +105°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

Storage Temperature ..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................ -1.0V to VCC + .5V

Voltage on RESET with respect to Ground.....-1.0V to + 13.0V

Maximum Operating Voltage ............................................ 6.6V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current VCC and GND........................................ 400.0 mA

DC Characteristics

TA = -40°C to 85°C, VCC = 2.7V to 3.6V and 4.0V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min Typ Max Units

VIL Input Low Voltage Except (XTAL) -0.5 0.3 VCC(1) V

VIL1 Input Low Voltage XTAL -0.5 0.1(1) V

VIH Input High Voltage Except (XTAL, RESET) 0.6 VCC(2) VCC + 0.5 V

VIH1 Input High Voltage XTAL 0.7 VCC(2) VCC + 0.5 V

VIH2 Input High Voltage RESET 0.85 VCC(2) VCC + 0.5 V

VOL

Output Low Voltage(3)

Ports A, B, C, D, E

IOL = 20 mA, VCC = 5V

IOL = 10 mA, VCC = 3V

0.6

0.5

VOH

Output High Voltage(4)

Ports A, B, C, D, E

IOH = -3 mA, VCC = 5V

IOH = -1.5 mA, VCC = 3V

4.3

2.2

IIL

Input Leakage

Current I/O Pin

VCC = 6V, Pin Low

(Absolute value) 8.0 µA

IIH

Input Leakage

Current I/O Pin

VCC = 6V, Pin High

(Absolute value) 8.0 µA

MSB

LSB

SERIAL CLOCK INPUT

PB1(SCK)

SERIAL DATA INPUT

PE0(PDI/RXD)

SERIAL DATA OUTPUT

PE1(PDO/TXD)

SAMPLE

ATmega103/103L

106

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.

2. “Min” means the lowest value where the pin is guaranteed to be read as high.

3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V) under steady state

conditions (non-transient), the following must be observed:

1] The sum of all IOL, for all ports, should not exceed 400 mA.

2] The sum of all IOL, for ports A0-A7, ALE, C3-C7 should not exceed 100 mA.

3] The sum of all IOL, for ports C0-C2, RD, WR, D0-D7, XTAL2 should not exceed 100 mA.

4] The sum of all IOL, for ports B0-B7, should not exceed 100 mA.

5] The sum of all IOL, for ports E0-E7, should not exceed 100 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

4. Although each I/O port can source more than the test conditions (3mA at VCC = 5V, 1.5mA at VCC = 3V) under steady state

conditions (non-transient), the following must be observed:

1] The sum of all IOH, for all ports, should not exceed 400 mA.

2] The sum of all IOH, for ports A0-A7, ALE, C3-C7 should not exceed 100 mA.

3] The sum of all IOH, for ports C0-C2, RD, WR, D0-D7, XTAL2 should not exceed 100 mA.

4] The sum of all IOH, for ports B0-B7, should not exceed 100 mA.

5] The sum of all IOH, for ports E0-E7, should not exceed 100 mA.

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

5. Minimum VCC for Power-down is 2V.

RRST Reset Pull-up 100 500 kΩ

RI/O I/O Pin Pull-up 35 120 kΩ

ICC Power Supply Current Active 4 MHz, VCC = 3V 5.0 mA

Idle 4 MHz, VCC = 3V 2.0 mA

Power-down(5), VCC = 3V

WDT Enabled 40.0 µA

Power-down(5), VCC = 3V

WDT Disabled 25.0 µA

Power Save(5), VCC = 3V

WDT Disabled 35.0 µA

VACIO

Analog Comp

Input Offset V

VCC = 5V

VIN = VCC/2 40 mV

IACLK

Analog Comp

Input Leakage A

VCC = 5V

VIN = VCC/2 -50 50 nA

tACPD

Analog Comparator

Propagation Delay

VCC = 2.7V

VCC = 4.0V

750

500 ns

DC Characteristics (Continued)

TA = -40°C to 85°C, VCC = 2.7V to 3.6V and 4.0V to 5.5V (unless otherwise noted)

Symbol Parameter Condition Min Typ Max Units

ATmega103/103L

107

External Data Memory Timing

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 45. External Data Memory Characteristics, 4.0 - 6.0 Volts, No Wait State

Symbol Parameter

6 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 6.0 MHz

LHLL ALE Pulse Width 48.3 0.5tCLCL - 35.0(1) ns

AVLL Address Valid A to ALE Low 43.3 0.5tCLCL - 40.0(1) ns

3a tLLAX_ST

Address Hold after ALE Low,

ST/STD/STS Instructions 77.3 0.5tCLCL - 10.0(2) ns

3b tLLAX_LD

Address Hold after ALE Low,

LD/LDD/LDS Instructions 15.0 15.0 ns

AVLLC Address Valid C to ALE Low 43.3 0.5tCLCL - 40.0(1) ns

AVRL Address Valid to RD Low 136.7 1.0tCLCL - 30.0 ns

AVWL Address Valid to WR Low 215.0 1.5tCLCL - 35.0(1) ns

LLWL ALE Low to WR Low 146.7 186.7 1.0tCLCL - 20.0 1.0tCLCL + 20.0 ns

LLRL ALE Low to RD Low 146.7 186.7 0.5tCLCL - 20.0(2) 0.5tCLCL + 20.0(2) ns

DVRH Data Setup to RD High 65.0 65.0 ns

10 tRLDV Read Low to Data Valid 136.7 1.0tCLCL - 30.0 ns

11 tRHDX Data Hold after RD High 0.0 0.0 ns

12 tRLRH RD Pulse Width 146.7 1.0tCLCL - 20.0 ns

13 tDVWL Data Setup to WR Low 53.3 0.5tCLCL - 30.0(2) ns

14 tWHDX Data Hold after WR High 0.0 0.0 ns

15 tDVWH Data Valid to WR High 146.7 1.0tCLCL - 20.0 ns

16 tWLWH WR Pulse Width 63.3 0.5tCLCL - 20.0(1) ns

Table 46. External Data Memory Characteristics, 4.0 - 6.0 Volts, 1 Cycle Wait State

Symbol Parameter

6 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 6.0 MHz

10 tRLDV Read Low to Data Valid 303.4 2.0tCLCL - 30.0 ns

12 tRLRH RD Pulse Width 313.4 2.0tCLCL - 20.0 ns

15 tDVWH Data Valid to WR High 313.4 2.0tCLCL - 20.0 ns

16 tWLWH WR Pulse Width 230.0 1.5tCLCL - 20.0(2) ns

ATmega103/103L

108

Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.

2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 47. External Data Memory Characteristics, 2.7 - 3.6 Volts, No Wait State

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 4.0 MHz

LHLL ALE Pulse Width 65.0 0.5tCLCL - 60.0(1) ns

AVLL Address Valid A to ALE Low 75.0 0.5tCLCL - 50.0(1) ns

3a tLLAX_ST

Address Hold after ALE Low,

ST/STD/STS Instructions 125.0 0.5tCLCL(2) ns

3b tLLAX_LD

Address Hold after ALE Low,

LD/LDD/LDS Instructions 15.0 15.0 ns

AVLLC Address Valid C to ALE Low 75.0 0.5tCLCL - 50.0(1) ns

AVRL Address Valid to RD Low 205.0 1.0tCLCL - 45.0 ns

AVWL Address Valid to WR Low 325.0 1.5tCLCL - 50.0(1) ns

LLWL ALE Low to WR Low 230.0 270.0 1.0tCLCL - 20.0 1.0tCLCL + 20.0 ns

LLRL ALE Low to RD Low 105.0 145.0 0.5tCLCL - 20.0(2) 0.5tCLCL + 20.0(2) ns

DVRH Data Setup to RD High 110.0 110.0 ns

10 tRLDV Read Low to Data Valid 210.0 1.0tCLCL - 40.0 ns

11 tRHDX Data Hold after RD High 0.0 0.0 ns

12 tRLRH RD Pulse Width 230.0 1.0tCLCL - 20.0 ns

13 tDVWL Data Setup to WR Low 90.0 0.5tCLCL - 35.0(1) ns

14 tWHDX Data Hold after WR High 0.0 0.0 ns

15 tDVWH Data Valid to WR High 230.0 1.0tCLCL - 20.0 ns

16 tWLWH WR Pulse Width 100.0 0.5tCLCL - 25.0(2) ns

Table 48. External Data Memory Characteristics, 2.7 - 3.6 Volts, 1 Cycle Wait State

Symbol Parameter

4 MHz Oscillator Variable Oscillator

UnitMin Max Min Max

01/t

CLCL Oscillator Frequency 0.0 4.0 MHz

10 tRLDV Read Low to Data Valid 460.00 2.0tCLCL - 40.0 ns

12 tRLRH RD Pulse Width 480.0 2.0tCLCL - 20.0 ns

15 tDVWH Data Valid to WR High 480.0 2.0tCLCL - 20.0 ns

16 tWLWH WR Pulse Width 350.0 1.5tCLCL - 25.0(2) ns

ATmega103/103L

109

Figure 78. External RAM Timing

External Clock Drive Waveforms

Figure 79. External Clock Drive Waveforms

Note: See “External Data Memory Timing” on page 107 for a description of how the duty cycle influences the timing for the External

Data Memory.

Table 49. External Clock Drive

Symbol Parameter VCC = 2.7V to 3.6V VCC = 4.0V to 5.5V Units

1/tCLCL Oscillator Frequency 0 4 0 6 MHz

tCLCL Clock Period 250 167 ns

tCHCX High Time 100 67 ns

tCLCX Low Time 100 67 ns

tCLCH Rise Time 1.6 0.5 µs

tCHCL Fall Time 1.6 0.5 µs

System Clock Ø

ALE

Data / Address [7..0]

Address [15..8]

Address

T1 T2 T3 T4

Prev. Address

213

Note: Clock cycle T3 is only present when external SRAM Wait State is enabled.

Data

WriteRead

Addr.

VIL1

VIH1

ATmega103/103L

110

Typical Characteristics

The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption

measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. All pins on Port F

pulled high externally. A sine wave generator with rail-to-rail output is used as clock source.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O

pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and

frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance,

VCC = operating voltage and f = average switching frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequen-

cies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog timer enabled and Power-down mode

with Watchdog timer disabled represents the differential current drawn by the Watchdog timer.

Figure 80. Active Supply Current vs. Frequency

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

ACTIVE SUPPLY CURRENT vs. FREQUENCY

T = 25˚C

Frequency (MHz)

(mA)

= 5.5V

= 5V

= 2.7V

= 3.0V

= 3.3V

= 3.6V

= 4V

= 4.5V

= 6V

ATmega103/103L

111

Figure 81. Active Supply Current vs. VCC

Figure 82. Idle Supply Current vs. Frequency

2 2.5 3 3.5 4 4.5 5 5.5 6

ACTIVE SUPPLY CURRENT vs. Vcc

FREQUENCY = 4 MHz

Icc

(mA)

Vcc(V)

T = 85˚C

T = 25˚C

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

= 6V

= 5.5V

= 5V

= 4.5V

= 4V

= 3.6V

= 3.3V

= 3.0V

= 2.7V

IDLE SUPPLY CURRENT vs. FREQUENCY

= 25˚CTA

Frequency (MHz)

(mA)

ATmega103/103L

112

Figure 83. Idle Supply Current vs. VCC

Figure 84. Power-down Supply Current vs. VCC

2 2.5 3 3.5 4 4.5 5 5.5 6

T = 25˚C

T = 85˚C

IDLE SUPPLY CURRENT vs. Vcc

Icc

(mA)

Vcc(V)

FREQUENCY = 4 MHz

2 2.5 3 3.5 4 4.5 5 5.5 6

T = 85˚C

T = 25˚C

POWER-DOWN SUPPLY CURRENT vs. Vcc

Icc (µA)

Vcc(V)

WATCHDOG TIMER DISABLED

T = 45˚C

T = 70˚C

ATmega103/103L

113

Figure 85. Power-down Supply Current vs. VCC

Figure 86. Power Save Supply Current vs. VCC

100

150

200

250

2 2.5 3 3.5 4 4.5 5 5.5 6

T = 85˚C

T = 25˚C

POWER-DOWN SUPPLY CURRENT vs. Vcc

Icc (µA)

Vcc(V)

WATCHDOG TIMER ENABLED

T = 85˚C

POWER SAVE SUPPLY CURRENT vs. Vcc

Icc (µA)

Vcc(V)

WATCHDOG TIMER DISABLED

T = 25˚C

2 2.5 3 3.5 4 4.5 5 5.5 6

ATmega103/103L

114

Figure 87. Analog Comparator Current vs. VCC

Analog comparator offset voltage is measured as absolute offset.

Figure 88. Analog Comparator Offset Voltage vs. Common Mode Voltage

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

2 2.5 3 3.5 4 4.5 5 5.5 6

ANALOG COMPARATOR CURRENT vs. Vcc

Icc

(mA)

Vcc(V)

T = 25˚C

T = 85˚C

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

ANALOG COMPARATOR OFFSET VOLTAGE vs.

V = 5V

COMMON MODE VOLTAGE

Common Mode Voltage (V)

Offset Voltage (mV)

T = 85˚C

T = 25˚C

ATmega103/103L

115

Figure 89. Analog Comparator Offset Voltage vs. Common Mode Voltage

Figure 90. Analog Comparator Input Leakage Current

0 0.5 1 1.5 2 2.5 3

ANALOG COMPARATOR OFFSET VOLTAGE vs.

COMMON MODE VOLTAGE

Common Mode Voltage (V)

Offset Voltage (mV)

V = 2.7V

T = 85˚C

T = 25˚C

-10

0 0.5 1.51 2 2.5 3.53 4 4.5 5 6 6.5 75.5

ANALOG COMPARATOR INPUT LEAKAGE CURRENT

T = 25˚C

I (nA)

ACLK

V (V)

V = 6V

ATmega103/103L

116

Figure 91. Watchdog Oscillator Frequency vs. VCC

Sink and source capabilities of I/O ports are measured on one pin at a time.

Figure 92. Pull-up Resistor Current vs. Input Voltage

200

400

600

800

1000

1200

1400

1600

2 2.5 3 3.5 4 4.5 5 5.5 6

T = 85˚C

T = 25˚C

WATCHDOG OSCILLATOR FREQUENCY vs. Vcc

V (V)

F (KHz)

100

120

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V = 5V

I (µA)

V (V)

T = 85˚C

T = 25˚C

ATmega103/103L

117

Figure 93. Pull-up Resistor Current vs. Input Voltage

Figure 94. I/O Pin Sink Current vs. Output Voltage

0 0.5 1 1.5 2 2.5 3

PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

I (µA)

V (V)

V = 2.7V

T = 85˚C

T = 25˚C

0 0.5 1 1.5 2 2.5 3

V = 5V

I (mA)

V (V)

T = 85˚C

T = 25˚C

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

ATmega103/103L

118

Figure 95. I/O Pin Source Current vs. Output Voltage

Figure 96. I/O Pin Sink Current vs. Output Voltage

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

V = 5V

I (mA)

V (V)

T = 85˚C

T = 25˚C

0 0.5 1 1.5 2

I (mA)

V (V)

T = 85˚C

T = 25˚C

I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE

V = 2.7V

ATmega103/103L

119

Figure 97. I/O Pin Source Current vs. Output Voltage

Figure 98. I/O Pin Input Threshold Voltage vs. VCC

0 0.5 1 1.5 2 2.5 3

I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE

I (mA)

V (V)

T = 85˚C

T = 25˚C

V = 2.7V

0.5

1.5

2.5

2.7 4.0 5.0

Threshold Voltage (V)

I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc

T = 25˚C

ATmega103/103L

120

Figure 99. I/O Pin Input Hysteresis vs. VCC

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

2.7 4.0 5.0

Input Hysteresis (V)

I/O PIN INPUT HYSTERESIS vs. Vcc

T = 25˚C

ATmega103/103L
121
Note: For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses 
should never be written. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instruc-
tions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and 
SBI instructions work with registers $00 to $1F only.
Register Summary
Address Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Page
$3F ($5F)   SREG I T H S V N Z C page 21
$3E ($5E)   SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 page 21
$3D ($5D)   SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 21
$3C ($5C)   XDIV XDIVEN XDIV6 XDIV5 XDIV4 XDIV3 XDIV2 XDIV1 XDIV0 page 23
$3B ($5B)   RAMPZ – – – – – – – RAMPZ0 page 22
$3A ($5A)   EICR ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 page 31
$39 ($59)   EIMSK INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 page 30
$38 ($58)   EIFR INTF7 INTF6 INTF5 INTF4 – – – – page 30
$37 ($57)   TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 page 31
$36 ($56)   TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 page 32
$35 ($55)   MCUCR SRE SRW SE SM1 SM0 – – – page 22
$34 ($54)   MCUSR – – – – – – EXTRF PORF page 29
$33 ($53)   TCCR0 –PWM0 COM01 COM00 CTC0 CS02 CS01 CS00 page 38 
$32 ($52)   TCNT0  Timer/Counter0 (8-bit) page 39 
$31 ($51)   OCR0  Timer/Counter0 Output Compare Register page 40
$30 ($50)   ASSR – – – – AS0 TCN0UB OCR0UB TCR0UB page 41
$2F ($4F)   TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – – PWM11 PWM10 page 45
$2E ($4E)   TCCR1B ICNC1 ICES1 – – CTC1 CS12 CS11 CS10 page 46
$2D ($4D)   TCNT1H  Timer/Counter1 – Counter Register High Byte page 47
$2C ($4C)   TCNT1L  Timer/Counter1 – Counter Register Low Byte page 47
$2B ($4B)   OCR1AH  Timer/Counter1 – Output Compare Register A High Byte page 48
$2A ($4A)   OCR1AL  Timer/Counter1 – Output Compare Register A Low Byte page 48
$29 ($49)   OCR1BH  Timer/Counter1 – Output Compare Register B High Byte page 48
$28 ($48)   OCR1BL  Timer/Counter1 – Output Compare Register B Low Byte page 48
$27 ($47)   ICR1H  Timer/Counter1 – Input Capture Register High Byte page 48
$26 ($46)   ICR1L  Timer/Counter1 – Input Capture Register Low Byte page 48
$25 ($45)   TCCR2 –PWM2 COM21 COM20 CTC2 CS22 CS21 CS20 page 38
$24 ($44)   TCNT2  Timer/Counter2 (8-bit) page 39
$23 ($43)   OCR2  Timer/Counter2 Output Compare Register page 40
$21 ($47)   WDTCR –– – WDTOE WDE WDP2 WDP1 WDP0 page 51
$1F ($3F)   EEARH –– – – EEAR11 EEAR10 EEAR9 EEAR8 page 52
$1E ($3E)   EEARL  EEPROM Address Register L page 52
$1D ($3D)   EEDR  EEPROM Data Register page 53
$1C ($3C)   EECR – – – – EERIE EEMWE EEWE EERE page 53
$1B  ($3 B )   PORTA PORTA 7 P O RTA 6 P ORTA 5 P ORTA 4 P O RTA3 P O RTA2 P O RTA 1 P O RTA 0 page 7 5
$1A ($3A)   DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 page 75
$19 ($39)   PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 page 75
$18 ($38)   PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 77
$17 ($37)   DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 77
$16 ($36)   PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 77
$15 ($35)   PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 page 82
$12 ($32)   PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 page 83
$11 ($31)   DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 page 84
$10 ($30)   PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 page 84
$0F ($2F)   SPDR  SPI Data Register page 58
$0E ($2E)   SPSR SPIF WCOL – – – – – – page 58
$0D ($2D)   SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 page 57
$0C ($2C)   UDR  UART I/O Data Register page 62
$0B ($2B)   USR RXC TXC UDRE FE OR – – – page 62
$0A ($2A)   UCR RXCIE TXCIE UDRIE RXEN TXEN CHR9 RXB8 TXB8 page 63
$09 ($29)   UBRR  UART Baud Rate Register page 65
$08 ($28)   ACSR ACD –ACO ACI ACIE ACIC ACIS1 ACIS0 page 65
$07 ($27)   ADMUX – – – – – MUX2 MUX1 MUX0 page 69
$06 ($26)   ADCSR ADEN ADSC –ADIF ADIE ADPS2 ADPS1 ADPS0 page 70
$05 ($25)   ADCH – – – – – – ADC9 ADC8 page 71
$04 ($24)   ADCL ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 page 71
$03 ($23)   PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 page 87
$02 ($22)   DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 page 87
$01 ($21)   PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 page 87
$00 ($20)   PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 page 91

ATmega103/103L

122

Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl, K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl, K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,H 1

SBR Rd, K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd, K Clear Bit(s) in Register Rd ← Rd • ($FF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd - 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← $FF None 1

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

JMP k Direct Jump PC ← kNone3

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

ICALL Indirect Call to (Z) PC ← ZNone3

CALL k Direct Subroutine Call PC ← kNone4

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd, Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3

CP Rd, Rr Compare Rd - Rr Z,N,V,C,H 1

CPC Rd, Rr Compare with Carry Rd - Rr - C Z,N,V,C,H 1

CPI Rd, K Compare Register with Immediate Rd - K Z,N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b) = 1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b) = 0) PC ← PC + 2 or 3 None 1/2/3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b) = 1) PC ← PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1 None 1/2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V = 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V = 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1/2

ATmega103/103L

123

DATA TRANSFER INSTRUCTIONS

ELPM Extended Load Program Memory R0 ← (Z+RAMPZ) None 3

MOV Rd, Rr Move between Registers Rd ← Rr None 1

LDI Rd, K Load Immediate Rd ← KNone1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-increment Rd ← (X), X ← X + 1 None 2

LD Rd, -X Load Indirect and Pre-decrement X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-increment Rd ← (Y), Y ← Y + 1 None 2

LD Rd, -Y Load Indirect and Pre-decrement Y ← Y - 1, Rd ← (Y) None 2

LDD Rd, Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-increment Rd ← (Z), Z ← Z+1 None 2

LD Rd, -Z Load Indirect and Pre-decrement Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post-increment (X) ← Rr, X ← X + 1 None 2

ST -X, Rr Store Indirect and Pre-decrement X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post-increment (Y) ← Rr, Y ← Y + 1 None 2

ST -Y, Rr Store Indirect and Pre-decrement Y ← Y - 1, (Y) ← Rr None 2

STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-increment (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-decrement Z ← Z - 1, (Z) ← Rr None 2

STD Z+q, Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

IN Rd, P In Port Rd ← PNone1

OUT P, Rr Out Port P ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from Stack Rd ← STACK None 2

BIT AND BIT-TEST INSTRUCTIONS

SBI P, b Set Bit in I/O Register I/O(P,b) ← 1None2

CBI P, b Clear Bit in I/O Register I/O(P,b) ← 0None2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left through Carry Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7) Z,C,N,V 1

ROR Rd Rotate Right through Carry Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n = 0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit Load from T to Register Rd(b) ← TNone1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow V ← 1V1

CLV Clear Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1H1

CLH Clear Half Carry Flag in SREG H ← 0 H 1

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep function) None 3

WDR Watchdog Reset (see specific descr. for WD timer) None 1

Instruction Set Summary (Continued)

Mnemonics Operands Description Operation Flags #Clocks

ATmega103/103L

124

Ordering Information

Speed (MHz) Power Supply Ordering Code Package Operation Range

4 2.7 - 3.6V ATmega103L-4AC 64A Commercial

(0°C to 70°C)

ATmega103L-4AI 64A Industrial

(-40°C to 85°C)

6 4.0 - 5.5V ATmega103-6AC 64A Commercial

(0°C to 70°C)

ATmega103-6AI 64A Industrial

(-40°C to 85°C)

Package Type

64A 64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

ATmega103/103L

125

Packaging Information

*Controlling dimension: millimeters

PIN 1 ID

0.80(0.031) BSC

16.25(0.640) SQ

15.75(0.620)

0.45(0.018)

0.30(0.012)

14.10(0.555)

13.90(0.547) 1.20 (.047) MAX

0.15(0.006)

0.05(0.002 )

0.75(0.030)

0.45(0.018)

0-7

0.20(0.008)

0.10(0.004)

64A, 64-lead, Thin (1.0 mm) Plastic Gull Wing Quad

Flat Package (TQFP)

Dimensions in Millimeters and (Inches)*

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