PJClamp0502Q
PRELIMINARY
DUAL ULTRA LOW CAPACITANCE ESD PROTECTOR ARRAY
SPECIFICATION FEATURES
APPLICATIONS
MAXIMUM RATINGS (Per Device)
Rating Symbol Value Units
This Dual Unidirectional ESD Protector Array family have been designed to protect
sensitive equipment against ESD in high speed transmission buses, operating at
5V and demanding the lowest insertion loss. This array offers an integrated
solution to protect up to 2 data lines in applications, where the board space is a
premium, in a Quad Flat no-Lead package that only occupies an area of 1.8 sq mm.
Peak Power Dissipation of 40W 8/20µs Waveform
Low Leakage Current, Maximum of 1µA at rated voltage
IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance
Maximum Capacitance of 1pF per device at 0Vdc 1MHz
USB2.0 and IEEE 1394 Firewire Ports
RF Power Amplifier Protection
ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C
Parameter Symbol Min Unit
s
Conditions Typical Max
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
Off State Junction Capacitance
VWRM
VBR
IR
c
V
Cj
BR
I =
R
V =
I =
pp
0 Vdc Bias f = 1MHz
between 4&2 or 6&2
5V
6V
µA1
12 V
1pF
1mA
5V
3A
40
3
25
-55 to +150
W
A
kV
°C
Peak Pulse Power (8/20µs Waveform)
ESD Voltage (HBM Per MIL STD883C - Method 3015-6)
Operating Temperature Range
PPP
VESD
TJ
Tstg
1/25/2006 Page 1www.panjit.com
Quad Flat No Lead package QFN (1.2x1.5 sq mm, Height: 0.75mm)
RF/Antenna Circuits
Storage Temperature Range
Lead Free Package 100% Tin Plating, Matte finish
11
°C
-55 to +150
Peak Pulse Current (8/20µs Waveform) IPPM
123
654
123
654
2
1
4
5
6
3
QFN 1.2x1.5 sq mm
1
2
3
4
8 8.5 9 9.5 10 10.5 11 11.5 12
Clamping Voltage, V
Ipp, Amps
www.panjit.com
PJClamp0502Q
PRELIMINARY
1/25/2006 Page 2
TYPICAL CHARACTERISTIC CURVES (Per Device) Tj = 25°C
Pulse W a veform
0
10
20
30
40
50
60
70
80
90
100
110
0 5 10 15 20 25 30
time, µsec
P er cen t of Ip p
50% o f Ipp @ 20µs
Rise time 10-90% - 8µs
Clamping Voltage vs 8/20µs Ipp
Typical Capacitance vs. Bias Vo ltage @1MHz
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
012345
Bias Voltage, Vdc
Capacitance, pF
PRELIMINARY
1/25/2006 Page 3 www.panjit.com
PACKAGE DIMENSIONS AND SUGGESTED PAD LAYOUT
PJClamp0502Q
1.5±0.05 mm
1.2±0.05 mm
0.5mm
0.20±0.05 mm
0.30±0.05 mm
22.04 mm
0.35±0.05 mm
0.6±0.05 mm
0.75±0.025 mm
0.2±0.025 mm
Suggested Pad Layout (in mils) Alternate Pad Layout SOT523 (in mils)
12.0
49.0
19.7
25.0
23.0 55 mil24 mil
16 mil
31 mil
39 mil
