UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
TRANSITION MODE PFC CONTROLLER
1
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FEATURES
DTransition Mode PFC Controller for Low
Implementation Cost
DIndustry Pin Compatibility With Improved
Feature Set
DImproved Transient Response With
Slew-Rate Comparator
DZero Power Detect to Prevent OVP During
Light Load Conditions
DAccurate Internal VREF for Tight Output
Regulation
DTwo UVLO Options
DOvervoltage Protection (OVP),
Open-Feedback Protection and Enable
Circuits
D± 750-mA Peak Gate Drive Current
DLow Start-Up and Operating Currents
DLead (Pb)-Free Packages
APPLICATIONS
DSwitch-Mode Power Supplies for Desktops,
Monitors, TVs and Set Top Boxes (STBs)
DAC Adapter Front-End Power Supplies
DElectronic Ballasts
DESCRIPTION
The UCC38050 and UCC38051 are PFC
controllers for low-to-medium power applications
requiring compliance with IEC 1000-3-2 harmonic
reduction standard. It is designed for controlling a
boost preregulator operating in transition mode
(also referred to as boundary conduction mode or
critical conduction mode operation). It features a
transconductance voltage amplifier for feedback
error processing, a simple multiplier for
generating a current command proportional to the
input voltage, a current-sense (PWM)
comparator, PWM logic and a totem-pole driver
for driving an external FET.
SIMPLIFIED APPLICATION DIAGRAM
UDG−02125
1
2
3
4
8
7
6
5
VCC
DRV
GND
ZCD
VO_SNS
COMP
MULTIN
CS
UCC38050
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
2www.ti.com
description (continued)
In the transition mode operation, the PWM circuit is self-oscillating with the turn-on being governed by an
inductor zero-current detector (ZCD pin) and the turn-off being governed by the current-sense comparator.
Additionally, the controller provides features such as peak current limit, default timer, overvoltage protection
(OVP) and enable.
The UCC38050 and UCC38051, while being pin compatible with other industry controllers providing similar
functionality, offer many feature enhancements and tighter specifications, leading to an overall reduction in
system implementation cost. The system performance is enhanced by incorporation of zero power detect
function which allows the controller output to shut down at light load conditions without running into overvoltage.
The device also features innovative slew rate enhancement circuits which improve the large signal transient
performance of the voltage error amplifier. The low start-up and operating currents of the device results in low
power consumption and ease of start-up. Highly accurate internal bandgap reference leads to tight regulation
of output voltage in normal and OVP conditions, resulting in higher system reliability. The enable comparator
ensures that the controller is off if the feedback sense path is broken or if the input voltage is very low.
There are two key parameteric differences between UCC38050 and UCC38051. The UVLO turn-on threshold
of UCC38050 is 15.8 V while for UCC38051 it is 12.5 V. Secondly, the gM amplifier’s source current for
UCC38050 is typically 1.3 mA while for UCC38051 it is 300 μA. The higher UVLO turn-on threshold of the
UCC38050 allows quicker and easier start-up with a smaller VCC capacitance while the lower UVLO turn-on
threshold of UCC38051 allows the operation of the PFC chip to be easily controlled by the downsteam PWM
controller in two-stage power converters. The UCC38050 gM amplifier also provides a full 1.3-mA typical source
current for faster start-up and improved transient response when output is low either at start-up or during
transient conditions. The UCC38051 scales this source current back down to 300- μA typical source current to
gradually increase the error voltage preventing a step increase in line currents at start-up but still provides good
transient response. The UCC38051 is suitable for multiple applications including AC adapters where a
two-stage power conversion is needed. The UCC38050 is suitable for applications such as electronic ballasts
where there is no down-stream PWM conversion and the advantages of smaller VCC capacitor and improved
transient response can be realized.
Devices are available in either the industrial temperature range of –40°C to 105°C (UCC2805x) or commercial
temperature range of 0°C to 70°C (UCC3805x). Package offerings are 8-pin SOIC (D) or 8-pin PDIP (P)
packages.
ORDERING INFORMATION
T T
UVLO Threshold
Voltage ON/OFF
gM Amplifier
Source Current
Packaged Devices(1)
TA = TJVoltage ON/OFF
(V)
Source Current
(μA) SOIC-8 (D) PDIP-8 (P)
40°C to 105°C
15.8 / 9.7 −1300 UCC28050D UCC28050P
−40°C to 105°C12.5 / 9.7 −300 UCC28051D UCC28051P
0°Cto70°C
15.8 / 9.7 −1300 UCC38050D UCC38050P
0°C to 70°C12.5 / 9.7 −300 UCC38051D UCC38051P
(1) D (SOIC-8) package is available taped and reeled. Add R suffix to device type (e.g.
UCC28050DR) to order quantities of 2,500 devices per reel.
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
3
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CONNECTION DIAGRAM
(TOP VIEW)
GND
DRV
VCC
ZCD
COMP
VO_SNS
MULTIN
CS
1
2
3
4
8
7
6
5
D or P PACKAGE
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UCCx805x UNIT
Supply voltage, VCC (Internally clamped) 20 V
Input current into VCC clamp IDD 30
Input current ZCD ±10 mA
Gate drive current (peak), IDRV DRV ±750
mA
Input voltage range, VCC VO_SNS, MULTIN, CS 5
V
Maximum negative voltage VO_SNS, MULTIN, DRV, CS −0.5 V
Power dissipation at T 50°C
D package 650 mW
Power dissipation at TA= 50°CP package 1 W
Operating junction temperature range, TJ−55 to 150
Storage temperature, Tstg −65 to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300
C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to
GND. Currents are positive into, negative out of the specified terminal.
THERMAL RATINGS
SO8 (D) DIP (P) UNIT
RθJA Max. thermal resistance junction to ambient 150 100 °C/WV
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
4www.ti.com
ELECTRICAL CHARACTERISTICS
TA = 0_C to 70_C for the UCC3805x, –40_C to 105_C for the UCC2805x, TA = TJ, VCC = 12 V.
supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
VCC operating voltage 18
V
Shunt voltage IVCC = 25 mA 18 19 20 V
Supply current, off VCC = VCC turn−on threshold –300 mV 75 125 μA
Supply current, disabled VO_SNS = 0.5 V 2 4
Supply current, on 75 kHz, CL = 0 nF 4 6 mA
Supply current, dynamic operating 75 kHz, CL = 1 nF 5 7
mA
UVLO
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Vturn on threshold
UCCx8050 15.4 15.8 16.4
VCC turn-on threshold UCCx8051 12.0 12.5 13.0
VCC turn-off threshold 9.4 9.7 10.0 V
UVLO hysteresis
UCCx8050 5.8 6.3 6.8
V
UVLO hysteresis UCCx8051 2.3 2.8 3.3
voltage amplifier (VO_SNS)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Input voltage (V )
UCC3805x 2.46 2.50 2.54
V
Input voltage (VREF)UCC2805x 2.45 2.50 2.55 V
Input bias current 0.5 μA
VCOMP high VO_SNS = 2.1 V 4.5 5.5
V
VCOMP low VO_SNS = 2.55 V 1.80 2.45 V
gMTJ = 25 _C, VCOMP= 3.5 V 60 90 130 μS
Source current
UCCx8050 VO_SNS = 2.1 V, VCOMP= 3.5 V −0.2 −1.0 mA
Source current UCCx8051 VO_SNS = 2.1 V, VCOMP= 2.5 V −200 −300 −400 μA
Sink current VO_SNS = 2.7 V VCOMP= 3.5 V 0.2 1.0 mA
over voltage protection / enable
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Overvoltage reference
UCCx8050 VREF +
0.165
VREF +
0.190
VREF +
0.210
V
Overvoltage reference
UCCx8051 VREF +
0.150
VREF +
0.180
VREF +
0.210
V
Hysteresis
UCCx8050 175 200 225
mV
Hysteresis UCCx8051 150 180 210 mV
Enable threshold
UCCx8050 0.62 0.67 0.72 V
Enable threshold UCCx8051 0.18 0.23 0.28 V
Enable hysteresis 0.05 0.10 0.20 V
multiplier
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Multiplier gain constant (k) VMULTIN = 0.5 V, COMP = 3.5 V 0.43 0.65 0.87 1/V
Dynamic input range, VMULTIN INPUT 0 to 2.5 0 to 3.5 V
Dynamic input range, COMP INPUT 2.5 to 3.8 2.5 to 4.0 V
Input bias current, MULTIN 0.1 1.0 μA
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
5
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ELECTRICAL CHARACTERISTICS
TA = 0_C to 70_C for the UCC3805x, –40_C to 105_C for the UCC2805x, TA = TJ, VCC = 12 V.
zero power
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Zero power comparator threshold(1) Measured on VCOMP 2.1 2.3 2.5 V
zero current detect
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Input threshold (rising edge) (1) 1.5 1.7 2.0 V
Hysteresis(1) 250 350 450 mV
Input high clamp I = 3 mA 5 6 V
Input low clamp I = −3 mA 0.30 0.65 0.90 V
Restart time delay 200 400 μs
current sense comparator
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Input bias current CS = 0 V 0.1 1.0 μA
Input offset voltage(1) −10 10 mV
Delay to output CS to DRV 300 450 ns
Maximum current sense threshold voltage 1.55 1.70 1.80 V
PFC gate driver
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
GT1 pull up resistance IOUT = –125 mA 5 12 Ω
GT1 pull down resistance IOUT = 125 mA 2 10 Ω
GT1 output rise time CLOAD = 1 nF, RLOAD = 10 Ω25 75 ns
GT1 output fall time CLOAD = 1 nF, RLOAD = 10 Ω10 50 ns
(1) Ensured by design. Not production tested.
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
6www.ti.com
BLOCK DIAGRAM
UDG−02008
1
2
5
6
7
8
3
4
40 kW
5 pF
+
+
+
x
xMULT
2.5 V
2.3 V
+
+OVP
ENABLE
2.7/2.5 V
gm VOL.
ERROR AMP
0.67/0.57 V
0.23/0.15 V
PWM
SQ
Q
R
+
TIMER
+
VREF
AND
BIAS REG
VREF
INT. BIAS
1.7/1.4 V
UVLO
VREF
GOOD
OVP
V0_SNS
COMP
MULTIN
CS ZCD
GND
DRV
VCCREF
ZERO
POWER
DETECT
PIN DESCRIPTIONS
VO_SNS (Pin 1): This pin senses the boost regulator output voltage through a voltage divider. Internally, this
pin is the inverting input to the transconductance amplifier (with a nominal value of 2.5 V) and also is input to
the OVP comparator. Additionally, pulling this pin below the ENABLE threshold turns off the output switching,
ensuring that the gate drive is held off while the boost output is pre-charging and also ensuring no runaway if
feedback path is open.
COMP (Pin 2): Output of the transconductance error amplifier. Loop compensation components are connected
between this pin and ground. The output current capability of this pin is 10-μA under normal conditions, but
increases to about 1-mA when the differential input is greater than the specified values in the specifications
table. This voltage is one of the inputs to the multiplier, with a dynamic input range of 2.5 V to 3.8 V. During zero
power or overvoltage conditions, this pin goes below 2.5 V nominal. When it goes below 2.3 V, the zero power
comparator is activated which prevents the gate drive from switching.
MULTIN (Pin 3): This pin senses the instantaneous boost regulator input voltage through a voltage divider. The
voltage acts as one of the inputs to the internal multiplier. Recommended operating range is 0 V to 2.5 V at high
line.
PIN DESCRIPTIONS (continued)
CS (Pin 4): This pin senses the instantaneous switch current in the boost switch and uses it as the internal ramp
for PWM comparator. The internal circuitry filters out switching noise spikes without requiring external
components. In addition, an external R-C filter may be required to suppress the noise spikes. An internal clamp
on the multiplier output terminates the switching cycle if this pin voltage exceeds 1.7 V. Additional external
filtering may be required. CS threshold is approximately equal to:
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
7
www.ti.com
VCS ^0.67 (COMP *2.5 V)ǒMULTIN )VOFFSETǓ
VOFFSET is approximately 75 mV to improve the zero crossing distortion.
ZCD (Pin 5): This pin is the input for the zero current detect comparator. The boost inductor current is indirectly
sensed through the bias winding on the boost inductor. The ZCD pin input goes low when the inductor current
reaches zero and that transition is detected. Internal active voltage clamps are provided to prevent this pin from
going below ground or too high. If zero current is not detected within 400 μs, a reset timer sets the latch and
gate drive.
GND (Pin 6): The chip reference ground. All bypassing elements are connected to ground pin with shortest loops
feasible.
DRV (Pin 7): The gate drive output for an external boost switch. This output is capable of delivering up to 750-mA
peak currents during turn-on and turn-off. An external gate drive resistor may be needed to limit the peak current
depending on the VCC voltage being used. Below the UVLO threshold, the output is held low.
VCC (Pin 8): The supply voltage for the chip. This pin should be bypassed with a high-frequency capacitor
(greater than 0.1-μF) and tied to GND. The UCC38050 has a wide UVLO hysteresis of approximately 6.3 V that
allows use of lower value supply capacitor on this pin for quicker and easier start-up. The UCC38051 has a
narrow UVLO hysteresis with of about 2.8 V and a start-up voltage of about 12.5 V for applications where the
operation of the PFC device needs to be controlled by a downstream PWM controller.
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
8www.ti.com
BLOCK DESCRIPTION
UVLO and Reference Block
This block generates a precision reference voltage used to obtain tightly controlled UVLO threshold. In addition
to generating a 2.5-V reference for the non-inverting terminal of the gM amplifier, it generates the reference
voltages for blocks such as OVP, enable, zero power and multiplier. An internal rail of 7.5 V is also generated
to drive all the internal blocks.
Error Amplifier
The voltage error amplifier in UCC3805x is a transcoductance amplifier with a typical transconductance value
of 90 μS. The advantage in using a transconductance amplifier is that the inverting input of the amplifier is solely
determined by the external resistive-divider from the output voltage and not the transient behavior of the
amplifier itself. This allows the VO_SNS pin to be used for sensing over voltage conditions.
The sink and source capability of the error amplifier is approximately 10 μA during normal operation of the
amplifier. But when the VO_SNS pin voltage is beyond the normal operating conditions (VO_SNS >1.05 ×VREF
,
VO_SNS < 0.88 × VREF), additional circuitry to enhance the slew-rate of the amplifier is activated. Enhanced
slew-rate of the compensation capacitor results in a faster start-up and transient response. This prevents the
output voltage from drifting too high or too low, which can happen if the compensation capacitor were to be
slewed by the normal slewing current of 10-μA. When VO_SNS rises above the normal range, the enhanced
sink current capability is in excess of 1 mA. When VO_SNS falls below the normal range, the UCC38050 can
source more than 1 mA and the UCC38051 sources approximately 300 μA. The limited source current in the
UCC38051 helps to gradually increase the error voltage on the COMP pin preventing a step increase in line
current. The actual rate of increase of VCOMP depends on the compensation network connected to the COMP
pin.
Zero Current Detection and Re-Start Timer Blocks
When the boost inductor current becomes zero, the voltage at the power MOSFET drain end falls. This is
indirectly sensed with a secondary winding that is connected to the ZCD pin. The internal active clamp circuitry
prevents the voltage from going to a negative or a high positive value. The clamp has the sink and source
capability of 10 mA. The resistor value in series with the secondary winding should be chosen to limit the ZCD
current to less than 10 mA. The rising edge threshold of the ZCD comparator can be as high as 2.0 V. The
auxiliary winding should be chosen such that the positive voltage (when the power MOSFET is off) at the ZCD
pin is in excess of 2.0 V.
The restart timer attempts to set the gate drive high in case the gate drive remains off for more than 400 μs
nominally. The minimum guaranteed time period of the timer is 200 μs. This translates to a minimum switching
frequency of 5 kHz. In other words, the boost inductor value should be chosen for switching frequencies greater
than 5 kHz.
Enable Block
The gate drive signal is held low if the voltage at the VO_SNS pin is less than the ENABLE threshold. This feature
can be used to disable the converter by pulling VO_SNS low. If the output feedback path is broken, VO_SNS
is pulled to ground and the output is disabled to protect the power stage.
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
9
www.ti.com
BLOCK DESCRIPTION (continued)
Zero Power Block
When the output of the gM amplifier goes below 2.3 V, the zero power comparator latches the gate drive signal
low. The slew rate enhancement circuitry of the gM amplifier that is activated during overvoltage conditions slews
the COMP pin to about 2.4 V. This ensures that the zero power comparator is not activated during transient
behavior (when the slew rate enhancement circuitry is enhanced).
Multiplier Block
The multiplier block has two inputs. One is the error amplifier output voltage (VCOMP), while the other is VMULTIN
which is obtained by a resistive divider from the rectified line. The multiplier output is approximately
0.67 ×VMULTIN ×(VCOMP−2.5 V). There is a positive offset of about 75 mV to the VMULTIN signal because this
improves the zero-crossing distortion and hence the THD performance of the controller in the application. The
dynamic range of the inputs can be found in the electrical characteristics table.
Overvoltage Protection (OVP) Block
The OVP feature in the part is not activated under most operating conditions because of the presence of the
slew rate enhancement circuitry present in the error amplifier. As soon as the output voltage reaches to about
5% to 7% above the nominal value, the slew rate enhancement circuit is activated and the error amplifier output
voltage is pulled below the dynamic range of the multiplier block. This prevents further rise in output voltage.
If the COMP pin is not pulled low fast enough, and the voltage rises further, the OVP circuit acts as a second
line of protection. When the voltage at the VO_SNS pin is more than 7.5% of the nominal value
( >(VREF+0.190)), the OVP feature is activated. It stops the gate drive from switching as long as the voltage at
the VO_SNS pin is above the nominal value (VREF). This prevents the output dc voltage from going above 7.5%
of the nominal value designed for, and protects the switch and other components of the system like the boost
capacitor.
Transition Mode Control
The boost converter, the most common topology used for power factor correction, can operate in two modes
– continuous conduction code (CCM) and discontinuous conduction mode (DCM). Transition mode control, also
referred to as critical conduction mode (CRM) or boundary conduction mode, maintains the converter at the
boundary between CCM and DCM by adjusting the switching frequency.
The CRM converter typically uses a variation of hysteretic control with the lower boundary equal to zero current.
It is a variable frequency control technique that has inherently stable input current control while eliminating
reverse recovery rectifier losses. As shown in Figure 1, the switch current is compared to the reference signal
(output of the multiplier) directly. This control method has the advantage of simple implementation and still can
provide very good power factor correction.
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
10 www.ti.com
TYPICAL APPLICATION DIAGRAM
UDG−02008
1
2
5
6
7
8
3
4
40 k Ω
5 pF
+
+
+
x
xMULT
2.5 V
2.3 V
+
+OVP
ENABLE
2.7/2.5 V
0.67/0.57 V (50)
PWM
SQ
Q
R
+
TIMER
+
VREF
INT. BIAS
1.7 V/1.4 V
UVLO
VREF
GOOD
OVP
VO_SNS
COMP
MULTIN
CS ZCD
GND
DRV
VCC
+
LRG1
RS1
COUT
RUP
RAC1
RO2
RV1
CV1
RAC2
CV2
RV1
ZERO
POWER
DETECT
gM E/A
RO1
VREF AND
BIAS REG
÷
CB
RB
CAC1 CS1
RZC
REF
0.23/0.15 V (51)
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
11
www.ti.com
APPLICATION INFORMATION
UDG−02124
+
C
D
Load
+
RIAC
X
X
MULT
L
SQ
R
Q
Gate Driver
Logic
VAC
IAC
÷
ZCD
IMO VEA
VREF
Figure 1. Basic Block Diagram of CRM Boost PFC
The power stage equations and the transfer functions of the CRM are the same as the CCM. However,
implementations of the control functions are different. Transition mode forces the inductor current to operate
just at the border of CCM and DCM. The current profile is also different and affects the component power loss
and filtering requirements. The peak current in the CRM boost is twice the amplitude of CCM leading to higher
conduction losses. The peak-to-peak ripple is twice the average current which affects MOSFET switching
losses and magnetics ac losses.
UDG−02123
IAVERAGE
(C) CRM
(b) DCM
(a) CCM
IPEAK
IAVERAGE
IPEAK
IAVERAGE
Note: Operating Frequency >> 120 Hz
Figure 2. PFC Inductor Current Profiles
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
12 www.ti.com
APPLICATION INFORMATION
For low to medium power applications up to approximately 300 W, the CRM boost has an advantage in losses.
The filtering requirement is not severe and therefore is not a disadvantage. For medium to higher power
applications, where the input filter requirements dominate the size of the magnetics, the CCM boost is a better
choice due to lower peak currents (which reduces conduction losses) and lower ripple current (which reduces
filter requirements). The main tradeoff in using CRM boost is lower losses due to no reverse recovery in the
boost diode vs. higher ripple and peak currents.
Design Procedure
For a selected VOUT and minimum switching frequency, the following equations outline the design guidelines
for power stage component selection. Refer to the typical application diagram for reference designators.
Inductor Selection
In the transition mode control, the inductor value needs to be calculated to start the next switching cycle at zero
current. The time it takes to reach zero depends on line voltage and inductance and as shown in equation (1),
L determines the converter’s frequency range.
L+ǒVAC(min)Ǔ2
ǒVOUT *2
Ǹ VAC(min)Ǔ
2 Fs(min) VOUT PIN
where
DVAC = RMS line voltage
DVAC(min) = minimum AC line voltage
DPIN = maximum input power averaged over the ac line period
IL(peak) +2 2
Ǹ PIN
VAC(min)
IL(rms) +
IL(peak)
6
Ǹ
MOSFET Selection
The main switch selection is driven by the amount of power dissipation allowable. It is important to choose a
device that minimizes gate charge and capacitance and minimizes the sum of switching and conduction losses
at a given frequency.
IQ(rms_crm) +1
6*ǒ4 2
ǸǓ ǒVAC(min)
9p VOUTǓ
Ǹ ILPEAK(crm)
VQ(max) +VOUT
(1)
(2)
(3)
(4)
(5)
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
13
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APPLICATION INFORMATION
Diode Selection
The effects of the reverse recovery current in the diode can be eliminated with relatively little negative impact
to the system. The diode selection is based on reverse voltage, forward current, and switching speed.
ID(avg) +IOUT(avg)
ID(rms) +IL(peak)
2
Ǹ VAC
p VOUT
Ǹ
VD(peak) +VOUT
Capacitor Selection
The hold-up time is the main requirement in determining the output capacitance. ESR and the maximum RMS
ripple current rating may also be important especially at higher power levels.
COUT(min) +ǒ2 POUT tHOLDUPǓ
ǒǒVOUTǓ2
*ǒVOUT(min)Ǔ2Ǔ
where:
DVOUT(min) = minimum regulator input voltage for operation
IC(rms) +ǒIL(peak)Ǔ2
2
Ǹ VAC(max)
p VOUT *ǒPOUT
VOUTǓ2
)(ac rms load currents)2
Ǹ
Multiplier Set-Up
Select RAC1 and RAC2 so that their ratio uses the full dynamic range of the multiplier input at the peak line voltage
yet, their values are small enough to make the effects of the multiplier bias current negligible. In order to use
the maximum range of the multiplier, select the divider ratio so that VMULTIN evaluated at the peak of the
maximum ac line voltage is the maximum of the minimum dynamic input range of MULTIN, which is 2.5 V.
Choose RAC1 so that it has at least 100-μA at the peak of the minimum ac operating line voltage.
RAC1
RAC2 +ǒ2
Ǹ
2.5 VAC(max)Ǔ*1
In extreme cases, switching transients can contaminate the MULTIN signal and it can be beneficial to add
capacitor CAC1. Select the value of CAC1 so that the corner frequency of the resulting filter is greater than the
lowest switching frequency. Keep in mind that the low corner frequency of this filter may compromise the overall
power factor.
(6)
(7)
(8)
(9)
(10)
(11)
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
14 www.ti.com
APPLICATION INFORMATION
Sense Resistor Selection
The current sense resistor value must be chosen to limit the output power and it must also use the full dynamic
range of the multiplier during normal steady state operation. The value of RS1 is thus selected for maximum
power operation at low ac line voltage conditions. In order to use the full dynamic range, set the VSENSE
threshold as a function of the dynamic input range of VCOMP and the peak of the minimum MULTIN voltage.
RS1 +
0.67 ǒCOMP(MAX) *COMP(MIN)Ǔ ǒMULTIN(PEAK)@VAC(min) *0.075Ǔ
2 2
Ǹ
PIN(max)
VAC(min)
where:
DCOMP(MAX) = 3.8 V
DCOMP(MIN) = 2.5 V
DMULTIN(PEAK)@VAC(min) +2
Ǹ VAC(min) ǒRAC2
RAC2 )RAC1Ǔ
If the exact value RS1 is not available. RS2 and RS3 can be added for further scaling. The CS pin already has
an internal filter for noise due to switching transients. Additional filtering at switching transient frequencies can
be achieved by adding CS1.
Output Voltage Sense Design
Select the divider ratio of RO1 and RO2 to set the VO_SNS voltage to 2.5 V at the desired output voltage. The
current through the divider should be at least 200 μA.
Voltage Loop Design
How well the voltage control loop is designed directly impacts line current distortion. UCC38050 employs a
transconductance amplifier (gM amp) with gain scheduling for improved transient response (refer to Figure 14.
gM Amplifier Output Current vs. Current Sense Voltage). Integral type control at low frequencies is preferred
here because the loop gain varies considerably with line conditions. The largest gain occurs at maximum line
voltage. If the power factor corrector load is dc-to-dc switching converter, the small signal model of the controller
and the power factor corrector, from COMP to PFC output voltage is given by:
V
^
OUT(s)
V
^
COMP(s) +
k1 ǒVACǓ2
VOUT(avg) RS1 kCRM COUT 1
S
where:
DV
^
OUT = small signal variations in VOUT
DV
^
COMP = small signal variations in VCOMP
Dk1 = multiplier gain = 0.65
DkCRM = peak to average factor = 2
(12)
(13)
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
15
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APPLICATION INFORMATION
A controller that has integral control at low frequencies requires a zero near the crossover frequency in order
to be stable. The resulting gM amplifer configuration is shown in Figure 3.
UDG−02122
VREF
VOUT
+
RV1
CV1
CV2
Figure 3. gM Amplifier Configuration
The compensator transfer function is:
AV+gM
CV1 )CV2
1)ǒRV1 CV1 sǓ
sǒ1)ǒRV1 ƪCV1 CV2ƫ
ƪCV1)CV2ƫǓ sǓ
where gM = dc transconductance gain = 100 μs
The limiting factor of the gain is usually the allowable third harmonic distortion, though other harmonics can
dominate. The crossover frequency of the control loop will be much lower than twice the ac line voltage. In order
to choose the compensator dynamics, determine the maximum allowable loop gain at twice the line frequency
and solve for capacitor CV2. This also determines the crossover frequency.
CV2 +ǒVAC(max)
4pfAC Ǔ2
ǒgM k1
VOUT(avg) RS1 k(crm) COUT(max loop gain @ 2 fAC)Ǔ
fCO +VAC
p
gM k1
CV2 VOUT RS1 k(cmr) COUT
Ǹ
Select CV1 so that the low frequency zero is one-tenth of the crossover frequency.
CV1 +9C
V2
Select RV1 so that the pole is at the crossover frequency.
[1
2pfCO CV2
(14)
(15)
(16)
(17)
(18)
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
16 www.ti.com
Bias Current
The bias voltage is supplied by a bias winding on the inductor. Select the turns ratio so that sufficient bias voltage
can be achieved at low ac line voltage. The bias capacitor must be large enough to maintain sufficient voltage
with ac line variations. Be sure to connect a 0.1-μF bypass capacitor between the VCC pin and the GND pin
as close to the integrated circuit as possible. For wide line variations, a resistor, RB, is necessary in order to
permit clamping action. The bias voltage should also be clamped with an external zener diode to a maximum
of 18 V.
Zero Current Detection
The zero current detection activates when the ZCD voltage falls below 1.4 V. The bias winding can provide the
necessary voltage. This pin has a clamp at approximately 5 V. Add a current limiting resistor, RZC, to keep the
maximum current below 1 mA.
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
17
www.ti.com
REFERENCE DESIGN
A reference design is discussed in 100-W Universal Line Input PFC Boost Converter Using the UCC38050, TI
Literature No. SLUU134. The UCC38050 is used for the off-line power factor corrected pre-regulator with
operation over a universal input range of 85 V to 265 V with a 400 Vdc regulated output. The schematic is shown
in Figure 4 and the board layout for the reference design is shown in Figure 5. Refer to the document for further
details.
+
+
+
Figure 4. Universal Line Input 100-W Boost Converter Reference Design Schematic
Figure 5. Reference Design Board Layout
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
18 www.ti.com
TYPICAL CHARACTERISTICS
Figure 6
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
ICC − Supply Current − mA
VCC − Supply Voltage − V
2.5
3.0
3.5
2.0
4.0
0
0.5
1.0
1.5
200128416
UCC38051
UCC38050
SUPPLY CURRENT
vs
TEMPERATURE
TJ − Temperature − °C
Figure 7
4
5
3
0
1
2
125−50 50250 100
−25 75
ICC − Supply Current − mA
ICC = ON
75 kHZ, 1 nF
ICC = ON
75 kHZ, No Load
ICC = ON
No Switching
6
14
16
10
4
6
2
8
12
18
0
125−50 50250 100−25 75
20
Figure 8
UVLO THRESHOLDS
vs
TEMPERATURE
VUVLO − UVLO Threshold VOltage − V
TJ − Temperature − °C
UVLO ON
(UCCx8050)
UVLO OFF
UVLO HYSTERESIS (UCCx8050)
UVLO ON
(UCCx8051)
UVLO HYSTERESIS (UCCx8051)
REFERENCE VOLTAGE
vs
TEMPERATURE
VREF − Reference Voltage − V
TJ − Temperature − °C
Figure 9
2.54
2.56
2.50
2.60
2.44
2.46
2.42
2.48
2.52
2.58
2.40
12
5
−50 50250 100−25 75
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
19
www.ti.com
TYPICAL CHARACTERISTICS
Figure 10
CURRENT SENSE INPUT THRESHOLD
vs
MULTIPLIER INPUT VOLTAGE
VCS − CS Input Voltage − V
VMULTIN − Multiplier Input Voltage− V
1.2
1.4
0.8
1.8
0.4
0.2
0.6
1.0
1.6
0.0 3.00 1.51.00.5 2.52.0
COMP = 3.5 V
COMP = 3.25 V
COMP = 2.75 V
COMP = 3 V
COMP = 3.75 V
COMP = 2.5 V
MAXIMUM CURRENT SENSE THRESHOLD
vs
TEMPERATURE
VCS(max) Maximum Current Sense Threshold − V
TJ − Temperature − °C
Figure 11
12
5
−50 50250 100−25 75
1.725
1.750
1.675
1.550
1.600
1.625
1.575
1.650
1.700
1.775
1.800
Figure 12
CS TO OUTPUT DELAY TIME
vs
TEMPERATURE
tDELAY − Cureent Sense to Output Delay Time − ns
TJ − Temperature − °C
125−50 50250 100−25 75
350
400
250
0
100
150
50
200
300
450
TRANSCONDUCTANCE
vs
TEMPERATURE
gM − Transconductance − μS
TJ − Temperature − °C
Figure 13
125−50 50250 100−25 75
100
90
120
60
70
80
110
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
20 www.ti.com
TYPICAL CHARACTERISTICS
Figure 14
gM AMPLIFIER OUTPUT CURRENT
vs
OUTPUT SENSE VOLTAGE
ICOMP − gM Amplifier Output Current − mA
VVO_SNS − Output Sense Voltage − V
2.82.0 2.52.42.2 2.72.1 2.6
0.5
0
−1.5
−1.0
−0.5
1.0
2.3
1.5
UCCx8051
UCCx8050
gM AMPLIFIER OUTPUT CURRENT
vs
OUTPUT SENSE VOLTAGE
(SMALL SIGNAL VIEW)
ICOMP − gM Amplifier Output Current − mA
VVO_SNS − Output Sense Voltage − V
Figure 15
2.602.40 2.502.45 2.55
−0.012
−0.004
0
0.004
0.008
0.012
−0.008
Figure 16
VOLTAGE AMPLIFIER OUTPUT
vs
TIME (UCC38050)
VCOMP − Voltage Amplifier Output − V
25 μs / div
4.5
5.0
3.5
1.5
2.5
2.0
3.0
4.0
5.5
VSENSE
VAO
CLOAD = 10 nF
OVERVOLTAGE PROTECTION THRESHOLDS
vs
TEMPERATURE
VOVP − OVP Threshold Voltage − V
TJ − Temperature − °C
Figure 17
12
5
−50 50250 100−25 75
2.65
2.60
2.80
2.40
2.45
2.55
2.75
2.70
2.50
OVP OFF
OVP ON
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
21
www.ti.com
TYPICAL CHARACTERISTICS
Figure 18
ZERO CURRENT DETECTION CLAMP
CURRENT vs VOLTAGE
IZCD − ZCD Current − mA
VZCD − ZCD Voltage − V
70432615
2
0
10
−10
−8
−2
8
6
−6
−4
4
RESTART TIME
vs
TEMPERATURE
tRESTART − Restart Time − μs
TJ − Temperature − °C
Figure 19
125−50 50250 100−25 75
400
300
600
0
100
200
500
Figure 20
OUTPUT SATURATION VOLTAGE
vs
SOURCE CURRENT
VOUT(sat) − Output Saturation Voltage − V
ISOURCE − Source Current − mA
7000 400300200 600100 500
5
4
8
0
1
3
7
800
2
6
VCC = 12 V
OUTPUT SATURATION VOLTAGE
vs
SINK CURRENT
VOUT(sat) − Output Saturation Voltage − V
ISINK − Sink Current − mA
Figure 21
2.5
1.5
0
0.5
1.0
2.0
7000 400300200 600100 500 800
VCC = 12 V
UCC28050, UCC28051
UCC38050, UCC38051
SLUS515F−SEPTEMBER 2002 − REVISED MARCH 2009
22 www.ti.com
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
8
0.197
(5,00)
A MAX
A MIN (4,80)
0.189 0.337
(8,55)
(8,75)
0.344
14
0.386
(9,80)
(10,00)
0.394
16
DIM
PINS **
4040047/E 09/01
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.010 (0,25)
0.016 (0,40)
0.044 (1,12)
0.244 (6,20)
0.228 (5,80)
0.020 (0,51)
0.014 (0,35)
1 4
8 5
0.150 (3,81)
0.157 (4,00)
0.008 (0,20) NOM
0°− 8°
Gage Plane
A
0.004 (0,10)
0.010 (0,25)0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012