1
DS3102DK Demo Kit
Evaluates: DS3102 Timing IC
General D es cription
The DS3102DK is an easy-to-use demo and
evaluation kit for the DS3102 line card timing IC. A
surface-mounted DS3102 and careful layout provide
maximum signal integrity. An on-board 8051-
compatible microcontroller and included software
give point-and-click access to configuration and
status registers from a Windows®-based PC. LEDs
on the board indicate interrupt, power-supply
function, and lock status. Single-ended and
differential clock s are accessed via SMB connectors.
All LEDs and connectors are clearly labeled with
silkscreening to identify associated signals.
Windows is a registered trademark of Microsoft Corp.
Demo Kit Contents
DS3102D K Board
CD-ROM Includes:
DS3102 Software
DS3102 Initialization File
DS3102DK Data Sheet
DS3102 Data Sheet/ Err ata She et
Features
♦ Soldered DS3102 for Best Signal Integrity
♦ SMB Connectors and Termination Ease
Connectivity
♦ Careful Layout for Analog Signal Paths
♦ On-Board Stratum 3 Oscillator with Footprin ts
for Stratum 3E and Stratum 4 Oscillators
♦ On-Board Microc o n troller and Inc luded
Software Provide Point-and-Click Access to
the DS3102 Register Set
♦ LEDs for Interrupt, Power Supplies, and Lock
Status
♦ Banana Jack VDD and GND Connectors
Support Use of Lab Power Supplies
♦ Easy-to-Read Silkscreen Labels Identify the
Signal s Associated with All Connectors,
Jumpers, and LEDs
♦ Software Provides GUI Fields for Most
Commonly Used Features Plus Full
Read/Write Access to the Entire Register Set
♦ Software Supp o rt for Creating and Running
Configura tion Scripts Saves Time During
Evaluation
Minim um System Requirements
♦ PC Running Win d o ws X P or Windows 2000
♦ Display with 1024 x 768 Resolution or Higher
♦ Available USB or Serial (COM) Port
♦ USB Cable or DB-9 Serial Cable
Order ing Information
PART
DESCRIPTION
DS3102DK Demo kit for DS3102
Data Sheet
May 2012
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Table of Cont ents
1. BOARD FLOORPLAN .................................................................................................................. 4
1.1 INPUT AND OUTPUT CLOCKS ......................................................................................................... 5
1.2 JUMPERS, HEADERS, AND SWITCH SETTINGS ................................................................................. 5
1.3 MICROCONTROLLER ..................................................................................................................... 5
1.4 POWER-SUPPLY CONNECTORS ..................................................................................................... 5
2. BASIC HARDWARE SETUP ......................................................................................................... 6
2.1 USB DRIVER INSTALLATION .......................................................................................................... 6
3. INSTALLING AND RUNNING THE SOFTWARE .......................................................................... 7
3.1 COMMAND LINE OPTIONS.............................................................................................................. 7
4. OVERVIEW OF THE SOFTW ARE INTERFACE ........................................................................... 8
4.1 GLOBAL CONFIGURATION .............................................................................................................. 8
4.2 INPUT CLOCK MONITOR, DIVIDER, AND SELECTOR ......................................................................... 8
4.3 T0 DPLL ....................................................................................................................................10
4.4 T4 DPLL ....................................................................................................................................12
4.5 T0 APLL AND T0 APLL2 .............................................................................................................13
4.6 T4 APLL.....................................................................................................................................13
4.7 OUTPUT CLOCKS .........................................................................................................................14
4.8 DPLL FREQUENCY LIMITS, PHASE DETECTORS, DPLL LOCK CRITERIA ..........................................15
4.9 REFCLK CALIBRATION ................................................................................................................15
4.10 PROGRAMMABLE DFS ..............................................................................................................15
4.11 I/O PINS ..................................................................................................................................17
4.12 REGISTER VIEW WINDOW .........................................................................................................17
4.13 CONFIGURATION SCRIPTS AND LOG FILE ...................................................................................19
4.13.1 Configuration Log File .......................................................................................................................... 19
4.13.2 Configuration Scripts ............................................................................................................................ 19
5. APPENDIX 1: HARDWARE COMPONENTS ...............................................................................20
6. SCHEMATICS ..............................................................................................................................22
7. DOCUMENT REVISION HISTORY ..............................................................................................22
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List of Figures
Figure 1-1. DS3102DK Board Floorplan .......................................................................................................................4
Figure 4-1. Soft ware Mai n Scr een ................................................................................................................................8
Figure 4-2. Soft ware Input Clock Window ....................................................................................................................9
Figure 4-3. Software T0 DPLL Window ..................................................................................................................... 11
Figure 4-4. Software T4 DPLL Software .................................................................................................................... 12
Figure 4-5. Software-Programmable DFS Window ................................................................................................... 16
Figure 4-6. Soft ware I/O P ins W indo w ...................................................................................................................... 17
Figure 4-7. Software Register View Window ............................................................................................................. 18
List of Tables
Table 4-1. Mapping Between Input Clock Software Fields and DS3102 Register Fields ......................................... 10
Table 4-2. Mapping Between T0 DPLL Software Fields and DS3102 Register Fields ............................................. 11
Table 4-3. Mapping Between T4 DPLL Software Fields and DS3102 Register Fields ............................................. 13
Table 4-4. Ma pping Bet w een T0 APLL Software Fields and DS3102 Register Fields ............................................. 13
Table 4-5. Mapping Between T4 APLL Software Fields and DS3102 Register Fields ............................................. 14
Table 4-6. Mapping Between Output Clock Software Fields and DS3102 Register Fields....................................... 14
Table 4-7. Mapping Between DPLL Software Fields and DS3102 Register Fields .................................................. 15
Table 4-8. Mapping Between REFCLK Software Fields and DS3102 Register Fields ............................................. 15
Table 4-9. Mapping Between I/O Pins Software Fields and DS3102 Register Fields............................................... 17
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1.
Board Floor plan
Figure 1-1 sho ws the DS3102DK f loorplan. T he DS3102 is in the ce nter of the board, input clock SMB connec tors
are along the left edge of the board, and output clock connectors are on the right edge. Between the input clock
connectors and the D S3102, l and patter ns are pr ovided for several dif ferent t ypes of local oscillator s, rangin g from
inexpensive XOs to higher performance TCXOs and OCXOs. The top edge contains, from left to right, power-
supply connectors, DC-DC converters and power-indicator LEDs, reset pushbutton, serial connector, and USB
connector. An on-board DS87C520 microcontroller is located near the USB connector. The bottom edge of the
board is occupied by a JTAG connector and LED indicators.
See Appendix 1: Hardware Components for a complete component list. Complete board schematics follow in
Section 7.
Figure 1-1. DS3102DK Board Floorplan
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1.1
Input and Output Clocks
There are seven SMB connectors at the left of the board labeled IC3, IC4, IC7, IC8, and SYNC1–SYNC3 that
provide a single-end ed clock input to t he DS 3102. All single-ende d cloc k inputs are connec ted to t he DS3102 with
a 50Ω characteristic im pedance trace and term inated with 50Ω at the device (SYNC1–SYNC3 require a jumper in
the TERM position to terminate due to dual functionality). Eight additional SMB connectors labeled IC1P, IC1N,
IC2P, IC2N, IC 5P, IC5N, IC6P, and IC6N provide differential clock inputs to the DS3102. These differential inputs
have 50Ω trace impedance, test points, and 50Ω termination at the device (i.e., 100Ω differential).
On the other side of the PCB are 12 SMB clock output connectors label ed OC1–OC 5, OC1B–OC5B, FSYNC, and
MFSYNC. All single-ended clock outputs are buffered at the DS3102 and connected to the SMB connector via a
50Ω characteristic impedance trace. Cables attached to the single-ended output connectors must have 50Ω
termination and characteristic impedance for proper operation. Eight additional SMB connectors labeled OC4P,
OC4N, OC5P, OC5N, OC6P, OC6N, OC7P, and OC7N provide connections to the differential outputs from the
DS3102.
1.2
Jumpers, Headers, and Switch Settings
Jumpers JMP9–JMP12 and JMP16 (lower right of board) provide the means to pull up or pull down the TEST,
SRFAIL, LOCK, SRCSW, and SONSDH pins of the DS3102. (Note that som e of these jumpers only make sense
for other DS310x products where the pin has a different function.) Labels specify which position is used to pull each
pin to a 1 or a 0 (if jumper is not installed, pin is left to float to accommodate a pin’s output function). Jumpers
JMP1–JMP4 (middle right of board) provide access to the SYNC1–SYNC3 and IC9 pins of the DS3102. Labels
specify the position to install the jumper to pull the pin up (signified by “1”) or pull it down through a 50Ω resistor
(signified by “TERM\0”). The 50Ω resistor is used as a termination resistor when the pin is used as a input clock
signal. Jumper JMP6 (labeled VDDIOB) is used to set the VDDIOB supply voltage for output clock pins OC1B–
OC5B. The options are labeled for 2.5V or 3.3V. Jumpers JMP62 and JMP63 select the computer interface to be
USB or RS-232. Jum per JMP5 (upp er-left) selects whether the board shoul d be powered f rom the US B connector
or from the power-supply jacks (J3 or J13/J19). LEDs DS1–DS4 (upper-left) indicate the labeled power supply is
operational. LED DS16 (upper-right) indicates that the microprocessor is operational. LEDs DS5, DS6, and DS10
(lower middle) indicate the status of the SRFAIL, LOCK, and INTREQ pins, respectively. Switch SW1 is used to
select a sq uaring circu it to accomm odate a sinusoida l input on IC3. H eader J51 p rovides access to the JTAG por t
of the DS3102. Test points are provided for differential inputs and outputs, the watchdog timer pin, SPI port pins,
and ground plane connection.
1.3
Microcontroller
The DS87C520 microcontroller has factory-installed firmware in on-chip nonvolatile memory. This firmware
translates memory access requests from the RS-232 serial port or USB port into register accesses on the D3102.
W hen the m ic roc ontr oller s t arts up it t ur ns on DS 16 to i ndicate that t he c o ntr o ller i s working corr ectly. A pus h butto n
switch labeled RESET near the RS-232 connector resets the microcontroller as well as the DS3102.
1.4
Power-Supply Connectors
A 5V lab po wer suppl y can be conn ected acros s the red ( J13) and bl ack (J19) banana jack s. Optional ly, the board
can be p owered f rom the USB conn ector b y placin g jum per JMP5 i n the US B pos ition. T he 5V inp ut from either of
these sources is then regulated to 3.3V, 2.5V, and 1.8V, and distributed to board components.
Note that the bo ard cannot be USB p owered through some USB hubs. Bef ore trying to power the bo ard through a
USB hub, check the voltage at JMP5 to ensure the board is getting 5V from the hub.
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2.
Basic Hardware Setup
The following steps provide a quick start to using the DS3102DK.
1) To communicate with the board using a USB cable:
a) Configur e the board for USB com munication b y plac in g j umpers to c onnec t the middle and right pi ns of
JMP62 and JMP63 (i.e., place the jumpers toward the “USB” silkscreen).
b) Connect a USB cable between the USB connector on the DS3102DK and an available USB port on the
host computer.
2) To communicate with the board using a serial (RS-232) cable:
a) Configur e the board for serial comm unication b y plac ing jum pers to connect the lef t and middle pins of
JMP62 and JMP63 (i.e., place the jumpers toward the “RS232” silkscreen).
b) Connect a standard DB-9 serial cable between the serial port connector on the DS3102DK and an
available serial port on the host computer. (Be sure the cable is a standard straight-through cable
rather than a null-modem cable. Null-modem cables prevent proper operation.)
3) To power the board from a lab power supply, place the POWER jumper (JMP5) in the PS position and
connect a 5V supply across the J13 and J19 connectors.
4) To power the board from the USB port, place the POWER jumper (JMP5) in the USB position.
At this point the po wer indicator LEDs DS1–DS4 shou ld be lit. Microcontro ller status LED DS16 ( to the right of the
USB connector) should also be lit.
2.1
USB Driver Ins t all ation
When the DS3102DK is first connected to the PC using a USB cable, an on-board USB-to-serial converter IC is
automatically detected by Windows and the Found New Hardware Wizard is automatically started. Follow these
steps to install the drivers:
1) In the first screen of this wizard, select “Install from a list or specific location” and click “Next”.
2) In the second screen, select “Search for the best driver in these locations”, check “Include this location in
the search,” and browse to the “USB” directory in the DS3102DK CD-ROM or downloaded ZIP file. Click
“Next”.
3) Click “Finished”.
4) Repeats steps 1 to 3 the second time the Found New Hardware Wizard starts.
After the dri vers ar e insta lle d, whene ver th e DS310 2DK bo ard is c onnected t o a USB port o n the PC, t he W indo ws
operating system will see the U SB-to-serial converter IC as an additional COM port. T he DS3102DK software will
automatically list the additional COM port in the PORT selection combo box in the upper-left corner of the main
window.
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3.
Installing and Running the Software
At this time the DS3102 demo kit software only runs on Windows 2000 or Windows XP operating systems.
To install the demo kit software, run SET UP.EXE from the disk included in the DS3102DK box or from the zip file
available on the Microsemi website or from Microsemi timing products technical support.
After software installation is complete, set up the hardware as described above and run the software by double-
clicking the DS3102 Demo Kit icon on the Windows desktop or by selecting Start→Programs→Microsemi→
DS3102 Demo Kit. When the main window appears, select the correct serial port in the box in the upper-left
corner. When communication has been proper ly estab lishe d bet wee n t he sof tware and t he hardware, t he ID field in
the upper-left corner should indicate 3102 rev x, where x = 0 for a revision A1 device, and x = 1 for a revision A2
device.
The demo kit software always starts in demo mode (with the DEMO MODE checkbox in the upper-left corner
check ed) to allow a user to look at the software without ha ving the DK hardwar e connected to the P C. To connect
the software with the demo kit hardware, uncheck the DEMO MODE box. The software optionally initializes the
DS3102 device and then reads the state of the device to get ready for use.
3.1
Command Line O ptions
The demo kit software has these command line options:
-l <filepath>
specifies an alternate log file
example: “DS3102DK.exe –l mylog.mfg
-p[port#] sets the serial (COM) port number example: “DS3102DK.exe –p2” sets COM2
To add comm and line options to the DS3 102 demo k it shortcut that the instal ler adds to the desk top, right-click on
the shortcut and select Properties. In the Shortcut tab, at the end of the text in the Target textbox, add a space
followed by the command line option.
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4.
Overv iew of the Software I nterface
Figure 4-1. Soft war e Mai n Scr een
4.1
Global C onfiguration
In the upper-l eft corner of the main window are se veral global stat us and config uration fields. T he ID field displa ys
the device part number and revision. The PORT field shows the COM port to which the DK board is connected.
The DEMO MODE check box, which is checked by default, must be unchecked to enable the software to
communicate with the DK board. The ENABLE POLLING checkbox, also checked by default, controls software
polling of the device. The RESET checkbox controls MCR1:RESET in the device. Finally, the SDH and SONET
radio buttons (which control device register field MCR3:SON SDH) specify whet her 1.544MHz (SON) or 2.048MHz
(SDH) is an available frequency option for input clocks IC1–IC9.
4.2
Input Clock M onit or , Di v ider, and Selector
This box occupying the left -center sec tion of the m ain wind ow contai ns the m ost frequentl y used conf iguratio n and
status associated with input clocks IC1–IC6, IC8, and IC9. Note that the device does not have an IC7 input clock.
Just to the right of the input clock numbers are software LEDs that indicate the state of each input as reported by
its input m onitor. T hese L ED s are red in the a bsenc e of any other c ondit ion. When a clock of the corr ect f requenc y
is applied to an input, the associated LED turns yellow when activity is detected and green if the input clock
frequenc y is within range. I f an input is disqua lified b y one of the DPLLs beca use the DPLL coul d not lock t o it, the
LED turns magenta.
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In the m iddle of the box, t he F REQ and LK MO DE f ields c onfigure the f reque nc y and lock mode (dir ect -lock, D IVN,
LOCK8K, or alternate direct-lock) for each input clock. At the bottom is a field to configure the DIVN divider used
for inputs configured for DIVN mode.
All the fields in the box containing the PRIORITY fields display information about either the T0 DPLL or the T4
DPLL, depending on which of two radio buttons is selected at the top of the box. The PRIORITY fields configure
the input clock priorities for the selected DPLL (1 highest, 15 lowest, 0 disabled). The SEL REF field shows the
selected reference for the DPLL, while the REF 1, REF 2, and REF 3 f ields display the three highest priority valid
inputs for the DPLL. The FREQ and PHASE fields show the real-time frequency and phase reported by the DPLL.
Clicking the More button opens another window (Figure 4-2) with additional input clock configuration and status
fields. See Table 4-1 for further details.
Figure 4-2. Software Input Clock Window
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Table 4-1. Mapping Between Input Clock Software Fields and DS3102 Register Fields
SOFTWARE FIELD
DS3102 REGISTER FIELDS
MAIN WINDOW
Input Clock Status LED s 1 to 9
ISR1–ISR5 registers
LED red when ACT = 1, HARD = 1, LOCK = 0
LED yellow when ACT = 0, HARD = 1, LOCK = 0
LED green when ACT = 0, HARD = 0, LOCK = 0
LED magenta when LOCK = 1
FREQ 1 to 9
ICR1 to ICR9:FREQ[3:0]
LK MODE 1 to 9
ICR1 to ICR9:LOCK8K, and DIVN
PRIORITY 1 to 9
IPR1 to IPR5
SEL REF
PTAB1:SELREF
REF 1
PTAB1:REF1
REF 2
PTAB2:REF2
REF 3
PTAB3:REF3
FREQ (ppm)
FREQ1, FREQ2, and FREQ3 registers concatenated
PHASE (deg)
PHASE1 and PHASE2 register concatenated
SUBWINDOW
Soft 1 to 9
ISR1 to ISR5:SOFT
Hard 1 to 9
ISR1 to IS R5:HARD
Act 1 to 9
ISR1 to ISR5:ACT
Lock 1 to 9
ISR1 to ISR5:LOCK
Valid 1 to 9
VALSR1, VALSR2
Enable 1 to 9
VALCR1, VALCR2
Bucket 1 to 9
ICR1 to ICR9:BUCKET
PHLKTO and PHLKTOM
PHLKTO
Alarm Timeout
MCR3:LKATO
External Switching
MCR10:EXTSW
Ultra-Fast Switching
MCR10:UFSW
Freq Range Enable
MCR1:FREN
Soft Alarm Enable
MCR10:SOFTEN
Hard Alarm Enable
MCR10:HARDEN
8K Polarity
TEST1:8KPOL
Freq Measurement Input
MCR11:FMEASIN
Freq Measurement Freq
FMEAS
Freq Measurement Reference
MCR10:FMONCLK
Leaky Bucket Settings
LBxU, LBxL, BLxS, LBxD (x = 1 to 4)
Freq Monitor Limits, Input Clock
ILIMIT
Freq Monitor Limits, Selected Ref
SRLIMIT
4.3
T0 DPLL
The state of the T0 DPLL (free-run, locked, holdover, etc.) is shown in the STATE textbox. The STATE, SRFAIL,
and PHMON butt ons re pres ent latc hed st atus bits in t he dev ice. W hen the b utton is red, t he cor respo nding latched
status bit has been set in the DS3102. Pressing the button clears the latched status bit and changes the color of
the button back to green. The STATE button indicates the state of the T0 DPLL has changed since the last time the
button was pres sed. SRFAI L ind icat es th e s elec t ed reference has f ail ed sinc e t he last time the button was pr e ss ed.
PHMON indicates the phase monitor limit (set by PMLIM) has been exceeded since the last time the button was
pressed.
The state of the T0 DPLL can be forced using the combo box to the left of the STATE textbox, and the selected
reference can be forced using the CLK SEL field. Below the CLK SEL field is a field that configures the T0 DPLL for
revertive or nonrevertive input reference switching.
The frequency of the T0 DPLL is displayed in the FREQ field (fixed at 77.76MHz for the DS3102 T0 DPLL). The
acquisitio n and loc ked ban dwidths ar e set b y the AB W and LBW fields, r especti vely, and t he dam ping fact or is set
by the DAMP field. The acquisition bandwidth is only used if AUTOBW is checked. If the frequency of the T0
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DPLL’s selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY LIMITS box at the top of
the main window), the SOFTLIM LED turns red.
The PALARM status LED and the PHASE MONITOR and BUILDOUT fields are advanced topics. See Table 4-2
and the DS 3102 data shee t for m ore details. Click ing the More button opens an other win dow (see Figure 4-3) wi th
additional T0 DPLL configuration and status fields.
Figure 4-3. Software T0 DPLL Window
Table 4-2. Mapping Between T0 DPLL Software Fields and DS3102 Register Fields
SOFTWARE FIELD DS3102 REGISTER FIELDS
MAIN WINDOW
STATE combo box
MCR1:T0STATE
STATE status box
OPSTATE:T0STATE
CLK SEL
MCR2:T0FORCE
Revertive/Nonrevertive
MCR3:REVERT
FREQ
Fixed by T0 DPLL architecture
ABW
T0ABW
LBW
T0LBW
DAMP
T0CR2:DAMP
STATE latched status button
MSR2:STATE
SRFAIL
MSR2:SRFAIL
PALARM
TEST1:PALARM
SOFTLIM
OPSTATE:T0SOFT
AUTOBW
MCR9:AUTOBW
LIMINT
MCR9:LIMINT
PBOEN
MCR10:PBOEN
PBOFRZ
MCR10:PBOFRZ
RECAL
FSCR3:RECAL
MANUAL PBO
OFFSET1 and OFFSET2
SUBWINDOW
Manual Holdover
MCR3:MANHO
Holdover Type
HOCR3:AVG
Mini HO Type
HOCR3:MINIHO
HO Freq
HOCR1, HOCR2, HOCR3[2:0]
RDAVG
HOCR3:RDAVG
Fast Ready, Slow Ready
MSR4:FHORDY, SHORDY
SYNC2K Mode
FSCR3:SOURCE, FSCR1:SYNCSRC
MONLIM
FSCR3:MONLIM
AEFSEN
MCR3:AEFSEN
EFSEN
MCR3:EFSEN
INDEP
FSCR2:INDEP
OCN
FSCR2:OCN
FSMON
OPSTATE:FSMON
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SOFTWARE FIELD DS3102 REGISTER FIELDS
SYNC1 Source
Derived by software from SYNC2K Mode
SYNC1 Phase
FSCR2:PHASE1
SYNC2 Source
Derived by software from SYNC2K Mode
SYNC2 Phase
FSCR2:PHASE2
SYNC3 Source
Derived by software from SYNC2K Mode
SYNC3 Phase
FSCR2:PHASE3
PD2 Enable
T0CR3:PD2EN
PD2G
T0CR3:PD2G
PD2G8K
T0CR2:PD2G8K
APBO OFFSET
PBOFF
4.4
T4 DPLL
The state of the T4 DPLL (locked or not locked) is shown in the STATE field. The LOCK and NO INPUT buttons
represent latched status bits in the device. When the button is red, the corresponding latched status bit has been
set in the DS3102. Pressing the button clears the latched status bit and changes the color of the button back to
green. LOCK indicates the state of the T4 DPLL has changed since the last time the button was pressed. NO
INPUT means the T4 DPLL has no valid inputs available. The selected reference for the T4 DPLL can be forced
using the CLK SEL field.
The frequenc y of the T4 DPLL is displa yed in the FR EQ field. When the FREQ field is changed, if the SRC DPLL
field in the T4 APLL box is set to T4 then the Input Freq and Output Freq fields in the T4 APLL box change to
matc h the ne w T 4 DPLL f requency, and all th e T 4 options i n t he O C 1–O C7 output c lock com bo box es also c hang e
to frequencies derived from the new T4 APLL frequency. These changes match what happens in the DS3102.
The bandwidth of the T4 DPLL is set by the BW field, while the damping factor is set by the DAMP field. If the
frequency of the T4 DPLL’s selected reference exceeds the SOFT LIMIT setting (in the DPLL FREQUENCY
LIMITS box at the top of the window), the SOFTLIM LED turns red.
The LKT4T0 and T4MT0 fields are advanced topics. See Table 4-3 and the DS3102 data sheet for more details.
Clicking the More button opens another window (Figure 4-4) with additional T4 DPLL configuration and status
fields.
Figure 4-4. Software T4 DPLL Software
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Table 4-3. Mapping Between T4 DPLL Software Fields and DS3102 Register Fields
SOFTWARE FIELD
DS3102 REGISTER FIELDS
MAIN WINDOW
STATE
OPSTATE:T4LOCK
CLK SEL
MCR4:T4FORCE
FREQ
T4CR1:T4FREQ
BW
T4BW
DAMP
T4CR2:DAMP
LOCK
MSR3:T4LOCK
NO INPUT
MSR3:T4NOIN
SOFTLIM
OPSTATE:T4SOFT
LKT4T0
MCR4:LKT4T0
T4MT0
T0CR1:T4MT0
SUBWINDOW
PD2 Enable
T4CR3:PD2EN
PD2G
T4CR3:PD2G
PD2G8K
T4CR2:PD2G8K
4.5
T0 APLL and T0 APLL2
The Input Fr eq field conf igur es the f requenc y of the T0 APLL DFS ( refer to the DS3102 d ata s he et for details ). T he
APLL outp ut frequenc y is always f our times the input freque ncy. W hen the Inp ut Freq fiel d is changed, the Output
Freq field changes to match, and all the T0 options in the OC1–OC7 output clock combo boxes also change to
frequencies derived from the new T0 APLL frequency. These changes match what happens in the DS3102.
In norm al opera tio n th e T0 APLL2 has a f ixed output f r eque ncy of 312.5 MH z (t wic e the s ta ndard XG MII c lock rate).
The rate is displayed in the T0 APLL2 Output Freq textbox.
Whenever the T0 APLL DFS or the T0 APLL2 DFS are configured for programmable DFS operation (see section
4.10) their respective Input Freq and Output Freq fields specify their frequencies with a “P” prefix to indicate that
programmable DFS mode is enabled.
Table 4-4. Mapping Between T0 APLL Software Fields and DS3102 Register Fields
SOFTWARE FIELD DS3102 REGISTER FIELDS
Input Freq
T0CR1:T0FREQ
Output Freq
Derived by software from Input Freq
4.6
T4 APLL
The T4 APLL can be connected to the out put of the T 4 DPLL or to the output of the T 0 DPLL as specified by the
SRC DPLL field. When SRC DPLL is set to T4, the Input Freq field follows the T4 DPLL FREQ field. When SRC
DPLL is set to T0, several frequency options are available in the Input Freq field.
The Input Fr eq field conf igur es the f requenc y of the T4 APLL DFS ( refer to the DS3102 d ata she et for details) . The
APLL outp ut frequenc y is always f our times the input freque ncy. W hen the Inp ut Freq fiel d is changed, the Output
Freq field changes to match, and all the T4 options in the OC1–OC7 output clock combo boxes also change to
frequencies derived from the new T4 APLL frequency. These changes match what happens in the DS3102.
Similarl y, when the FREQ field is c hanged in the T4 DPLL box, if the SRC DPLL field in the T 4 APLL box is set to
T4 then the Input Freq and Output Freq fields in the T4 APLL box change to match the new T4 DPLL frequency,
and all the T4 options in the OC1–OC7 output clock combo boxes also change to frequencies derived from the new
T4 APLL frequency.
_________________________________________________________________________________________ DS3102DK
14
W henever the T4 A PLL DFS is configur ed for pr ogramm able DFS operation ( see Secti on 4.10) the Inp ut Freq an d
Output Freq fields specify their frequencies with a “P” prefix to indicate that programmable DFS mode is enabled
for the T4 APLL DFS.
Table 4-5. Mapping Between T4 APLL Software Fields and DS3102 Register Fields
SOFTWARE FIELD
DS3102 REGISTER FIELDS
SRC DPLL
T0CR1:T4APT0
Input Freq
T0CR1:T0FT4
Output Freq
Derived by software from Input Freq
4.7
Output Clocks
The fields in this box configure the DS3102’s output clocks. The 2K8K SOURCE field specifies the source (T0 or
T4) for the 2kHz and 8kHz clock options for output clocks OC1–OC7. Similarly, the DIG1 SOURCE, DIG2
SOURCE, DIG1, and DIG2 fields configure the Digital1 and Digital2 frequency options for OC1–OC7 (refer to the
DS3102 data sheet for details).
The OC 1–OC7 fields sp ecif y the output frequencies for outputs O C1–OC7. Note that when the T0 APLL s etting is
changed, the f requencies o f all the T0 options in the O C1–OC7 fields autom atically ch ange to frequenc ies derived
from the new T0 APLL frequency. Similarly, when the T4 APLL setting is changed, the frequencies of all the T4
options in the OC1–OC7 fields automatically change to frequencies derived from the new T4 APLL frequency.
These changes match what happens in the DS3102.
Whenever the T0 APLL DFS, T4 APLL DFS, or T0 APLL2 DFS are configured for programmable DFS operation
(see Sect ion 4.10) the T0, T4, and T 02 o pti ons, res p e c tively, in the O C 1–O C7 f ie lds cha nge t o f requ enc i es deri ved
from the programmable DFS settings. These options all have a “P” prefix, for example, “PT0” or “PT4” to indicate
they are controlled by the programmable DFS mode. Similarly, whenever the DIG1 DFS or the DIG2 DFS are
configured for programmable DFS operation, the DIG1 and DIG2 fields change to display the programmable DFS
frequency with a “P” prefix.
FSYNC is an 8k H z output t hat can b e conf igured as a 50% dut y cycle clock or a fram e pulse and can o pt ionall y be
inverted. MFSYNC is a 2kHz output that can be similarly configured.
Table 4-6. Mapping Between Output Clock Software Fields and DS3102 Register Fields
SOFTWARE FIELD DS3102 REGISTER FIELDS
2K8K SOURCE
FSCR1:2K8KSRC
DIG1 SOURCE
MCR7:DIG1SRC
DIG2 SOURCE
MCR7:DIG2SRC
DIG1
MCR6:DIG1SS, MCR7:DIG1F
DIG2
MCR6:DIG2SS, MCR7:DIG2F, MCR7:DIG2AF
OC1 to OC7
OCR1 to OCR5
FSYNC
OCR4:FSEN, FSCR1:8KPUL, FSCR1:8KINV
MFSYNC
OCR4:MFSEN, FSCR1:2KPUL, FSCR1 :2KINV
_________________________________________________________________________________________ DS3102DK
15
4.8
DPLL Frequency Limi ts, Phase Detectors, DPLL Lock Cri teria
The DPLL frequency limits specify the hard and soft limits of the DPLL frequency range. When the selected
reference for a DPLL exceeds the soft limit, the SOFTLIM LED for that DPLL turns red but the selected reference is
not disq ualified. If the FL LOL (f requenc y limit loss of l ock) box is check ed in th e DPLL L ock C riteria box, when the
selected reference for a DPLL exceeds the hard limit the DPLL will lose lock (T4 transitions to Not Locked state,
and T0 transitions to LOL state).
The remaining fields are advanced topics. See Table 4-7 and the DS3102 data sheet for more details.
Table 4-7. Mapping Between DPLL Software Fields and DS3102 Register Fields
SOFTWARE FIELD DS3102 REGISTER FIELDS
MCPDEN
PHLIM2:MCPDEN
USEMCPD
PHLIM2:USEMCPD
D180
TEST1:D180
COURSELIM
PHLIM2:COARSELIM
FINELIM
PHLIM1:FINELIM
FLEN
PHLIM1:FLEN
CLEN
PHLIM2:CLEN
FLLOL
DLIMIT3:FLLOL
NALOL
PHLIM1:NALOL
HARD LIMIT
HARDLIM[9:0] in DLIMIT1 and DLIMIT2
SOFT LIMIT
DLIMIT3:SOFTLIM
4.9
REFCLK Calibration
Any k nown frequenc y error in the loc al oscillat or can be c alibrated out inside th e DS3102 b y setting the ppm value
in the REFCLK box. Also, the significant edge of the REFCLK signal can be selected in XOEDGE field.
Table 4-8. Mapping Between REFCLK Software Fields and DS3102 Register Fields
SOFTWARE FIELD DS3102 REGISTER FIELDS
REFCLK slider/textbox
MCLKFREQ[15:0] in MCLK1 and MCLK2
XOEDGE MCR3:XOEDGE
4.10
Programmable DFS
When the Programmable DFS button in the upper-right corner of the main window is pressed, the Programmable
DFS window appears (Figure 4-5). In this window one or more of the output DFS engines in the DS3102 can be
configured to synthesize a custom frequency that is a multiple of 2kHz (f < 77.76MHz) or a multiple of 8kHz (f ≤
311.04MHz). The desired frequency can be entered in the Target Output Clock Frequency box at the top of the
window, and the software will perform the necessary computations to fill in the other numerical fields in window.
The programmable DFS configuration can be applied to one or more DFS engines as specified in the Use
Programm able DF S b ox. F requenc ies b elow 77.76M Hz ar e t ypicall y s ynthesi zed b y the DIG1 or D IG2 DF S engine
and brought out on CMOS/TTL output clock pin(s) by selecting DIG1 or DIG2 in the appropriate output clock
configuration field in the main window of the software. Frequencies of 77.76MHz or above must be synthesized
using an APLL DFS and its associated APLL and are typically brought out on differential output clock pin(s).
If a group of custom clock rates that ar e related to one anoth er by factors of 1, 2, 4, 6, 8, 10, 12, 16, 20, 48, or 64
are needed, often the highest frequency clock can be produced through one of the APLL DFS blocks and then
various lo wer rate c lock s can be se lecte d on one or m ore of the output p ins. Ref er to the OCR1 –O CR4 reg ister s in
the DS3102 data sheet for details.
_________________________________________________________________________________________ DS3102DK
16
If the software-com puted values for DFS Frequenc y, DIG1, DIG2 & APLL Input Frequency, or APLL Multiplier are
manuall y overridd en, the u ser must manuall y ensur e that the DF S Freque ncy fall s within its allowe d range and that
the APLL VCO Frequency falls within its allowed range. Note that the APL VCO Frequency does not need to be
within its allowed range if none of the APLL DFS blocks are selected for use.
The Register Configuration section of the Programmable DFS window show the values that are written to the
DFSC1–DFSC15 r egisters to get th e configuration spe cified in the upper part of the window. DF SC1–DFSC 15 are
located at device addresses 1E0h–1EEh, respectively.
Figure 4-5. Soft war e-Programmable DFS Window
_________________________________________________________________________________________ DS3102DK
17
4.11
I/O P ins
The fields in this window configure the general-purpose I/O available on the DS3102. See Figure 4-6,
Table 4-9, and the DS3102 data sheet for details.
Figure 4-6. Soft ware I/O Pins Window
Table 4-9. Mapping Between I/O Pins Software Fields and DS3102 Register Fields
SOFTWARE FIELD DS3102 REGISTER FIELDS
GPIO1 to GPIO4 Config GPCR:GPIOxD and GP IOxO
GPIO1 to GPIO4 Status GPSR:GPIOx
INTREQ Mode INTCR:LOS, GPO
INTREQ Polarity INTCR:POL
INTREQ Open -Drain Enable INTCR:OD
LOCK Pin Enable MCR1:LOCKPIN
SRFAIL Pin Enable MCR10:SRFPIN
OC1B to OC5 Enable OCR6:OCxEN
OC4POS/NEG to OC7POS/NEG format MCR8:OC4SF to OC7S F
4.12
Register View Window
W hen the Register Vie w button in t he upper -right corner of the main window is pres sed, the Regist er Vie w window
appears (Figure 4-7). In this window the DS3102’s entire register set can be viewed and manually written as
needed.
The large grid that takes up most of the window displays the DS3102 register map. For each register, its
hexadecimal address in square brackets is followed by its register name and its contents in two-digit hex format.
W hen a register is click ed in the main regist er grid, its regis ter descript ion and fiel ds are displa yed at the bottom of
the window. Due to the limited speed of the serial port, the demo kit software does not continually poll every
register and d oes not m ake real-tim e updates to the data dis played on the Re gister Vie w screen. Re gisters can be
manually read as described below.
_________________________________________________________________________________________ DS3102DK
18
The Register Vi e w windo w suppor ts the f ollo wing ac tio ns :
• Read a register. Select the register in the register map.
• Read a register field. Select the register in the map or the register field at the bottom of the window.
• Read all registers. Press the R ea d Al l button.
• Write a register. Double-click the register name in the register map and enter the value to be written.
• Write a register field. Select the register, double-click the field, and enter the value to be written.
• Write a multiregister field. Double-click one of the register names and enter the value for the field.
Figure 4-7. Software Register View Window
_________________________________________________________________________________________ DS3102DK
19
4.13
Confi gur ati on Scr ipts and Log File
4.13.1
Confi gur ati on Log Fil e
Every write comm and issued by the software to the DS3102DK board is logged in file DS3102DKLog.mfg located
in the same directory as the software executable. This file can be viewed in Notepad by pressing the Log File
button in the upper -right corner of the m ain wind ow. C omm and line option "-l <fi lepath>" c an be us ed to c ause the
software to write to a file other than DS3102DKLog.mfg.
4.13.2
Confi gur ati on Scr ipts
All or par t of the text in the Conf iguratio n Log F ile c an be cop ied to a text f ile with a .m fg f ile extens ion for use as a
configuration scr ipt. Conf ig uratio n s c ripts are us ef ul f o r quickly conf iguri ng th e D S 3102 wit hout having to r emember
all the required settings.
Two types of configuration scripts are possible: full a nd partial. A f ull configur ation sc ript can start with th e DS3102
in its power-on default state and configure every aspect of the device to bring it to a desired state. To m ake a full
configuration sc r ipt, r un the s of tware , u nc hec k the De mo Mode c h eckbox, init ia liz e th e de vice, conf igur e t he dev ic e
using the DK software fields, press the Log File button, and use File→Save As in Notepad to save a copy of the
entire log file to a different file name.
A partial configuration file only affects a subset of the DS3102 device settings. To make a partial configuration
script, press the Log File button to view the Log File, press Ctrl-End to jump to the end of the file, and add to the
end of the file a carriage return or comment line (starting with a semicolon) to delimit the start of the desired
configuration. Then save and exit the Log File. Next, configure the device using the DK software fields. Finally,
view the lo g f ile a gai n, j ump to the e nd, and copy ever yth ing from t he d elimiter to the end of the f ile i nto a n e w .m fg
file.
To run a configuration script, press the Config Script button in the upper-right corner of the main window. In the
script window, type the path to the file or press the Browse button to navigate to the file.
Note that when the Demo Mode checkbox is unchecked, during the "Initializing the DS3102" step, the software
runs conf iguration sc ript startup.m fg located in the sam e directory as the sof tware execut able. The star tup.mf g file
can be edi ted or replaced as needed to cha nge the init ial configuratio n of the dev ice. Be aware, h owever, that the
section of the startup.mfg file labeled “Required Initialization” must be executed af ter device power-up or reset for
the DS3102 to operate correctly.
_________________________________________________________________________________________ DS3102DK
20
5.
Appendix 1: Hardwar e Com ponents
DESIGNATION QTY DESCRIPTION SUPPLIER PART
C1, C2, C5, C6,
C9–C12, C15, C42,
C59–C138, C140,
C142, C143, C145,
C147, C151, C155,
C163–C166, C168,
C169
103 0.1µF ±20%, 16V X7R ceramic capacitors (0603) AVX 0603YC104MAT
C3, C13, C14, C16,
C41
5 4.7µF ±10%, 25V X5R ceramic capacitors (1206) PAN ECJ-3YB1E475K
C4, C17, C18, C20 4 6.8µF ±10%, 6.3V X5R ceramic capacitors (1206) PAN ECJ-3YB0J685K
C7 1 68µF ±20%, 16V tantalum capacitor (D case) PAN ECS-T1CD686R
C8 1 0.01µF ±10%, 50V X7R ceramic capacitor (0603) AVX 06035C103KAT
C19 1 100µF ±20%, 4V cerami c cap acit or (1206) TAI AMK316BJ107ML-T
C34–C38, C51–C58,
C139, C141, C153,
C154
17 10µF ±20%, 10V ceramic capacitors ( 1206) PAN ECJ-3YB1A106M
C39, C40 2 22pF ±10%, 100V cera mi c ca paci tors (120 6) AVX 12061A220KAT2A
C43 1 1µF ±10%, 16V ceramic capacitor (1206) PAN ECJ-3YB1C105K
D1 1 1A, 50V general-pur po se sil icon diode GEN 1N4001
D2, D7 2 1A, 40V Schottky diode IRF 10BQ040
DS1–DS4, DS6 5 SMD green LEDs PAN LN1351C
DS5, DS10 2 SMD red LEDs PAN LN1251C
DS16 1 SMD green LED PAN LN1351C
J1, J2, J4–J12,
J15–J18, J20–J31,
J34–J41
35 CONNECTOR, SMB, 50 OHM VERTICAL, 5-PIN AMP 413990-1
J3 1 CONN 2.1MM/5.5MM PWRJACK RT ANGLE PCB,
closed frame, high curr e nt 24VDC@5A CUI, INC PJ-002AH
J13 1 SOCKET, BANANA PLUG, HORIZONTAL, RED MSR 164-6219
J14 1 CONNECTOR, SMB, 50 OHM VERTICAL, 5PI N,
DO NOT POPULATE AMP 413990-1
J19 1 SOCKET, BANANA PLUG, HORIZONTAL, BLACK MSR 164-6218
J50 1 CONN, DB9 RA, LONG CASE AMP 747459-1
J51 1 TERMINAL STRIP, 10 PIN, DUAL ROW, VERT NA NA
J54 1 CONN, USB, TYPE B SINGLE RT ANGLE, BLACK MOL 67068-0000
JMP1–JMP6,
JMP9–JMP12,
JMP16
11 3-pin headers, 0.100 cent er s, v ertical STC TSW-103-07-T-S
JMP7, JMP8 ,
JMP36, JMP37
4 2-pin headers, 0.100 cent er s, v ertical STC TSW-102-07-T-S
JMP13, JMP14,
JMP15
3
DO NOT PLACE
Shorted 2-pin through-hole jumpers
NA NA
JMP62, JMP63 2 3-pin headers, 0.100 cent er s, v ertical STC TSW-103-07-T-S
R1–R4, R17, R19,
R20, R25–R27, R33,
R34, R41, R43, R45,
R47–R63, R111,
R112, R117, R118
36 0Ω ±1%, 1/16W resistors (0603) AVX CJ10-000F
R5, R11, R13, R15,
R21–R24, R29–R32,
R65–R68
16 51.1Ω ±1%, 1/16 W resistors (0603) PAN ERJ-3EKF51R1V
_________________________________________________________________________________________ DS3102DK
21
DESIGNATION QTY DESCRIPTION SUPPLIER PART
R6
1
100k
Ω
±
5%, 1/16W resistor (0603)
PAN
ERJ-3GEYJ104V
R7, R9, R10, R12,
R14, R84, R110,
R113, R115, R116,
R120–R123
14 10kΩ ±5%, 1/16W resistors (0 603) PAN ERJ-3GEYJ103V
R8, R16, R18, R46,
R64, R83, R100,
R101, R102
9 Resistors (0603) DO NOT POPULATE NA NA
R28 1 33.2Ω ±1%, 1/16W resistor (0 603) PAN ERJ-3EKF33R2V
R35–R40, R42, R44,
R94, R108 10 330Ω ±5%, 1/16W resistors (0603) PAN ERJ-3GEYJ331V
R97 1 20kΩ ±5%, 1/16W resistor (0603) PAN ERJ-3GEYJ203V
SW1 1 SWITCH DPDT SLIDE 6 P IN TH TYC SSA22
SW5
1
SWITCH MOM 4PIN SINGLE P OLE
PAN
EVQPAE04M
TP1–TP22,
TP49–TP60,
TP65–TP84
54 Test Points, 1 PLATED HOLE, DO NOT STUFF NA NA
U1, U2, U5, U9–U24,
U27, U28, U30–U34 26 L_TINYLOGIC HIGH SPEED 2-INPUT OR GATE,
5 PIN SOT23 FAI NC7SZ32M5
U3 1 IC, LINE CARD TIMING, -40°C to +85°C, 64 PIN
QFP, DO NOT POPULATE
DAL NOT POPULATED
U4, U6 2 LINEAR REGULATOR, 3.3V, 16 PIN TSSOP-EP MAX MAX1793EUE-33
U7, U25 2 L_TINYLOGIC HIGH SPEED 2-INPUT XOR
GATE, 5 PIN SOT23
FAI NC7SZ86M5
U8 1 LINEAR REGULATOR, 1.8V, 16 PIN TSSOP-EP MAX MAX1793EUE-18
U26 1 IC, LINEAR REGULA TOR, 1. 5W, 2.5V OR ADJ,
1A, 16 PIN TSSOP-EP
MAX MAX1793EUE-25
U29 1 IC, TCXO, 12.8MHz, 0°C to +70°C, 16-PIN SOIC DAL DS4026+BCC
U35 1 IC, LINE CARD TIMING WITH SYNCHRONOUS
ETHERNET SUPPORT, -40 TO 85C, 81 PIN BGA
DAL DS3102
U41 1
DUAL RS-232 XMITR/RCVR 16 PIN SOIC (300
MIL)
DAL DS232AS
U42 1 HIGH SPEED MICRO 44-PIN TQFP 0°C to +70°C DAL DS87C520-ECL
U44 1 MICROPROCESSOR VOL TAGE MONITOR,
3.08V RESET, 4PIN SOT143
MAX MAX811TEUS-T
U45 1
MICROPROCESSOR VOL TAGE MONITOR,
4.38V RESET, 4PIN SOT143
MAX MAX812MEUS-T
U46 1 IC, SINGLE-CHIP USB TO UART BRIDGE, 28 PIN
QFN
SIL CP2101
_________________________________________________________________________________________ DS3102DK
22
DESIGNATION QTY DESCRIPTION SUPPLIER PART
Y1 1 OSCILLATOR, CRYSTAL CL OCK, 3.3V -
12.8MHz
SAR NTH069A3-12.8
Y2 1
OSCILLATOR, RAKON TCXO, 3.3V, 12.8MHz, 4
PIN SMD
RAK E4837LF
Y3 1 OSCILLATOR, CRYSTAL CLOCK XO 1613,
3.3V CMOS, LOW JITTER-12.8MHz, 4-PIN
SMD, DO NOT POPULATE
SAR S1613A-12.8000
Y4 1 OSCILLATOR, CRYSTAL CLOCK XO 1633,
3.3V CMOS, LOW JITTER-12.8MHz, 4-PIN
SMD, DO NOT POPULATE SAR S1633A-12.8000
Y7 1 11.0592MHz low-profile crysta l PLE LP49-33-11.0592M
6.
Schematics
The schematics are featured in the following pages.
7.
Document Revision Hi s tory
REVISION
DATE
DESCRIPTION
061107 Initial release.
092107
In Section 4.13.2, fourth paragraph, deleted last two sentences; in the fifth paragraph, added new
last sentence.
In Appendix 1, component U3, changed Part to “Not Populated.”
101607
Removed references to “included international power supply.” Not shipping power supply
because the board can be USB powered.
In the Minimum System Requirements, third bullet, added “USB or” to “Available USB or Serial
(COM) Port.”
112007
In Section 1.1, added a sentence indicating that cables connected to single-ended outputs must
have 50
Ω
termination.
In Appendix 1, changed component Y2 to Rakon TCXO E4837LF.
2012-05 Reformatted for Microsemi. No content change.
OR DS3102
Wed May 30 13:54:19 2007
DS3104DK01B0
JML
013007
1OF 12
1
TP20
1
TP22
1
TP21
1
TP17
1
TP16
2
1
R42
2
1
R44
3
2
1
JMP16
3
2
1
JMP12
3
2
1
JMP11
3
2
1
JMP10
3
2
1
JMP9
2
1
R34
2
1
C163
2
1
C164
2
1
C165
2
1
C166
2
1
DS5
2
1
R35
2
1
DS6
2
1
R40
2
1
R33
2
1
R27
2
1
R26
2
1
R25
D8
G4
D3
F5
F4
E5
E4
D5
D4
C6
G3
F6
D6
C4
G5
E3
G6
E6
C5
A2
G8
H9
H8
F7
G1
B3
C7
E8
C9
B9
C1
H3
J3
H2
J2
E2
E1
B6
D2
D1
A6
B5
A5
B4
A4
A3
B7
A7
B8
J1
G7
F8
E9
C8
A8
A9
B1
H6
J6
H4
J4
H7
J7
H5
J5
G9
F9
J9
J8
H1
D9
D7
E7
G2
F1
C3
A1
F3
F2
C2
B2
U35
2
1
R84
2
1
R10
2
1
R83
2
1
R8
2
1
DS10
2
1
C8
2
1
R94
2
1
R97
JTDI
NA
VPLL1
VPLL4
VPLL3
VPLL2
VDDIOB
0.0
0.0
0.0
OC4POS
OC4NEG
OC4B
OC3
OC2
OC2B
OC4
NA
OC3B
NA
OC1B
OC1 NA
330
SRFAIL
IC8
DUT33
JTDO
DUT18
330
.01UF
20K
NA
WDT
NA
LOCK
SRFAIL
RED
GREEN
RED
PORNOT
REFCLK
INTREQ
SRFAIL
IC6POS
IC6NEG
IC4
SONSDH
TEST
SONSDH
MFSYNC
OC7NEG
NA
NA
NA
LOCK
DNP
DNP
10K
CPOL
CPHA
OC5POS
SYNC3
SYNC2
IC9
IC3
IC1NEG
WDT
0.0
FSYNC
OC7POS
SCLK
SDI
VPLL1
.1UF
.1UF
.1UF
VPLL3
VPLL2
LOCK
SRCSW
OC6NEG
OC5
.1UF
IC5POS
IC2NEG
IC2POS
OC6POS
VPLL4
CPHA
SDO
330
NA
NA
INTREQ
JTRST
IC1POS
DUT18
10K
JTCLK
TEST
SRCSW
CS
0.0
330
OC5B
OC5NEG
IC5NEG
SYNC1
330
CPOL
JTMS
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
VCC
VCC
BGA
DS3104_U1
JTCLK
SRFAIL
SRCSW
GPIO4/SONSDH
VDD1
VSS_OC45
VSS_OC67
AVSS_PLL1
JTMS
VDD_OC67
VDD_OC45
IC2NEG
IC1POS
IC4
IC9
IC5POS
IC5NEG
AVSS_PLL4
VSS6
AVSS_PLL3
AVSS_PLL2
IC3
IC8
IC6POS
IC6NEG
REFCLK
VSS2
VSS3
VSS5
VSS4
VSS1
RST*
SYNC1
SYNC2
SYNC3
WDT
TEST
IC1NEG
VDDIOB
AVDD_PLL1
VDDIO3
VDDIO2
VDDIO4
VDDIO1
VDD3
VDD2
JTDO
JTDI
JTRST*
LOCK
AVDD_PLL4
AVDD_PLL3
AVDD_PLL2
OC1
OC1B/GPIO1
OC2
OC2B/GPIO2
OC3
OC3B/GPIO3
OC4
OC4B
OC4NEG
OC4POS
OC5
OC5B
OC5NEG
OC5POS
OC6NEG
OC6POS
OC7NEG
OC7POS
FSYNC
CS*
MFSYNC
SDI
SCLK
SDO
CPOL
CPHA
IC2POS
INTREQ/SRFAIL
VCC
OR DS3106
Wed May 30 13:54:21 2007
JML
2OF 12
013007
DS3104DK01B0
12
10
8
3
21
62
60
53
40
31
16
15
1
61
54
32
14
11
9
7
4
22
58
57
39
27
2
33
28
13
64
52
43
47
48
6
19
20
56
63
46
45
36
38
35
18
37
41
50
51
49
5
25
26
23
24
34
30
29
17
44
42
55
59
U3
DUT33DUT18
VPLL4
VPLL3
VPLL2
VPLL1
OC3
SRFAIL
FSYNC
MFSYNC
SDO
SCLK
SRCSW
IC9
JTRST
JTCLK
JTDO
JTMS
JTDI
NA
DS3105-SE
OC6NEG
OC6POS
CPHA
CS
REFCLK SYNC3
LOCK
OC1B
OC2B
OC3B
SDI
SYNC1
IC6NEG
IC6POS
IC5NEG
IC5POS
IC4
IC3
INTREQ
TEST
SONSDH
SYNC2
PORNOT
I26
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
DS3105_U2
QFP
JTRST*
TEST
RST*
SYNC1
SYNC2
GPIO4/SONSDH
IC9
IC6NEG
SDI
SDO
VDD2
VDD4
VDDIO1
IC5NEG
O3F1/SRFAIL
VDDIO2
VDDIO3
VDDIO4
SRCSW
VSS6
VSS7
OC3
FSYNC
IC6POS
IC5POS
IC4
REFCLK
VSS1
CPHA
CS*
SCLK
MFSYNC
O6F1/GPIO2
O6F2/GPIO3
O3F2/LOCK
O6F0/GPIO1
OC6NEG
VSS5
VSS8
VSS_OC6
AVSS_DL
VSS_PLL1
VSS_PLL2
VSS_PLL3
VSS_PLL4
VDD_PLL1
VDD_PLL2
VDD_PLL3
VDD_PLL4
JTCLK
JTDI
VDD1
INTREQ/SRFAIL
O3F0/SYNC3
OC6POS
VSS4
VSS3
VSS2
JTMS
IC3
JTDO
VDD_OC6
AVDD_DL
VDD3
ALL SIGNAL TRACKS ARE 50 OHM WITH RESPECT TO PLANE
THAT IS SINUSOIDAL
CAN BE SWITCHED INTO
IC3 PATH ARE USED
TO SQUARE ACLOCK
INPUT CLOCKS
THE INVERTERS THAT
Wed May 30 13:54:19 2007
3OF 12
013007
JML
DS3104DK01B0
2
1
R64
2
1
C10
8
1
54
Y4
8
1
54
Y3
1
TP19
1
TP18
2
1
R46
2
1
C5
8
1
54
Y1
6
54
3
2
1
SW1
2
1
R5
2
1
C1
2
1
R6
4
2
1
U25
4
2
1
U7
3
2
1
JMP4
2
1
R15
2
1
R14
3
2
1
JMP3
2
1
R13
2
1
R12
3
2
1
JMP2
2
1
R11
2
1
R9
3
2
1
JMP1
2
1
R7
2
1
R102
2
1
C15
2
1
R101
2
1
R100
2
1
C12
2
1
C19
2
1
C11
2
4
16
3
12
13
5
14
1
11
15
U29
1
J14
2
1
R16
2
1
R18
4
1
3
2
Y2
2
1
C2
2
1
R28
1
J12
1
J11
1
J10
2
1
R32
1
J9
2
1
R31
1
J8
2
1
R30
1
J7
2
1
R29
1
J6
VCC
SYNC2
100K
VCC
VCC
VCC
VCC
51.1
51.1
51.1
REFCLK
NA
.1UF
NA
12.8MHZ
DNP
DNP
OSC33
12.8MHZ_3.3V
12.8MHZ_3.3V
12.8MHZ_3.3V_XO
.1UF
DNP
12.8MHZ_3.3V_XO
REFCLK
DNP
OSC33
DNP
.1UF
OSC33
33.2
100UF
DNP
IC3
51.1 51.1
IC4
IC8
10K
51.1
IC9
SYNC3
SYNC1
10K
10K
51.1
10K
51.1
.1UF
.1UF
.1UF
.1UF
DNP
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
RF_OUT
OSC_TCXO
VC VS
GND
OUTGND
OSC
1
VCC
OUTGND
OSC
1
VCC
OUTGND
OSC
1
VCC
DPDT
NC7SZ86
C
B
A
NC7SZ86
C
B
A
DS4026_U
VOSC
VCCD
VCC
VREF
GNDOSC
GNDA
GND
GNDD
FOUT
SCL
SDA
ALL SIGNAL TRACKS ARE 50 OHM WITH RESPECT TO PLANE
INPUT CLOCKS
Wed May 30 13:54:20 2007
DS3104DK01B0
JML
013007
4OF 12
1
J31
1
TP8
1
TP7
1
J30
1
J29
1
TP6
1
J28
1
TP5
1
TP12
1
TP11
2
1
R24
2
1
R23
1
TP10
2
1
R22
1
TP9
2
1
R21
2
1
JMP8
2
1
JMP7
1
TP56
1
TP55
1
TP54
1
TP53
1
J37
1
TP52
1
TP51
1
J36
2
1
R68
2
1
R67
2
1
JMP37
2
1
JMP36
1
TP50
1
TP49
1
J35
2
1
R66
1
J34
2
1
R65
IC2NEG
IC2POS
IC1NEG
IC1POS
IC5NEG
IC5POS
51.1
51.1 51.151.151.1
51.1 51.1 51.1
IC6NEG
IC6POS
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
OUTPUT CLOCKS
5OF 12
Wed May 30 13:54:20 2007
013007
JML
DS3104DK01B0
2
1
R62
2
1
R61
2
1
R60
2
1
R59
2
1
R58
2
1
R63
2
1
R50
2
1
R57
2
1
R56
2
1
R54
2
1
R52
2
1
R48
4
2
1
U34
2
1
R20
4
2
1
U33
4
2
1
U32
4
2
1
U31
2
1
R19
4
2
1
U30
1
J18
1
J17
2
1
R17
4
2
1
U27
1
J16
4
2
1
U2
4
2
1
U1
1
J1
2
1
R1
4
2
1
U24
2
1
R55
4
2
1
U23
4
2
1
U22
4
2
1
U21
2
1
R53
1
J26
1
J27
4
2
1
U20
4
2
1
U19
2
1
R51
1
J25
4
2
1
U18
4
2
1
U17
2
1
R49
1
J24
4
2
1
U16
4
2
1
U15
2
1
R47
1
J23
4
2
1
U14
4
2
1
U13
2
1
R45
1
J22
4
2
1
U12
4
2
1
U11
2
1
R43
1
J21
2
1
R41
4
2
1
U10
4
2
1
U9
1
J20
OC1
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
OC5B
MFSYNC
FSYNC
OC3B
OC2B
OC1B
OC5
OC4
OC3
OC2
OC4B
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
NC7SZ32
AC
B
OUTPUT CLOCKS 6OF 12
Thu Feb 15 16:29:11 2007
013007
DS3104DK01B0
JML
1
J40
1
J41
1
J38
1
J39
1
TP59
1
TP60
1
TP57
1
TP58
1
TP4
1
TP3
1
TP2
1
TP1
1
J15
1
J5
1
J4
1
J2
OC4POS
OC4NEG
OC5POS
OC5NEG
OC6NEG
OC6POS
OC7NEG
OC7POS
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
INTENTIONALLY LEFT BLANK
7OF 12
Wed Feb 21 13:57:17 2007
JML
DS3104DK01B0
013007
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
FIRMWARE V2.28
DS3104DK01B0
Wed May 30 13:54:18 2007
013007
8OF 12
JML
1
TP13
1
TP14
1
TP15
2
1
R4
2
1
R3
2
1
R2
4
2
1
U5
3
2
1
JMP63
3
2
1
JMP62
9
8
7
6
5
4
3
2
1
J50
2
1
C39
2
1
C40
1
2
Y7
2
1
C34
2
1
C36
2
1
C37
2
1
C35
2
6
16
7
10
14
11
9
8
12
13
15
4
5
1
3
U41
2
1
C38
2
1
R110
2
1
R108
2
1
DS16
15
14
38
4
26
13
12
11
10
9
8
7
5
25
24
23
22
21
20
19
18
3
2
1
44
43
42
41
40
29
27
30
31
32
33
34
35
36
37
U42
SCLK
0.0
POR
0.0
0.0
RX232
CS
USB_RXD
USB_TXD
10UF
SDI
RXD0
11.0592MHZ
RX232
TX232
TX232
TXD0
RXD0
RS232
10UF
10UF
10UF
10UF
TXD0
INTREQ
22PF
22PF
10K
NA
330
GREEN
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
VCC
NC7SZ32
AC
B
CONN_DB9P
H
G
F
C
A
B
D
E
J
DS87C520_TQFP
P1_5
GND<2-0>
XTAL2
VCC
AD0
AD1
AD2
AD4
AD6
AD7
ALE
PSEN
P2_7
P2_6
P2_5
P2_3
P2_4
P2_2
P2_1
P2_0
P1_4
RST
P1_6
P3_1
P3_0
P3_2
P3_4
P3_3
P3_7
P3_6
P3_5
XTAL1
AD3
P1_3
P1_1
P1_2
P1_7
EA
AD5
P1_0
DS232A
T2IN
T1IN
R1IN
R2IN
T2OUT
T1OUT
R2OUT
R1OUT
C1POS
C1NEG
VNEG
VPOS
C2NEG
GND
C2POS
VCC
V5_0
V5_0
Wed May 30 13:54:19 2007
013007
JML
9OF 12
DS3104DK01B0
4
3
2
1
SW5
4
2
3
1
U44
2
1
R111
4
2
3
1
U45
2
1
R112
1
TP83
1
TP84
2
1
R123
2
1
R122
2
1
R121
2
1
R120
5
4
3
2
1
J54
2
1
R118
2
1
R117
2
1
C41
2
1
C43
2
1
C42
2
1
R116
2
1
R115
10
9
8
7
65
4
3
2
1
J51
2
1
R113
6
8
4
5
26
11
12
25
24
9 2
7
20
19
18
17
16
15
14
13
22
21
10
3
28
27
1
23
U46
USBPWR
NA
1UF
10K
10K
NA
10K
10K
0.0
0.0
USB_RXD
USB_TXD
10K
4.38V
JTCLK
10K
10K
JTMS
JTDI
JTRST
JTDO
0.0
0.0
3.08V
POR
PORNOT
.1UF
4.7UF
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
MAX811_U
RESET*
VCC
GND
MR*
VCC
MAX812_U
VCC
GND
MR*
RESET
V5_0
CP2101_U1
USBDM
VBUS
USBDP
RTS*
DTR*
CTS*
DSR*
DCD*
RI*
NC7
NC8
NC9
NC10
NC11
RST*
REGIN
NC6
NC4
NC5
NC3
NC2
NC1
GND
VDD
TXD
RXD
SUSPEND_HIGH
SUSPEND_LOW*
USB
GND
SH
DAT+
DAT-
VDD
VCC
6
10
8
4
1
2
3
5
7
9
CONN_10P
2.5 VOLT REGULATOR
Wed May 30 13:54:20 2007
10 OF 12
013007
JML
DS3104DK01B0
3
2
1
JMP5
3
2
1
JMP6
1
2
D2
2
1
C3
7
11
6
15
14
13
12
5
4
3
2
10
U26
2
1
C4
2
1
JMP14
2
1
JMP15
2
1
JMP13
4
2
1
U28
7
11
6
15
14
13
12
5
4
3
2
10
U8
1
2
J3
2
1
J19
1
2
D7
2
1
J13
1
2
D1
2
1
C7
2
1
R39
2
1
DS4
2
1
R38
2
1
DS3
2
1
R37
2
1
DS2
2
1
R36
2
1
DS1
2
1
C16
2
1
C13
7
11
6
15
14
13
12
5
4
3
2
10
U4
2
1
C20
2
1
C18
2
1
C17
2
1
C14
7
11
6
15
14
13
12
5
4
3
2
10
U6
1AMP
2.1MM/5.5MM
USBPWR
V5_0
330
NA
DUT18
68UF
OSC33
DUT33
VDDIOB
DUT18
DUT33
4.7UF
6.8UF 6.8UF
4.7UF
6.8UF
6.8UF
330
330
330
OSC33
4.7UF
1AMP
4.7UF
DUT33
PAGE:
DATE:
TITLE:
ENGINEER:
A A
B B
C C
DD
1
1
2
2
3
3
4
45
56
6
7
7
8
8
V5_0
MAX1793
IN2
IN1
IN3
OUT3
OUT2
OUT4
OUT1
RST*
SET
IN4
SHDN*
GND
NC7SZ32
AC
B
MAX1793_U2
IN2
IN3
GND
SHDN*
IN4
IN1
SET
RST*
OUT1
OUT4
OUT2
OUT3
CONN_BANANA_2P
B
A
V5_0
V5_0
CONN_BANANA_2P
B
A
VCC
MAX1793_U2
IN2
IN3
GND
SHDN*
IN4
IN1
SET
RST*
OUT1
OUT4
OUT2
OUT3
V5_0
V5_0
V5_0
MAX1793_U2
IN2
IN3
GND
SHDN*
IN4
IN1
SET
RST*
OUT1
OUT4
OUT2
OUT3
Wed May 30 13:54:21 2007
013007
DS3104DK01B0
JML
11 OF 12
2
1
C9
2
1
C6
2
1
C142
2
1
C140
2
1
C58
2
1
C54
2
1
C57
2
1
C53
2
1
C56
2
1
C52
2
1
C62
2
1
C66
2
1
C70
2
1
C74
2
1
C78
2
1
C61
2
1
C65
2
1
C69
2
1
C73
2
1
C77
2
1
C82
2
1
C86
2
1
C90
2
1
C94
2
1
C98
2
1
C102
2
1
C106
2
1
C81
2
1
C85
2
1
C89
2
1
C93
2
1
C97
2
1
C101
2
1
C105
2
1
C110
2
1
C114
2
1
C118
2
1
C122
2
1
C126
2
1
C130
2
1
C134
2
1
C109
2
1
C113
2
1
C117
2
1
C121
2
1
C125
2
1
C129
2
1
C133
2
1
C138
2
1
C137
2
1
C60
2
1
C64
2
1
C68
2
1
C72
2
1
C76
1
TP65
1
TP66
1
TP67
2
1
C51
2
1
C55
2
1
C59
2
1
C63
2
1
C67
2
1
C71
2
1
C75
2
1
C80
2
1
C84
2
1
C88
2
1
C92
1
TP68
1
TP69
1
TP71
1
TP70
2
1
C96
2
1
C100
2
1
C104
1
TP72
1
TP73
1
TP74
2
1
C79
2
1
C83
2
1
C87
2
1
C91
2
1
C95
2
1
C99
2
1
C103
2
1
C108
2
1
C112
2
1
C116
1
TP75
1
TP76
1
TP77
1
TP78
2
1
C120
2
1
C124
2
1
C128
2
1
C132
1
TP79
1
TP81
1
TP80
2
1
C107
2
1
C111
2
1
C115
2
1
C119
2
1
C123
2
1
C127
2
1
C131
2
1
C136
1
TP82
2
1
C135
2
1
C153
2
1
C154
2
1
C155
2
1
C169
2
1
C168
2
1
C139
2
1
C141
2
1
C143
2
1
C145
2
1
C147
2
1
C151
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
10UF
10UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
10UF
10UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
10UF
10UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
10UF
10UF
GND
VCC
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
10UF
10UF
.1UF
V5_0
VDDIOB
10UF
.1UF
.1UF
10UF
.1UF
.1UF
OSC33
.1UF
.1UF.1UF
.1UF.1UF
DUT33
DUT18
.1UF
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V5_0
VCC
VCC
01 -021907 -RELEASE FOR REVIEW
02 -030907 -ADDED TWO FOOTPRINTS FOR SMD STRATUM 4OSC,
-ADDED SPI TESTPOINTS, CHANGED 4.7UF TO 100 UF
REVISION HISTORY -
A0 -051707 -GENERAL CLEANUP, RELEASE TO DATASHEET,
-ON DS OSC, OTHER CHANGES MADE PER DESIGN REVIEW
B0 -052907 -FIXED USBPWR NET, FIXED SILKSCREEN BELOW SONSDH HEADER
Tue May 29 13:45:02 2007
JML
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