1. General description
The 74LVC157A-Q100 is a quad 2-input multip lexer which select four bits of data from two
sources under the control of a common select input (S). The four outputs present the
selected data in the true (non-inverted) form. The enable input (E) is active LOW. When
pin E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all the other
input conditions. Moving the data from two groups of registers to four common output
buses is a common use of the 74LVC157A-Q100. The state of the common da ta select
input (S) determines the p articular register from which the dat a comes. It can also be used
as function generator.
It is useful for implementing highly irregular logic by generating any 4 of the 16 different
functions of two variables with one variable common.
The device is the logic implement ation of a 4-pole, 2-position switch, where the position of
the switch is determined by the logic levels applied to pin S.
Inputs ca n be driven from e ither 3.3 V or 5 V devices. This f eature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74LVC157A-Q100
Quad 2-input multiplexer
Rev. 2 — 2 May 2013 Product data sheet
74LVC157A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 2 May 2013 2 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC157AD-Q100 40 Cto+125C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74LVC157ADB-Q100 40 Cto+125C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74LVC157APW-Q100 40 Cto+125C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
74LVC157ABQ-Q100 40 Cto+125C DHVQFN16 plastic dual In-line compatible thermal enhanced
very thin quad flat package; no leads; 16
terminals; body 2.5 3.5 0.85 mm
SOT763-1
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna481
S
1
15
12974
131410116532
E1Y
1I11I0
2Y
2I12I0
3Y
3I13I0
4Y
4I14I0
mna482
12
9
7
1G1
15 EN
1MUX
14
13
14
10
11
6
5
3
2
Fig 3. Functional diagram
mna483
MULTIPLEXER
OUTPUTS
SELECTOR
1Y
2Y
3Y
4Y 12
9
7
4
S
13
151
14
10
11
6
5
3
2
E
1I0
1I1
2I0
2I1
3I0
3I1
4I0
4I1
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Product data sheet Rev. 2 — 2 May 2013 3 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
5. Pinning information
5.1 Pinning
Fig 4. Logic diagra m
1Y
1I1
1I0
2Y
2I1
2I0
3Y
3I1
3I0
mna484
4Y
4I1
4I0
S
E
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration for SO16 and (T)SSOP16 Fig 6. Pin configuration for DHVQFN16
/9&$4
6
9&&
, (
, ,
<
,
, <
, ,
<
,
*1' <
DDD







DDD
/9&$4
< ,
, ,
, <
*1'

< ,
, ,
, (
*1'
<
6
9
&&
7UDQVSDUHQWWRSYLHZ







WHUPLQDO
LQGH[DUHD
74LVC157A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 2 May 2013 4 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care
Table 2. Pin de scription
Symbol Pin Description
S 1 common data select input
1I0 2 data input from source 0
1I1 3 data input from source 1
1Y 4 multiplexer output
2I0 5 data input from source 0
2I1 6 data input from source 1
2Y 7 multiplexer output
GND 8 ground (0 V)
3Y 9 multiplexer output
3I1 10 data input from source 1
3I0 11 data input from source 0
4Y 12 multiplexer output
4I1 13 data input from source 1
4I0 14 data input from source 0
E15 enable input (active LOW)
VCC 16 supply voltage
Table 3. Function table[1]
Input Output
ESnI0 nI1 nY
HXXXL
LLLXL
LLHXH
LHXLL
LHXHH
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Product data sheet Rev. 2 — 2 May 2013 5 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO16 packages: above 70 C the value of PDd erates linearly with 8 mW/K.
For (T)SSOP16 packages: above 60 C the value of PDderates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of PDderates linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI<0 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO>V
CC or VO<0 - 50 mA
VOoutput voltage [2] 0.5 VCC +0.5 V
IOoutput curren t VO=0V toV
CC -50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C[3] -500mW
Table 5. Re commended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V
VIinput voltage 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temp erature 40 - +125 C
t/V input transition rise and fall
rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
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Product data sheet Rev. 2 — 2 May 2013 6 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
9. Static characteristics
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25C.
Table 6. Static characteristics
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC -0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage
VI=V
IH or VIL
IO=100 A;
VCC =1.65Vto3.6V VCC 0.2 - - VCC 0.3 - V
IO=4mA; V
CC = 1.65 V 1.2 - - 1.05 - V
IO=8mA; V
CC = 2.3 V 1.8 - - 1.65 - V
IO=12 mA; VCC = 2.7 V 2.2 - - 2.05 - V
IO=18 mA; VCC = 3.0 V 2.4 - - 2.25 - V
IO=24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage
VI=V
IH or VIL
IO= 100 A;
VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V
IO=4mA; V
CC = 1.65 V - - 0.45 - 0.65 V
IO=8mA; V
CC = 2.3 V - - 0.6 - 0.8 V
IO=12mA; V
CC = 2.7 V - - 0.4 - 0.6 V
IO=24mA; V
CC = 3.0 V - - 0.55 - 0.8 V
IIinput leakage
current VCC = 3.6 V; VI=5.5VorGND - 0.1 5- 20 A
ICC supply
current VCC = 3.6 V; VI=V
CC or GND;
IO=0A -0.110-40A
ICC additional
supply
current
per input pin;
VCC = 2.7 V to 3.6 V;
VI=V
CC 0.6 V; IO=0A
- 5 500 - 5000 A
CIinput
capacitance VCC = 0 V to 3.6 V;
VI=GNDtoV
CC
-5.0---pF
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Product data sheet Rev. 2 — 2 May 2013 7 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
10. Dynamic characteristics
[1] Typical values are measured at Tamb =25C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz; fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
(CLVCC2fo) = sum of outputs
Table 7. Dynamic characteristics
Vo ltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay nI0, nI1 to nY; see Figure 8 [2]
VCC = 1.2 V - 16 - - - ns
VCC = 1.65 V to 1.95 V 1.0 4.8 10.2 1.0 11.8 ns
VCC = 2.3 V to 2.7 V 1.5 2.8 5.8 1.5 6.7 ns
VCC = 2.7 V 1.0 2.9 5.9 1.0 7.5 ns
VCC = 3.0 V to 3.6 V 1.0 2.5 5.2 1.0 6.5 ns
Eto nY; see Figure 7 [2]
VCC = 1.2 V - 17 - - - ns
VCC = 1.65 V to 1.95 V 0.5 4.8 12.8 0.5 14.7 ns
VCC = 2.3 V to 2.7 V 1.5 2.8 7.2 1.5 8.3 ns
VCC = 2.7 V 1.0 2.9 7.8 1.0 10.0 ns
VCC = 3.0 V to 3.6 V 1.0 2.6 6.5 1.0 8.5 ns
S to nY; see Figure 8 [2]
VCC = 1.2 V - 16 - - - ns
VCC = 1.65 V to 1.95 V 1.0 5.1 12.4 1.0 14.3 ns
VCC = 2.3 V to 2.7 V 1.5 3.0 7.0 1.5 8.1 ns
VCC = 2.7 V 1.0 3.1 7.3 1.0 9.5 ns
VCC = 3.0 V to 3.6 V 1.0 2.7 6.3 1.0 8.0 ns
tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns
CPD power dissipation
capacitance per input; VI = GND to VCC [4]
VCC = 1.65 V to 1.95 V - 9.4 - - - pF
VCC = 2.3 V to 2.7 V - 12.8 - - - pF
VCC = 3.0 V to 3.6 V - 15.9 - - - pF
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Product data sheet Rev. 2 — 2 May 2013 8 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
11. Waveforms
VM= 1.5 V at VCC 2.7 V; VM=0.5VCC at VCC <2.7V.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7. Enable input (E) to output (nY) propagation delays
mna485
tPHL tPLH
VM
VM
E input
nY output
GND
VCC
VOH
VOL
VM= 1.5 V at VCC 2.7 V; VM=0.5VCC at VCC <2.7V.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. Data inputs (nI0, nI1) and common data select input (S) to output (nY) propagation delays
mna486
t
PHL
t
PLH
V
M
V
M
nI0, nI1, S
input
nY output
GND
V
I
V
OH
V
OL
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Product data sheet Rev. 2 — 2 May 2013 9 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
Test data is given in Table 8. Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 9. Test circuit for measuring switching times
Table 8. Test data
Supply voltage Input Load
VItr, tfCLRL
1.2 V VCC 2 ns 30 pF 1 k
1.65 V to 1.95 V VCC 2 ns 30 pF 1 k
2.3 V to 2.7 V VCC 2 ns 30 pF 500
2.7V 2.7V 2.5 ns 50 pF 500
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500
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Product data sheet Rev. 2 — 2 May 2013 10 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
12. Package outline
Fig 10. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
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Product data sheet Rev. 2 — 2 May 2013 11 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
Fig 11. Package outline SOT338-1 (SSOP16)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25
7.9
7.6 1.03
0.63 0.9
0.7 1.00
0.55 8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2
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Product data sheet Rev. 2 — 2 May 2013 12 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
Fig 12. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
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Product data sheet Rev. 2 — 2 May 2013 13 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
Fig 13. Package outline SOT763-1 (DHVQFN16)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4 1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
27
15 10
9
8
1
16
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
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Product data sheet Rev. 2 — 2 May 2013 14 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
13. Abbreviations
14. Revision history
Table 9. Abbreviations
Acronym Description
CDM Charged Device Mo del
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Tran s istor Logic
MIL Military
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC157A_Q100 v.2 20130502 Product data sheet - 74LVC157A_Q100 v.1
Modifications: •74LVC157ADB-Q100 added.
74LVC157A_Q100 v.1 20120807 Product data sheet - -
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Product data sheet Rev. 2 — 2 May 2013 15 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsisten cy or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyon d those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — T his NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the pre liminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LVC157A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 2 May 2013 16 of 17
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC157A-Q100
Quad 2-input multiplexer
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 May 2013
Document identifier: 74LVC157A_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16 Contact information. . . . . . . . . . . . . . . . . . . . . 16
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17