1
DS3105
Line Card Timing IC
General D es cription
The DS3105 is a low-cost, feature-rich timing IC for
telecom line cards. Typically, the device accepts two
reference clocks from dual redundant system timing
cards. The DS3105 continually monitors both inputs
and performs automatic hitless reference switching if
the prim ary ref erence fai ls. T he highly progr amm able
DS3105 supports numerous input and output
frequencies including frequencies required for
SONET/SDH, Synchronous Ethernet (1G, 10G, and
100Mbps), wireless base stations, and CMTS
systems. PLL bandwidths from 18Hz to 400Hz are
supported, and a wide variety of PLL characteristics
and device features can be configured to meet the
needs of many different applications.
The DS3105 re gister s et is back ward c om patible with
Semtech’s ACS8525 line card timing IC. The DS3105
pinout is sim ilar but not ide ntic a l to the ACS85 25.
Applications
SONET/SDH, Synchronous Ethernet, PDH, and
Other Line Cards in WAN Equipment Including
MSPPs, Ethernet Switches, Routers, DSLAMs,
and Wireless Base Stations
Order ing Information
PART T E MP RANGE PIN-PACKAGE
DS3105LN
-40°C to +85°C
64 LQFP
DS3105LN+
-40
°
C to +85
°
C
64 LQFP
+Denotes a lead(Pb)-free/RoHS-compliant pack age.
Features
♦ Advanced DPLL Technology
♦ Programmable PLL Bandwidth: 18Hz to 400Hz
♦ Hitless Reference Switching, Automatic or Manual
♦ Holdover on Loss of All Input References
♦ Frequency Conversion Among SONET/SDH,
PDH, Ethernet, Wireless, and CMTS Rates
♦ Five Input Clocks
♦ Two CMOS/TTL Inputs (≤ 125MHz)
♦ Two LVDS/LVPECL/CMOS/TTL (≤ 156.25MHz)
♦ Backup Input (CMOS/TLL) in Case of Complete
Loss of System Timing References
♦ Three Optional Frame-Sync Inputs (CMOS/TTL)
♦ Continuous Input Clock Quality Monitoring
♦ Numerous Input Clock Frequencies Supported
Ethernet xMII: 2.5, 25, 125, 156.25MHz
SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
PDH: N x DS1, N x E1, N x DS2, DS 3, E3
Frame Sync: 2kHz, 4kHz, 8kHz
Custom Clock Rates: Any Multiple of 2kHz Up to
131.072MHz, Any Multiple of 8kHz Up to
155.52MHz
♦ Two Output Clocks
♦ One CMOS/TTL Output (≤ 125MHz)
♦ One LVDS/LVPECL Output (≤ 312.50MHz)
♦ Two Optional Frame-Sync Outputs: 2kHz, 8kHz
♦ Numerous Output Clock Frequencies Supported
Ethernet xMII: 2.5, 25, 125, 156.25, 312. 5MHz
SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
PDH: N x DS1, N x E1, N x DS2, DS 3, E3
Other: 10, 10.24, 13, 30.72MHz
Frame Sync: 2kHz, 8kHz
Custom Clock Rates: Any Multiple of 2kHz Up to
77.76MHz, Any Multiple of 8kHz Up to
311.04MHz, Any Multiple of 10kHz Up to
388.79MHz
♦ General
♦ Suitable Line Card IC for Stratum 3/3E/4, SMC,
SEC
♦ Internal Compensation for Master Clock Oscillator
♦ SPI™ Processor Interface
♦ 1.8V Operation with 3.3V I/O (5V Tolerant)
♦ Industrial Operating Temperature Range
Data Sheet
April 2012
DS3105
2
Table of Cont ents
1. STANDARDS COMPLIANCE ....................................................................................................... 6
2. APP LICAT IO N EXAMPLE ............................................................................................................ 7
3. BLOCK DIAGRAM ........................................................................................................................ 8
4. DETAILED DESCRI P TION ............................................................................................................ 9
5. DETAILED FEATURES ............................................................................................................... 11
5.1 INPUT CLOCK FEATURES ............................................................................................................ 11
5.2 T0 DPLL FEATURES ................................................................................................................... 11
5.3 T4 DPLL FEATURES ................................................................................................................... 11
5.4 OUTPUT APLL FEATURES ........................................................................................................... 12
5.5 OUTPUT CLOCK FEATURES ......................................................................................................... 12
5.6 GENERAL FEATURES .................................................................................................................. 12
6. PIN DESCRIPTIONS ................................................................................................................... 13
7. FUNCTIONAL DESCRIPTION .................................................................................................... 18
7.1 OVERVIEW ................................................................................................................................. 18
7.2 DEVICE IDENTIFICATION AND PROTECTION ................................................................................... 19
7.3 LOCAL OSCILLA TOR AND MASTER CLOCK CONFIGURATION ........................................................... 19
7.4 INPUT CLOCK CONFIGURATION .................................................................................................... 19
7.4.1 Signal Format Configuration ................................................................................................................ 19
7.4.2 Frequency Configuration ...................................................................................................................... 20
7.5 INPUT CLOCK MONITORING ......................................................................................................... 21
7.5.1 Fr equency Mon itori ng .......................................................................................................................... 21
7.5.2 Ac tiv ity M on it oring ................................................................................................................................ 21
7.5.3 Selected Ref er enc e Activ ity Monitoring ............................................................................................... 22
7.6 INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING .................................................................. 22
7.6.1 Priority Configuration ............................................................................................................................ 22
7.6.2 Automatic Selection Algorithm ............................................................................................................. 23
7.6.3 Forced Selection .................................................................................................................................. 23
7.6.4 Ultra-Fast Reference Switching ........................................................................................................... 24
7.6.5 External Reference Switching Mode .................................................................................................... 24
7.6.6 Output Clock Phase Continuity During Referenc e Switching .............................................................. 24
7.7 DPLL ARCHITECTURE AND CONFIGURATION ................................................................................ 25
7.7.1 T0 DPLL Stat e Mac hin e ....................................................................................................................... 26
7.7.2 T4 DPLL Stat e Mac hin e ....................................................................................................................... 29
7.7.3 Bandwidth ............................................................................................................................................ 29
7.7.4 Damping Factor .................................................................................................................................... 30
7.7.5 Phase Detec t or s ................................................................................................................................... 30
7.7.6 Loss-of-Lock Detection ........................................................................................................................ 31
7.7.7 Phase Bu il d-Out ................................................................................................................................... 31
7.7.8 Input to Output (Manual) Phase Adjustment ........................................................................................ 32
7.7.9 Phase Rec a libra ti on ............................................................................................................................. 32
7.7.10 Frequency and Phas e Mea s urement ................................................................................................... 33
7.7.11 Input Jitter Tolerance ........................................................................................................................... 34
7.7.12 Jitter Transfer ....................................................................................................................................... 34
7.7.13 Output Jitter and Wander ..................................................................................................................... 34
7.8 OUTPUT CLOCK CONFIGURATION ................................................................................................ 35
7.8.1 Signal Format Configuration ................................................................................................................ 35
7.8.2 Frequency Configuration ...................................................................................................................... 35
7.9 FRAME AND MULTIFRAME ALIGNMENT .......................................................................................... 44
DS3105
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7.9.1 Enable and SYNCn Pin Selection ........................................................................................................ 44
7.9.2 Sampling .............................................................................................................................................. 45
7.9.3 Resampling .......................................................................................................................................... 45
7.9.4 Qualification ......................................................................................................................................... 45
7.9.5 Output Clock Alignment ....................................................................................................................... 45
7.9.6 Frame-Sync Monitor ............................................................................................................................. 46
7.9.7 Other Configuration Options ................................................................................................................ 46
7.10 MICROPROCESSOR INTERFACE ................................................................................................ 46
7.11 RESET LOGIC .......................................................................................................................... 49
7.12 POWER-SUPPLY CONSIDERATIONS .......................................................................................... 49
7.13 INITIALIZATION......................................................................................................................... 49
8. REGISTER DESCRI PTIONS ....................................................................................................... 50
8.1 STATUS BITS .............................................................................................................................. 50
8.2 CONFIGURATION FIELDS ............................................................................................................. 50
8.3 MULTIREGISTER FIELDS .............................................................................................................. 50
8.4 REGISTER DEFINITIONS .............................................................................................................. 51
9. JTAG TEST ACCESS PORT AND BOUNDARY SCAN............................................................ 104
9.1 JTAG DESCRIPTION ................................................................................................................. 104
9.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION ........................................................... 105
9.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS .................................................................... 107
9.4 JTAG TEST REGISTERS ............................................................................................................ 108
10. ELECTRICAL CHARACTERISTICS ......................................................................................... 109
10.1 DC CHARACTERISTICS .......................................................................................................... 109
10.2 INPUT CLOCK TIMING ............................................................................................................. 113
10.3 OUTPUT CLOCK TIMING ......................................................................................................... 113
10.4 SPI INTERFACE TIMING .......................................................................................................... 114
10.5 JTAG INTERFACE TIMING ...................................................................................................... 116
10.6 RESET PIN TIMING ................................................................................................................ 117
11. PIN ASSIGNMENTS .................................................................................................................. 118
12. PACKAGE INFORMATION ....................................................................................................... 120
13. THERMAL INFO RMATION ....................................................................................................... 121
14. ACRO NYMS AND ABBREVI ATIONS ....................................................................................... 122
15. DATA SHEET REVISION HI STORY ......................................................................................... 123
DS3105
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List of Figures
Figure 2-1. T ypical Appl ic at ion Example ..................................................................................................................... 7
Figure 3-1. Block Diagram ........................................................................................................................................... 8
Figure 7-1. DPLL Block Diagram ............................................................................................................................... 25
Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 27
Figure 7-3. FSYNC 8kHz Options .............................................................................................................................. 43
Figure 7-4. SPI Clock Phase Options ........................................................................................................................ 48
Figure 7-5. SPI Bus Transactions .............................................................................................................................. 48
Figure 9-1. JTAG Block Diagram ............................................................................................................................. 104
Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 106
Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 111
Figure 10-2. Recommended Termination for LVPECL Signals on LVDS Input Pins .............................................. 111
Figure 10-3. Recommended Termination for LVPECL-Compatible Output Pins .................................................... 112
Figure 10-4. SPI Interface Timing Diagram ............................................................................................................. 115
Figure 10-5. JTAG Timing Diagram ......................................................................................................................... 116
Figure 10-6. Reset Pin Timing Diagram .................................................................................................................. 117
Figure 11-1. Pin Ass ignment Diagram ..................................................................................................................... 119
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List of Tables
Table 1-1. Applicable Telecom Standards ................................................................................................................... 6
Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 13
Table 6-2. Output Clock Pin Descriptions .................................................................................................................. 13
Table 6-3. Global Pin Descriptions ............................................................................................................................ 14
Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 16
Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 16
Table 6-6. Po wer-Supply Pin Descriptions ................................................................................................................ 17
Table 7-1. Input Clock Capabilities ............................................................................................................................ 20
Table 7-2. Locking Frequen cy Modes ....................................................................................................................... 20
Table 7-3. Default Input Clock Priorities .................................................................................................................... 23
Table 7-4. Damping Factors and Peak Jitter/Wander Gain ....................................................................................... 30
Table 7-5. T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode .......................................................... 34
Table 7-6. Output Clock Capabilities ......................................................................................................................... 35
Table 7-7. Digital1 Frequencies ................................................................................................................................. 37
Table 7-8. Digital2 Frequencies ................................................................................................................................. 37
Table 7-9. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) .......................................................... 38
Table 7-10. T0 APLL Frequency Configuration ......................................................................................................... 38
Table 7-11. T0 APLL2 Frequency Configuration ....................................................................................................... 38
Table 7-12. T4 APLL Frequency Configuration ......................................................................................................... 39
Table 7-13. OC3 and OC6 Output Frequency Selection ........................................................................................... 39
Table 7-14. Standard Frequencies for Programmable Outputs ................................................................................ 40
Table 7-15. T0CR1.T0FREQ Default Settings .......................................................................................................... 42
Table 7-16. T4CR1.T4FREQ Default Settings .......................................................................................................... 42
Table 7-17. OC6 Default Frequency Configuration ................................................................................................... 42
Table 7-18. OC3 Default Frequency Configuration ................................................................................................... 43
Table 7-19. External Frame-Sync Mode and Source ................................................................................................ 45
Table 8-1. Register Map ............................................................................................................................................ 51
Table 9-1. JTAG Instruction Codes ......................................................................................................................... 107
Table 9-2. JTAG ID Code ........................................................................................................................................ 108
Table 10-1. Recommended DC Operating Conditions ............................................................................................ 109
Table 10-2. DC Characteristics ................................................................................................................................ 109
Table 10-3. CMOS/TTL Pins ................................................................................................................................... 110
Table 10-4. LVDS/LVPECL Input Pins .................................................................................................................... 110
Table 10-5. LVDS Output Pins ................................................................................................................................ 110
Table 10-6. LVPECL Level-Compatible Output Pins ............................................................................................... 111
Table 10-7. Input Clock Timing ................................................................................................................................ 113
Table 10-8. Input Clock to Output Clock Delay ....................................................................................................... 113
Table 10-9. Output Clock Phase Alignment, Frame-Sync Alignment Mode............................................................ 113
Table 10-10. SPI Interface Timing ........................................................................................................................... 114
Table 10-11. JTAG Interface Timing........................................................................................................................ 116
Table 10-12. Reset Pin Timing ................................................................................................................................ 117
Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 118
Table 13-1. LQFP Package Thermal Properties, Natural Convection ..................................................................... 121
Table 13-2. LQFP Theta-JA (θJA) vs. Airflow ........................................................................................................... 121
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1.
Standards Compliance
Table 1-1. Applicable Telecom Stan d ard s
SPECIFICATION SPECIFICATION TITLE
ANSI
T1.101
Synchronization Interface Standard, 1999
TIA/EIA-644-A
Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, 2001
ETSI
EN 300 417-6-1
Transmission and Multiplexing (TM); Generic requirements of transport functionality of
equipment; Par t 6-1: Synchronization layer functions, v1.1.3 (1999-05)
EN 300 462-3-1
Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part
3-1: The control of jitter and wander within synchronization networks, v1.1.1 (1998-05)
EN 300 462-5-1
Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part
5-1: Timing characteristics of slave cocks suitable for operation in Synchronous Digital
Hierarchy (SDH) Equipment, v1.1.2 (1998-05)
IEEE
IEEE 1149.1
Standard Test Access Port and Bou nd ar y -Scan Architecture, 1990
ITU-T
G.783
Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks (10/2000
plus Amendment 1 06/2002 and Corrigendum 2 03/2003)
G.813
Timing characteristics of SDH equipment slave clocks (SEC) (03/2003)
G.823
The control of jitter and wander within digital networks which are based on the 2048 kbit/s
hierarchy (03/2000)
G.824
The control of jitter and wander within digital networks which are based on the 1544 kbit/s
hierarchy (03/2000)
G.825
The control of jitter and wander within digital networks which are based on the synchronous
digital hierarchy (SDH) (03/2000)
G.8261
Timing and synchronization aspects in packet networks (05/2006, prepublished)
G.8262
Timing characteristics of synchronous Ethernet equipment slave clock (EEC) (08/2007,
prepublished)
TELCORDIA
GR-253-CORE
SONET Transport Systems: Common Generic Criteria, Issue 3, September 2000
GR-1244-CORE
Clocks for the Synchronized Network: Common Generic Criteria, Issue 2, December 2000
DS3105
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2.
Applicat ion Exampl e
Figure 2-1. Typ ic al Appl ic at ion Exam pl e
To SONET/SDH framers,
Clock Multiplying APLLs, etc.
on the Line Card
T0 DPLL
Input Clock
Selector,
Divider,
Monitor
From Master Timing Card IC3
IC4
OC3
19.44 MHz
OC6
prog. bandwidth,
phase build-out,
holdover, etc.
DS3105
Output
Clock
Synthesizer
and Selector
19.44 MHz 155.52MHz differential
19.44 MHz
XO or
TCXO
From Slave Timing Card
DS3105
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3.
Block Diagr am
Figure 3-1. Block Diagram
T0 DPLL
(Filtering, Hol dover,
Hitless Switching,
Frequency Conversion)
Master Clock
Generator
OC6 POS/ NEG
FSYNC
MFSYNC
IC3
IC4
IC5 POS/ NEG
IC6 POS/ NEG
IC9
Microprocessor Port
(SPI Serial)
and HW Contr ol and Status P ins
Local
Oscillator
RST*
CS
CPHA
SCLK
SDI
SDO
INTREQ / SRFAIL
T4 DPLL
(phase/freq.
measurement)
SONSDH / GPIO4
SRCSW
REFCLK
JTAG
Input
Clock
Selector,
Divider
and
Monitor
Output
Clock
Synthesizer
and
Selector
(Muxes,
7 DFS Blocks,
3 APLLs,
Output Dividers)
SYNC1
TEST
O3F[1] / SRFAIL
O3F[2] / LOCK
SYNC3/ O3F0
SYNC2
OC3
JTRST*
JTMS
JTCLK
JTDI
JTDO
O6F[2:0] / GPIO[3:1]
PLL Bypass
See Figure 7-1 for a detailed view of the T0 and T4 DPLLs and the Output Clock Synthesizer and Selector block.
DS3105
DS3105
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4.
Detail ed Des cription
Figure 3-1 illustrates the blocks described in this sect ion and how the y r elate to one another . Section 5 provi des a
detailed feature list.
The DS3105 is a c om plete lin e car d timing IC. At the c or e of this devic e ar e t wo digita l ph as e-locked loops (DPLLs)
labeled T 0 an d T41. D PLL t ec hno logy makes us e of digital -sig nal proc es s ing ( D S P) an d d ig ita l-f requency s ynthesis
(DFS) techniques to implement PLLs that are precise, flexible, and have consistent performance over voltage,
temperature, and manufacturing process variations. The DS3105’s DPLLs are digitally configurable for input and
output frequencies, loop bandwidth, damping factor, pull-in/hold-in range, and a variety of other factors. Both
DPLLs can directly lock to many common telecom frequencies and also can lock at 8kHz to any multiple of 8kHz
up to 156.25MHz. The DPLLs can also tolerate and filter significant amounts of jitter and wander.
In typical line card applications, the T0 DPLL takes reference clock signals from two redundant system timing
cards, monitors both, selects one, and uses that reference to produce a variety of clocks that are needed to time
the outgoin g traffic inter faces of the line c ard (SONET /SDH, Synchron ous Ethernet, etc .). To perform this role in a
variety of systems with diverse performance requirements, the T0 DPLL has a sophisticated feature set and is
highly configurable. T0 can automatically transition among free-run, locked, and holdover states without software
intervention. In free-run, T0 generates a stable, low-noise clock with the same frequency accuracy as the external
oscillator connected to the REFCLK pin. With software calibration the DS3105 can even improve the accuracy to
within ±0 .02ppm. W hen at least one input reference clock has been validat ed, T0 transit ions to the loc ked state in
which its output clock accuracy is equal to the accuracy of the input reference. While in the locked state, T0
acquires an average frequency value to use as the holdover frequency. When its selected reference fails, T0 can
very quic kly detect the f ailure and en ter the holdo ver state to a void aff ecting its output clock. From holdover it c an
automatically switch to another input reference, again without affecting its output clock (hitless switching).
Switching among input references can be either revertive or nonrevertive. When all input references are lost, T0
stays in holdover in which it generates a stable low-noise clock with initial frequency accuracy equal to its stored
holdover value and drift performance determined by the quality of the external oscillator. T0 can also perform
phase build-outs and fine-granularity output clock phase adjustments.
In the D S3105 the T 4 DPLL can on ly be used as an optional c lock m onitoring block . T4 can be d irected to lock to
an input clock and can measure the frequency of the input clock or the phase difference between two input clocks.
At the front end of the T0 DPLL is the Input Clock Selector, Divider, and Monitor (ICSDM) block. This block
continuous ly monitors as many as 5 different input clocks of various frequencies for activity and coarse frequenc y
accurac y. In addition, ICSDM maintains an input clock priorit y table for the T 0 DPLL, and can autom atically select
and provide the highest priority valid clock to T0 without any software intervention. The ICSDM block can also
divide the selected clock down to a lower rate as needed by the DPLL.
The Output Clock Synthesizer and Selector (OCSS) block shown in Figure 3-1 and in more detail in Figure 7-1
contains three output APLLs—T0 APLL, T0 APLL2, and T4 APLL—and their associated DFS engines and output
divider logic plus several additional DFS engines. The APLL DFS blocks perform frequency translation, creating
clocks of other frequencies that are phase/frequency locked to the output clock of the associated DPLL. The APLLs
multipl y the cloc k r ates f rom the APLL DF S b lock s and sim ultane ousl y attenuat e jitter. A ltoget her the o utp ut block s
of the DS310 5 can produce m ore than 90 different output frequencies including common SONET/SDH, PDH, and
Synchrono us Ethernet rate s plus 2kHz and 8kHz fram e-sync pulses. Note that in the DS3105 the T4 APLL a nd its
DFS engine are hardwired to the T0 DPLL and cannot be connected to the T4 DPLL.
The entire chip is clocked from the external oscillator connected to the REFCLK pin. Thus, the free-run and
holdover stability of the DS3105 is entirely a function of the stability of the external oscillator, the performance of
which can be selected to match the application: XO or TCXO. The 12.8MHz clock from the external oscillator is
1 These names are adapted from output ports of the SETS function specified in ITU-T and ETSI standards such as ETSI EN 300 462-2-1.
Although stri ct l y s peaki ng t hese names are appropriate only f or t i m ing card ICs such as the DS3100 that can s erve as the SETS functi on, t he
names have been carried over to the DS3105 so that all of the products in Maxim’s timing IC product line have consistent nomenclature.
DS3105
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multiplied b y 16 b y th e Master Clock G enerator block to create the 20 4.8MHz mas ter clock used by the remain der
of the device.
DS3105
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5.
Detail ed Features
5.1
Input Clock Feat ures
• Five input clocks: three CMOS/TTL (≤ 125MHz) and two LVDS/LVPECL/CMOS/TTL (≤ 156.25MHz)
• CMOS/TTL input clocks accept any multiple of 2kHz up to 125MHz
• LVDS/LVPECL inputs accept any multiple of 2kHz up to 131.072MHz, any multiple of 8kHz up to
155.52MHz plus 156.25MHz
• All input clocks are constantly monitored by programmable activity monitors
• Fast activity monitor can disqualify the selected reference after two missing clock cycles
• Three optional 2/4/8kHz frame-sync inputs for frame-sync signals from master and slave timing cards and
an optional backup timing source
5.2
T0 DPLL Features
• High-resolution DPLL plus three low-jitter out put APLL s
• Sophisticated state machine automatically transitions between free-run, locked, and holdover states
• Revertive or nonrevertive reference selection algorithm
• Programmable bandwidth from 18Hz to 400Hz
• Separately configurable acquisition bandwidth and locked bandwidth
• Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20
• Multiple phase detectors: phase/frequency, early/late, and multicycle
• Phase/frequency locking (±360° capture) or nearest edge phase locking (±180° capture)
• Multicycl e phase detec t ion and loc k ing (up to ±8191UI) improves jitter tolerance and lock time
• Phase build-out in response to reference switching
• Less than 5ns output clock phase transient during phase build-out
• Output phase adjustment up to ±200ns in 6ps steps w it h respect to selec ted in put reference
• High-resolution frequency and phase measurement
• Holdover frequency averaging over 1 second interval
• Fast detection of input clock failure and transition to holdover mode
• Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks
5.3
T4 DPLL Features
• High-resolution DPLL can be used to monitor inputs
• Programmable bandwidth from 18Hz to 70Hz
• Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20
• Multiple phase detectors: phase/frequency, early/late, and multicycle
• Phase/frequency locking (±360° capture) or nearest edge phase locking (±180° capture)
• Multicycl e phase detec t ion and locking (up to ±8191UI) improves jitter tolerance and lock time
• Phase detector can be used to measure phase difference between two input clocks
• High-resolution frequency and phase measurement
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5.4
Output APLL Features
• Three separate clock-multiplying, jitter attenuating APLLs can simultaneously produce SONET/SDH rates,
Fast/Gigabit Ethernet rates, and 10G Ethernet rates, all locked to a common reference clock
• The T0 APLL has frequency options suitable for N x 19.44MHz, N x DS1, N x E1, N x 25MHz, and
N x 62.5MHz
• The T4 APLL has frequency options suitable for N x 19.44MHz, N x DS1, N x E1, N x DS2, DS3, E3,
N x 10MHz, N x 10.24MHz, N x 13MHz, N x 25MHz, and N x 62.5MHz
• The T0 APLL2 produces 312.5MHz for 10G Synchronous Ethernet applications
5.5
Output Clock Features
• Two output clocks: one CMOS/TTL (≤ 125MHz) and one LVDS/LVPECL (≤ 312.50MHz)
• Output clock rates include 2kHz, 8kHz, N x DS1, N x E1, DS2, DS3, E3, 6.48MHz, 19.44MHz, 38.88MHz,
51.84MH z, 77.7 6MH z, 155. 52MH z, 311. 04 MHz, 2.5MH z, 25MHz, 125 MH z, 156. 25MHz, 312.50MHz,
10MHz, 10.24MHz, 13MHz, 30.72MHz, and various multiples and submultiples of these rates
• Custom clock rates also available: any multiple of 2kHz up to 77.76MHz, any multiple of 8kHz up to 311.04MHz,
and any multiple of 10kHz up to 388.79MHz
• All outputs have < 1ns peak-to-peak output jitter; outputs from APLLs have < 0.5ns peak-to-peak
• 8kHz frame-sync and 2kHz multiframe-sync outputs have programmable polarity and pulse width, and can
be disciplined by a 2kHz or 8kHz sync input
5.6
General Feat ures
• Operates from a single external 12.800MHz local oscillator (XO or TCXO)
• SPI serial microprocessor interface
• Four general-purpose I/O pins
• Register set can be wr ite protec ted
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6.
Pin Descriptions
Table 6-1. Input Clock Pin Descriptions
PIN NAME(1) TYPE(2) PIN DESCRIPTION
REFCLK I
Reference Clock. Connect to a 12.800MHz, high-accuracy , high-stability, low-noise local
oscillator (XO or TCXO). See Section 7.3.
IC3 IPD
Input Clock 3. CMOS/TTL. Programmable frequency (default 8kHz). This input can be
associated with the SYNC1 pin.
IC4 IPD
Input Clock 4. CMOS/TTL. Programmable frequency (default 8kHz). This input can be
associated with the SYNC2 pin.
IC5POS,
IC5NEG IDIFF
Input Clock 5. LVDS/LVPECL or CMOS/TTL. Programmabl e frequency (default 19.44MHz).
LVDS/LVPECL: See Table 10-4, Figure 10-1, and Figure 10-2.
CMOS/TTL: Bias IC5NEG to 1.4V and connect the single-ended signal to IC5POS.
If not used these pins should be left unconnected (one input is internally pul led high and the
other internal ly pulled low). This input can be associated with the SYNC1 pin.
IC6POS,
IC6NEG IDIFF
Input Clock 6. LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 19.44 MHz).
LVDS/LVPECL: See Table 10-4, Figure 10-1, and Figure 10-2.
CMOS/TTL: Bias IC6NEG to 1.4V and connect the single-ended signal to IC6POS.
If not used these pins should be left unconnected (one input is internally pul led high and the
other internally pulled low). This input can be associated with the SYNC2 pin.
IC9 IPD
Input Clock 9. CMOS/TTL. Programmable frequency (default 19.44MHz). This input can be
associated with the SYNC3 pin.
SYNC1 IPD
Frame-Sync 1 Input. 2kHz, 4kHz, or 8kHz.
FSCR3:SOURCE ! = 11XX. This pin is the external fra me-sync input associated with any input
pin using the FSCR3:SOURCE field.
FSCR3:SOURCE = 11XX. This pin is the external frame-sync signal associat ed wi th I C3 or
IC5, dependi ng on which one is currentl y selected and the setting of FSCR1.SYNCSRC[1:0].
SYNC2 IPD
Frame-Sync 2 Input. 2kHz, 4kHz, or 8kHz.
FSCR3:SOURCE ! = 11XX. This pin is not used for the exter nal frame-sync signal.
FSCR3:SOURCE = 11XX. This pin is the external frame-sync signal associated with IC4 or
IC6, dependi ng on which one is currently selected and the setting of FSCR1.SYNCSRC[1:0].
SYNC3/O3F0 IPU
Frame-Sync 3 Input/OC3 Frequency Select 0. 2kHz, 4kHz, or 8kHz. This pin is sampled
when the RST pin goe s high a nd the value is us ed as O3F0, which, together with O3F2 and
O3F1, sets the default frequency of the OC3 output clock pin. See Table 7-18. After RST goes
high, this pin becomes the SYNC3 input pin (2kHz, 4kHz, or 8kHz) associated with IC9. It is
only used as SYNC3 when FSCR2.SOURCE = 11XX.
Table 6-2. Output Clock Pin Descriptions
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
OC3 O
Output Clock 3. CMOS/TTL. Programmable frequency. Default frequency selected by
O3F[2:0] pins when the RST pin goes high, 19.44MHz if O3F[2:0] pins l eft open.See Table
7-18.
OC6POS,
OC6NEG ODIFF
Output Clock 6. LVDS/LVPECL. Programmable frequency. Default frequency selected by
O6F[2:0] pins when the RST pin goes high, 38.88MHz if O6F[2:0] pins l eft open. The output
mode is selected by MCR8.OC6SF[1:0]. See Table 10-5, Table 10-6, Figure 10-1, and Figure
10-3.
FSYNC O3
8kHz FSY NC. CMOS/TTL. 8kHz frame sync or clock (default 50% duty cycle clock,
noninverted). The pulse polarity and width are selectable using FSCR1.8KINV and
FSCR1.8KPUL.
MFSYNC O3
2kHz MFSYNC. CMOS/TTL. 2kHz frame sync or clock (default 50% duty cycle clock,
noninverted). The pulse polarity and width are selectable using FSCR1.2KINV and
FSCR1.2KPUL.
DS3105
14
Table 6-3. Global Pin Descriptions
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
RST IPU
Reset (Active Low). When this global asynchronous reset is pulled low, all internal circ uitry is
reset to default values. The device is held in reset as long as RST is low. RST should be held
low for at leas t two REFCLK cycles after the external oscillator has stabilized and is providing
valid clock signal s.
SRCSW IPD
Source Switching. Fast source-switching control input. See Section 7.6.5. The value of this pin
is latched into MCR10:EXTSW when RST goes hi gh. After RST goes high this pin can be used
to select between IC3/IC5 and IC4/IC 6, if enabl ed.
TEST
IPD
Factory Test Mode Select. Wi re this pin to VSS for normal operation.
O3F1/SRFAIL IOPU
OC3 Frequency Select 1/SRFAIL Status Pin. This pin is sampled when the RST pin goes high
and the value is used as O3F1, which, together with O3F2 and O3F0, sets the default
frequency of the OC3 output clock pin. See Table 7-18. After RST goes high, if MCR10:SRFPIN
= 1, this pin follows the state of the SRFAIL status bit in the MSR2 register. This gives the
system a very fast indication of the failure of the current reference. When MCR10:SRFPIN = 0,
SRFAIL is disabled (hi gh impedance).
O3F2/LOCK IOPD
OC3 Frequency Select 2/T0 DPLL LOCK Status. This pin is sampled when the RST pin goes
high and the value is used as O3F2, which, together with O3F1 and O3F0, sets the default
frequency of the OC3 output clock pin. See Table 7-18. After RST goes high, if
MCR1.LOCKPIN = 1, this pin indicates the lock state of the T0 DPLL. When MCR1.LOCKPIN =
0, LOCK is disabled (low).
0 = Not locked
1 = Locked
O6F0/GPIO1 IOPD
OC6 Frequency Select 0/General-Purpose I/O Pin 1. This pin is sampled when the RST pin
goes high and the value is used as O6F0, which, together with O6F2 and O6F1, sets the
default frequency of the OC6 output clock pin. See Table 7-17. After RST goes high, this pi n
can be used as a general-purpose I/O pin. GPCR:GPIO1D configures this pin as an input or an
output. GPCR:GPIO1O specifies the output value. GPSR:GPIO 1 indicat es the stat e of the p in.
O6F1/GPIO2 IOPD
OC6 Frequency Select 1/General-Purpose I/O Pin 2. This pin is sampled when the RST pin
goes high and the value is used as O6F1 which together with O6F2 and O6F0 sets the default
frequency of the OC6 output clock pin . See Table 7-17. After RST goes high this pin can be
used as a general purpose I/O pin. GPCR:GPIO2D configures this pin as an input or an output.
GPCR:GPIO2O specifies the output value. GPSR:GPIO2 indicates the state of the pin.
O6F2 GPIO3 IOPU
OC6 Frequency Select 2/General-Purpose I/O Pin 3. This pin is sampled when the RST pin
goes high and the value is used as O6F2, which, together with O6F1 and O6F0, sets the
default frequency of the OC6 output clock pin. See Table 7-17. After RST goes high, th is pin
can be used as a general-purpose I/O pin. GPCR:GPIO3D configures this pin as an input or an
output. GPCR:GPIO3O specifies the output value. GPSR:GPIO 3 indicat es the stat e of the pin.
SONSDH/
GPIO4 I/OPD
SONET/SDH Frequency Select Input/General-Purpose I/O 4. When RST goes high the state
of this pin sets the reset-default state of MCR3:SONSDH, MCR6:DIG1SS, and MCR6:DIG2SS.
After RST goes high this pin can be used as a general-purpose I/O pin. GPCR:GPIO4D
configures this pin as an input or an output. GPCR:GPIO 4O specifi es the outp ut valu e.
GPSR:GPIO4 indicates the state of the pin.
Reset latched value s:
0 = SDH rates (N x 2.048MHz)
1 = SONET rates (N x 1.544MHz)
DS3105
15
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
INTREQ/LOS O3
Interrupt Request/Loss of Signal. Programmable (default: INTREQ). The INTCR:LOS bit
determines whether the pin indicates interrupt reques ts or loss of signal (i.e., loss of selected
reference).
INTCR:LOS = 0: INTREQ mode
The behavior of this pin is conf igur ed in the INTCR register. Polarity can be active high or
active low. Drive action can be push-pull or open drain. The pin can also be configured as
a general-purpose output if the interrupt request function is not needed.
INTCR:LOS = 1: LOS mode
This pin indicates the real-time state of the selec ted reference activity monitor (s ee Section
7.5.3). This function is most useful when external switching mode (Section 7.6.5) is
enabled (MCR10:EXTSW = 1).
DS3105
16
Table 6-4. SPI Bus Mode Pin Desc r iptions
See Section 7.10 for functional description and Section 10.4 for timing specifications.
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
CS IPU Chip Select. This pin must be asserted (low) to read or write internal registers.
SCLK
I
Serial Clock. SCLK is always driven by the SPI bus ma ster .
SDI
I
Serial Data Input. The SPI bus master trans mits data to the device on this pin.
SDO
O
Serial Data Output. The device transmits data to the SPI bus master on this pin.
CPHA I
Clock Phase. See Figure 7-4.
0 = Data is latched on the leading edge of the SCLK pulse.
1 = Data is latched on the trailing edge of the SCLK pulse.
Table 6-5. JTAG Interface Pin Descriptions
See Section 9 for functional descripti on and Secti on 10.5 for timing specifications.
PIN NAME(1)
TYPE(2)
PIN DESCRIPTION
JTRST IPU
JTAG Test Reset (Active Low). Asynchronously resets the tes t access port (TAP) controller. If
not used, JTRST can be held low or high.
JTCLK I
JTAG Clock. Shifts data into JTDI on the rising edge and out of JTDO on the falli ng edge. If
not used, JTCLK can be held low or high.
JTDI IPU
JTAG Test Data Input. Test instructions and data are clocked in on this pin on the rising edge
of JTCLK. If not used, JTDI can be held low or high.
JTDO O3
JTAG Test Data Output. Test instructions and data are clocked out on this pin on the falling
edge of JTCLK. If not used, le av e unconnected.
JTMS IPU
JTAG Test Mode Select. Sampled on the rising edge of JTCLK and is used to place the port
into the various defined IEEE 1149.1 states. If not used connect to VDDIO or leave
unconnected.
DS3105
17
Table 6-6. Power-Supply Pin Descriptions
PIN NAME(1)
TYPE(2)
PIN DESCRIPTION
VDD
P
Core Power Supply. 1.8V ±10%.
VDDIO
P
I/O Power Supply. 3.3V ±5%.
VSS
P
Ground Reference
AVDD_DL
P
Power Supply for OC6 Digital Logic. 1.8V ±10%.
AVSS_DL
P
Return for OC6 Digital Logic
VDD_OC6
P
Power Supply for Differential Output OC6POS/NEG. 1.8V ±10%.
VSS_OC6
P
Return for LVDS Differential Output OC6POS/NEG
AVDD_PLL1
P
Power Supply for Master Clock Generator APLL. 1.8V ±10%.
AVSS_PLL1
P
Return for Master Clock Generator APLL
AVDD_PLL2
P
Power Supply for T0 APLL. 1.8V ±10%.
AVSS_PLL2
P
Return for T0 APLL
AVDD_PLL3
P
Power Supply for T4 APLL. 1.8V ±10%.
AVSS_PLL3
P
Return for T4 APLL
AVDD_PLL4
P
Power Supply for T0 APLL2. 1.8V ±10%.
AVSS_PLL4
P
Return for T0 APLL2
Note 1: All pin names with an overbar (e.g., RST) are active low.
Note 2: All pins, except power and analog pins, are CMOS/TTL, unless otherwise specified in the pin description.
PIN TYPES
I = input pin
IDIFF = input pin that is LVDS/LVPECL differential signal compatible
IPD = input pin with internal 50kΩ pulldown
IPU = input pin with internal 50kΩ pullup
I/O = input/output pin
IOPD = input/output pin with internal 50kΩ pulldown
IOPU = input/output pin with internal 50kΩ pullup
O = output pin
O3 = output pin that can be placed in a high-impedanc e state
ODIFF = output pin that is LVDS/LVPECL differential signal compatible
P = power-supply pin
Note 3: All digital pins, except OCn, are I/O pins in JTAG mode. OCn pins do not have JTAG functionality.
DS3105
18
7.
Functional D es cription
7.1
Overview
The DS3105 has five input clocks and two output clocks. There are two separate DPLLs in the device: the high-
performance T0 DPLL and the simpler the T4 DPLL. The T0 DPLL can generate output clocks; the T4 DPLL can
be used to monitor inputs for frequency and phase. See Figure 3-1.
Three of the input clock pins are single-ended and can accept clock signals from 2kHz to 125MH z. T he other two
are differential inputs that can accept clock signals up to 156.25MHz. The differential inputs can be configured to
accept differential LVDS or LVPECL signals or single-ended CMOS/TTL signals.
Each input clock can be monitored continually for activity, and each can be marked unavailable or given a priority
number. Separate input priority numbers are maintained for the T0 DPLL and the T4 DPLL. Except in special
modes , the highest priority va lid input is autom atically s elected as the referenc e for the T 0 DPLL. SRF AIL is s et or
cleared based on activity and/or frequency of the selected input.
Both the T0 DPLL and the T4 DPLL can directly lock to many common telecom and datacom frequencies,
including, but not limited to, 8kHz, DS1, E1, 10MHz, 19.44MHz, and 38.88MHz as well as Ethernet frequencies
including 2 5MHz, 62.5 MH z, 125 MHz, and 15 6.2 5MH z. The DPLLs c an also loc k t o m ultiples of the s t and ar d d irec t -
lock frequencies including 8kHz.
The T0 DPLL is the high-performance path with all the features needed for synchronizing a line card to dual
redundant system timing cards. The T4 DPLL can be used to monitor input clock signals but it cannot drive any
output clocks. The T4 APLL is always connected to the T0 DPLL to provide low-jitter output frequencies from the
T0 DPLL. There is also a dedicated low-jitter APLL output that operates at 312.5MHz for 10G Ethernet
applications.
Using the optional PLL bypass, the T4 selected reference, after any frequency division, can be directly output on
either of the OC3 or OC6 output clock pins.
Both DPLLs have these features:
Automatic reference selection based on input activity and priority
Manual reference selection/forcing
Adjustable PLL characteristics, including bandwidth, pull-in range, and damping factor
Ability to lock to several common telecom and Ethernet frequencies plus multiples of any standard
direct lock frequency
Six bandwidth selections from 18Hz to 400Hz
The T0 DPLL has these additional features not available in the T4 DPLL:
A full state machine for automatic transitions among free-run, locked, and holdover states
Optional manual reference switching mode
Nonrevertive reference switching mode
Phase build-out for reference switching (“hitless”)
Output vs. input phase offset control
Noise rejection circuitry for low-frequency references
Output phase alignment to input frame-sync signal
Instant digit al one-second averaging and free-run holdover modes
Frequency conversion between input and output using digital frequency synthesis
The T4 DPLL has an additional feature not available in the T0 DPLL:
Optional mode to measure the phase difference between two input clocks
T ypically, the int er na l stat e machine contr ols the T0 D PLL, but manual c ontro l by s ystem software is als o a vailable.
The T 4 DPLL has a sim pler state m achine th at soft ware cann ot direct ly contro l. In e ither DPLL, howe ver, sof tware
can override the DPLL logic using manual reference selection.
DS3105
19
The outputs of the T0 DPLL and the T4 DPLL can be connected to seven output DFS engines. See Figure 7-1.
Three of these output DFS engines are associated with high-speed APLLs that multiply the DPLL clock rate and
filter DP LL output j itter. T he outputs of the APLLs ar e divid ed down to m ak e a wide variet y of possibl e frequenc ies
availab le at th e output cloc k pins. The output frequenc ies from the T 0 DPLL can be synchr onized to an in put 2, 4,
or 8kHz sync signal (SYNC1, SYNC2, or SYNC3 input pins).
The OC3 and OC6 output clocks can be configured for a variety of different frequencies that are frequency and
phase-locked to the T0 DPLL. The OC6 output is LVDS/LVPECL; the OC3 is CMOS. Altogether more than 60
output frequencies are possible, ranging from 2kHz to 312.5MHz. The FSYNC output clock is always 8kHz, and the
MFSYNC output clock is always 2kHz.
7.2
Device I denti fi cat ion and Protection
The 16-bit read-only ID field in the ID1 and ID2 regist ers is set to 0C21h = 31 05 decim al. The device revision ca n
be read from the REV register. Contact the factory to interpret this value and determine the latest revision. The
register set can be protected from inadvertent writes using the PROT register.
7.3
Local Oscil lator and Master Clock Configuration
The T 0 D PLL, th e T 4 DP LL , and th e o utpu t D FS en gi n es operate fr om a 204.8MHz master c lock. The m as ter clock
is synthes ized f rom a 12.80 0MH z clock or iginating f rom a loc al osc illator attac hed to the R EFCL K pin. The stabi lit y
of the T0 DPLL in free-r un or holdo ver is equival ent to the stability of the local osc i llator . Se lecti on of an appr o pr iate
local oscillator is therefore of crucial im portance if the telecom standards listed in Table 1-1 are to be met. Simple
XOs can be used in less stringent cases, but TCXOs or even OCXOs may be required in the most demanding
applications. Careful evaluation of the local oscillator component is necessary to ensure proper performance.
Contact Microsemi timing products technical support for recommended oscillators.
The stabilit y of the local oscillator is ver y im portant, but its absolute f requency accurac y is less im portant because
the DPLLs can compensate for frequency inaccuracies when synthesizing the 204.8MHz master clock from the
local oscillator clock . The MCLKFREQ field in regist ers MCLK1 and MCLK2 specifies the frequency adjustment to
be applied. The adjust can be from -771ppm to +514ppm in 0.0196229ppm (i.e., ~0.02ppm) steps.
7.4
Input Clock Configuration
The DS310 5 has five input cloc ks: IC3 to IC6 and IC9. Table 7-1 prov ides summar y inform ation about each clock,
including s igna l form at and avail able fr equenc ies. T he device to lerates a wide r ange of duty cyc les on inp ut clock s ,
out to a minimum high time or minimum low time of 3ns or 30% of the clock period, whichever is smaller.
7.4.1
Sign al Format Configu r at ion
Inputs with CMOS/T TL signal for mat acc ept both T TL and 3.3V C MOS le ve ls. O ne key configur ati on b it th at af f ec ts
the available frequencies is the SONSDH bit in MCR3. When SONSDH = 1 (SONET mode), the 1.544MHz
frequency is available. When SONSDH = 0 (SDH mode), the 2.048MHz frequency is available. During reset the
default value of this bit is latched from the SONSDH pin.
Input clocks IC5 and IC6 can be configured to accept LVDS, LVPECL, or CMOS/TTL signals by using the proper
set of ex terna l com ponents . The r ecom m ended LVDS termination is sh own in Figure 10-1 whi le the rec om mended
LVPECL t erm ination is sh own in Figure 10-2. The ele ctrical spec ificatio ns for t hese inputs are lis ted in Table 10-4.
To configure these differential inputs to accept single-ended CMOS/TTL signals, use a voltage-divider to bias the
ICxNEG p in to approx imately 1.4V an d connect the s ingle-ended s ignal to the IC xPOS pin. If a differ ential input is
not used it shou ld be left unconnected ( one input is inter nally pulled high a nd the other inter nally pulled lo w). (See
also MCR5:IC5SF and IC6SF.)
DS3105
20
Table 7-1. Input Clock Capabilities
INPUT CLOCK SIGNAL FORMATS FREQUENCIES (MHz) DEFAULT FREQUENCY
IC3
CMOS/TTL
Up to 125(1)
8kHz
IC4
CMOS/TTL
Up to 125(1)
8kHz
IC5
LVDS/LVPECL or CMOS/TTL
Up to 156.25(2)
19.44MHz
IC6
LVDS/LVPECL or CMOS/TTL
Up to 156.25(2)
19.44MHz
IC9
CMOS/TTL
Up to 125(1)
19.44MHz
Note 1: Available frequencies f or CMOS/TTL input cl ocks are: 2kHz, 4kHz, 8kHz, 1.544MHz (SONET mode), 2.048MHz (SDH mode),
6.312MHz, 6.48MHz, 19.44MHz, 25.0MHz, 25. 92MHz, 38. 88MHz, 51. 84MHz, 62. 5MHz, 77. 76MHz, and any multipl e of 2kHz up to 125MHz.
Note 2: Available frequencies f or LVDS/LVPE CL input clocks incl ude all CMOS/TTL frequencies in Note 1 plus any multiple of 8kHz up to
155.52MHz and 156.25MHz.
7.4.2
Frequency Configuration
Input cloc k f requenc ies ar e conf igure d in t he FR EQ fie ld of the ICR re gisters . T he DIVN and LOCK 8K bi ts of these
same registers specify the locking frequency mode, as s ho wn in Table 7-2.
Table 7-2. Locking Frequency Modes
DIVN LOCK8K
LOCKING FREQUENCY
MODE
0
0
Direct Lock
0
1
LOCK8K
1
0
DIVN
1
1
Alternate Direct Lock
7.4.2.1
Direct Lock Mode
In direct lock mode, the DPLLs lock to the selected reference at the frequency specified in the correspo nding ICR
register. Direct lock mode can only be used for input clocks with these specific frequencies: 2kHz, 4kHz, 8kHz,
1.544MHz, 2.048MHz, 5MHz, 6.312MHz, 6.48MHz, 19.44MHz, 25.92MHz, 31.25MHz, 38.88MHz, 51.84MHz,
77.76MHz, and 155.52MHz. For the 155.52MHz case, the input clock is internally divided by two, and the DPLL
direct-lock s at 77. 76 MHz. T he DIVN m ode can b e us ed to div ide an input do wn to an y of these frequenc ies exc ept
155.52MHz.
MTIE figures may be marginally better in direct lock mode because the higher frequencies allow more frequent
phase updates .
7.4.2.2
Alternate D irect Lock Mode
Alternate direct lock mode is the same as direct lock mode except an alternate list of direct lock frequencies is used
(see the FREQ field definition in the ICR register description). The alternate frequencies are included to support
clock rates found in Ethernet, CMTS, wireless, and GPS applications. The alternate frequencies are: 10MHz,
25MHz, 62.5MHz, 125MHz, and 156.25MHz. The frequencies 62.5MHz, 125MHz, and 156.25MHz are internally
divided down to 31.25MHz, while 10MHz and 25MHz are internally divided down to 5MHz.
7.4.2.3
LOCK 8K Mode
In LOCK8K mode, a n internal divider is c onfigured t o divid e the select ed referen ce down to 8k Hz. T he DPL L locks
to the 8kHz output of the divider. LOCK8K mode can only be used for input clocks with the standard direct lock
frequencies: 8kHz, 1.544MHz, 2.048MHz, 5MHz, 6.312MHz, 6.48MHz, 19.44MHz, 25.0MHz, 25.92MHz,
31.25MH z, 3 8.88 MH z, 51 .8 4MH z, 62 .5MHz, 77.76MHz, an d 15 5.5 2MHz. LOC K8 K mode is enable d f or a pa r ticular
input clock by setting the LOCK8K bit in the corresponding ICR register.
DS3105
21
LOCK8K mode gives a greater tolerance to input jitter when the multicycle phase detector is disabled because it
uses lower frequencies for phase comparisons. The clock edge to lock to on the selected reference can be
configured using the 8KPOL bit in the TEST1 register. For 2kHz and 4kHz clocks the LOCK8K bit is ignored and
direct-lock mode is used.
7.4.2.4
DIVN Mode
In DIVN mode, an interna l divider is configured from the value stored in the DIVN registers. The DIVN value must
be chose n so that when the s elected ref erence is divided by DIVN+ 1, the resu lting clock frequenc y is the s ame as
the standard direct lock frequency selected in the FREQ field of the ICR register . The DPLL lock s to the output of
the divider. DIVN mode can only be used for input clocks whose frequency is less than or equal to 155.52MHz. The
DIVN register field can range from 0 to 65,535 inclusive. The same DIVN+1 factor is used for all input clocks
configured for DIVN mode. Note that although the DIVN divider is able to divide down clock rates as high as
155.52MHz, the CMOS/TTL inputs are only rated for a maximum clock rate of 125MHz.
7.5
Input Clock M onit or ing
Each inpu t clock is continu ously monitored f or activit y. Activit y m onitoring is des cribed in Sect ions 7.5.2 and 7.5.3.
The valid/i nvalid state of each input clock is reported in the correspo nding real-ti me status bit in regist ers VALSR1
or VALSR2. W hen the valid/in valid state of a clock changes, the corr esponding l atched stat us bit is set in registers
MSR1 or MSR2, and a n int errupt re quest occ urs if the c orrespond ing i nterrup t en able b it is s et in reg isters IER1 or
IER2. Input clocks marked invalid cannot be automatically selected as the reference for either DPLL.
7.5.1
Frequency Moni t oring
The DS3105 monitors the frequency of each input clock and invalidates any clock whose frequency is more than
10,000ppm away fr om nominal. T he f r equency range monitor c an be disab le d b y c leari ng the MCR1.FR EN b it. The
frequency range measurement uses the internal 204.8MHz master clock as the frequency reference.
7.5.2
Activity Monitoring
Each input clock is monitored for activity and proper behavior using a leaky bucket accumulator. A leaky bucket
accumulator is sim ilar to an analog integrator: the output amplitude increases in the presence of input events and
gradually decays in the absence of events. When events occur infrequently, the accumulator value decays fully
between e vents and no alarm is declared. W hen events oc cur close enough toge ther, the accum ulator increm ents
faster than it can decay and eventually reaches the alarm threshold. After an alarm has been declared, if events
occur infrequently enough, the accumulator can decay faster than it is incremented and eventually reaches the
alarm clear threshold. The leaky bucket events come from the frequency range and fast activity monitors.
The leaky bucket accumulator for each input clock can be assigned one of four configurations (0 to 3) in the
BUCKET field of the ICR registers. Each leaky bucket configuration has programmable size, alarm declare
threshold, alarm clear threshold, and decay rate, all of which are specified in the LBxy registers.
Activit y monitorin g is divi ded into 1 28m s intervals. T he ac cum ulator is incr em ented once f or each 128m s inter val in
which the input clock is inactive for more than two cycles (more than four cycles for 155.52MHz, 156.25MHz,
125MH z, 62.5MHz, 25MH z and 10MHz input c locks ). Thus, the “f ill” rate of the buck et is at most 1 unit per 128m s,
or approximately 8 units/second. During each period of 1, 2, 4, or 8 intervals (programmable), the accumulator
decrem ents if no irregu larities occur . Thus the “leak ” rate of the buck et is approx imately 8, 4, 2, or 1 units/sec ond.
A leak is prevented when a fill event occurs in the same interval.
W hen the valu e of an ac cum ulator r eac hes the alarm thr es hold (LBxU register ), the c orr es pond ing AC T alarm bit is
set to 1 in the ISR registers, and the clock is marked invalid in the VALSR registers. When the value of an
accumulator reaches the alarm clear threshold (LBxL register), the activity alarm is cleared by clearing the clock’s
ACT bit. The accumulator cannot increment past the size of the bucket specified in the LBxS register. The decay
rate of the accumulator is specified in the LBxD register. The values stored in the leaky bucket configuration
registers must have the following relationship at all times: LBxS ≥ LBxU > LBxL.
DS3105
22
W hen the leaky buc k et is empt y, the m inim um tim e t o dec lare an ac ti vit y al arm in sec onds is L Bx U / 8 (where the x
in LBxU is the leaky bucket configuration number, 0 to 3). The minimum time to clear an activity alarm in seconds is
2^LBxD × (LBxS – LBxL) / 8. As an example, assume LBxU = 8, LBxL = 1, LBxS = 10, and LBxD = 0. The
minim um time to dec lare an ac tivity alarm would be 8 / 8 = 1 second . The m inimum tim e to clear the ac tivity alarm
would be 2^0 × (10 – 1) / 8 = 1.125 seconds.
7.5.3
Sele ct ed Re f erence Activity Monit or ing
The input clock that each DPLL is currently locked to is called the selected reference. The quality of a DPLL’s
selected reference is exceedingly important, since missing cycles and other anomalies on the selected reference
can cause unwanted jitter, wander, or frequency offset on the output clocks. When anomalies occur on the selected
reference they must be detected as soon as possible to give the DPLL opportunit y to temporarily disconnect from
the reference until the reference is available again. By design, the regular input clock activity monitor (Section
7.5.2) is too s low to be suitabl e for monitorin g the selected ref erence. Instead, ea ch DPLL has its o wn fast a ctivity
monitor that detects that the frequency is within range (approximately 10,000ppm) and detects inactivity within
approximately two missing reference clock cycles (approximately four missing cycles for 156.25MHz, 155.52MHz,
125MHz, 62.5MHz, 25MHz, and 10MHz references).
When the T0 DPLL detects a no-activity event, it immediately enters m ini-holdover mode to isolate itself from the
selected ref erence and s ets the SRFAIL b it in MSR2. T he setting of the SRFAIL bit can cause an interrup t request
if the corr esponding en able bit is set in IER2. If MCR10:SRFPIN = 1, t he SRFAIL output pin f ollo ws the state of the
SRFAIL status bit. Optiona lly, a n o-activit y event can a lso cause a n ultra-fas t referenc e switch (se e Sectio n 7.6.4).
When PHLIM1:NALOL = 0 (default), the T0 DPLL does not declare loss-of-lock during no-activity events. If the
selected reference becomes available again before any alarms are declared by the activity monitor, the T0 DPLL
continues to track the selected reference using neare st edge locking ( ±180°) to avoid c yc le slips. W hen NALOL =
1, the T0 DPLL declares loss-of-lock during no-activity events. This causes the T0 DPLL state machine to transition
to the loss -of-lock state, wh ich s ets the MSR2:STATE bit a nd c aus es a n in ter rupt reques t if en abl ed. If the s e lec ted
referenc e becom es availab le again bef ore an y alarms are declared b y the acti vity m onitor, the T0 D PLL track s the
selected reference using phase/frequency locking (±360°) until phase lock is reestablished.
When the T4 DPLL detects a no-activity event, its behavior is similar to the T0 DPLL with respect to the
PHLIM1:NALOL control bit. Unlike the T0 DPLL, however, the T4 DPLL does not set the SRFAIL status bit. If
NALOL = 1, the T4 DPLL clears the OPSTATE:T4LOCK status bit, which sets MSR3:T4LOCK and causes an
interrupt request if enabled.
7.6
Input Clock Pr iority, Selection, and Switching
7.6.1
Prior ity Configuration
During normal operation, the selected reference for the T0 DPLL is chosen automatically based on the priority
rank ings assigned to t he input c locks in the input pr iority regis ters (IPR2, IPR3, a nd IPR5). Eac h of these re gisters
has prior ity fields for one or two inp ut clock s. W hen T4T0 = 0 in the MCR11 r egister, the IPR registers s pecify the
input clock priorities for the T 0 DPLL. When T 4T0 = 1, they ha ve no meaning. T he default input clock priorities ar e
shown in Table 7-3.
There is an inter-loc k mec hanism betwe en IC3 a nd IC5 and betwee n IC 4 an d IC6 s o that only two of the inpu t s c an
be automat ically selected. W hen IPR2.PRI3 is written with a priorit y other than 0, IPR3.PR I5 is autom aticall y set to
0. When IPR3.PRI5 is written with a priority other than 0, IPR2. PRI3 is automaticall y set to 0. W hen IPR2.PRI4 is
written with a priority other than 0, IPR3.PRI6 is automatically set to 0. When IPR3.PRI6 is written with a priority
other than 0, IPR2.PRI4 is automatically set to 0.
Any unused input clock should be given the priority value 0, which disables the clock and marks it as unavailable
for selection. Priority 1 is highest while priority 15 is lowest. The same priority can be given to two or more clocks.
DS3105
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Table 7-3. Default Input Clock Priorities
INPUT CLOCK
T0 DPLL
DEFAULT
PRIORITY
IC3
2
IC4
3
IC5
0 (off)
IC6
0 (off)
IC9
5
7.6.2
Automatic Sele ct ion Algorithm
The real-time valid/invalid state of each input clock is maintained in the VALSR1 and VALSR2 registers. The
selected reference can be marked invalid for phase lock, frequency, or activity. Other input clocks can be
invalidated for frequency or activity.
The ref erence selection a lgorithm f or the T0 DPLL cho oses the highest pr iority valid input clock to be the selected
referenc e. To select the proper inp ut c l ock based on t hes e c riteria, the s election alg orithm mainta ins a pri or ity table
of valid inputs. The top three entries in this table and the selected reference are displayed in the PTAB1 and
PTAB2 registers. When T4T0 = 0 in the MCR11 register, these registers indicate the highest priority input clocks
for the T0 DPLL. When T4T0 = 1, they have no meaning.
If two or more input clocks are given the same priority number, those inputs are prioritized among themselves using
a fixed circular list. If one equal-priority clock is the selected reference but becom es invalid, the next equal-priority
clock in the list becomes the selected reference. If an equal-priority clock that is not the selected reference
becomes invalid, it is simply skippe d over in the circul ar list. The s election am ong equal-pr iorit y inputs is in herentl y
nonrevertive, and revertive switching mode (see next paragraph) has no effect in the case where multiple equal-
priority inputs have the highest priority.
An important input to the selection a lgorithm for the T0 DPLL is the REVERT bit in the MCR3 regist er. In revertive
mode (REVERT = 1), if an input clock with a higher priorit y than the selected reference becomes valid, the higher
priority reference immediately becomes the selected reference. In nonrevertive mode (REVERT = 0), the higher
priority reference does not immediately become the selected reference but does become the highest priority
reference in the priority table (REF1 field in the PTAB1 register). (The selection algorithm always switches to the
highest priority valid input when the selected reference goes invalid, regardless of the state of the REVERT bit.) For
many applications, nonrevertive mode is preferred for the T0 DPLL because it minimizes disturbances on the
output clocks due to reference switching.
In nonrevertive mode, planned switchover to a newly valid higher priority input clock can be done manually under
software control. The validation of the new higher priority clock sets the corresponding status bit in the MSR1 or
MSR2 register, which can drive an interrupt request on the INTREQ pin if needed. System software can then
respond to this change of state by briefly enabling revertive mode (toggling REVERT high then back low) to drive
the switchover to the higher priority clock.
7.6.3
Forced Sel ection
The T0FORCE field in the MCR2 register and the T4FORCE field in the MCR4 register provide a way to force a
specified input clock to be the selected reference for the T0 and T4 DPLLs, respectively. In both T0FORCE and
T4FORCE, values of 0 an d 15 specif y norm al operat ion with aut om atic ref erence s election. Values f rom 3 to 6 and
9 specify the input clock to be the forced selection; other values will cause no input to be selected. Internally,
forc ing is accom plished b y givin g the s pecif ied cloc k the highest prior it y (as spec ified i n PTAB1:REF1). In r ever tive
mode (MCR3:REVERT = 1) the forced clock automatically becomes the selected reference (as specified in
PTAB1:SELREF) as well. In nonrevertive mode (T0 DPLL only) the forced clock only becomes the selected
reference when the existing selected reference is invalidated or made unavailable for selection. In both revertive
and nonrevertive modes when an input is forced to be the highest priority, the norm al highest priority input (when
DS3105
24
no input is forced) is listed as the second-highest priority (PTAB2:REF2) and the normal second-highest priority
input is listed as the third-highest priority (PTAB2:REF3).
W hen the T4 DPLL is us ed to m easure t he phase dif fer ence bet ween the T 0 DPL L selected ref erenc e and a nother
reference input by setting the T0CR1:T4MT0 bit, the T4FORCE field in the MCR4 register can be used to select the
other reference input.
7.6.4
Ultra-Fast R efere nce Switchi ng
By default, disqualification of the selected reference and switchover to another reference occurs when the activit y
monitor’s inactivity alarm threshold has been crossed, a process that takes on the order of hundreds of
milliseconds or seconds. For the T0 DPLL, an option for extremely fast disqualification and switchover is also
available. When ultra-fast switching is enabled (MCR10:UFSW = 1), if the fast activity monitor detects
approximately two m issing clock cyc les, it declares the refer ence failed b y f orcing the leaky buck et accum ulator to
its upper t hres ho ld (s ee Se c tion 7.5.2) and initia tes r ef erenc e switchin g. T his is in add iti on to s et ti ng th e SRFAIL bit
in MSR2 and optionally generating an interrupt request, as described in Section 7.5.3. W hen ultra-fast switching
occurs, the T0 DPLL transitions to the prelocked 2 state, which allows switching to occur faster by bypassing the
loss-of-lock state. The devic e should be in nonre vertive m ode when ultr a-fast switc hing is enabled. If the device is
in revert ive mode, ultra-f ast switching could cause excessive reference switching when the highest priority input is
intermittent.
7.6.5
External Reference Switc hing M ode
In this m ode the SRCSW input pin controls ref erenc e switchi ng bet ween t wo clock inputs. T his m ode is enabl ed by
setting the EX TSW bit to 1 in the MCR10 r egister . In this mode, if the SRCSW pin is high, the T 0 DPLL is f orced to
lock to input IC3 (if the priority of IC3 is nonzero in IPR2) or IC5 (if the priority of IC3 is zero) whether or not the
selected input has a valid reference signal. If the SRCSW pin is low, the T0 DPLL is forced to lock to input IC4 (if
the priority of IC4 is nonzero in IPR2) or IC6 (if the priority of IC4 is zero) whethe r or not the selected input has a
valid ref erence signa l. During reset the default value of the EX TSW bit is la tched from the SRCSW pin. If external
referenc e switching m ode is enabled during r eset, the def ault frequenc y to lerance ( DLIMIT registers ) is configured
to ±80ppm rather than the normal default of ±9.2ppm.
In external reference switching mode the device is simply a clock switch, and the T0 DPLL is forced to lock onto the
selected reference whether or not it is valid. Unlike forced reference selection (Section 7.6.3) this mode controls the
PTAB1: SELREF f ield directl y and is, therefore, not af fected b y the state of the MCR3:REVERT bit. During ext ernal
reference switching mode, only PTAB1:SELREF is affected; the REF1, REF2, and REF3 fields in the PTAB
registers continue to indicate the highest, second-highest, and third-highest priority valid inputs chosen by the
automatic selection logic. External reference switching mode only affects the T0 DPLL.
7.6.6
Output Clock Phase Continuity Dur ing R eference Switching
If phase build-out is enabled (PBOEN = 1 in MCR10) or the DPLL frequency limit (DLIMIT) is set to less than
±30ppm, the dev ice always com plies with the GR-1244-CORE requ irement that the rate of phase change m ust be
less than 81ns per 1.326ms during reference switching.
DS3105
25
7.7
DPLL Architecture and Confi guration
Both the T0 DPLL and T4 DPLL are digital PLLs. The T0 DPLL has separate analog PLLs (APLLs) as output
stages as well as some outputs that are not cleaned up by an APLL. This architecture combines the benefits of
both PLL types. Se e Figure 7-1.
Figure 7-1. DPLL Block Diagram
T0 DPLL
T4 DPLL
Locking
Frequency
T0
PFD and
Loop Filter
T0
Foward
DFS
T0
Feedback
DFS
DIG12
DFS
T0 selected
reference
OC3, OC6
T4
Foward
DFS
T4
Feedback
DFS
T4
PFD and
Loop Filter
Locking
Frequency
T4 selected
reference
T0CR1:T0FREQ[2:0]
OCRm:OFREQn[3:0]
OCR5:AOFn
T0CR1:T4MT0
T4CR1:T4FREQ[3:0]
T0CR1:T0FT4[2:0]
1
0
APLL
Output
Dividers
T0
Output
APLL
T0
APLL
DFS
APLL
Output
Dividers
T4
Output
APLL
T4
APLL
DFS
DIG12
DFS
2K8K
DFS
MCR6:DIG2SS
MCR6:DIG2F[1:0]
MCR6:DIG2AF
MCR6:DIG1SS
MCR6:DIG1F[1:0]
OUTPUT DFS
FSYNC
DFS
SYNC2K
SYNC2K
FSCR2:INDEP
DIG2
DIG1
2K8K
ICRn:FREQ[3:0]
ICRn:FREQ[3:0]
APLL
Output
Dividers
T0
Output
APLL2
T0
APLL2
DFS
2
2FSYNC,
MFSYNC
OCR4:FSEN, MFSEN
FSCR1:8KI NV, 2KINV
FSCR1:8KP O L , 2KPOL
PLL Bypass
DS3105
26
Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations,
temperature, and voltage; and (2) flexible behavior that is easily programmed through the configuration registers.
DPLLs use digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock
(204.8MHz) is multiplied up from the 12.800MHz local oscillator clock applied to the REFCLK pin. This master
clock is then digitally divided down to the desired output frequency. The DFS output clock has jitter of about 1ns pk-
pk.
The analog PLLs filter the jitter from the DPLLs, reducing the 1ns pk-pk jitter to less than 0.5ns pk-pk and 60ps
RMS, typical, measured broadband (10Hz to 1GHz).
The DPLLs in the device are configurable for many PLL parameters including bandwidth, damping factor, input
frequency, pull-in/hold-in range, input-to-output phase offset, phase build-out, and more. No knowledge of loop
equations or gain parameters is required to configure and operate the device. No external components are
required for the DPLLs or the APLLs except the high-quality local oscillator connected to the REFCLK pin.
The T0 DPLL has a full free-run/lock ed/holdover state machine and full programm ability. The secondary T4 DPLL
can be used to measure frequency and phase of inputs but cannot supply output clock signals.
7.7.1
T0 DPLL State Ma chine
The T0 DPLL has three main timing modes: locked, holdover, and free-run. The control state machine for the T0
DPLL has s tates f or each ti ming m ode as well as three tem porar y states: pre locked, pre lock ed 2, and loss-of-lock.
The stat e transition diagra m is shown in Figure 7-2. Desc riptions of each s tate are give n in the paragraph s below.
During norm al operation the state machine controls state transitions. When necessary, however, the state can be
forced using the T0STATE field of the MCR1 register.
Whenever the T0 DPLL changes state, the STATE bit in MSR2 is set, which can cause an interrupt request if
enabled. The current T0 DPLL state can be read from the T0STATE field of the OPSTATE register.
7.7.1.1
Free-R un State
Free-run mode is the reset default state. In free-run all output clocks are derived from the 12.800 MHz local
oscillator attached to the REFCLK pin. The frequency of each output clock is a specific multiple of the local
oscillator. The frequency accuracy of each output clock is equal to the frequency accuracy of the master clock,
which can be calibrated using the MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3). The state
machine transitions from free-run to the prelocked state when at least one input clock is valid.
7.7.1.2
Prelocked Stat e
The prelocked state provides a 100-second period (default value of PHLKTO register) for the DPLL to lock to the
selected reference. If phase lock (see Section 7.7.6) is achieved for 2 seconds during this period, the state
machine transitions to locked mode.
If the DPLL fails to lock to the selected reference within the phase-lock timeout period specified by PHLKTO, a
phase-lock alarm is r aised ( corr esponding LOCK bit set in the ISR register), inva lidat ing th e inpu t (ICn bit goes low
in VALSR registers). If another input c lock is valid, the st ate m achine re-enters the pr elock ed state and tries to lock
to the altern ate input c lock. If no other input clock s are valid for two sec onds, the state m achine transitions back to
the free-run state.
In revertive mode (REVERT = 1 in MCR3), if a higher priority input clock becomes valid during the phase-lock
timeout period, the state machine re-enters the prelocked state and tries to lock the higher priority input.
If a phase-lock timeout period longer than 100 seconds is required for locking, the PHLKTO register must be
configured ac c ordin gly.
DS3105
27
Figure 7-2. T0 DPLL State Transition Diagram
Free-Run
select ref
(001)
Prelocked
wait for ≤ 100s
(110)
Reset
all input clocks evaluated
at least one input valid
(selected reference invalid > 2s
OR out of lock >100s)
AND no valid input clock
Locked
(100)
phase-locked to
selected reference > 2s
Loss-of-Lock
wait for ≤ 100s
(111)
Holdover
select ref
(010)
loss-of-lock on
selected reference
phase-lock regained
on selected reference
within 100s
Prelocked 2
wait for ≤ 100s
(101)
(selected reference inval id > 2s
OR out of lock > 100s) AND
no valid input clock available
[selected reference inval id OR
(revertive mode AND vali d higher priority input)
OR out of lock > 100s] AND
valid input clock available
[selected reference inval id OR
out of lock > 100s OR
(revertive mode AND vali d higher priority input)]
AND valid input clock avai lable
[selected reference inval id OR
out of lock >100s OR
(revertive mode AND vali d higher priority input)]
AND valid input clock avai lable
(selected reference inval id > 2s
OR out of lock >100s) AND
no valid input clock available
all input clocks evaluated
at least one input valid
selected reference invalid > 2s
AND
no valid input clock avai lable
[selected reference inval id OR
(revertive mode AND vali d higher priority input)]
AND valid input clock avai lable
phase-locked
to selected
reference > 2s
Note 1:
An input clock is valid when it has no activity alarm and no phase-lock alarm (see the VALSR regi sters and the ISR registers).
Note 2:
All input clocks are continuous l y monitored for act i vity.
Note 3:
Only the selected reference is monitored for l oss-of-lock.
Note 4:
Phase lock is declared internally when the DP LL has maintained phase lock continuously f or approximately 1 to 2 seconds.
Note 5:
To simply the diagram, the phase-lock timeout period is al ways shown as 100s, which is the default value of the PHLKTO
register. Longer or s hort er timeout periods can be specified as needed by writing the appropriate value to the PHLKTO register.
Note 6:
When selected reference is invalid and the DPLL is not in free-run or holdover, the DPLL is in a temporary holdover state.
DS3105
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7.7.1.3
Lock ed State
The T0 DPLL state machine can reach the locked state from the prelocked, prelocked 2, or loss-of-lock states
when the D PLL has loc ked to the s elected r eference f or at least 2 s econds (see Section 7.7.6). In the locked s tate
the output clocks track the phase and frequency of the selected reference.
If the MCR1.LOCKPIN bit is set, the LOCK pin is driven high when the T0 DPLL is in the locked state.
While in the locked state, if the selected reference is so impaired that an activity alarm is raised (corresponding
ACT bit s et in t he ISR re gis t er) , the s e lecte d r ef er ence is in vali date d ( ICn bit go es lo w in VALSR reg ister s) , an d the
state machine immediately transitions to either the prelocked 2 state (if another valid input clock is available) or,
after being invalid for 2 seconds, to the holdover state (if no other input clock is valid).
If los s-of-lock (see Sec tion 7.7.6) is declar ed while in the lock ed state, the state machine trans itions to the los s-of-
lock state.
7.7.1.4
Loss-of-Loc k S tate
When the loss-of-lock detectors (see Section 7.7.6) indicate loss-of-phase lock, the state machine immediately
transitions from the locked state to the loss-of-lock state. In the loss-of-lock state the DPLL tries for 100 seconds
(default valu e of PHLKTO register) to r egain phase lock . If phase lock is regained during that period f or m ore than
2 seconds, the state machine transitions back to the locked state.
If, during the ph ase-lock tim eout period s pecified b y PHLKTO, the selected ref erence is so impaired t hat an activ it y
alarm is raised (c orresponding ACT bit set in the ISR regist ers), the selected r eference is invalid ated (ICn bit goes
low in VALSR register s), and af ter being invalid f or 2 seconds the s tate m achine trans itions to eit her th e prelock ed
2 state (if another valid input clock is available) or the holdover state (if no other input clock is valid).
If phase lock cannot be regained by the end of the phase-lock timeout period, a phase-lock alarm is raised
(corr esponding LO CK b it set in the ISR re gisters ), the selected r eferenc e is in val idate d (ICn b it goes l ow in VALSR
registers ), and th e stat e m achine transit ions to eit her t he preloc ked 2 s tate ( if an other valid input c lock is ava ilable)
or, after being invalid for 2 seconds, to the holdover state (if no other input clock is valid).
7.7.1.5
Prelocked 2 S tate
The prelocked and prelocked 2 states are similar. The prelocked 2 state provides a 100-second period (default
value of PHLKTO register) for the D PLL to lock to the new selected reference. If phas e lock (s ee Section 7.7.6) is
achieved for more than 2 seconds during this period, the state machine transitions to locked mode.
If the DPLL f ai ls to l oc k to the new se lec te d ref er enc e with in th e ph as e-lock tim eout peri od specified by PHLKTO, a
phase-lock alarm is raised (corresponding LOCK bit set in the ISR registers), invalidating the input (ICn bit goes
low in VALSR registers). If anot her input cloc k is valid, the stat e machine re-en ters the pre locked 2 state and tries
to lock to the a lternate i nput clock . If no o ther in put clock s are va lid for 2 seconds , the stat e mac hine transit ions to
the holdover state.
In revertive mode (REVERT = 1 in MCR3), if a higher priority input clock becomes valid during the phase-lock
timeout period, the state machine re-enters the prelocked 2 state and tries to lock to the higher priority input.
If a phase-lock timeout period longer than 100 seconds is required for locking, the PHLKTO register must be
configured ac c ordin gly.
7.7.1.6
Holdover State
The device reaches the holdover state when it declares its selected reference invalid for 2 seconds and has no
other valid input clocks available. During holdover the T0 DPLL is not phase-locked to any input clock but instead
generates its o utp ut f reque ncy from s tored f r equency inform ation ac qu ired whi le it was in t he l ocked state. When at
least one input clock has been declared valid, the state machine immediately transitions from holdover to the
prelocked 2 state, and tries to lock to the highest priority valid clock.
DS3105
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7.7.1.6.1
Automatic Holdover
For autom atic holdover (FRUNHO = 0 in MCR3), the device can be further configured for instantaneous mode or
average d mode. In instantaneous mode (AVG = 0 in HOCR3) , the holdover fr equency is set to the DPLL’s current
frequenc y 50m s to 100m s before entr y into holdo ver (i.e., the va lue of the FREQ field in the FREQ1, FREQ2, and
FREQ3 r egist er s when MCR11:T 4T 0 = 0). T he FR EQ field is the DP LL ’s inte gral path an d, theref ore, is an averag e
frequenc y with a rat e of change inverse ly proportio nal to th e DPLL ban dwidth. T he DPLL ’s proporti onal pat h is not
used in order to minimize the effect of recent phase disturbances on the holdover frequency.
In avera ged mode (AVG = 1 in HOCR3 and FRUNHO = 1 in MCR3), the hold over f requency is s et to a n inte rnally
averaged value. During locked operation the frequency indicated in the FREQ field is internally averaged over a
one-secon d per iod . The T 0 DPL L i nd icates th at it h as ac quire d a va li d h oldover v alu e by setting t h e HO RD Y s tatus
bit in VALSR2 (real-time status) and MSR4 (latched status). If the T0 DPLL must enter holdover before the
one-second average is available, an instantaneous value 50ms to 100ms old from the integral path is used instead.
7.7.1.6.2
Free-Run Holdover
For free-run holdover (FRUNHO = 1 in MCR3), the output frequency accuracy is generated with the accuracy of
the external oscillator frequency. The actual frequenc y is the frequency of the external oscillator plus the value of
the MCLK offset specified in the MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3). When
MCR3.FRUNHO is set the HOCR3:AVG bit is ignored.
7.7.1.7
Mini-Holdover
W hen the selected ref erence f ails, the fas t activit y monitor (Sec tion 7.5.3) is olate s the T0 DPLL f rom the refer ence
within one or t wo c lock c ycles to avoid adv erse ef fec ts on the DPLL fr equenc y. When this f ast isolati on oc curs, the
DPLL enters a temporary mini-holdover mode, with a frequency equal to an instantaneous value 50ms to 100 ms
old from the integral path of the loop filter. Mini-holdover lasts until the selected reference becomes active or the
state machine enters the holdover state. If the free-run holdover mode is set (FRUNHO = 1 in MCR3), the mini-
holdover frequency accuracy is exactly the same as the external oscillator accuracy plus the offset set by the
MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3).
7.7.2
T4 DPLL State Ma chine
The T4 DPLL state machine is simpler than the T0 DPLL state machine. The T4 DPLL does not generate any
output clock signals but it can be used to measure phase between two inputs and it can lock to an input to measure
the frequency and possibly stability of the input.
7.7.3
Bandwidth
The bandwidth of the T4 DPLL is configured in the T4BW register to be 18Hz to 70Hz.
The bandwidth of the T0 DPLL is configured in the T0ABW and T0LBW registers for various values from 18Hz to
400Hz. The AUTOBW bit in the MCR9 register controls automatic bandwidth selection. When AUTOBW = 1, the
T0 DPLL uses the T0ABW bandwidth during acquisition (not phase-locked) and the T0LBW bandwidth when
phase-locked. When AUTOBW = 0 the T0 DPLL uses the T0LBW bandwidth all the time, both during acquisition
and when phase-locked.
When LIMINT = 1 in the MCR9 register, the DPLL’s integral path is limited (i.e., frozen) when the DPLL reaches
minimum or maximum frequency. Setting LIMINT = 1 minimizes overshoot when the DPLL is pulling in.
DS3105
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7.7.4
Dampi ng Fa ctor
The damping factor for the T0 DPLL is configured in the DAMP field of the T0CR2 register, while the damping
factor of the T4 D PLL is c onfigured in the D AMP fie ld of the T4CR2 r egister. T he res et default damping factors for
both DPLLs ar e chos e n to gi ve a maxim um jitter/w and er gain p eak of appr ox im atel y 0.1dB. A v ailab le s ett ing s are a
function of DPLL bandwidth (configured in the T4BW, T0ABW, and T0LBW registers). See Table 7-4.
Table 7-4. Damping Factors and Peak Jitter/Wander Gain
BANDWIDTH
(Hz) DAMP[2:0]
VALUE DAMPING
FACTOR GAIN PEAK
(dB)
18
1
1.2
0.4
2
2.5
0.2
3, 4, 5
5
0.1
35
1
1.2
0.4
2
2.5
0.2
3
5
0.1
4, 5
10
0.06
70 to 400
1
1.2
0.4
2
2.5
0.2
3
5
0.1
4
10
0.06
5
20
0.03
7.7.5
Phas e Detectors
Phase detectors are used to compare a PLL’s feedback clock with its input clock. Several phase detectors are
available in the T0 and T4 DPLLs:
Phase/frequency detector (PFD)
Early/late phase detector (PD2) for fine resolution
Multicycle phase detector (MCPD) for large input jitter tolerance and/or faster lock times
These detectors can be used in combination to give fine phase resolution combined with large jitter tolerance. As
with the rest of the DPLL logic, the phase detectors operate at input frequencies up to 77.76MHz. The multicycle
phase det ector d etects and rem em bers phase diff eren ces of man y cycles (up to 8191U I). When locking to 8kH z or
lower, the normal phase/frequency detectors are always used.
The T0 DPLL phase detectors can be configured for normal phase/frequency locking (±360° capture) or nearest
edge phase locking (±180° capture). With nearest edge detection the phase detectors are immune to occasional
missing c lock c ycles. T he DPLL aut omatically switche s to nearest ed ge locking w hen t he multic ycle p hase detec tor
is disabled and the other phase detectors determine that phase lock has been achieved. Setting D180 = 1 in the
TEST1 register disables nearest edge locking and forces the T0 DPLL to use phase/frequency locking. The T4
DPLL always has nearest edge locking enabled.
The early/late phase detector, also known as phase detector 2, is enabled and configured in the PD2 fields of
registers T0CR2 and T0CR3 for the T 0 DPLL an d regis ters T4CR2 and T4CR3 for the T4 DPL L. The reset d efault
settings of these registers are appropriate for all operating modes. Adjustments only affect small signal overshoot
and bandwidth.
The multicycle phase detector is enabled by setting MCPDEN = 1 in the PHLIM2 register. The range of the
MCPD—from ±1UI up to ±8191UI—is configured in the COARSELIM field of PHLIM2. The MCPD tracks phase
position over m an y clock c ycles, giving high j itter to ler ance. T hus, th e use of the MCPD is an a lternat ive to the us e
of LOCK8 K mode for j itter tolerance. W hen a DPLL is dir ect locking to 8k Hz, 4kHz, or 2kHz, or in LOC K8K m ode,
the multicycle phase detector is automatically disabled.
DS3105
31
W hen USEMC PD = 1 in PHLIM2, the M CPD is used in the DPLL l oop, giving f aster pull-in bu t more overs hoot. In
this m ode the loop has s imilar behav ior to LOCK8 K mode. In both cases lar ge phase dif ferences c ontribute to the
dynamics of the loop. When enabled by MCPDEN = 1, the MCPD tracks the phase position whether or not it is
used in the DPLL loop.
W hen the input clock is divided b efore being s ent to the phas e detector, t he divid er output clock edge gets a ligned
to the feedb ack clock edge before t he DPLL starts to lock to a new inp ut clock signal or after the inp ut clock s ignal
has a temporary signal loss. This helps ensure locking to the nearest input clock edge, which reduces output
transients and decreases lock times.
7.7.6
Loss-of-Loc k Detect io n
Loss-of-lock can be triggered by any of the following in both the T0 and T4 DPLLs:
The fine phase-lock detector (measures phase between input and feedback clocks)
The coarse phase-lock detector (measures whole cycle slips)
Hard frequency limit detector
Inactivity detector
The fine phase-lock detector is enabled by setting FLEN = 1 in the PHLIM1 register. The fine phase limit is
configured in the FI NELIM field of PHLIM1.
The coarse phase-lock detector is enabled b y setting CLEN = 1 in the PHLIM2 register. The coarse phase limit is
configured in the COARSELIM field of PHLIM2. This coarse phase-lock detector is part of the multicycle phase
detector (MCPD) described in Section 7.7.5. The COARSELIM field sets both the MCPD range and the coarse
phase limit, since the two are equivalent. If loss-of-lock should not be declared for multiple-UI input jitter, the fine
phase-lock detector should be disabled and the coarse phase-lock detector should be used instead.
The hard f r equ ency limit detec tor is ena bled b y setting FLLO L = 1 in the DLIMIT3 register. The har d l imit for the T 0
DPLL is c onfigured i n regis ters DLIMIT1 and DLIMIT2. The T 4 DPLL har d lim it is fixed at ±80ppm. When the DPLL
frequency reaches the hard limit, loss-of-lock is declared. The DLIMIT3 register also has the SOFTLIM field to
specif y a sof t frequenc y l imit. Exceeding the s oft frequenc y limit does not caus e loss-of-lock to be declared. W hen
the T0 DP LL frequ ency rea ches the sof t limit, the T 0SOF T status bit is set in the OPSTATE register . W hen the T 4
DPLL frequency reaches the soft limit, the T4SOFT status bit is set in OPSTATE.
The inact ivity detector is enab led by setting N ALOL = 1 in the PHLIM1 re gister. W hen this detect or is enabl ed the
DPLL declares loss-of-lock after one or two missing clock cycles on the selected reference. See Section 7.5.3.
W hen the T0 DPLL dec lares loss-of-lock , the state m achine imm ediately trans itions t o the loss-of-lock state, whic h
sets the STATE bit in the MSR2 register and requests an interrupt if enabled.
When the T4 DPLL declares loss-of-lock, the T4LOCK bit is cleared in the OPSTATE register, which sets the
T4LOCK bit in the MSR3 register and requests an interrupt if enabled.
7.7.7
Phas e Build-Out
7.7.7.1
Automatic Phas e Build-Out in Resp onse to Referenc e Swit ching
When MCR10:PBOEN = 0, phase build-out is not performed during reference switching. The T0 DPLL always
locks to the selecte d reference at zero degre es of pha se. W ith PBO disabled, transiti ons from a failed ref erence to
the next h ighes t prior it y reference a nd tr ansitions from holdo ver or f ree-run to loc k ed m ode cause p hase tra nsients
on output clocks as the T0 DPLL jumps from its previous phase to the phase of the new selected reference.
When MCR10:PBOEN = 1, phas e bu ild-out is perf or m ed dur ing r ef er ence switchi ng (or exitin g f r om holdover ). With
PBO enabled, if the selec ted ref erenc e fails and anoth er valid ref erenc e is availab le, the dev ice enter s a temporary
holdover state in which the phase difference between the new reference and the output is measured and fed into
the DPLL loop to absorb the input phase difference. Similarly, during transitions from full-holdover, mini-holdover,
DS3105
32
or free-run to locked m ode, the phase difference between the new reference and the output is measured and fed
into the DPLL loop to absorb the input phase difference. After a PBO event, regardless of the input phase
difference, the output phase transient is less than or equal to 5ns.
Any time that PBO is enabled it can also be frozen at the current phase offset by setting MCR10:PBOFRZ = 1.
When PBO is frozen, the T0 DPLL ignores subsequent phase build-out events and maintains the current phase
offset between inputs and outputs.
Disabling PBO while the T0 DPLL is not in the free-run or holdover states (locking or locked) causes a phase
change on the output clocks while the DPLL switches to tracking the selected reference with zero degrees of phase
error. The rate of phase change on the output clocks depends on the DPLL bandwidth. Enabling PBO (which
includes unfreezing) while locking or locked also causes a PBO event.
7.7.7.2
PBO Phase O ffset A djust m ent
An uncertainty of up to 5ns is introduced each time a phase build-out event occurs. This uncertainty results in a
phase hit on the output. Over a large number of phase build-out events, the mean error should be zero. The
PBOFF r egister sp ecifies a sm all fixed of fset for each phase build-out event to sk ew the a verage error towar d zero
and eliminate accumulation of phase shifts in one direction.
7.7.8
Input to Out put (M anual ) P hase Adjust ment
W hen phase build-out is disabled ( PBOEN = 0 in MCR10), the OFFSET register s can be us ed to adj ust the phas e
of the T0 DPLL output clocks with respect to the selected reference when locked. Output phase offset can be
adjusted over a ±200ns range in 6ps increments. This phase adjustm ent occurs in the feedback clock so that the
output clocks are adjusted to compensate. The rate of change is therefore a function of DPLL bandwidth. Simply
writing t o the OFFSET r egi sters with ph ase build-out dis abled causes a ch ange in the inp ut to output phas e, which
can be co nsidered t o be a del ay adjustm ent. Cha nging the OFFSET adjustm ent while in f ree-run or ho ldover s tate
does not cause an output phase offset until it exits the state and enters one of the locking states.
7.7.9
Phas e Recalibrat ion
When a phase buildout occurs, either automatic or manual, the feedback frequency synthesizer does not get an
internal alignment signal to keep it aligned with the output dividers, and therefore the phase difference between
input and output can become incorrect. Setting the FSCR3:RECAL bit periodically causes a recalibration process
to be executed, which corrects any phase error that may have occurred.
During the recalibration process the device puts the DPLL into mini-holdover, internally ramps the phase offset to
zero, resets all clock dividers, ramps the phase offset to the value stored in the OFFSET registers, and switches
the DPLL out of mini-holdover. If the OFFSET registers are written during the recalibration process, the process
ramps the phase offset to the new offset value.
DS3105
33
7.7.10
Frequency and Phase Measurement
The T4 DPLL can measure frequency by locking onto any input. It can also measure phase between the T0
selected reference and any input by setting the T0CR1.T4MT0 bit.
Accurate measurement of frequency and phase can be accomplished using the DPLLs. The T0 DPLL is always
monitoring its selected reference, but the T4 DPLL can be configured as a high-resolution phase monitor. The
REFCLK signal accurac y after being adjusted with MCLKFREQ is used for the frequency reference. Software can
then connec t the T4 DPLL to vari ous inp ut cloc ks on a rotating bas is to meas ure phas e bet ween the T0 D PLL input
and another inp ut. See the T4FORCE field of MCR4.
DPLL f requency m eas urements c an b e read fr om the FREQ f iel d s pan ni ng reg is t ers FREQ1, FREQ2, and FREQ3.
This field indicates the frequency of the selected reference for either the T0 DPLL or the T4 DPLL, depending on
the setting of the T4T0 bit in MCR11. This frequency measurement has a resolution of 0.0003068ppm over a
±80ppm range. The value read from the FREQ field is the DPLL’s integral path value, which is an averaged
measurement with an averaging time inversely proportional to DPLL bandwidth.
DPLL phase measurements can be read from the PHASE field spanning registers PHASE1 and PHASE2. This
field indica tes the phase dif ference seen b y t he phase detec tor for either the T 0 DPLL or the T4 DPLL , depending
on the setting of the T4T0 bit in MCR11. This phase measurement has a resolution of approximately 0.703 degrees
and is internally averaged with a -3dB attenuation point of approximately 100Hz. Thus, for low DPLL bandwidths
the PHASE field gives input phase wander in the frequency band from the DPLL corner frequency up to 100Hz.
This information could be used by software to compute a crude MTIE measurement.
For the T0 DPLL the PHASE field always indicates the phase difference between the selected reference and the
internal fee dback clock . T he T 4 DPLL, however, can be configured to measure the phase difference between two
input clocks. When T0CR1:T4MT0 = 1, the T4 DPLL locking capability is disabled and the T4 phase detector is
configured to compare the T0 DPLL selected reference with another input by using the T4FORCE field of MCR4.
This featur e c an be use d, f or ex ample, to meas ur e the phas e dif f erenc e bet ween the T0 D PLL ’s s elected r ef er ence
and its next highest priority reference. Software could compute MTIE and TDEV with respect to the T0 DPLL
selected reference for any or all the other input clocks.
When comparing the phase of the T0 selected references and a T4 forced input by setting T0CR1:T4MT0 = 1,
several d etails mus t be considered. I n this m ode, the T4 path r eceives a c opy of the T 0 selected refer ence, either
directl y or thro ugh a div ider to 8kH z. If the T4 se lected refer ence is divided down to 8k Hz using LOC K8K or DIVN
modes (see Section 7.4.2), the copy of the T0 selected reference is also divided do wn t o 8kHz. If the T4 selected
referenc e is configured for direct-lock mode, the cop y of the T 0 selected r ef er ence is not di vided d o wn a nd must be
the sam e frequency as the T4 for ced input. See Table 7-5 for m ore details. (W hile T0CR1:T 4MT0 = 1, the T 0 path
continues to lock to the T0 selected reference in the manner specified in the corresponding ICR register.)
DS3105
34
Table 7-5. T0 DP LL Adaptation for the T4 DPLL Phase Measurement Mode
LOCKING MODE
FOR T4
FORCED
REFERENCE
LOCKING
MODE FOR T0
SELECTED
REFERENCE
LOCKING
MODE FOR
COPY OF T0
SELECTED
REFERENCE
FREQUENCY OF THE
T4 FORCED
REFERENCE FOR
T4MT0 PHASE
MEASUREMENT
FREQUENCY OF THE
T0 SELECTED
REFERENCE FOR
T4MT0 PHASE
MEASUREMENT
LOCK8K or
DIVN(8K)
DIRECT LOCK8K 8kHz 8kHz
LOCK8K or
DIVN(8K)
LOCK8K LOCK8K 8kHz 8kHz
LOCK8K or
DIVN(8K)
DIVN (8K) DIVN 8kHz 8kHz
LOCK8K or
DIVN(8K)
DIVN (not 8K) DIRECT 8kHz 8kHz
DIVN (not 8K) Any DIRECT
Same as the T4 forced
reference input
frequency
Same as the T0 selected
reference input
frequency
(1)
DIRECT Any DIRECT
Same as the T4 forced
reference input
frequency
Same as the T0 selected
reference input
frequency
(1)
Note 1: In this case, the T0 select reference must be the same frequency as the T4 selected reference.
Note 2: If the T4 selected reference frequency is 8kHz and the T0 selected reference is a different frequency, the two referenc es can be
compared by configuring the T4 forced reference for 8kHz and LOCK8K mode. This forces the copy of the T0 selected reference to be divided
down to 8kHz using either LOCK8K or DIVN mode.
Note 3: DIVN(8K) means that the FREQ field is set to 8kHz, DIVN(not 8K) means the FREQ field is not set to 8kHz.
7.7.11
Input Ji tter Toler ance
The device is compliant with the jitter tolerance requirements of the standards listed in Table 1-1. When using the
±360°/±180° PFD, jitter c an be toler ated up to the po int of e ye closur e. E ither LO CK8 K m ode (see Sect ion 7.4.2.2)
or the multicycle phase detector (see Section 7.7.5) should be used for high jitter tolerance.
7.7.12
Jitter T ransfer
The transfer of jitter from the selected reference t o the output clocks has a programmable transfer function that is
determined by the DPLL bandwidth. (See Section 7.7.3.) In the T0 DPLL, the 3dB corner frequency of the jitter
transf er function can b e set to any of 7 posit ions from 18Hz to 400Hz. In the T 4 DPLL the 3d B corner fr equenc y of
the jitter transfer function can be set to various values from 18Hz to 70Hz.
7.7.13
Output Jit ter and W an der
Several factors contribute to jitter and wander on the output clocks, including:
Jitter and wander amplitude on the selected reference (while in the locked state)
The jitter transfer characteristic of the device (while in the locked state)
The jitter and wander on the local oscillator clock signal (especially wander while in the holdover
state)
The DPLL in the d evice ha s progr amm able bandwi dth (s ee Section 7.7.3) . W ith respect to j itter, the DPLL b ehaves
as a lowpass filter with a programmable pole. The bandwidth of the DPLL is normally set low enough to strongly
attenuate jitter.
DS3105
35
7.8
Output Clock Configuration
A total of four output clock pins, OC3, OC6, FSYNC, and MFSYNC, are available on the device. Output clocks OC3
and OC6 are individually configurable for a variety of frequencies. Output clocks FSYNC and MFSYNC are more
specialized, serving as an 8kHz frame sync (FSYNC) and a 2kHz multiframe sync (MFSYNC). Table 7-6 provides
more detail on the capabilities of the output clock pins.
Table 7-6. Output Clock Capabilities
OUTPUT
CLOCK
SIGNAL
FORMAT
FREQU EN C IE S SUP PORTED
OC3 CMOS/TTL Frequency selection per Section 7.8.2.3 and Table 7-7 to Table 7-13.
OC6 LVDS/LVPECL
FSYNC
CMOS/TTL
8kHz frame sync with programmable pulse width and polarity.
MFSYNC
2kHz multif rame sync with program mable pulse width and polar ity.
7.8.1
Sign al Format Configu r ation
Output cl ock OC6 is an LV DS-c ompatible, L VP ECL le vel-c om patible outputs . The type of outp ut c an be s e le cted or
the output can be disabled us ing th e OC 6 SF c onf igura tion b its in t he MCR8 regis ter. The LVPECL l ev el-compatible
mode generates a differential signal that is large enough for most LVPECL receivers. Some LVPECL receivers
have a limited common-mode signal range that can be accommodated for by using an AC-coupled signal. The
LVDS elec trica l spec ificatio ns are l isted in Table 10-5, and t he recom m ended LV DS term ination is s hown i n Figure
10-1. The LVPECL level-compatible electrical specifications are listed in Table 10-6, and the recommended
LVPECL r eceiver ter minati on is sho wn in Figure 10-3. T hese diff erential outp uts c an be easil y interf aced to LVD S,
LVPECL, and CM L inputs on neighboring ICs using a f ew external passive components. See App Note HFAN-1.0
for details.
Output clocks OC3, FSYNC, and MFSYNC are CMOS/TTL signal format.
7.8.2
Frequency Configuration
The f requenc y of outpu t clo cks OC3 and OC 6 is a func tion of the se ttings us ed to c onfigure t he com ponen ts of the
T0 and T4 PLL paths. These components are shown in the detailed block diagram of Figure 7-1.
The DS310 5 uses digita l frequenc y synthes is (DFS) to gen erate various clock s. In DFS a high-sp eed mas ter clock
(204.8MHz) is divided down to the desired output frequency by adding a number to an accumulator. The DFS
output is a c oding of the cl ock output phase that is us ed b y a special c ircuit to deter m ine where to put the e dges of
the output clock between the clock edges of the master clock. The edges of the output clock, however, are not
ideally located in time, resulting in jitter with an amplitude typically less than 1ns pk-pk.
7.8.2.1
T0 and T4 DPLL Details
See Figure 7-1. The T0 and T4 forward-DFS blocks use the 204.8MHz master clock and DFS technology to
synthesize internal clocks from which the output and feedback clocks are derived. The T4 DPLL only has a single
DFS output clock signal, whereas there are two DFS output clock signals in the T0 DPLL—one for the output
clocks and one for the feedback clock.
In the T0 DPLL the feedback clock-signal output handles phase build-out or any phase offset configured in the
OFFSET register s. Thus the T0 DPLL o utput-clock signals a nd the feedb ack clock signal are f requenc y-locked bu t
may have a phase offset. The T0 and T4 feedback -DFS blocks are always connected to the T 0 forward DFS and
the T4 f or ward D F S, r espectively. The f eed back DFS bloc k s synthesize th e a ppropriat e locking fr eque nc ies f or us e
by the phase-frequency detectors (PFDs). See Section 7.4.2.
DS3105
36
7.8.2.2
Output DFS and APLL Det ails
See Figure 7-1. The output clock frequencies are determined by two 2kHz/8kHz DFS blocks, two DIG12 DFS
blocks , and three APLL DF S block s. T he T0 APLL, th e T0 APLL 2, and th e T4 A PLL (and th eir out put divid ers) get
their freque ncy referenc es f rom thr ee ass oc iated APL L D FS b loc k s . All th e out put DF S b locks are c onnec ted to the
T0 DPLL.
The 2K8K DFS and FSYNC DFS blocks generate both 2k Hz and 8kHz signals, which have about 1ns pk -pk jitter.
The FS YNC (8k Hz) and MF SYNC(2 k Hz) signals c ome fr om the FSYNC D FS blo ck, which is always co nnected t o
the T0 DPLL when not in independent mode (FSCR2:INDEP = 1). In independent mode they will be frequency
locked, but not phase aligned with the OC3 and OC6 outputs. The 2kHz and 8 kHz signals that can be output on
OC3 or OC6 always come from the 2K8K DFS, which is always connected to the T0 DPLL.
The DIG 1 DFS c an ge nerat e an N x DS 1 or N x E1 s ig nal with abo ut 1ns pk -pk jitter. T he DIG2 DFS c an gen erat e
an N x DS1, N x E1, 6.312 MHz, 10MH z, or N x 19.44MH z clock with approx imatel y 1ns pk -pk jitter. T he frequency
of the DIG1 c loc k is c onf igured b y the DIG 1S S bit in MCR6 and the DIG 1F[1 :0] f ie ld in MCR7. The fr equenc y of the
DIG2 clock is configured by the DIG2AF and DIG2SS bits in MCR6 and the DIG2F[1:0] field in MCR7. DIG1 and
DIG2 can be independently configured for any of the frequencies shown in Table 7-7 and Table 7-8, respectively.
The APLL DFS blocks and their associated output APLLs and output dividers can generate many different
frequencies. The APLL DFS blocks are always connected to the T0 DPLL. The T0 APLL frequencies that can be
generated are listed in Table 7-10. The T 0 AP LL2 f r equency is al wa ys 3 12. 500 M H z. The T4 APL L f r equencies t hat
can be gener at ed ar e lis t ed in Table 7-12. The output fr eque ncies tha t c an be gen er ated f rom the APLL cir cu i ts ar e
listed in Table 7-9.
DS3105
37
7.8.2.3
OC3 and OC6 C onfi gurati on
The following is a step-by-step procedure for configuring the frequencies of output clocks OC3 and OC6:
Use Table 7-9 to s elec t a s et of output freque ncies f or eac h A PLL , T0 and T4. Each APL L c an on ly
generate one set of output frequencies. (In SONET/SDH equipment, the T0 APLL is typically
configured for a frequency of 311.04MHz to get N x 19.44MHz output clocks to distribute to
system line cards.)
Determ ine fr om Table 7-9 t he T 0 and T 4 APLL f reque ncies req uired for the f requ enc y sets ch osen
in step 2.
Configure the T0FREQ f ield in regist er T0CR1 as show n in Table 7-10 for the T 0 APLL fr equency
determined in step 3. Configure fields T4CR1:T4FREQ, T0CR1:T4APT0, and T0CR1:T0FT4
as shown in Table 7-12 for the T4 APLL frequency determined in step 3.
Using Table 7-9 and Table 7-13, configure the frequencies of output clocks OC3 and OC6 in the
OFREQn fields of registers OCR2 and OCR4 and the AOFn bits in the OCR5 register.
Table 7-14 lists all standard frequencies for the output clocks and specifies how to configure the T0 APLL and/or
the T4 APLL to obtain each frequency. Table 7-14 also indicates the expected jitter amplitude for each frequency.
Table 7-7. Digita l1 Frequencies
DIG1F[1:0]
SETTING IN
MCR7
DIG1SS
SETTING IN
MCR6
FREQUENCY
(MHz)
JITTER
(pk-pk, ns,
typ)
00
0
2.048
< 1
01
0
4.096
< 1
10
0
8.192
< 1
11
0
16.384
< 1
00
1
1.544
< 1
01
1
3.088
< 1
10
1
6.176
< 1
11
1
12.352
< 1
Table 7-8. Digita l2 Frequencies
DIG2AF
SETTING
IN MCR6
DIG2F[1:0]
SETTING
IN MCR7
DIG2SS
SETTING
IN MCR6
FREQUENCY
(MHz)
JITTER
(pk-pk,
ns, typ)
1
00
0
6.312
< 1
1
10
0
10.000
<1
1
00
1
19.440
< 1
1
01
1
38.880
< 1
0
00
0
2.048
< 1
0
01
0
4.096
< 1
0
10
0
8.192
< 1
0
11
0
16.384
< 1
0
00
1
1.544
< 1
0
01
1
3.088
< 1
0
10
1
6.176
< 1
0
11
1
12.352
< 1
DS3105
38
Table 7-9. APLL Frequency to Output Fre quencies (T0 APLL and T4 APLL)
APLL
FREQUENCY
APLL /
2
APLL /
4
APLL /
5
APLL /
6
APLL /
8
APLL /
10
APLL /
12
APLL /
16
APLL /
20
APLL /
48
APLL /
64
312.500
156.250
—
62.500
—
—
31.250
—
—
—
—
—
311.040
155.520
77.760
62.208
51.840
38.880
31.104
25.920
19.440
15.552
6.480
4.860
274.944
137.472
68.376
—
45.824
34.368
—
22.912
17.184
—
5.728
4.296
250.000
125.000
62.500
50.000
—
31.250
25.000
—
—
12.500
—
—
178.944
89.472
44.736
—
29.824
22.368
—
14.912
11.184
—
3.728
2.796
160.000
80.000
40.000
32.00
—
20.000
16.000
—
10.000
8.000
—
2.500
148.224
74.112
37.056
—
24.704
18.528
—
12.352
9.264
—
3.088
2.316
131.072
65.536
32.768
—
—
16.384
—
—
8.192
—
—
2.048
122.880
61.440
30.720
24.576
20.480
15.360
12.288
10.240
7.680
6.144
2.560
1.920
104.000
52.000
26.000
20.800
—
13.000
10.400
—
6.500
5.200
—
—
100.992
50.496
25.248
—
16.832
12.624
—
8.416
6.312
—
2.104
1.578
98.816
49.408
24.704
—
—
12.352
—
—
6.176
—
—
1.544
98.304
49.152
24.576
—
16.384
12.288
—
8.192
6.144
—
2.048
1.536
Note: All frequenc i es i n MHz. Common telecom, datacom, and synchroni zation frequenc i es are in bold type.
Table 7-10. T0 APLL Frequency Configuration
T0 APLL
FREQUENCY (MHz)
T0 APLL DFS
FREQUENCY (MHz)
T0 APLL
FREQUENCY MODE
T0FREQ[2:0] SETTING
IN T0CR1
OUTPUT JITTER
(pk-pk, ns, typ)
311.04
77.76
77.76MHz
000
< 0.5
311.04
77.76
77.76MHz
001
< 0.5
98.304
24.576
12 x E1
010
< 0.5
131.072
32.768
16 x E1
011
< 0.5
148.224
37.056
24 x DS1
100
< 0.5
98.816
24.704
16 x DS1
101
< 0.5
100.992
25.248
4 x 6312kHz
110
< 0.5
250.000
62.500
GbE ÷ 16
111
< 0.5
Table 7-11. T0 APLL2 Frequency Configuration
T0 APLL2
FREQUENCY (MHz)
T0 APLL2 DFS
FREQUENCY(MHz)
OUTPUT JITTER
(pk-pk, ns, typ)
312.500 62.500 < 0.5
DS3105
39
Table 7-12. T4 APLL Frequency Configuration
T4 APLL
FREQUENCY
(MHz)
T4 APLL DFS
FREQUENCY
(MHz)
T4 APLL
FREQUENCY
MODE
T4APT0
SETTING IN
T0CR1
T4FREQ[3:0]
SETTING IN
T4CR1
T0FT4[2:0]
SETTING IN
T0CR1
OUTPUT
JITTER
(pk-pk, ns, typ)
Disabled
77.76
Squelched
0
0000
XXX
< 0.5
311.04
77.76
77.76MHz
0
0001
XXX
< 0.5
98.304
24.576
12 x E1
0
0010
XXX
< 0.5
131.072
32.768
16 x E1
0
0011
XXX
< 0.5
148.224
37.056
24 x DS1
0
0100
XXX
< 0.5
98.816
24.704
16 x DS1
0
0101
XXX
< 0.5
274.944
68.736
2 x E3
0
0110
XXX
< 0.5
178.944
44.736
DS3
0
0111
XXX
< 0.5
100.992
25.248
4 x 6312kHz
0
1000
XXX
< 0.5
250.000
62.500
GbE ÷ 16
0
1001
XXX
< 0.5
122.88
30.720
3 x 10.24
0
1010
XXX
< 0.5
160.000
40.000
4 x 10
0
1011
XXX
< 0.5
104.000
26.000
2 x 13
0
1100
XXX
< 0.5
98.304
24.576
T0 12 x E1
1
XXXX
000
< 0.5
250.000
62.500
T0 GbE ÷ 16
1
XXXX
001
< 0.5
131.072
32.768
T0 16 x E1
1
XXXX
010
< 0.5
148.224
37.056
T0 24 x DS1
1
XXXX
100
< 0.5
98.816
24.704
T0 16 x DS1
1
XXXX
110
< 0.5
100.992
25.248
T0 4 x 6312kHz
1
XXXX
111
< 0.5
Table 7-13. OC3 and OC6 Output Frequency Selection
AOF BIT OFREQ(1)
FREQUENCY
OC3
OC6
0
0000
Disabled
Disabled
0
0001
2kHz
2kHz
0
0010
8kHz
8kHz
0
0011
Digital2
T0 / 2
0
0100
Digital1
Digital1
0
0101
T0 / 48
T0 / 1
0
0110
T0 / 16
T0 / 16
0
0111
T0 / 12
T0 / 12
0
1000
T0 / 8
T0 / 8
0
1001
T0 / 6
T0 / 6
0
1010
T0 / 4
T0 / 4
0
1011
T4 / 64
T4 / 64
0
1100
T4 / 48
T4 / 48
0
1101
T4 / 16
T4 / 16
0
1110
T4 / 8
T4 / 8
0
1111
T4 / 4
T4 / 4
1
0000
Disabled
Disabled
1
0001
T0 / 64
T4 / 5
1
0010
T4 / 20
T4 / 2
1
0011
T4 / 12
T4 / 1
1
0100
T4 / 10
T02 / 5
1
0101
T4 / 5
T02 / 2
1
0110
T4 / 2
T02 / 1
1
0111
T4SELREF
T4SELREF
Note 1: The value of the OFREQn field (in the OCR2 to OCR4 registers) c orres pondi ng to output clock OCn.
Note 2: T0 = T0 APLL. T02 = T0 APLL2. T4 = T4 APLL.
DS3105
40
Table 7-14. Standard Frequencies for P r ogramm able Outputs
FREQUENCY (MHz)
T0 APLL T4 APLL
OFREQn
JITTER
(TYP)
T0FREQ T4FT0 T4FREQ RMS
(ps) pk-pk
(ns)
2 kHz
2kHz
100
1.00
8 kHz
8kHz
100
1.00
1.536
Not OC6 from T0 APLL
12 x E1
12 x E1
12 x E1
APLL/64
100
1.00
1.544
Not OC6 from DIG2
DIG1, DIG2
100
1.00
1.544
Not OC6 from T0 APLL
16 x DS1
16 x DS1
16 x DS1
APLL/64
75
0.75
1.578
Not OC6 from T0 APLL
4 x 6.312
4 x 6.312
4 x 6.312
APLL/64
60
0.60
2.048
Not OC6 from DIG2
DIG1, DIG2
100
1.00
2.048
Not OC6 from T0 APLL
12 x E1
12 x E1
12 x E1
APLL/48
100
1.00
2.048
Not OC6 from T0 APLL
16 x E1
16 x E1
16 x E1
APLL/64
70
0.70
2.104
Not OC6 from T0 APLL
4 x 6.312
4 x 6.312
4 x 6.312
APLL/48
60
0.60
2.316
Not OC6 from T0 APLL
24 x DS1
24 x DS1
24 x DS1
APLL/64
60
0.60
2.500
4 x 10
APLL/64
80
0.80
2.560
3 x 10.24
APLL/48
90
0.90
2.796
DS3
APLL/64
50
0.50
3.088
Not OC6 from DIG2
DIG1, DIG2
100
1.00
3.088
Not OC6 from T0 APLL
24 x DS1
24 x DS1
24 x DS1
APLL/48
60
0.60
3.728
DS3
APLL/48
50
0.50
4.096
Not OC6 from DIG2
DIG1, DIG2
100
1.00
4.296
2 x E3
APLL/64
70
0.70
4.860
Not OC6 from T0 APLL
77.76
77.76
APLL/64
50
0.50
5.200
OC3 only
2 x 13
APLL/20
90
0.90
5.728
2 x E3
APLL/48
70
0.70
6.144
OC3 only
3 x 10.24
APLL/20
90
0.90
6.144
12 x E1
12 x E1
12 x E1
APLL/16
100
1.00
6.176
not OC6 from DIG2
DIG1, DIG2
100
1.00
6.176
16 x DS1
16 x DS1
16 x DS1
APLL/16
75
075
6.312
OC3 only
DIG2
100
1.00
6.312
4 x 6.312
4 x 6.312
4 x 6.312
APLL/16
60
0.60
6.480
Not OC6 from T0 APLL
77.76
77.76
APLL/48
60
0.6
8.000
OC3 only
4 x 10
APLL/20
80
0.80
8.192
Not OC6 from DIG2
DIG1, DIG2
100
1.00
8.192
12 x E1
APLL/12
100
1.00
8.192
16 x E1
16 x E1
16 x E1
APLL/16
70
0.70
8.416
4 x 6.312
APLL/12
60
0.60
9.264
24 x DS1
24 x DS1
24 x DS1
APLL/16
60
0.60
10.000
not OC6
DIG2
100
1.00
10.000
4 x 10
APLL/16
80
0.80
10.240
OC3 only
3 x 10.24
APLL/12
90
0.90
10.400
OC3 only
3 x 10.24
APLL/10
90
0.90
11.184
DS3
APLL/16
50
0.50
12.288
12 x E1
12 x E1
12 x E1
APLL/8
100
1.00
12.288
OC3 only
2 x 13
APLL/10
90
0.90
12.352
24 x DS1
APLL/12
60
0.60
12.352
16 x DS1
16 x DS1
16 x DS1
APLL/8
75
0.75
12.352
Not OC6 from D IG2
DIG1, DIG2
100
1.00
12.500
OC3 only
GbE ÷ 16
GbE ÷ 16
APLL/20
60
0.60
12.624
4 x 6.312
4 x 6.312
4 x 6.312
APLL/8
60
0.60
13.000
2 x 13
APLL/8
90
0.90
15.360
3 x 10.24
APLL/8
90
0.90
15.552
OC3 only
77.76
APLL/20
50
0.50
16.000
OC3 only
4 x 10
APLL/10
80
0.80
16.384
Not OC6 from DIG2
DIG1, DIG2
100
1.00
16.384
12 x E1
APLL/6
100
1.00
DS3105
41
FREQUENCY (MHz)
T0 APLL T4 APLL
OFREQn
JITTER
(TYP)
T0FREQ T4FT0 T4FREQ RMS
(ps) pk-pk
(ns)
16.384
16 x E1
16 x E1
16 x E1
APLL/8
70
0.70
16.832
4 x 6.312
APLL/6
60
0.60
17.184
2 x E3
APLL/16
70
0.70
18.528
24 x DS1
24 x DS1
24 x DS1
APLL/8
60
0.60
19.440
OC3 only
DIG2
100
1.00
19.440
77.76
77.76
APLL/16
50
0.50
20.000
4 x 10
APLL/8
80
0.80
20.800
2 x 13
APLL/5
90
0.90
22.368
DS3
APLL/8
50
0.50
24.576
12 x E1
12 x E1
12 x E1
APLL/4
100
1.00
24.576
3 x 10.24
APLL/5
90
0.90
24.704
24 x DS1
APLL/6
60
0.60
24.704
16 x DS1
16 x DS1
16 x DS1
APLL/4
75
0.75
25.000
OC3 only
GbE ÷ 16
GbE ÷ 16
APLL/10
60
0.60
25.248
4 x 6.312
4 x 6.312
4 x 6.312
APLL/4
60
0.60
25.920
77.76
APLL/12
50
0.50
26.000
2 x 13
APLL/4
90
0.90
30.720
3 x 10.24
APLL/4
90
0.90
31.104
OC3 only
77.76
APLL/10
50
0.50
31.250
GbE ÷ 16
GbE ÷ 16
GbE ÷ 16
APLL/8
60
0.60
32.000
4 x 10
APLL/5
80
0.80
32.768
16 x E1
16 x E1
16 x E1
APLL/4
70
0.70
34.368
2 x E3
APLL/8
70
0.70
37.056
24 x DS1
24 x DS1
24 x DS1
APLL/4
60
0.60
38.880
77.76
77.76
APLL/8
50
0.50
40.000
4 x 10
APLL/4
80
0.80
44.736
DS3
APLL/4
50
0.50
49.152
Not OC3 from T0 APLL
12 x E1
12 x E1
12 x E1
APLL/2
100
1.00
49.408
Not OC3 from T0 APLL
16 x DS1
16 x DS1
16 x DS1
APLL/2
75
0.75
50.000
GbE ÷ 16
GbE ÷ 16
APLL/5
60
0.60
50.496
Not OC3 from T0 APLL
4 x 6.312
4 x 6.312
4 x 6.312
APLL/2
60
0.60
51.840
77.76
APLL/6
50
0.50
52.000
2 x 13
APLL/2
90
0.90
61.440
3 x 10.24
APLL/2
90
0.90
62.208
77.76
APLL/5
50
0.50
62.500
GbE ÷ 16
GbE ÷ 16
GbE ÷ 16
APLL/4
60
0.60
62.500
OC6 only from T0 APLL2
APLL/5
60
0.60
65.536
Not OC3 from T0 APLL
16 x E1
16 x E1
16 x E1
APLL/2
70
0.70
68.736
2 x E3
APLL/4
70
0.70
74.112
Not OC3 from T0 APLL
24 x DS1
24 x DS1
24 x DS1
APLL/2
60
0.60
77.76
77.76
77.76
APLL/4
50
0.50
80.000
4 x 10
APLL/2
80
0.80
89.472
DS3
APLL/2
50
0.50
98.304
OC6 only
12 x E1
12 x E1
12 x E1
APLL/1
100
1.00
98.816
OC6 only
16 x DS1
16 x DS1
16 x DS1
APLL/1
75
0.75
100.992
OC6 only
4 x 6312 kHz
4 x 6312 kHz
4 x 6312 kHz
APLL/1
60
0.60
104.000
OC6 only
2 x 13
APLL/1
90
0.90
122.880
OC6 only
3 x 10.24
APLL/1
90
0.90
125.000
Not OC3 from T0 APLL
GbE ÷ 16
GbE ÷ 16
GbE ÷ 16
APLL/2
60
0.60
131.072
OC6 only
16 x E1
16 x E1
16 x E1
APLL/1
70
0.70
137.472
OC6 only
2 x E3
APLL/2
70
0.70
148.224
OC6 only
24 x DS1
24 x DS1
24 x DS1
APLL/1
60
0.60
155.520
Not OC3 from T0 APLL
77.76
77.76
APLL/2
50
0.50
156.250
OC6 only from T0 APLL2
APLL/2
60
0.60
160.000
OC6 only
4 x 10
APLL/1
80
0.80
178.944
OC6 only
DS3
APLL/1
50
0.50
DS3105
42
FREQUENCY (MHz)
T0 APLL T4 APLL
OFREQn
JITTER
(TYP)
T0FREQ T4FT0 T4FREQ RMS
(ps) pk-pk
(ns)
250.000
OC6 only
GbE ÷ 16
APLL/1
60
0.60
274.944
OC6 only
70
0.70
311.040
OC6 only
77.76
APLL/1
50
0.50
312.500
OC6 only from T0 APLL2
APLL/2
60
0.60
7.8.2.4
OC3 and OC6 D efaul t Frequency Select Pins
There ar e two s ets of f r equenc y se lect pi ns , O 3F[2: 0] and O6F[ 2:0], that co ntrol t he r es et d ef ault f r eque ncie s of the
OC3 and OC6 output clock pins, respectively. The SONSDH pin also selects the output frequencies for some of the
pin settings. There is also an interaction between O3F[2:0] and O6F[2:0] when O6F[2:0] uses some internal
resourc e that is needed to generate certain freque nc ie s . Af ter r es et the O3F [2: 0] and O 6F[2:0] pins can be used as
GPIO pins an d s tatus out p ut pins . T he def ault o utp ut f reque nc ies are af f ec ted b y chang ing th e regis t er bit v al ues of
four registers: OCR2, OCR3, T0CR1, and T4CR1. The register defaults can be changed after reset using the
microprocessor interface.
Table 7-15. T0CR1.T0FREQ Default Settings
O6F[2:0]
O3F[2:0]
SONSDH
T0CR1.T0FREQ
=001 =001
0
010
12 x E1 DFB
1
100
24 x DS1 DFB
!=001
X
X
001
77.76 AFB
X
!=001
X
001
77.76 AFB
Table 7-16. T4CR1.T4FREQ Default Settings
O6F[2:0]
O3F[2:0]
SONSDH
T4CR1.T4FREQ
=001 X
0
0110
E3
1
0111
DS3
X =010
0
0110
E3
1
0111
DS3
!=001 !=010
0
0011
16 x E1
1
0101
16 x DS1
Table 7-17. OC6 Default Frequency Configuration
O6F[2:0] SONSDH FREQUENCY
(MHz) OCR3.
OFREQ6 APLL
SRC
000
X
0
0000
—
001
0
68.736
1111
T4
1
22.368
1110
T4
010
X
19.44
0110
T0
011
X
25.92
0111
T0
100*
X
38.88
1000
T0
101
X
51.84
1001
T0
110
X
77.76
1010
T0
111
X
155.52
0011
T0
*Occurs when O6F[2:0] are left unconnected.
DS3105
43
Table 7-18. OC3 Default Frequency Configuration
O3F[2:0] SONSDH FREQUENCY
(MHz) O6F[2:0]
=001 OCR2.
OFREQ3 APLL
SRC
000
X
0
X
0000
—
001
0
8.192
FALSE
1101
T4
1
6.176
1101
T4
001
001
0
8.192
TRUE
0111
T0
1
12.352
0111
T0
010
0
68.736
X
1111
T4
010
1
22.368
X
1110
T4
011*
X
19.44
X
0110
T0
100
X
25.92
X
0111
T0
101
X
38.88
X
1000
T0
110
X
51.84
X
1001
T0
111
X
77.76
X
1010
T0
*Occurs when O3F[2:0] are left unconnected.
7.8.2.5
FSYNC and MFSYNC Configurati on
The FSYNC out put is enabled b y sett ing FSEN = 1 in the OCR4 reg ister, while the MF SYNC output is ena bled by
setting MFSEN = 1 in OCR4. When disabled, these pins are driven low.
When 8KPUL = 0 in FSCR1, FSYNC is configured as an 8kHz clock with 50% duty cycle. When 8KPUL = 1,
FSYNC is an 8kHz frame sync that pulses low once every 125µs with pulse width equal to one cycle of output
clock OC3. When 8KINV = 1 in FSCR1, the clock or pulse polarity of FSYNC is inverted.
When 2KPUL = 0 in FSCR1, MFSYNC is configured as an 2kHz clock with 50% duty cycle. When 2KPUL = 1,
MFSYNC is a 2kHz frame sync that pulses low once every 500µs with pulse width equal to one cycle of output
clock OC3. When 2KINV = 1 in FSCR1, the clock or pulse polarity f MFSYNC is inverted.
If either 8K PUL = 1 or 2 KP UL = 1, outp ut clock O C3 m ust be generated f rom the T 0 DPLL and m ust be configur ed
for a f requency of 1.544M Hz or higher or th e FSYNC/MFSYN C pulses m ay not be generat ed correctl y. Figure 7-3
shows how the 8KPUL and 8KINV control bits affect the FSYNC output. The 2KPUL and 2KINV bits have an
identical effect on MFSYNC.
Figure 7-3. FSYNC 8kHz Options
OC3 OUTPUT CLOCK
FSYNC, 8KPUL=0, 8KINV=0
FSYNC, 8KPUL=0, 8KINV=1
FSYNC, 8KPUL=1, 8KINV=0
FSYNC, 8KPUL=1, 8KINV=1
DS3105
44
7.8.2.6
Custom Out put Fre quenci es
In addition to the many standard frequencies available in the device, any of the seven output DFS blocks can be
configured to generate a custom frequency. Possible custom frequencies include any multiple of 2kHz up to
77.76MHz and any multiple of 8kHz up to 311.04MHz. (An APLL must be used to achieve frequencies above
77.76MHz.) Any of the programmable output clocks can be configured to output the custom frequency or
submultiples thereof. Contact Microsemi timing products technical support for help with custom frequencies.
7.9
Frame and Multif r ame Alignment
In addition to receiving and locking to clocks such as 19.44MHz from system timing cards, the DS3105 can also
receive a nd align its output s to 2k Hz multifr ame-s ync or 8k Hz fram e-sync signals from s ys tem timing cards . In this
mode of operation, both a higher speed clock (such as 6.48MHz or 19.44MHz) and a frame (or multiframe) sync
signal from each timing card are passed to the line cards. The higher speed clock from each timing card is
connecte d to a regular input clock pin on the DS31 05, such as IC 3 or IC4, while the as sociated fram e-sync signal
is connected to a SYNCn input pin on the DS3105, such as SYNC1 or SYNC2. The DS3105 locks to the higher
speed clock from one of the timing cards and samples the associated frame-sync signal. The DS3105 then uses
the SYNCn signal to falling-edge align some or all the output clocks. When the SYNCn signal is a 2kHz clock,
output cl oc ks 2kH z and ab ove ar e f al ling-e dge a lig ne d. A 4kH z or 8kHz clock can a lso b e us e d o n th e SYNCn p ins
without any changes to the register configuration, but only output clocks of 8kHz and above are aligned in this
case. Onl y the falling ed ge of t he SYNCn signa l has signif icance. Ph ase build-out should be d isabled (PBO EN = 0
in MCR10) when using SYNCn signals.
An externa l fr ame s ync signal is on l y allowed to align output c lock s if the T 0 DPL L is loc k ed and the SYNCn signa l
is enabled and qualified. Section 7.9.1 discusses enable, while Section 7.9.4 covers qualification.
7.9.1
Enabl e and SYNCn Pin S election
Table 7-19 shows how to configure the device for various external frame-sync modes. W hen MCR3:EFSEN = 0,
external frame sync is disabled. When EFSEN = 1, three different external frame-sync modes are available:
SYNC1 Manual, SYNC1 Auto, and SYNC123.
In SYNC1 Manual mode, external frame sync is enabled on the SYNC1 pin whenever the T0 DPLL is locked,
regardless of which input clock is the selected reference. W hen the T 0 DPLL is not lock ed, external frame sync is
disabled. In this mode the SYNC2 and SYNC3 pins are ignored.
In SYNC1 Aut o mode, exte r nal f rame sync is automatic ally enabled o n th e S YNC 1 pin whe n the T0 DPLL is locked
to the input clock pin specified by FSCR3:SOURCE. If the T0 DPLL is not locked or is locked to a different input
clock than the one specified b y the SOURC E field, then external frame sync is disabled. In this m ode the SYNC2
and SYNC3 pins are ignored.
In SYNC123 mode, the SYNC1, SYNC2, and SYNC3 pins are each associated with one or more input clock pins
as specified by FSCR1:SYNCSRC. SYNC1 can be as sociated with IC3 or IC5 or both. SYNC2 can be associated
with IC4 or IC6 or both. SYNC3 is always associated with IC9. When the T0 DPLL is locked to one of the input
clock pins associated with a SYNCn pin, external frame sync is automatically enabled with the corresponding
SYNCn p in as the source. W hen the T0 DPLL is not l ocked or is locked to an input c lock pin that is not assoc iated
with a SYNCn pin then external frame sync is disabled.
Since SYNC123 mode is always autom atic, MCR3:AEFSEN takes on a different meaning in this mode, specifying
whether or not MCR3:EFSEN is automatically cleared when the T0 DPLL’s selected reference changes.
DS3105
45
Table 7-19. External Frame-Sync Mode and S our ce
T0 DPLL
LOCKED
1
MCR3:
EFSEN
FSCR3:
SOURCE
MCR3:
AEFSEN
FSCR1:
SYNCSRC
PTAB1:
SELREF
FRAME-SYNC
MODE
FRAME-SYNC
SOURCE
0
X
XXXX2
X
XXX
XXXX
Disabled
Internal3
1
0
XXXX
X
XXX
XXXX
Disabled
Internal
1
1
<>11XX
0
XXX
XXXX
SYNC1 Manual
SYNC1
1 1 <>11XX 1 XXX
=FSCR3:
SOURCE
SYNC1 Auto SYNC1
<>FSCR3:
SOURCE
Internal
1 1 11XX X4
0XX
IC3 or IC5
SYNC123
(Auto4)
SYNC1
IC4 or IC6
SYNC2
1X0
IC3
SYNC1
IC4
SYNC2
1X1
IC5
SYNC1
IC6
SYNC2
XXX
IC9
SYNC3
all other cases
Internal
Note 1: That is, when OPSTATE:T0STATE = 100.
Note 2: X = Don’t care.
Note 3: None of the SYNCn pins is used. The internal 2kHz alignment generators free-run at their existi ng alignment. See Section 7.9.5.
Note 4: When SOURCE=11XX, selection and enable of SYNCn pins are automatic regardless of the setting of AEFSEN. In this mode the
AEFSEN bit is retasked to specify whether or not MCR3:EFSEN is automatically cleared when the T0 DPLL’s selected reference
changes.
7.9.2
Sampling
By default the external frame-sync signal on the enabled SYNCn pin is first sampled on the rising edge of the
selected reference. This gives the most margin, given that the external frame-sync signal is falling-edge aligned
with the sel ected reference since both com e from the same tim ing card. The expected tim ing of the SYNC n signal
with respect to the sampling clock can be adjusted from 0.5 cycles early to 1 cycle late using the
FSCR2:PHASEn[1:0] field.
7.9.3
Resampling
The SYNCn s ignal is then r esampled b y an inter nal cl o ck derived fr om the T 0 D PLL. T he r esam pling res ol uti o n is a
function of the fr equenc y of the se lected ref erence an d FSCR2:OCN . W hen OCN = 0, the resam pling res olution is
6.48MH z, which gi ves t he most sam pling m ar gin and also al ig ns all c loc ks at 6.48MHz and m ultiples th ereof. W hen
OCN = 1, if the s e lected r eferenc e is 19 .44MHz, the r e sam plin g r esolut io n is 19.44MH z. If the s elec te d reference is
38.88MH z, the resam pling res olution is 38.88MH z. The selected r eference m ust be either 1 9.44MHz or 38. 88MHz
when OCN = 1.
7.9.4
Qualification
The S YNCn signal is qu alifi ed when it h as cons istent p hase an d corr ect f requenc y. Sp ecific ally, it is qualif ied when
its significant edge has been found at exact 2kHz boundaries (when resampled as previously described) for 64
cycles in a row. It is disqualified when one significant edge is not found at the 2kHz boundary.
7.9.5
Output Clock Alignment
W hen the T0 DPLL is loc k ed, external f rame s ync is enabled, a nd the S YNCn sig nal is qual ified, the S YNCn signal
can be us ed to fal ling-edge al ign the T 0 DPLL d erived outp ut clock s. Output c locks FSYNC and MFSYNC share a
2kHz alignment generator, while the rest of the T0 DPLL-derived output clocks share a second 2kHz alignment
generator. When external frame sync is not enabled or the SYNCn signal is not qualified, these 2Hz alignment
DS3105
46
generators free-run with their existing 2kHz alignments. When the external frame sync is enabled and the SYNCn
signal is qualified, the FSYNC/MFSYNC 2kHz alignment generator is always synchronized by the SYNCn signal,
and, therefore, FSYNC and MFSYNC are always falling-edge al igned with SYN Cn. W hen FSCR2:INDEP = 0, the
T0 DPLL 2kHz alignment generator is also synchronized with the FSYNC/MFSYNC 2kHz alignment generator to
falling-edge align all T0-derived output clocks with the SYNCn signal. When INDEP = 1, the T0 DPLL 2-kHz
alignment generator is not synchronized with the FSYNC/MFSYNC 2kHz alignment generator and continues to
free-run with its existing 2kH z alignm ent. This avoids any disturbance on t he T0 DPLL deri ved output clock s when
the SYNCn signal has a change of phase position.
7.9.6
Frame-S y nc Mo nit or
The f rame-sync monitor signal OPSTATE:FSMON operates in two modes, depending on the setting of the enable
bit (MCR3:EFSEN).
When EFSEN = 1 (external frame sync enabled), the OPSTATE:FSMON bit is set when the SYNCn signal is not
qualified an d c lear ed when S YNC n is q ua lif ie d. If the S YNC n s ign al is dis q ual if ied, both 2k Hz alignm ent ge nerators
are immediately disconnected from SYNCn to avoid phase movement on the T0-derived outputs clocks. When
OPSTATE:FSMO N is set, the latc hed status b it MSR3:FSMON is also s et, which can cause an int errupt if en abled
in the IER3 regis t er. If SYNCn im mediatel y st abil i zes at a ne w phas e a nd pr oper frequency, it is re qua lif i ed after 64
2kHz cycles (nominally 32ms). Unless system software intervenes, after the SYNCn signal is requalified th e 2kHz
alignm ent generators will synchr onize w ith SYNCn’s n ew phase al ignment, c ausing a sudd en phase m ovement on
the output clocks. S yst em software can avoid this sud den phase m ovement on the output clock s by respondin g to
the FSMON inter rupt withi n the 32m s windo w with app ropriat e act ion, which m ight inc lude disab ling ext erna l fram e
sync (MCR3:EFSEN = 0) to prevent the resynchronization of the 2kHz alignment generators with SYNCn, forcing
the T0 DP LL into holdov er (MCR1:T0STAT E = 010) to avoid affecting the ou tput cloc ks with any other phase hits,
and possibly even disabling the master timing card and promoting the slave timing card to master since the 2kHz
signal from the master should not have such phase movements.
When EFSEN = 0 (external frame sync disabled), OPSTATE:FSMON is set when the negative edge of the
resam pled SYNCn signal is outside the window determined by FSCR3:MONLIM relative to the MFSYNC negative
edge (or pos itive edge if MFS YNC is inverted) and clear when within t he windo w. When OPSTATE:FSMON is set ,
the latched status bit MSR3:FSMON is also set, which can cause an interrupt if enabled in the IER3 register.
7.9.7
Other Configuration O pt ions
FSYNC an d MFSYNC are always produced f rom the T 0 DPLL. The other out put clock s can also be configu red as
2kHz or 8kHz outputs, derived from the T0 DPLL.
7.10
Microprocessor Interface
The DS3105 presents an SPI interface on the CS, SCLK, SDI, and SDO pins. SPI is a widely used master/slave
bus protocol that allows a master device and one or more slave devices to communicate over a serial bus. The
DS3105 is always a slave device. Masters are typically microprocessors, ASICs, or FPGAs. Data transfers are
always initiated b y th e master devic e, which als o gener ates the SCLK s ignal. The DS3 105 receives s erial data on
the SDI pin and transmits serial data on the SDO pin. SDO is high impedance except when the DS3105 is
transmitting data to the bus master.
Bit Ord er. W hen both bit 3 and bit 4 are low at de vice address 3FF Fh, the register addres s and all data bytes ar e
transmitted MSB first on both SDI and SDO. When either bit 3 or bit 4 is set to 1 at device address 3FFFh, the
register address and all data bytes are transmitted LSB first on both SDI and SDO. The reset default setting and
Motorola SPI convention is MSB first.
Clock Polarit y and Phase . When CPOL = 0, SCLK is normally low and pulses high during bus transactions. The
CPHA pin s ets th e ph as e ( ac tiv e ed ge) of SCLK. When C PH A = 0, data is latc he d in on SD I o n th e l ead in g edge of
the SCLK pulse and updated on SDO on the trailing edge. When CPHA = 1, data is latched in on SDI on the
trailing ed ge of the SCL K pulse a nd updat ed on S DO on th e follo wing l eading ed ge. SC LK do es not hav e to togg le
between acc es s es, i.e., when CS is high. See Figure 7-4.
DS3105
47
Device Selection. Each SPI device has its own chip-select line. To select the DS3105, pull its CS p in lo w.
Control Word. After CS is pulled low, the bus m aster transm its the control word during th e fir st 16 SCLK c ycles. In
MSB-first mode the control word has the form:
R/W A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 BURST
where A[1 3:0] is the reg iste r addres s, R/W is the d ata direc tion bit (1 = read , 0 = wri te), a nd BU RST is the burs t bit
(1 = burst access, 0 = single-byte access). In LSB-first mode the order of the 14 address bits is reversed. In the
discussion that follows, a control word with R/W = 1 is a read control word, while a control word with R/W = 0 is a
write control word.
Single-Byte Writes. See Figure 7-5. After CS goes low, the bus master transmits a write control word with
BURST = 0, followed by th e data byte to be wr itten. The bus m aster then term inates the t ransaction b y pull ing CS
high.
Single-Byte Reads. See Figure 7-5. After CS goes low, the bus master transmits a read control word with
BURST = 0. The DS3105 then responds with the requested data byte. The bus master then terminates the
transaction by pulling CS high.
Burst Writes. See Figure 7-5. After CS goes low, the bus master transmits a write control word with BURST = 1
followed by the first data byte to be written. The DS3105 receives the first data byte on SDI, writes it to the
specif ied register , increm ents its interna l address r egister , and prep ares to rec eive the next data b yte. If the m aster
continues t o trans mit, the D S31 05 c o nti nues to writ e t h e dat a r ece iv ed and inc rem ent its ad dr es s c ount er . Af t er the
address counter reaches 3FFFh it rolls over to address 0000h and continues to increment.
Burst Reads. See Figure 7-5. After CS goes low, the bus master transmits a read control word with BURST = 1.
The DS310 5 then respond s with the reques ted data byte on SDO , increm ents its address count er, and prefetc hes
the next data byte. If the bu s m as ter c ontinues t o d em and d ata, t he DS3105 continues t o pro v ide t he da ta o n SDO ,
increment its address counter, and prefetch the following byte. After the address counter reaches 3FFFh, it rolls
over to address 0000h and continues to increment.
Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by
pulling CS high. In response to ear ly term inations, the DS3 105 resets its SPI inte rface logic and waits for th e start
of the next transaction. If a write transaction is terminated prior to the SCLK edge that latches the LSB of a data
byte, the data byte is not written.
Design Option: Wiring SDI and SDO Together. Because communication between the bus master and the
DS3105 is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support
this option, the bus master must not drive the SDI/SDO line when the DS3105 is transmitting.
AC Timing. See Table 10-10 and Figure 10-4 for AC timing specifications for the SPI interface.
DS3105
48
Figure 7-4. SPI Clock Phase Options
CS
MSB
LSB
6
5
4
3
2
1
SDI/SDO
CLOCK EDGE USED FOR DATA CAPTURE (ALL MODES)
CPHA = 0
CPHA = 1
SCLK
SCLK
Figure 7-5. SPI Bus Transactions
R/WRegist er A ddress Burst Data B yt e
SDI
CS
SDO
Single-Byte Write
Single-Byte Read
R/WRegist er A ddress Burst
Data Byte
R/WRegist er A ddress Burst Data B yt e 1
Burst Write
SDI
CS
SDO
SDI
CS
SDO
0 (Write) 0 (single-byte)
1 (Read) 0 (single-byte)
0 (Write) 1 (burst)
Data Byte N
R/WRegist er A ddress Burst
Data Byte 1
Burst Read
SDI
CS
1 (Read) 1 (burst)
Data Byte N
DS3105
49
7.11
Reset Logi c
The device has three reset controls: the RST pin, the RST bit in MCR1, and the JTAG reset pin JTRST. The RST
pin asynchronously resets the entire device, except for the JTAG logic. When the RST pin is low all internal
registers are r ese t to the ir def ault va lues , includin g th os e f ields t hat latc h the ir de fault values f r om , or bas ed on, the
states of configuration input pins when the RST goes high. The
RST
pin must be asserted once after power-up
while the external oscillator is stabilizing.
The MCR1:RST bit resets the entire dev ice (except for the microproc essor interface, the JT AG logic, and the RST
bit itse lf ), but w he n R ST is ac tiv e, t he r eg ister f ields w ith pin-progr am med defaults do not latc h t he ir v al ues from, or
based on, th e c or res po nd in g i npu t p ins. Inst ea d, thes e f ields ar e res e t t o the def ault va lu es th at were latched when
the RST pin was last active.
Microsemi recommends holding RST low while the external oscillator starts up and stabilizes. An incorrect reset
condition could result if RST is released before the oscillator has started up completely.
Important: System software must wait at least 100µs after reset (RST pin or RST bit) is deasserted before
initializing the device as described in Section 7.13.
7.12
Power-Supply Considerations
Due to the DS3105’s dual-power-supply nature, some I/Os have parasitic diodes between a 1.8V supply and a
3.3V supp ly. W hen ramping po wer suppli es up or do wn, care m ust be tak en to avoid f orward-bias ing thes e diodes
because it could c ause latc hup. T wo methods are avai lable to pr event th is. The f irst m ethod is to p lace a Sc hottk y
diode ex ternal to t he de v ice b etween the 1.8V supply and t he 3. 3V suppl y to f orc e th e 3 .3 V s up ply to be within on e
parasitic diode dr op below the 1.8V supply (i.e., VDDIO > VDD - ~0.4V). The second method is to ramp up the 3.3V
supply first and then ramp up the 1.8V supply.
7.13
Initialization
After power-up or reset, a series of writes must be done to the DS3105 to tune it for optimal performance. This
series of writes is c alled th e init ia lizat io n s cr ipt. Each DS3105 d ie rev is ion has a di ff er ent initia li za tion s c ript. F or the
latest initialization scripts contact Microsemi timing products technical support.
Important: System software must wait at least 100µs after reset (RST pin or RST bit) is deasserted before
initializi ng the de vice .
DS3105
50
8.
Register Descriptions
The DS3 105 has an overa ll ad dress r ange f rom 000h t o 1FFh . Table 8-1 i n Section 8.4 shows the register map. In
each register, bit 7 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked “—“ are reserved
and must be written with 0. Writing other values to these registers may put the device in a factory test mode
resulting in undefined operation. Bits labeled “0” or “1” must be written with that value for proper operation. Register
fields with underlined names are read-only fields; writes to these fields have no effect. All other fields are read-
write. Register fields are described in detail in the register descriptions that follow Table 8-1.
Note: Systems must be able to access the entire address range from 0 to 01FFh. Proper device initialization
requires a sequence of writes to addresses in the range 0180-01FFh.
8.1
Status Bits
The device has two types of status bits. Rea l-time s tatus bits are read-on ly and indicate th e state of a s ignal at the
time it is read. Latched status bits are set when a signal changes state (low-to-high, high-to-low, or both, depending
on the bit) and c leared whe n written with a l ogic 1 va lue. W riting a 0 h as no ef fect. W hen set, som e latched s tatus
bits can cause an interrupt request on the INTREQ pin if enabled to do so b y corresponding interrupt ena ble bits.
ISR#.LOCK # are specia l-case latched st atus bits bec ause they cann ot create an interrupt reques t on the IN TREQ
pin and a “write 0” is needed to clear them.
8.2
Confi gur ati on Fields
Configuration fields are read-write. During reset, each configuration field reverts to the default value shown in the
register definition. Configuration register bits marked “—” are reserved and must be written with 0.
8.3
Multiregister Fields
Multiregister fields—such as FREQ[18:0] in registers FREQ1, FREQ2, and FREQ3—must be handled carefully to
ensure that the bytes of the field remain consistent. A write access to a multiregister field is accomplished by
writing all the registers of the field in any order, with no other accesses to the device in between. If the write
sequence is inter rupted b y anot her acc ess, non e of the bytes ar e written and the MSR4:MRAA latc hed st atu s bit is
set to indicate the write was aborted. A read access from a multiregister field is accomplished by reading the
registers of the field in any order, with no other accesses to the device in between. When one register of a
multiregister field is read, the other register(s) in the field are frozen until after they are all read. If the read
sequence is interrupted by another access, the registers of the multibyte field are unfrozen and the MSR4:MRAA
bit is set to indicate the read was aborted. For best results, interrupt servicing should be disabled in the
microprocessor before a multiregister access and then enabled again after the access is complete. The
multiregister fields are:
FIELD
REGISTERS
ADDRESSES
TYPE
FREQ[18:0]
FREQ1, FREQ2, FREQ3
0Ch, 0Dh, 07h
Read Only
MCLKFREQ[15:0] MCLK1, MCLK2 3Ch, 3Dh Read/Write
HARDLIM[9:0]
DLIMIT1, DLIMIT2
41h, 42h
Read/Write
DIVN[15:0]
DIVN1, DIVN2
46h, 47h
Read/Write
OFFSET[15:0]
OFFSET1, OFFSET2
70h, 71h
Read/Write
PHASE[15:0] PHASE1, PHASE2 77h, 78h Read Only
DS3105
51
8.4
Regist er D efi nit ions
Table 8-1. Register Map
Note: Regist er names are hyperl i nks to register def i niti ons. Underlined fields are read-only.
ADDR
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00h
ID1
ID[7:0]
01h
ID2
ID[15:8]
02h
REV
REV[7:0]
03h
TEST1
PALARM
D180
—
RA
0
8KPOL
0
0
05h
MSR1
—
—
IC6
IC5
IC4
IC3
—
—
06h
MSR2
STATE
SRFAIL
—
—
—
—
—
IC9
07h
FREQ3
—
—
—
—
—
FREQ[18:16]
08h
MSR3
FSMON
T4LOCK
—
T4NOIN
—
—
—
—
09h
OPSTATE
FSMON
T4LOCK
T0SOFT
T4SOFT
—
T0STATE[2:0]
0Ah
PTAB1
REF1[3:0]
SELREF[3:0]
0Bh
PTAB2
REF3[3:0]
REF2[3:0]
0Ch
FREQ1
FREQ[7:0]
0Dh
FREQ2
FREQ[15:8]
0Eh
VALSR1
—
—
IC6
IC5
IC4
IC3
—
—
0Fh
VALSR2
—
HORDY
—
—
—
—
—
IC9
11h
ISR2
—
—
ACT4
LOCK4
—
—
ACT3
LOCK3
12h
ISR3
—
—
ACT6
LOCK6
—
—
ACT5
LOCK5
14h
ISR5
—
—
—
—
—
—
ACT9
LOCK9
17h
MSR4
—
HORDY
MRAA
—
—
—
—
—
19h
IPR2
PRI4[3:0]
PRI3[3:0]
1Ah
IPR3
PRI6[3:0]
PRI5[3:0]
1Ch
IPR5
—
—
—
—
PRI9[3:0]
22h
ICR3
DIVN
LOCK8K
BUCKET[1:0]
FREQ[3:0]
23h
ICR4
DIVN
LOCK8K
BUCKET[1:0]
FREQ[3:0]
24h
ICR5
DIVN
LOCK8K
BUCKET[1:0]
FREQ[3:0]
25h
ICR6
DIVN
LOCK8K
BUCKET[1:0]
FREQ[3:0]
28h
ICR9
DIVN
LOCK8K
BUCKET[1:0]
FREQ[3:0]
30h
VALCR1
—
—
IC6
IC5
IC4
IC3
—
—
31h
VALCR2
—
—
—
—
—
—
—
IC9
32h
MCR1
RST
—
FREN
LOCKPIN
—
T0STATE[2:0]
33h
MCR2
—
—
—
—
T0FORCE[3:0]
34h
MCR3
AEFSEN
LKATO
XOEDGE
FRUNHO
EFSEN
SONSDH
—
REVERT
35h
MCR4
LKT4T0
—
—
—
T4FORCE[3:0]
36h
MCR5
RSV4
RSV3
RSV2
RSV1
—
—
IC6SF
—
38h
MCR6
DIG2AF
DIG2SS
DIG1SS
—
—
—
—
—
39h
MCR7
DIG2F[1:0]
DIG1F[1:0]
—
—
DIG2SRC
DIG1SRC
3Ah
MCR8
—
—
—
—
—
—
OC6SF[1:0]
3Bh
MCR9
AUTOBW
—
—
—
LIMINT
—
—
—
3Ch
MCLK1
MCLKFREQ[7:0]
3Dh
MCLK2
MCLKFREQ[15:8]
40h
HOCR3
AVG
—
—
—
—
—
—
—
41h
DLIMIT1
HARDLIM[7:0]
42h
DLIMIT2
—
—
—
—
—
—
HARDLIM[9:8]
DS3105
52
ADDR
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
43h
IER1
—
—
IC6
IC5
IC4
IC3
—
—
44h
IER2
STATE
SRFAIL
—
—
—
—
—
IC9
45h
IER3
FSMON
T4LOCK
—
—
—
—
—
—
46h
DIVN1
DIVN[7:0]
47h
DIVN2
DIVN[15:8]
48h
MCR10
—
SRFPIN
UFSW
EXTSW
PBOFRZ
PBOEN
—
—
4Bh
MCR11
—
—
—
T4T0
—
—
—
—
4Dh
DLIMIT3
FLLOL
SOFTLIM[6:0]
4Eh
IER4
—
HORDY
—
—
—
—
—
—
4Fh
OCR5
—
—
AOF6
—
—
AOF3
—
—
50h
LB0U
LB0U[7:0]
51h
LB0L
LB0L[7:0]
52h
LB0S
LB0S[7:0]
53h
LB0D
—
—
—
—
—
—
LB0D[1:0]
54h
LB1U
LB1U[7:0]
55h
LB1L
LB1L[7:0]
56h
LB1S
LB1S[7:0]
57h
LB1D
—
—
—
—
—
—
LB1D[1:0]
58h
LB2U
LB2U[7:0]
59h
LB2L
LB2L[7:0]
5Ah
LB2S
LB2S[7:0]
5Bh
LB2D
—
—
—
—
—
—
LB2D[1:0]
5Ch
LB3U
LB3U[7:0]
5Dh
LB3L
LB3L[7:0]
5Eh
LB3S
LB3S[7:0]
5Fh
LB3D
—
—
—
—
—
—
LB3D[1:0]
61h
OCR2
—
—
—
—
OFREQ3[3:0]
62h
OCR3
OFREQ6[3:0]
—
—
—
—
63h
OCR4
MFSEN
FSEN
—
—
—
—
—
—
64h
T4CR1
—
—
—
—
T4FREQ[3:0]
65h
T0CR1
T4MT0
T4APT0
T0FT4[2:0]
T0FREQ[2:0]
66h
T4BW
—
—
—
—
—
—
T4BW[1:0]
67h
T0LBW
—
—
—
RSV1
RSV2
T0LBW[2:0]
69h
T0ABW
—
—
—
RSV1
RSV2
T0ABW[2:0]
6Ah
T4CR2
—
PD2G8K[2:0]
—
DAMP[2:0]
6Bh
T0CR2
—
PD2G8K[2:0]
—
DAMP[2:0]
6Ch
T4CR3
PD2EN
—
—
—
—
PD2G[2:0]
6Dh
T0CR3
PD2EN
—
—
—
—
PD2G[2:0]
6Eh
GPCR
GPIO4D
GPIO3D
GPIO2D
GPIO1D
GPIO4O
GPIO3O
GPIO2O
GPIO1O
6Fh
GPSR
—
—
—
—
GPIO4
GPIO3
GPIO2
GPIO1
70h
OFFSET1
OFFSET[7:0]
71h
OFFSET2
OFFSET[15:8]
72h
PBOFF
—
—
PBOFF[5:0]
73h
PHLIM1
FLEN
NALOL
1
—
—
FINELIM[2:0]
74h
PHLIM2
CLEN
MCPDEN
USEMCPD
—
COARSELIM[3:0]
76h
PHMON
NW
—
—
—
—
77h
PHASE1
PHASE[7:0]
78h
PHASE2
PHASE[15:8]
79h
PHLKTO
PHLKTOM[1:0]
PHLKTO[5:0]
DS3105
53
ADDR
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
7Ah
FSCR1
—
SYNCSRC
8KINV
8KPUL
2KINV
2KPUL
7Bh
FSCR2
INDEP
OCN
PHASE3[1:0]
PHASE2[1:0]
PHASE1[1:0]
7Ch
FSCR3
RECAL
MONLIM[2:0]
SOURCE[3:0]
7Dh
INTCR
—
—
—
—
LOS
GPO
OD
POL
7Eh
PROT
PROT[7:0]
7Fh-
1FFh
reserved — — — — — — — —
Register Map Color Coding
Device Identification and Protection
Local Oscillator and Master Clock Configuration
Input Clock Configuration
Input Clock Monitoring
Input Clock Selection
DPLL Configuration
DPLL State
Output Clock Configuration
Frame/Multiframe-Sync Configuration
DS3105
54
Register Name:
ID1
Register Description:
Device Id entification Register, LSB
Register Address:
00h
Bit #
7
6
5
4
3
2
1
0
Name
ID[7:0]
Default
0
0
1
0
0
0
0
0
Bits 7 to 0: Device ID (ID[7:0]). ID[15:0] = 0C21h = 3105 decim al.
Register Name:
ID2
Register Description:
Device Id entification Register, MSB
Register Address:
01h
Bit #
7
6
5
4
3
2
1
0
Name
ID[15:8]
Default
0
0
0
0
1
1
0
0
Bits 7 to 0: Device ID (ID[15:8]). See the ID1 register description.
Register Name:
REV
Register Description:
Device Revision Register
Register Address:
02h
Bit #
7
6
5
4
3
2
1
0
Name
REV[7:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Device Revision (REV[7:0]). Contact the factory to interpret this value and determine the latest
revision.
DS3105
55
Register Name:
TEST1
Register Description:
Test Register 1 (Not Normally Used)
Register Address:
03h
Bit #
7
6
5
4
3
2
1
0
Name
PALARM
D180
—
RA
0
8KPOL
0
0
Default
0
0
0
1
0
1
0
0
Bit 7: Phase Alarm (PALARM). This real-time status bit indicates the state of the T0 DPLL phase-lock detector.
See Section 7.7.6. (Note: This is not the same as T0STATE = locked.)
0 = T0 DPLL phase-lock parameters are met (FLEN, CLEN, NALOL, FLLOL)
1 = T0 DPLL loss-of-phase lock
Bit 6: Di sable 180 (D1 80). W hen locking to a ne w reference, t he T0 DPLL first tries n earest edge loc king (±180°)
for the first two seconds. If unsuccessful, it tries full phase/frequency locking (±360°). Disabling the nearest edge
locking can reduce lock time by up to two seconds but may cause an unnecessary phase shift (up to 360°) when
the new reference is close in frequency/phase to the old reference. See Section 7.7.5.
0 = Normal operation: try nearest edge locking then phase/frequency locking
1 = Phase/frequency locking only
Bit 4: Resync Analog Dividers (RA). When this bit is set the analog output dividers are always synchronized to
ensure that low-frequency outputs are in sync with the higher frequency clock from the DPLL.
0 = Synchronized for the first two seconds after power-up
1 = Always synchronized
Bits 3, 1, and 0: Leave set to zero (test control).
Bit 2: 8kHz Edge Polarity (8KPOL). Specif ies the input clock edge to lock to on the select ed reference whe n it is
configured for LOCK8K mode. See Section 7.4.2.
0 = Falling edge
1 = Rising edge
DS3105
56
Register Name:
MSR1
Register Description:
Master Status Register 1
Register Address:
05h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
IC6
IC5
IC4
IC3
—
—
Default
1
0
1
1
1
1
1
1
Bits 5 to 2: Input Clock Status Change (IC[6:3]). Each of these latched status bits is set to 1 when the
corresponding VALSR1 s tatus bit changes state (set or cleared) . Each bit is cleared whe n writte n with a 1 and not
set again until the VALSR1 bit changes state again. W hen one of these latched status bits is set, it can cause an
interrupt request on the INTREQ pin if the corresponding interrupt enable bit is set in the IER1 register. See
Section 7.5 for input clock validation/invalidation criteria.
Register Name:
MSR2
Register Description:
Master Status Register 2
Register Address:
06h
Bit #
7
6
5
4
3
2
1
0
Name
STATE
SRFAIL
—
—
—
—
—
IC9
Default
0
0
0
0
0
0
0
1
Bit 7: T0 DPLL State Change (STAT E). This lat ched s tatus bit is s et to 1 wh en t he op er at ing sta te of the T 0 DP L L
changes. STATE is cleared when writt en with a 1 a nd not set again unt il the oper ating state changes ag ain. W hen
STATE is set it can cause an interrupt request on the INTREQ pin if the STATE interrupt enable bit is set in the
IER2 register. The current operating state can be read from the T0STATE field of the OPSTATE register. See
Section 7.7.1.
Bit 6: Selected Reference Failed (SRFAIL). This latc hed status bit is s et to 1 when the s elected referenc e to the
T0 DPLL f ails, ( i.e., n o cloc k edges in tw o UI). SRF AIL is c leared when written with a 1 . W hen SR FAIL is s et it c an
cause an int errupt requ est on the INTREQ pin if the SRF AIL interr upt enab le bit is set in the IER2 register. S RFAIL
is not set in free-run mode or holdover mode. See Section 7.5.3.
Bit 0: Input Clock Status Change (IC9). This la tched s tatus bit is set to 1 when the corres ponding VALSR status
bit changes s tate (set or cleared). Each bit is cleared when written with a 1 and not set aga in until the VALSR2 bit
changes state again. W hen this latched status bi t is set it can cause an inter rupt request on the INTREQ pin if the
corresponding interrupt en able bit is set i n the IER2 r egister. See Section 7.5 f or input cloc k validation /invalidation
criteria.
Register Name:
FREQ3
Register Description:
Frequency Register 3
Register Address:
07h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
FREQ[18:16]
Default
0
0
0
0
0
0
0
0
Bits 2 to 0: Current DPLL Frequency (FR EQ[18:16]). See the FREQ1 register description.
DS3105
57
Register Name:
MSR3
Register Description:
Master Status Register 3
Register Address:
08h
Bit #
7
6
5
4
3
2
1
0
Name
FSMON
T4LOCK
—
—
—
—
—
—
Default
0
1
0
1
0
0
0
0
Bit 7: Frame-Sync Input Monitor Alarm (FSMON). This latched status bit is set to 1 when OPSTATE:FSMON
transitions from 0 to 1. FSMON is cleared when written with a 1. When FSMON is set it can cause an interrupt
request on the INTREQ pin if the FSMON interrupt enable bit is set in the IER3 register. See Section 7.9.
Bit 6: T4 DPLL Lock Status Change (T4LOCK). This latched status bit is set to 1 when the lock s tatus of the T4
DPLL (OPSTATE:T4LOCK) changes (becomes locked when previously unlocked or becomes unlocked when
previously locked). T4LOCK is cleared when written with a 1 and not set again until the T4 lock status changes
again. When T4LO CK is s et it can c aus e an int err upt request o n the INT REQ pin if the T4LOCK interr u pt en a ble b it
is set in the IER3 re gis ter. See Sec t ion 7.7.6.
DS3105
58
Register Name:
OPSTATE
Register Description:
Operating State Register
Register Address:
09h
Bit #
7
6
5
4
3
2
1
0
Name
FSMON
T4LOCK
T0SOFT
T4SOFT
—
T0STATE[2:0]
Default
1
0
0
0
0
0
0
1
Bit 7: Frame-Sync Input Monitor Alarm (FSMON). This real-time status bit indicates the current status of the
frame-sync input monitor. See Section 7.9.6.
0 = No alarm
1 = Alarm
Bit 6: T4 DPLL Lock Status (T4LOCK). This real-ti me status bit indica tes the current phas e-lock status of the T4
DPLL. See Sections 7.5.3 and 7.7.6.
0 = Not locked to selected reference
1 = Locked to selected reference
Bit 5: T0 DPLL Frequency Soft Alarm (T0SOFT). This real-time status bit indicates whether the T0 DPLL is
tracking its reference within the soft alarm limits specified in the SOFT[6:0] field of the DLIMIT3 register. See
Section 7.7.6.
0 = No alarm; frequency is within the soft alarm limits
1 = Soft alarm; frequency is outside the soft alarm limits
Bit 4: T4 DPLL Frequency Soft Alarm (T4SOFT). This real-time status bit indicates whether the T4 DPLL is
tracking its reference within the soft alarm limits specified in the SOFT[6:0] field of the DLIMIT3 register. See
Section 7.7.6.
0 = No alarm; frequency is within the soft alarm limits
1 = Soft alarm; frequency is outside the soft alarm limits
Bits 2 to 0: T0 DPLL Operating State (T0ST ATE[2:0]). This r eal-time status f ield indicat es th e c ur rent s tat e of the
T0 DPLL state machine. Values not listed below correspond to invalid (unused) states. See Section 7.7.1.
001 = Free-run
010 = Holdover
100 = Locked
101 = Prelocked 2
110 = Prelocked
111 = Loss-of-lock
DS3105
59
Register Name:
PTAB1
Register Description:
Priority Table Register 1
Register Address:
0Ah
Bit #
7
6
5
4
3
2
1
0
Name
REF1[3:0]
SELREF[3:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 4: Highest Priority Valid Reference (REF1[3:0]). This real-tim e status field ind icates the highest p riorit y
valid input reference. When T4T0 = 0 in the MCR11 register, this field indicates the highest priority reference for
the T0 DPLL. When T4T0 = 1, it indicates the highest priority reference for the T4 DPLL. Note that an input
reference cannot be indicated in this f ield if it has been m arked invalid in the VALCR1 or VALCR2 reg ister. When
the T0 DPLL is in nonrevertive m ode (REVERT = 0 in the MCR3 register) this field may not have the same value
as the SELREF[3:0] field. See Section 7.6.2.
0000 = No valid input reference available
0001–0010 = {unused values}
0011 = Input IC3
0100 = Input IC4
0101 = Input IC5
0110 = Input IC6
0111–1000 {unused values}
1001 = Input IC9
1010–1111 = {unused values}
Bits 3 to 0: Selected Reference (SELREF[3:0]). This real-time status field indicates the current selected
referenc e. When T4T0 = 0 in the MCR11 register, th is f ield in dic at es the sel ec ted refer ence for the T 0 DPLL. When
T4T0 = 1, it indicates the selected reference for the T4 DPLL. Not e that an input clock cannot be indicated in this
field if it has been m arked invalid in th e VALCR1 or VALCR2 register. W hen the T0 D PLL is in nonrevertive mode
(REVERT = 0 in the MCR3 register) this field may not have the same value as the REF1[3:0] field. See Section
7.6.2.
0000 = No source currently selected
0001–0010 = {unused values}
0011 = Input IC3
0100 = Input IC4
0101 = Input IC5
0110 = Input IC6
0111–1000 {unused values}
1001 = Input IC9
1010–1111 = {unused values}
DS3105
60
Register Name:
PTAB2
Register Description:
Priority Table Register 2
Register Address:
0Bh
Bit #
7
6
5
4
3
2
1
0
Name
REF3[3:0]
REF2[3:0]
Default
0
0
0
0
0
0
0
0
Bits 7 to 4: Third Highest Priority Valid Reference (REF3[3:0]). This real-time status field indicates the third
highest priority validated input reference. When T4T0 = 0 in the MCR11 register, this field indicates the third
highest prior it y reference f or the T 0 DPLL. W hen T 4T0 = 1, it indicates the third hi ghest ref erenc e for the T 4 DPLL.
Note that an input reference cannot be indicated in this field if it has been marked invalid in the VALCR1 or
VALCR2 register. See Section 7.6.2.
0000 = No valid input reference available
0001–0010 = {unused values}
0011 = Input IC3
0100 = Input IC4
0101 = Input IC5
0110 = Input IC6
0111–1000 = {unused values}
1001 = Input IC9
1010–1111 = {unused values}
Bits 3 to 0: Second Highest Priority Valid Reference (REF2[3:0]). This real-time status field indicates the
second highest priority validated input reference. When T4T0 = 0 in the MCR11 register, this field indicates the
second highes t pr i ority referenc e for the T0 DPLL. When T4T0 = 1, it indica tes th e s ec ond hig hest r ef er ence for the
T4 DPLL. Note t hat an inpu t ref erence c annot be in dic ated in this f ield if it has be en m ark ed invali d in t he VALCR1
or VALCR2 register. See Section 7.6.2.
0000 = No valid input reference available
0001–0010 = {unused values}
0011 = Input IC3
0100 = Input IC4
0101 = Input IC5
0110 = Input IC6
0111–1000 = {unused values}
1001 = Input IC9
1010–1111 = {unused values}
DS3105
61
Register Name:
FREQ1
Register Description:
Frequency Register 1
Register Address:
0Ch
Bit #
7
6
5
4
3
2
1
0
Name
FREQ[7:0]
Default
0
0
0
0
0
0
0
0
Note: The FREQ1, FREQ2, and FREQ3 regi st ers must be read consecutiv ely. See Secti on 8.3.
Bits 7 to 0: Current DPLL Frequency (FREQ[7:0]). The full 19-bit FREQ[18:0] field spans this register, FREQ2,
and FREQ3. FREQ is a two’s-complement signed integer that expresses the current frequency as an offset with
respect to the master clock frequency (see Section 7.3). When T4T0 = 0 in the MCR11 register, FREQ indicates
the current f r equency offs et of the T0 D PLL. When T4T0 = 1, FREQ indic ates the c urr ent f r equenc y off s et of the T 4
path. Because the value in this register field is derived from the DPLL integral path, it can be considered an
average frequenc y with a rate of c hange in versel y proportiona l to the DPLL ban dwidt h. If LIMINT = 1 in the MCR9
register, the value of FREQ freezes when the DPLL reaches its minimum or maximum frequency. The frequency
offset in ppm is equal to FREQ[18:0] × 0.0003068. See Section 7.7.1.6.
Applicatio n N o te: Fr e que nc y meas ur ements ar e rel ati v e, i. e., t hey meas ure the fre quency of the select ed ref erence
with resp ect to the local os cillator. As s uch, when a freque ncy differ ence exists, it is dif ficult to dist inguish whether
the selected reference is off frequency or the local oscillator is off frequency. In systems with timing card
redundancy, the us e of two tim ing c ards, m as ter and s lave, ca n addr ess th is dif ficult y. Bot h m aster and s lave ha ve
separate local oscillators, and each measures the selected reference. These two measurements provide the
necessary information to distinguish which reference is off frequency, if we make the simple assumption that at
most one reference has a significant frequency deviation at any given time (i.e., a single point of failure). If both
master and slave indicate a significant frequency offset, then the selected reference must be off frequency. If the
master indicates a f requenc y off set but th e slave does not, the n the m as ter’s loc al osc illator m ust be of f frequenc y.
Likewise, if the slave indicates a frequency offset but the master does not, the slave’s local oscillator must be off
frequency.
Register Name:
FREQ2
Register Description:
Frequency Register 2
Register Address:
0Dh
Bit #
7
6
5
4
3
2
1
0
Name
FREQ[15:8]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Current DPLL Frequency (FR EQ[15:8]). See the FREQ1 register description.
DS3105
62
Register Name:
VALSR1
Register Description:
Input Clock Valid Status Register 1
Register Address:
0Eh
Bit #
7
6
5
4
3
2
1
0
Name
—
—
IC6
IC5
IC4
IC3
—
—
Default
0
0
0
0
0
0
0
0
Bits 5 to 2: Input Clock Valid Status (IC[6:3]). Each of these real-time status bits is set to 1 when the
corresponding input clock is valid. An input is valid if it has no active alarms (ACT = 0, LOCK = 0 in the
corresponding ISR register). See also the MSR1 register and Section 7.5.
0 = Invalid
1 = Valid
Register Name:
VALSR2
Register Description:
Input Clock Valid St atu s Regist er 2
Register Address:
0Fh
Bit #
7
6
5
4
3
2
1
0
Name
—
HORDY
—
—
—
—
—
IC9
Default
0
0
0
0
0
0
0
0
Bit 6: Holdover Frequency Ready (HORDY). This real-time status bit is set to 1 when the T0 DPLL has a
holdover value that has been averaged over the one-second holdover averaging period. See the related latched
status bit in MSR4 and Section 7.7.1.6.
Bit 0: Input Clock Valid Status (IC9). This bit has the same behavior as the bits in VALSR1 but for the IC9 clock.
DS3105
63
Register Name:
ISR2
Register Description:
Input Status Register 2
Register Address:
11h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
ACT4
LOCK4
—
—
ACT3
LOCK3
Default
0
0
1
0
0
0
1
0
Bit 5: Activity Alarm for Input Clock 4 (ACT4). This real-time status bit is set to 1 when the leaky bucket
accum ulator for IC4 re aches the alarm thr eshold sp ecif ied in the LBxU regis ter (where x in LBx U is spec if ied in t he
BUCKET field of ICR4). An activity alarm clears the IC4 status bit in the VALSR1 register, invalidating the IC4
clock. See Section 7.5.2.
Bit 4: Phase-Lock Alarm for Input Clock 4 (LOCK4). This status bit is set to 1 if IC4 is the selected reference
and the T0 DPLL cannot phase lock to IC4 within the duration specified in the PHLKTO register (default = 100
seconds). A phase-lock alarm clears the IC4 status bit in VALSR1, invalidating the IC4 clock. If LKATO = 1 in
MCR3, LOCK4 is autom atically cleared after a timeout period of 128 seconds. LOCK4 is a read/write bit. System
software can clear LOCK4 b y writing 0 to it, but writi ng 1 is ignored. Se e Sectio n 7.7.1.
Bit 1: Activity Alarm for Input Clock 3 (ACT3). This bit has the same behavior as the ACT4 bit but for the IC3
input clock.
Bit 0: Phase-Lock Alarm for Input Clock 3 (LOCK3). This bit has the same behavior as the LOC K4 bit b ut for the
IC3 input clock.
Register Name:
ISR3
Register Description:
Input Status Register 3
Register Address:
12h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
ACT6
LOCK6
—
—
ACT5
LOCK5
Default
0
0
1
0
0
0
1
0
This register has the same behavior as the ISR2 register but for input clocks IC5 and IC6.
Register Name:
ISR5
Register Description:
Input Status Register 5
Register Address:
14h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
ACT9
LOCK9
Default
0
0
0
0
0
0
1
0
This register has the same behavior as the ISR2 register but for input clock IC9.
DS3105
64
Register Name:
MSR4
Register Description:
Master Status Register 4
Register Address:
17h
Bit #
7
6
5
4
3
2
1
0
Name
—
HORDY
MRAA
—
—
—
—
—
Default
0
0
0
0
0
0
0
0
Bit 6: Holdover F requency Ready (HORDY). T his l atched s tatus bit is s et to 1 w hen the T 0 D PLL has a hol dover
value that has been averaged over the one-second holdover averaging period. HORDY is cleared when written
with a 1. W hen HORDY is set it can caus e an interrup t request on t he INTREQ pin if the HO RDY interru pt enable
bit is set in the IER4 register. See Section 7.7.1.6.
Bit 5: Multiregister Ac cess Aborted (MRAA). T his latched s tatus bit is set to 1 when a m ultib yte access ( read or
write) is int errupted b y an other access to the device. MRAA is c leared when wri tten with a 1. MRA A cannot caus e
an interrupt to occur. See Section 8.3.
DS3105
65
Register Name:
IPR2
Register Description:
Input Priority Register 2
Register Address:
19h
Bit #
7
6
5
4
3
2
1
0
Name
PRI4[3:0]
PRI3[3:0]
Default
0
0
1
1
0
0
1
0
Bits 7 to 4: Priority for Input Clock 4 (PRI4[3:0]). Priority 0001 is highest; priority 1111 is lowest. When
MCR11:T 4T0 = 0, PRI4 configures IC4’s priority for the T 0 DPLL. See Section 7.6.1. W hen PRI4 is written with a
value > 0, IPR3:PRI6 is forced to 0 (disabled).
0000 = IC4 unavailable for selection
0001–1111= IC4 relative priority
Bits 3 to 0: Priority for Input Clock 3 (PRI3[3:0]). Priority 0001 is highest; priority 1111 is lowest. When
MCR11:T 4T0 = 0, PRI3 configures IC3’s priority for the T0 DPLL. See Section 7.6.1. When PRI3 is written with a
value > 0, IPR3:PRI5 is forced to 0 (disabled).
0000 = IC3 unavailable for selection
0001–1111= IC3 relative priority
Register Name:
IPR3
Register Description:
Input Priority Register 3
Register Address:
1Ah
Bit #
7
6
5
4
3
2
1
0
Name
PRI6[3:0]
PRI5[3:0]
Default
0
0
0
0
0
0
0
0
This register has the same behavior as IPR2 but for input clocks IC5 and IC6.
Register Name:
IPR5
Register Description:
Input Priority Register 5
Register Address:
1Ch
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
PRI9[3:0]
Default
0
0
0
0
0
1
0
0
This register has the same behavior as IPR2 but for input clock IC9.
DS3105
66
Register Name:
ICR3, ICR4, ICR5, ICR6, ICR9
Register Description:
Input Configuration Register 3, 4, 5, 6, 9
Register Address:
22h, 23h, 24h, 25h, 28h
Bit #
7
6
5
4
3
2
1
0
Name
DIVN
LOCK8K
BUCKET[1:0]
FREQ[3:0]
Default
0
0
0
0
see below
Note: These registers are identical in function. ICRx is the control regist er for input clock ICx.
Bit 7: DIVN Mode (DIVN). When DIVN is set to 1 and LOCK8K = 0, the input clock is divided down by a
programm able pred ivider. The resultin g output c lock is then passed t o the DPLL. All input c lock s for which DIVN =
1 are divided b y the fac tor spec ified in DIVN1 and DIVN2. When DIVN = 1 and LOCK8 K = 0 in an ICR regis ter , the
FREQ field of that register must be set to the input frequency divided by the divide factor. When DIVN = 1 and
LOCK8K = 1 in an ICR register, the FREQ field of that register is decoded as the alternate frequencies. See
Sections 7.4.2.2 and 7.4.2.4.
0 = Disabled
1 = Enabled
Bit 6: LOCK8K Mode (LOCK8K). When LOCK8K is set to 1 and DIVN = 0, the input clock is divided down by a
preset predivider. The resulting output clock, which is always 8kHz, is then passed to the DPLL. LOCK8K is
ignored whe n DI VN = 0 an d FR EQ[ 3:0] = 1 001 ( 2kHz) or 1 010 ( 4kHz). When DIVN = 1 and LO C K8 K = 1 in an ICR
register, the FREQ field of that register is decoded as the alternate frequencies. See Sections 7.4.2.2 and 7.4.2.3
0 = Disabled
1 = Enabled
Bits 5 and 4: Leaky Bucket Configuration (BUCKET[1:0]). Each input cloc k has leaky buck et accumulator logic
in its activ it y monitor . T he LBxy registers at addres s es 50h to 5F h s pec ify four differ ent l eaky buck et c onf iguratio ns .
Any of the four configurations can be specified for the input clock. See Section 7.5.2.
00 = Leaky bucket configuration 0
01 = Leaky bucket configuration 1
10 = Leaky bucket configuration 2
11 = Leaky bucket configuration 3
Bits 3 to 0: Input Clock Frequency (FREQ[3:0]). W hen DIVN = 0 an d LOCK8K = 0 ( standard direc t-lock m ode),
this field specifies the input clock’s nominal frequency for direct-lock operation. When DIVN = 0 and LOCK8K = 1
(LOCK8K mode) this field specifies the input clock’s nominal frequency for LOCK8K operation. When DIVN = 1 and
LOCK8K = 0 (DIV N m ode), this field spec ifies the fr equency after the DI VN divider (i.e., input fr equenc y divided b y
DIVN + 1) . When DIVN = 1 and LOC K8K = 1 ( a lternate direct-lock f requenc ies) , t his f ield s pecifies the i nput c lock’s
nominal frequency for direct-lock operation.
DIVN = 0 or LOCK8K = 0: (Standard direct-lock mode, LOCK8K mode, or DIVN mode)
0000 = 8kHz
0001 = 1544kHz or 2048kHz (as determined by SONSDH bit in the MCR3 register)
0010 = 6.48MHz
0011 = 19.44MHz
0100 = 25.92MHz
0101 = 38.88MHz
0110 = 51.84MHz
0111 = 77.76MHz
1000 = 155.52MHz (only valid for LVDS inputs)
1001 = 2kHz
1010 = 4kHz
1011 = 6312kHz
1100 = 5MHz
1101 = 31.25 MHz (not a multiple of 8 kHz and therefore not valid for LOCK8K mode)
1110–1111 = undefined
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DIVN = 1 and LOCK8K = 1: (Alternate direct-lock frequency decode)
0000 = 10MHz (internally divided down to 5MHz)
0001 = 25MHz (internally divided down to 5MHz)
0010 = 62.5MHz (internally down to 31.25MHz)
0011 = 125MHz (internally down to 31.25MHz)
0100 = 156.25MHz (differential inputs only; internally divided down to 31.25MHz)
0101–1111 = undefined
FREQ[3:0] D efault Values:
ICR3–ICR4: 0000b
ICR5–ICR7, ICR9: 0011b
Register Name:
VALCR1
Register Description:
Input Clock Valid Control Register 1
Register Address:
30h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
IC6
IC5
IC4
IC3
—
—
Default
1
0
1
1
1
1
0
0
Bits 5 to 2: Input Clock Valid Control (IC[6:3]). These control bits can be used to force input clocks to be
considered invalid. If a clock is invalidated by one of these control bits it will not appear in the priority table in the
PTAB1 and PTAB2 registers, even if the clock is otherwise valid. These bits are useful when system software
needs to f or c e cloc ks to be in valid in res po ns e to O AM c om m ands . Not e tha t s ett i ng a V ALCR b it lo w has n o ef fect
on the correspon di ng bit in the VALSR registers. See Sections 7.6.2.
0 = Force invalid
1 = Do not force invalid; determine validity normally
Register Name:
VALCR2
Register Description:
Input Clock Valid Control Register 2
Register Address:
31h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
IC9
Default
0
0
0
0
0
0
0
1
Bit 0: Input Clock Valid Control (IC9). This bit has th e sam e behavior as the bit s in VALCR1 but for the IC 9 inp ut
clock.
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68
Register Name:
MCR1
Register Description:
Master Configuration Register 1
Register Address:
32h
Bit #
7
6
5
4
3
2
1
0
Name
RST
—
FREN
LOCKPIN
—
T0STATE[2:0]
Default
0
0
1
0
0
0
0
0
Bit 7: Dev ice Reset (RST). When this b it is h igh the e ntir e de vice is held in r es et, and al l re gis ter fields, ex c ept th e
RST bit itse lf , ar e r eset t o t heir def au lt s tat es . When RST is ac ti ve, the regis ter fie lds w ith p in-programmed def aults
do not latc h their values f rom the c orresponding input pins . Instea d these f ields are r eset to th e default values tha t
were latche d from the pins when the RST pin was last activ e. See Sect ion 7.11.
0 = Normal operation
1 = Reset
Bit 5: Frequency Range Detect Enable (FREN). When this bit is high the frequency of each input clock is
measured and used to quickly declare the input inactive.
0 = Frequency range detect disabled.
1 = Frequency range detect enabled.
Bit 4: T0 DPLL LOCK Pin Enable (LOCKPIN). When this bit is high the LOCK pin indicates when the T0 DPLL
state machine is in the LOCK state (OPSTATE.T0STATE = 100).
0 = LOCK pin is not driven.
1 = LOCK pin is driven high when the T0 DPLL is in the lock state.
Bits 2 to 0: T0 DPLL State Control (T0STAT E[2:0]). This f ield a llows the T0 D PLL state machine to be fo rced to
a specified state. The state machine remains in the forced state, and, therefore, cannot react to alarms and other
events as long as T0STATE is not equal to 000. See Section 7.7.1.
000 = Automatic (normal state machine operation)
001 = Free-run
010 = Holdover
011 = {unused valu e}
100 = Locked
101 = Prelocked 2
110 = Prelocked
111 = Loss-of-lock
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Register Name:
MCR2
Register Description:
Master Configuration Register 2
Register Address:
33h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
T0FORCE[3:0]
Default
0
0
0
0
1
1
1
1
Bits 3 to 0: T0 DPLL Force Selected Reference (T0FORCE[3:0]). This field provides a way to force a specified
input clock to be the selected reference for the T0 DPLL. Internally this is accomplished by forcing the clock to have
the highest priority (as specified in PTAB1:REF1). In revertive mode (MCR3:REVERT = 1) the forced clock
automatically becom es the selected reference (as specified in PTAB1:SELREF) as well. I n nonrevertive mode th e
forced clock only becomes the selected reference when the existing selected reference is invalidated or made
unavailable for selection.
When a reference is forced, the activity monitor for that input and the T0 DPLL’s loss-of-lock timeout logic all
continue to operate and affect the relevant ISR, VALSR, and MSR register bits. However, when the reference is
declared in valid the T 0 DPLL is no t allowed t o switch to another input clock . The T0 D PLL continues to respond to
the fast activity monitor, transitioning to mini-holdover in response to short-term events and to full holdover in
response to longer events. See Section 7.6.3.
0000 = Automatic source selection (normal operation)
0001 = {unused value, undefined}
0010 = {unused value, undefined}
0011 = Force to IC3
0100 = Force to IC4
0101 = Force to IC5
0110 = Force to IC6
0111 = {unused value}
1000 = {unused value, undefined}
1001 = Force to IC9
1010–1110 = {unused values}
1111 = Automatic source selection (normal operation)
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70
Register Name:
MCR3
Register Description:
Master Configuration Register 3
Register Address:
34h
Bit #
7
6
5
4
3
2
1
0
Name
AEFSEN
LKATO
XOEDGE
FRUNHO
EFSEN
SONSDH
—
REVERT
Default
1
1
0
0
1
see below
1
0
Bit 7: Auto External Frame-Sync Enable (AEFSEN). T his bit has t wo functi ons depe nding on the ex tern al fram e-
sync mode. See Section 7.9.1.
SYNC1 Modes:
0 = SYNC1 Manual mode: External frame sync is manually enabled on the SYNC1 pin when EF S EN = 1.
1 =SYNC1 Auto mode: External frame sync is automatically enabled on the SYNC1 pin when EFSEN = 1 and
the T0 DPLL is locked to the input clock specified in FSCR3:SOURCE.
SYNC123 Mode:
0 = EFSEN is not automatically cleared when the T0 DPLL’s selected reference changes.
1 = EFSEN is automatically cleared when the T0 DPLL’s selected reference changes.
(EFSEN must be set again by system software to enable it again.)
Bit 6: Phase-Lock Alarm Timeout (LKATO). This bit controls how phase alarms on input clocks can be
terminated. Phase alarms are indicated by the LOCK bits in ISR registers.
0 = Phase alarms on input clocks can only be cancelled by software.
1 = Phase alarms are automatically cancelled after a timeout period of 128 seconds.
Bit 5: Local Oscillator Edge (XOEDGE). This bit specifies the significant clock edge of the local oscillator clock
signal on the REFCLK input pin. The faster edge should be selected for best jitter performance. See Section 7.3.
0 = Rising edge
1 = Falling edge
Bit 4: Free-Run Holdover (FRUNHO). W hen this b it is set to 1 the T 0 DPLL holdover fr equenc y is set to 0 ppm so
the output frequency accuracy is set by the external oscillator accuracy. This effects both mini-holdover and the
holdover state.
0 = Digital holdover
1 = Free-run holdover, 0ppm
Bit 3: External F rame-Sync Enable (EFSEN). W hen this bit is set to 1 the T0 DPLL looks f or a fram e-sync pulse
on the SYNCn pin(s). In SYNC123 mode, if AEFSEN = 1 EFSEN is automatically cleared when the T0 DPLL’s
selected reference changes. See Section 7.9.1.
0 = Disable external frame sync; ignore SYNCn pin(s)
1 = Enable external frame sync on SYNCn pin(s)
Bit 2: SONET or SDH Frequencies (SONSDH). This bit s pec if ies the c lock rate for input cloc ks with FREQ = 0001
in the ICR registers (20h to 28h). During reset the default value of this bit is latched from the SONSDH pin. See
Section 7.4.2.
0 = 2048kHz
1 = 1544kHz
Bit 0: Revertive Mode (REVERT). This bit c onf igures the T0 DPLL for re vert iv e o r nonr e vert iv e o per at ion . (The T 4
DPLL is always revertive). In revertive mode, if an input clock with a higher priority than the selected reference
becom es valid, the hig her p riority reference im mediatel y becomes the selec ted ref erenc e. In no nr ever ti ve mode the
higher prior ity ref erence d oes not imm ediatel y becom e the selecte d ref erence but does becom e the hig hest p riorit y
reference in the priority table (REF1 field in the PTAB1 register). See Section 7.6.2.
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71
Register Name:
MCR4
Register Description:
Master Configuration Register 4
Register Address:
35h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
T4FORCE[3:0]
Default
1
0
0
0
0
0
0
0
Bits 3 to 0: T4 DPL Force Selected Reference (T4FORCE[3:0]). This field provides a way to force a specified
input clock to be the selected reference for the T4 DPLL. Internally this is accomplished by forcing the clock to have
the highest priority (as specified in PTAB1:REF1). Since the T4 DPLL always operates in revertive mode, the
forced clock automatically becomes the selected reference (as specified in PTAB1:SELREF) as well.
When a reference is forced, the activity monitor for that input continues to operate and affect the relevant ISR,
VALSR, and MSR regist er bits . See Sect ion 7.6.3.
0000 = Automatic source selection (normal operation)
0001 = {unused value, undefined}
0010 = {unused value, undefined}
0011 = Force to IC3
0100 = Force to IC4
0101 = Force to IC5
0110 = Force to IC6
0111 = {unused value, undefined}
1000 = {unused value, undefined}
1001 = Force to IC9
1010–1110 = {unused value, undefined}
1111 = Automatic source selection (normal operation)
Register Name:
MCR5
Register Description:
Master Configuration Register 5
Register Address:
36h
Bit #
7
6
5
4
3
2
1
0
Name
RSV4
RSV3
RSV2
RSV1
—
—
IC6SF
—
Default
0
0
0
0
0
0
0
0
Bits 7 to 4: Reserved Bit 4 to 1 (RSV[4:1]). These bi ts are r eser ved f or future use, and c an b e writt en to a nd r ead
back.
Bit 1: Input Clock 6 Signal Format (IC6SF). For backward compatibilit y this bit can be written to and read back,
but it does not affect the IC6POS/NEG inputs pins. See Section 7.4.1.
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72
Register Name:
MCR6
Register Description:
Master Configuration Register 6
Register Address:
38h
Bit #
7
6
5
4
3
2
1
0
Name
DIG2AF
DIG2SS
DIG1SS
—
—
—
—
—
Default
0
see below
see below
1
1
1
1
1
Bit 7: Digital Alternate Frequency (DIG2A F ). Selects alternative frequencies.
0 = Digital2 N x E1 or N x DS1 frequency specified by DIG2SS and MCR7:DIG2F.
1 = Digital2 6.312MHz, 10MHz, or N x 19.44MHz frequency specified by DIG2SS and MCR7:DIG2F.
Bit 6: Digital2 SONET o r SDH Frequ enci e s (DI G2S S). T his bit spec if ies whether the cloc k rates gener ate d b y the
Digital2 clock synthesizer are multiples of 1.544MHz (SONET compatible) or multiples of 2.048MHz (SDH
compatible) or alternate frequencies. The specific multiple is set in the DIG2F field of the MCR7 register. When
RST = 0 the default value of this bit is latched from the SONSDH pin.
DIG2AF = 0:
0 = Multiples of 2048kHz
1 = Multiples of 1544kHz
DIG2AF = 1:
6.312MHz, 10MHz, or N x 19.44MHz
Bit 5: Digital1 SONET or SDH Frequencies (DIG1SS). This bit specifies whet h er the c lock rates generate d b y the
Digital1 clock synthesizer are multiples of 1544kHz (SONET compatible) or multiples of 2048kHz (SDH
compatib le). The sp ec if ic m ult ipl e is s et in the D IG1F field of the MCR7 register. When RST = 0 the default v alue of
this bit is latched from the SONSDH pin.
0 = Multiples of 2048kHz
1 = Multiples of 1544kHz
Register Name:
MCR7
Register Description:
Master Configuration Register 7
Register Address:
39h
Bit #
7
6
5
4
3
2
1
0
Name
DIG2F[1:0]
DIG1F[1:0]
—
—
—
—
Default
0
0
0
0
1
0
0
0
Bits 7 and 6: Digital2 Frequency (DIG2F[1:0]). This field, MCR6:DIG2SS, and MCR6:DIG2AF configure the
frequency of the Digital2 clock synthesizer.
DIG2AF = 0
DIG2AF = 1
DIG2SS = 1
DIG2SS = 0
DIG2SS = 1
DIG2SS = 0
00 = 1544kHz
00 = 2048kHz
00 = 19.44MHz
00 = 6.312MHz
01 = 3088kHz
01 = 4096kHz
01 = 38.88MHz
01 = undefined
10 = 6176kHz
10 = 8192kHz
10 = undefined
10 = 10MHz
11 = 12,352kHz
11 = 16,384kHz
11 = undefined
11 = undefined
Bits 5 and 4: Digital1 Frequency (DIG1F[1:0]). This field and MCR6:DIG1SS configure the frequency of the
Digital1 clock synthesizer.
DIG1SS = 1
DIG1SS = 0
00 = 1544kHz
00 = 2048kHz
01 = 3088kHz
01 = 4096kHz
10 = 6176kHz
10 = 8192kHz
11 = 12,352kHz
11 = 16,384kHz
DS3105
73
Register Name:
MCR8
Register Description:
Master Configuration Register 8
Register Address:
3Ah
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
OC6SF[1:0]
Default
0
0
0
0
0
0
1
0
For Rev A2 devices, in LVPECL mode the differential output voltage will be higher than the MAX VODPECL spec in
Table 10-6 unless an adjustment register is written with the proper value. If differential voltages larger than
VODPECL,MAX are unacceptable, the following procedures must be followed when writing the OC6SF fields in this
register. If differential voltages larger than VODPECL,MAX are acceptable, only the OC6SF field must be written.
Procedure to configure OC6 for LVPECL mode:
1) Set the OC6SF[1:0] field to 01b.
2) Write 01h to address 01FFh.
3) Write 55h to the adjustment register at address 01D8h.
4) Write 00h to address 01FFh.
Procedure to configure OC6 for LVDS mode:
1) Set the OC6SF[1:0] field to 10b.
2) Write 01h to address 01FFh.
3) Write 00h to the adjustment register at address 01D8h.
4) Write 00h to address 01FFh.
Bits 1 a n d 0: Output Clock 6 Signa l Format (OC6SF[1:0]). See Section 7.8.1.
00 = Output disabled (powered down)
01 = 3V LVPECL level compatible
10 = 3V LVDS compatible (default)
11 = 3V LVDS compatible
Register Name:
MCR9
Register Description:
Master Configuration Register 9
Register Address:
3Bh
Bit #
7
6
5
4
3
2
1
0
Name
AUTOBW
—
—
—
LIMINT
—
—
—
Default
1
1
1
1
1
0
1
1
Bit 7: Automa tic Bandwidth Selection (AUTOBW). See Section 7.7.3.
0 = Always selects locked bandwidth from the T0LBW register.
1 = Automatically selects either locked bandwidth (T0LBW register) or acquisition bandwidth (T0ABW
register) as appropriate.
Bit 3: Limit Integral Path (LIMINT). When this bit is set to 1, the T0 DPLL’s integral path is limited (i.e., frozen)
when the DPLL reaches m inim um or maximum frequenc y, as set by the HARDLIM field in DLIMIT1 and DLIMIT2.
When the integral path is frozen, the current DPLL frequency in registers FREQ1, FREQ2, and FREQ3 is also
frozen. Setting LIMINT = 1 minimizes overshoot when the DPLL is pulling in. See Section 7.7.3.
0 = Do not freeze integral path at min/max frequency.
1 = Freeze integral path at min/max frequency.
DS3105
74
Register Name:
MCLK1
Register Description:
Master Clock Frequency Adjustment Register 1
Register Address:
3Ch
Bit #
7
6
5
4
3
2
1
0
Name
MCLKFREQ[7:0]
Default
1
0
0
1
1
0
0
1
Note: The MCLK1 and MCLK2 registers must be read consecutiv ely and written c onsecutively . See Secti on 8.3.
Bits 7 to 0: Master Clock Frequency Adjustment (MCLKFREQ[7:0]). The full 16-bit MCLKFREQ[15:0] field
spans this register and MCLK2. MCLKFREQ is an unsigned integer that adjusts the frequency of the internal
204.8MHz master clock with respect to the frequency of the local oscillator clock on the REFCLK pin by up to
+514ppm and -771ppm. The master clock adjustment has the effect of speeding up the master clock with a positive
adjustment and slowing it down with a negative adjustment. For example, if the oscillator connected to REFCLK
has an offset of +1ppm, the adjustment should be -1ppm to correct the offset.
The formulas below translate adjustments to register values and vice versa. The default register value of 39,321
corresponds to 0ppm. See Section 7.3.
MCLKFREQ[15:0] = adjustment_in_ppm / 0.0196229 + 39,321
adjustment_in_ppm = (MCLKFREQ[15:0] – 39,321) × 0.0196229
Register Name:
MCLK2
Register Description:
Master Clock Frequency Adjustment Register 2
Register Address:
3Dh
Bit #
7
6
5
4
3
2
1
0
Name
MLCKFREQ[15:8]
Default
1
0
0
1
1
0
0
1
Bits 7 to 0: Master Clock Freque n cy Adjustment (MCLKFREQ[15:8]). See the MCLK1 register description.
Register Name:
HOCR3
Register Description:
Holdover Configuration Register 3
Register Address:
40h
Bit #
7
6
5
4
3
2
1
0
Name
AVG
—
—
—
—
—
—
—
Default
1
0
0
0
1
0
0
0
Note: See Section 8.3 for important information about writing and reading this register.
Bit 7: Av eraging (AVG). When this bit is s et to 1 the T0 D PLL uses the a verage d fr equenc y value durin g hold over
mode. When FRUNHO = 1 in the MCR3 register, this bit is ignored. See Section 7.7.1.6.
0 = Not averaged frequency; holdover frequency is either free-run (FRUNHO = 1) or instantaneously
frozen.
1 = Averaged frequency over the last one second while locked to the input.
DS3105
75
DS3105
76
Register Name:
DLIMIT1
Register Description:
DPLL Frequency Limit Register 1
Register Address:
41h
Bit #
7
6
5
4
3
2
1
0
Name
HARDLIM[7:0]
Default
0
1
1
1
0
1
1
0
Note: The DLIMIT1 and DLIMIT2 registers must be read consecutively and written consecutively. See Section 8.3.
Bits 7 to 0: DPLL Hard Frequency Limit (HARDLIM[7:0]). The f ull 10-bit HARDLIM[9:0] field spans this register
and DLIMIT2. HARDLIM is an uns igne d integer that s pec ifies the har d frequenc y lim it or pull-in/hold-in rang e of the
T0 DPLL. When frequency limit detection is enabled by setting FLLOL = 1 in the DLIMIT3 register. If the DPLL
frequency exceeds the hard limit the DPLL declares loss-of-lock. The hard frequency limit in ppm is
±HARDLIM[9:0] × 0.0782. The default value is normally ±9.2ppm. If external reference switching mode is enabled
during reset (see Section 7.6.5), the default value is configured to ±79.794ppm (3FFh). See Section 7.7.6.
Register Name:
DLIMIT2
Register Description:
DPLL Frequency Limit Register 1
Register Address:
42h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
HARDLIM[9:8]
Default
0
0
0
0
0
0
0
0
Bits 1 a n d 0: DPLL Hard Frequency Lim it (HARDLIM[9:8]). See the DLIMIT1 register des c ript ion.
DS3105
77
Register Name:
IER1
Register Description:
Interrupt Enable Register 1
Register Address:
43h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
IC6
IC5
IC4
IC3
—
—
Default
0
0
0
0
0
0
0
0
Bits 5 to 2: Interrupt Enable for Input Clock Status Change (IC[6:3]). Each of these bits is an interrupt enable
control for the corresponding bit in the MSR1 register.
0 = Mask the interrupt
1 = Enable the interrupt
Register Name:
IER2
Register Description:
Interrupt Enable Register 2
Register Address:
44h
Bit #
7
6
5
4
3
2
1
0
Name
STATE
SRFAIL
—
—
—
—
—
IC9
Default
0
0
0
0
0
0
0
0
Bit 7: Interrupt Enable for T0 DPLL State Change (STATE). This bit is an interrupt enable for the STATE bit in
the MSR2 register.
0 = Mask the interrupt
1 = Enable the interrupt
Bit 6: Interrupt Enable for Selected Reference Failed (SRFAIL). This bit is an interrupt enable for the SRFAIL bit
in the MSR2 register.
0 = Mask the interrupt
1 = Enable the interrupt
Bit 0: Interrupt Enable for Input Clock Status Change (IC9). This bit is an inter rupt enab le contr ol for the IC 9 bit
in the MSR2 register.
0 = Mask the interrupt
1 = Enable the interrupt
Register Name:
IER3
Register Description:
Interrupt Enable Register 3
Register Address:
45h
Bit #
7
6
5
4
3
2
1
0
Name
FSMON
T4LOCK
—
—
—
—
—
—
Default
0
0
0
0
0
0
0
0
Bit 7: Interrupt Enable for Frame-Sync Input Monitor Alarm (FSMON). This bit is an interrupt enable for the
FSMON bit in the MSR3 register.
0 = Mask the interrupt
1 = Enable the interrupt
Bit 6: Interrupt Enable for the T4 DPLL Lock Status Change (T4LOCK). This bit is an interrupt enable for the
T4LOCK bit in the MSR3 register.
0 = Mask the interrupt
1 = Enable the interrupt
DS3105
78
Register Name:
DIVN1
Register Description:
DIVN Register 1
Register Address:
46h
Bit #
7
6
5
4
3
2
1
0
Name
DIVN[7:0]
Default
1
1
1
1
1
1
1
1
Note: The DIVN1 and DIVN2 registers must be read consecutiv ely and written consecutively. See Section 8.3.
Bits 7 to 0: DIVN Factor (DIVN[7:0]). The full 16-bit DIVN[15:0] field spans this register and DIVN2. This field
contains the integer value used to divide the frequency of input clocks that are configured for DIVN mode. The
frequency is divided by DIVN[15:0] + 1. See Section 7.4.2.4.
Register Name:
DIVN2
Register Description:
DIVN Register 2
Register Address:
47h
Bit #
7
6
5
4
3
2
1
0
Name
DIVN[15:8]
Default
0
0
1
1
1
1
1
1
Bits 7 to 0: DIVN Factor (DIVN[15:8]). See the DIVN1 register description.
DS3105
79
Register Name:
MCR10
Register Description:
Master Configuration Register 10
Register Address:
48h
Bit #
7
6
5
4
3
2
1
0
Name
—
SRFPIN
UFSW
EXTSW
PBOFRZ
PBOEN
—
—
Default
1
0
0
see below
0
1
0
0
Bit 6: SRFAIL Pin Enable (SRFPIN). When this bit is set to 1, the SRFAIL pin is enabled. When enabled the
SRFAIL pin follows the state of the SRFAIL status bit in the MSR2 register. This gives the system a very fast
indication of the failure of the current reference. See Section 7.5.3.
0 = SRFAIL pin disabled (high impedance)
1 = SRFAIL pin enabled
Bit 5: Ultra-Fast Switching Mode (UFSW). See Sect ion 7.6.4.
0 = Disabled
1 = Enabled. The current reference source is disqualified after less than three missing clock cycles.
Bit 4: External Reference Switching Mode (EXTSW). This bit enables ex ternal r eference s witching m ode. In this
mode, if the SRC SW pin is high the T 0 D PLL is f or ced to lock to input IC3 (if the prior ity of IC3 is non zero) or IC5 ( if
the priority of IC3 is zero) whether or not the selected input h as a valid ref erence signal. If the SRCSW pin is low
the devic e is f or ced t o lock to input IC4 (if the priorit y of IC4 is non zero) or IC6 ( if t he pr ior it y of IC4 is zero) wheth er
or not the selected input has a valid reference signal. During reset the default value of this bit is latched from the
SRCSW pin. This mode only controls the T0 DPLL. The T4 DPLL is not affected. See Section 7.6.5.
0 = Normal operation
1 = External switching mode
Bit 3: Phase Build-Out Freeze (PBOFRZ). This bit freezes the current input-output phase relationship and does
not allow fur ther phase bu ild-out e ven ts to oc cur . This bit affec ts phas e build-out i n r es ponse to r ef er ence s witc hi ng
(Section 7.7.7.1).
0 = Not frozen
1 = Frozen
Bit 2: Phase Build-Out Enable (PBOEN). W hen this bit is set to 1 a phase buil d-out event occ urs every tim e the
T0 DPLL chang es to a new reference, including exiting the holdover and free-run states. W hen this bit is set to 0,
the T0 DPLL locks to the new source with zero degrees of phase difference. See Section 7.7.7.
Register Name:
MCR11
Register Description:
Master Configuration Register 11
Register Address:
4Bh
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
T4T0
—
—
—
—
Default
0
0
0
0
0
0
0
0
Bit 4: T4 o r T0 Path Selec t (T 4T 0). T his bit spec if ies which pa th is be ing acc es s ed when r eads or wr ites ar e m ade
to the following registers: PTAB1, PTAB2, FREQ1, FREQ2, FREQ3, IPR2, IPR3, IPR5, PHASE1, and PHASE2.
0 = T0 path
1 = T4 path
DS3105
80
Register Name:
DLIMIT3
Register Description:
DPLL Frequency Limit Register 3
Register Address:
4Dh
Bit #
7
6
5
4
3
2
1
0
Name
FLLOL
SOFTLIM[6:0]
Default
1
0
0
0
1
1
1
0
Bit 7: Frequency Limit Loss-of-Lock (FLLOL). W hen this bit is set to 1, the T 0 DPLL and the T4 D PLL internal ly
declare loss-of-lock when their hard limits are reached. The T0 DPLL hard frequency limit is set in the
HARDLIM[9:0] field in the DLIMIT1 and DLIMIT2 registers. The T4 DPLL hard frequency limit is fixed at ±80ppm.
See Section 7.7.6.
0 = DPLL declares loss-of-lock normally.
1 = DPLL also declares loss-of-lock when the hard frequency limit is reached.
Bits 6 to 0: DPLL Soft Frequency Limit (SOFTLIM[6:0]). This field is an uns igned integer that specifies the sof t
frequency limit for the T0 DPLL and the T4 DPLL. The soft limit is only used for monitoring; exceeding this limit
does not cause l oss-of-lock. T he lim it in ppm is ±SOFTLIM[6:0] × 0.628. T he default va lue is ±8.7 9ppm . When the
T0 DPLL frequency reaches the soft limit the T0SOFT status bit is set in the OPSTATE register. When the T4
DPLL frequency reaches the soft limit the T4SOFT status bit is set in OPSTATE. See Section 7.7.6.
Register Name:
IER4
Register Description:
Interrupt Enable Register 4
Register Address:
4Eh
Bit #
7
6
5
4
3
2
1
0
Name
—
HORDY
—
—
—
—
—
—
Default
0
0
0
0
0
0
0
0
Bit 6: Interrupt Enable for Holdover Frequency Ready (HORDY). T his bit is an interrupt enable for the HOR DY
bit in the MSR4 register.
0 = Mask the interrupt
1 = Enable the interrupt
Register Name:
OCR5
Register Description:
Output Configuration Register 1
Register Address:
4Fh
Bit #
7
6
5
4
3
2
1
0
Name
—
—
AOF6
—
—
AOF3
—
—
Default
0
0
0
0
0
0
0
0
Bit 5: Alternate Output Frequency Mode Select 6 (AOF6). T his bit contr ols th e decoding of the OCR3.OFREQ6
field for the OC6 pin.
0 = Standard decodes
1 = Alternate decodes
Bit 2: Alternate Output Frequency Mode Select 3 (AOF3). T his bit contr ols th e decoding of the OCR2.OFREQ3
field for the OC3 pin.
0 = Standard decodes
1 = Alternate decodes
DS3105
81
Register Name:
LB0U
Register Description:
Leaky Bucket 0 Upper Threshold Register
Register Address:
50h
Bit #
7
6
5
4
3
2
1
0
Name
LB0U[7:0]
Default
0
0
0
0
0
1
1
0
Bits 7 to 0: Leaky Bucket 0 Upper Threshold (LB0U[7:0]). W hen the leaky bucket accumulator is equal to the
value stored in this field, the activity monitor declares an activity alarm by setting the input clock’s ACT bit in the
appropriate ISR register. Registers LB0U, LB0L, LB0S, and LB0D together specify leaky bucket configuration 0.
See Section 7.5.2.
Register Name:
LB0L
Register Description:
Leaky Bucket 0 Lower Threshold Register
Register Address:
51h
Bit #
7
6
5
4
3
2
1
0
Name
LB0L[7:0]
Default
0
0
0
0
0
1
0
0
Bits 7 to 0: Leaky Bucket 0 Lower Threshold (LB0L[7:0]). W hen the leaky bucket accumulator is equal to the
value store d in th is field, the activ ity monitorin g log ic c l ears the ac ti vity alarm (if previous ly declared) by cleari ng the
input clock’s ACT bit in the appropriate ISR register. Registers LB0U, LB0L, LB0S, and LB0D together specify
leaky bucket configuration 0. See Section 7.5.2.
Register Name:
LB0S
Register Description:
Leaky Bucket 0 Size Register
Register Address:
52h
Bit #
7
6
5
4
3
2
1
0
Name
LB0S[7:0]
Default
0
0
0
0
1
0
0
0
Bits 7 to 0: Leaky Bucket 0 Size (LB0S[7:0]). This field specifies the maximum value of the leaky bucket. The
accumulator cannot increment past this value. Registers LB0U, LB0L, LB0S, and LB0D together specify leaky
bucket configuration 0. See Section 7.5.2.
Register Name:
LB0D
Register Description:
Leaky Bucket 0 Decay Rate Register
Register Address:
53h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
LB0D[1:0]
Default
0
0
0
0
0
0
0
1
Bits 1 and 0: Leaky Bucket 0 Decay Rate (LB0D[1:0]). This field specifies the decay or “leak” rate of the leak y
bucket accumulator. For each period of 1, 2, 4, or 8 128ms intervals in which no irregularities are detected on the
input clock, the accumulator decrements by 1. Registers LB0U, LB0L, LB0S, and LB0D together specify leaky
bucket configuration 0. See Section 7.5.2.
00 = decrement every 128ms (8 units/second)
01 = decrement every 256ms (4 units/second)
10 = decrement every 512ms (2 units/second)
11 = decrement every 1024ms (1 unit/second)
DS3105
82
Register Name:
LB1U, LB2U, LB3U
Register Description:
Leaky Bucket 1/2/3 Upper Threshold Register
Register Address:
54h, 58h, 5Ch
Bit #
7
6
5
4
3
2
1
0
Name
LBxU[7:0]
Default
0
0
0
0
0
1
1
0
Bits 7 to 0: Leaky Bucket “x” Upper Thres h o ld (LBxU[7:0]). See the LB0U register description.
Registers LB1U, LB1L, LB1S, and LB1D together specify leaky bucket configuration 1.
Registers LB2U, LB2L, LB2S, and LB2D together specify leaky bucket configuration 2.
Registers LB3U, LB3L, LB3S, and LB3D together specify leaky bucket configuration 3.
Register Name:
LB1L, LB2 L , LB3L
Register Description:
Leaky Bucket 1/2/3 Lower Threshold Register
Register Address:
55h, 59h, 5Dh
Bit #
7
6
5
4
3
2
1
0
Name
LBxL[7:0]
Default
0
0
0
0
0
1
0
0
Bits 7 to 0: Leaky Bucket “x” Lower Threshold (LBxL[7:0]). See the LB0L register description.
Registers LB1U, LB1L, LB1S, and LB1D together specify leaky bucket configuration 1.
Registers LB2U, LB2L, LB2S, and LB2D together specify leaky bucket configuration 2.
Registers LB3U, LB3L, LB3S, and LB3D together specify leaky bucket configuration 3.
Register Name:
LB1S, LB2S, LB 3S
Register Description:
Leaky Bucket 1/2/3 Size Register
Register Address:
56h, 5Ah, 5Eh
Bit #
7
6
5
4
3
2
1
0
Name
LBxS[7:0]
Default
0
0
0
0
1
0
0
0
Bits 7 to 0: Leaky Bucket “x” Size (LBxS[7 :0]). See the LB0S register description.
Registers LB1U, LB1L, LB1S, and LB1D together specify leaky bucket configuration 1.
Registers LB2U, LB2L, LB2S, and LB2D together specify leaky bucket configuration 2.
Registers LB3U, LB3L, LB3S, and LB3D together specify leaky bucket configuration 3.
Register Name:
LB1D, LB2D, LB3D
Register Description:
Leaky Bucket 1/2/3 Decay Rate Register
Register Address:
57h, 5Bh, 5Fh
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
LBxD[1:0]
Default
0
0
0
0
0
0
0
1
Bits 1 and 0: Leaky Bucket “x” Decay Rate (LBxD[1:0]). See the LB0D register description.
Registers LB1U, LB1L, LB1S, and LB1D together configure leaky bucket algorithm 1.
Registers LB2U, LB2L, LB2S, and LB2D together configure leaky bucket algorithm 2.
Registers LB3U, LB3L, LB3S, and LB3D together configure leaky bucket algorithm 3.
DS3105
83
Register Name:
OCR2
Register Description:
Output Configuration Register 2
Register Address:
61h
Bit #
7
6
5
4
3
2
1
0
Name
0
0
0
0
OFREQ3[3:0]
Default
0
0
0
0
see below
Bits 3 to 0: Output Frequency of OC3 (OFREQ3[3:0]). This field specifies the frequency of output clock OC3.
The frequenc ies of the T 0 APLL and T4 APLL are c onfigur ed in the T0CR1 and T4CR1 register s. The Digit al1 and
Digital2 frequencies are configured in the MCR7 regis ter. See Section 7.8.2.3. The default frequency is set by the
O3F[2:0] bits. Se e Table 7-18. The decode of this field is controlled by the value of the OCR5.AOF3 bit.
AOF3 = 0: (standard decodes)
0000 = Output disabled (i.e., low)
0001 = 2kHz
0010 = 8kHz
0011 = Digital2 (see Table 7-8)
0100 = Digital1 (see Table 7-7)
0101 = T0 APLL frequency divided by 48
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
1010 = T0 APLL frequency divided by 4
1011 = T4 APLL frequency divided by 64
1100 = T4 APLL frequency divided by 48
1101 = T4 APLL f requency divided b y 16
1110 = T4 APLL frequency divided by 8
1111 = T4 APLL frequency divided by 4
AOF3 = 1: (alternate decodes)
0000 = Output disabled (i.e., low)
0001 = T0 APLL frequency divided by 64
0010 = T4 APLL frequency divided by 20
0011 = T4 APL L fr equency divided b y 12
0100 = T4 APLL frequency divided by 10
0101 = T4 APLL frequency divided by 5
0110 = T4 APLL frequency divided by 2
0111 = T4 selected reference (after dividing)
1000 = T0 selected reference (after dividing)
1001–1111 = undefined
DS3105
84
Register Name:
OCR3
Register Description:
Output Configuration Register 3
Register Address:
62h
Bit #
7
6
5
4
3
2
1
0
Name
OFREQ6[3:0]
0
0
0
0
Default
see below
0
0
0
0
Bits 7 to 4: Output Frequency of OC6 (OFREQ6[3:0]). This field specifies the frequency of output clock output
OC6. The frequencies of the T0 APLL and T4 APLL are configured in the T0CR1 and T4CR1 registers. The
Digital1 and Digital2 frequencies are configured in the MCR7 register. See Section 7.8.2.3. The default frequency is
set by the OC6[2:0] bits. See Table 7-17. The decode of this field is controlled by the value of the OCR5.AOF6 bit.
AOF6 = 0: (standard decodes)
0000 = Output disabled (i.e., low)
0001 = 2kHz
0010 = 8kHz
0011 = T0 APLL frequency divided by 2
0100 = Digital1 (see Table 7-7)
0101 = T0 APLL frequency
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
1010 = T0 APLL frequenc y divided b y 4
1011 = T4 APLL frequency divided by 64
1100 = T4 APLL frequency divided by 48
1101 = T4 APLL frequency divided by 16
1110 = T4 APLL frequency divided by 8
1111 = T4 APLL frequency divided by 4
AOF6 = 1: (alternate decodes)
0000 = Output disabled (i.e., low)
0001 = T4 APLL frequency divided by 5
0010 = T4 APLL frequency divided by 2
0011 = T4 APLL frequency
0100 = T0 APLL2 frequency divided by 5
0101 = T0 APLL2 frequency divided by 2
0110 = T0 APLL2 frequency
0111 = T4 selected reference (after dividing)
1000 = T0 selected reference (after dividing)
1001–1111 = undefined
DS3105
85
Register Name:
OCR4
Register Description:
Output Configuration Register 4
Register Address:
63h
Bit #
7
6
5
4
3
2
1
0
Name
MFSEN
FSEN
0
0
0
0
0
0
Default
1
1
0
0
0
0
0
0
Bit 7: MFSYNC Enable (MFSEN). This configuration bit enables the 2kHz output on the MFS YNC pin . See Secti o n
7.8.2.5.
0 = Disabled, driven low
1 = Enabled, output is 2k H z
Bit 6: FSYNC Enable (FSEN). This configuration bit enables the 8kHz output on the FSYNC pin. See Section
7.8.2.5.
0 = Disabled, driven low
1 = Enabled, output is 8k H z
DS3105
86
Register Name:
T4CR1
Register Description:
T4 DPLL Configuration Register 1
Register Address:
64h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
T4FREQ[3:0]
Default
0
0
0
0
see below
Bits 3 to 0: T4 APLL Frequency (T4FREQ[3:0]). When T0CR1:T4APT0 = 0, the T4 APLL DFS is connected to
the T4 DPLL, and this field configures the T4 APLL DFS frequency. The T4 APLL DFS frequency affects the
frequency of the T4 APLL which in turn affects the available output frequencies on the output clock pins (see the
OCR registers ). See Sect ion 7.8.2. T he default va lue of this f ield is cont ro ll ed by the O6F[2 :0] and O3F[2: 0] p ins as
described in Table 7-16.
T4FREQ[3:0] T4 APLL DFS FREQUENCY T4 APLL FREQUENCY (4 x T4 APLL DFS)
0000
APLL output disabled
Disabled, output is low
0001
77.76MHz
311.04MHz (4 x 77.76MHz)
0010
24.576MHz (12 x E1)
98.304MHz (48 x E1)
0011
32.768MHz (16 x E1)
131.072MHz (64 x E1)
0100
37.056MHz (24 x DS1)
148.224MHz (96 x DS1)
0101
24.704MHz (16 x DS1)
98.816MHz (64 x DS1)
0110
68.736MHz (2 x E3)
274.944MHz (8 x E3)
0111
44.736MHz (DS3)
178.944MHz (4 x DS3)
1000
25.248MHz (4 x 6312kHz)
100.992MHz (16 x 6312kHz)
1001
62.500MHz (GbE ÷ 16)
250.000MHz (GbE ÷ 4)
1010
30.720MHz (3 x 10.24)
122.880MHz (12 x 10.24)
1011
40.000MHz (4 x 10MHz)
160.000MHz (16 x 10MHz)
1100
26.000MHz (2 x 13MHz)
104.000MHz (8 x 13MHz)
1101–1111
{unused valu es }
{unused valu es }
DS3105
87
Register Name:
T0CR1
Register Description:
T0 DPLL Configur ation Register 1
Register Address:
65h
Bit #
7
6
5
4
3
2
1
0
Name
T4MT0
T4APT0
T0FT4[2:0]
T0FREQ[2:0]
Default
0
0
0
0
0
see below
Bit 7: T4 M easu re T 0 Phase ( T 4MT0). When this bit is set t o 1 the T4 phas e det ec tor is c onf igured to measure the
phase dif f er ence between the s el ec ted T 0 DPL L in put c loc k and the s elec t ed th e T4 DPLL input c loc k. See Sec tion
7.7.10.
0 = T4 can lock to an input to measure frequency.
1 = Enable T4-measure-T0-phase mode.
Bit 6: T4 APLL Source from T0 (T4APT0). When this bit is set to 0, T4CR1:T4FREQ configures the T4 APLL DFS
frequenc y. The T4 APLL D FS frequenc y aff ects the frequenc y of th e T4 APLL, which, in turn, aff ects the available
output f requencies on th e output cloc k pins (see the OCR reg isters). W hen this b it is set to 1, the fr equency of the
T4 APLL DFS is configured by the T0CR1:T0FT4[2:0] field below. See Section 7.8.2.
0 = T4 APLL frequency is determined by T4FREQ.
1 = T4 APLL frequency is determined by T0FT4.
Bits 5 to 3: T0 Frequency to T4 APLL (T0FT4[2:0]). When the T4APT0 bit is set to 1, this field specifies the
frequenc y of the T4 APLL DFS. This frequency can be different than the frequency specified by T0CR1:T0FREQ.
See Section 7.8.2.
T0FT4
T4 APLL DFS FREQUENCY
T4 APLL FREQUENCY (4 x T4 A PLL DFS)
000 =
24.576MHz (12 x E1)
98.304MHz (48 x E1)
001 =
62.500MHz (GbE ÷ 16)
250.000MHz (GbE ÷ 4)
010 =
32.768MHz (16 x E1)
131.072MHz (64 x E1)
011 =
{unused valu e}
{unused valu e}
100 =
37.056MHz (24 x DS1)
148.224MHz (96 x DS1)
101 =
{unused valu e}
{unused valu e}
110 =
24.704MHz (16 x DS1)
98.816MHz (64 x DS1)
111 =
25.248MHz (4 x 6312kHz)
100.992MHz (16 x 6312kHz)
Bits 2 to 0: T0 DPLL Output Frequency (T0FREQ[2:0]). This field configures the T0 APLL DFS frequency. The
T0 APLL DFS frequency affects the frequency of the T0 APLL, which, in turn, affects the available output
frequencies on the output clock pins (see the OCR registers). See Section 7.8.2. The default frequency is
controlled by the O6F[2:0] and O3F[2:0] pins as described in Table 7-15.
T0FREQ
T0 APLL DFS FREQUENCY
T0 APLL FREQUENCY (4 x T0 APLL DFS)
000 =
77.76MHz
311.04MHz (4 x 77.76MHz)
001 =
77.76MHz
311.04MHz (4 x 77.76MHz)
010 =
24.576MHz (12 x E1)
98.304MHz (48 x E1)
011 =
32.768MHz (16 x E1)
131.072MHz (64 x E1)
100 =
37.056MHz (24 x DS1)
148.224MHz (96 x DS1)
101 =
24.704MHz (16 x DS1)
98.816MHz (64 x DS1)
110 =
25.248MHz (4 x 6312kHz)
100.992MHz (16 x 6312kHz)
111 =
62.500MHz (GbE ÷ 16)
250.000MHz (GbE ÷ 4)
DS3105
88
Register Name:
T4BW
Register Description:
T4 Bandwidth Register
Register Address:
66h
Bit #
7
6
5
4
3
2
1
0
Name
0
0
0
0
0
0
T4BW[1:0]
Default
0
0
0
0
0
0
0
0
Bits 2 to 0: T4 DPLL Bandwidth (T4BW[2:0]). See Section 7.7.3.
00 = 18Hz
01 = 35Hz
10 = 70Hz
11 = {unused value, undefined}
Register Name:
T0LBW
Register Description:
T0 DPLL Locked Bandwidth Register
Register Address:
67h
Bit #
7
6
5
4
3
2
1
0
Name
0
0
0
RSV1
RSV2
T0LBW[2:0]
Default
0
0
0
0
0
0
0
0
Bits 4 and 3: Reserved Bit 1 and 2 (RSV[1:2]). These bi ts are reser ved for f uture use, a nd can b e written to an d
read back.
Bits 2 to 0: T0 DPLL Locked Bandwidth (T0LBW[2:0]). T his field config ur es the band widt h of the T0 D PL L whe n
locked to an input clock. When AUTOBW = 0 in the MCR9 register, the T0LBW bandwidth is used for acquisition
and for locked operation. W hen AUT OBW = 1, T0ABW bandwidth is used for acquisition while T0LBW bandwidth
is used for locked operation. See Section 7.7.3.
111 = 18Hz
000 = 35Hz
001 = 70Hz
010 = {unused value, undefined}
011 = 18Hz
100 = 120Hz
101 = 250Hz
110 = 400Hz
DS3105
89
Register Name:
T0ABW
Register Description:
T0 DPLL Acquisition Bandwidth Reg ister
Register Address:
69h
Bit #
7
6
5
4
3
2
1
0
Name
0
0
0
RSV1
RSV2
T0ABW[2:0]
Default
0
0
0
0
0
0
0
1
Bits 4 and 3: Reserved Bit 1 and 2 (RSV[1:2]). Thes e bits are reserv ed for futur e use, and ca n be written to and
read back.
Bits 2 to 0: T0 DPLL Acq uisition Bandwidth (T0 AB W[2:0]). T his field configur es the bandw idth of the T 0 DPLL
when acquiring lock . W hen AUTOBW = 0 in the MCR9 register, the T0LBW bandwidth is used for acquisition and
for locked operation. When AUTOBW = 1, T0ABW bandwidth is used for acquisition while T0LBW bandwidth is
used for locked operation. See Section 7.7.3.
111 = 18Hz (default)
000 = 35Hz
001 = 70Hz
010 = {unused value, undefined}
011 = 18Hz
100 = 120Hz
101 = 250Hz
110 = 400Hz
DS3105
90
Register Name:
T4CR2
Register Description:
T4 Configuratio n Register 2
Register Address:
6Ah
Bit #
7
6
5
4
3
2
1
0
Name
—
PD2G8K[2:0]
—
DAMP[2:0]
Default
0
0
0
1
0
0
1
1
Bits 6 to 4: Phase Detector 2 Gain 8kHz (PD2GA8K[2:0]). This field specifies the gain of the T4 phase detector 2
with an inpu t clock of 8kHz or les s. T his value is o nl y used if autom at ic gain sel ection is enabl ed b y setting P D2EN
= 1 in the T4CR3 r egister. See Sect ion 7.7.5.
Bits 2 to 0: Damping Factor (DAMP[2:0]). This field configures the damping factor of the T4 DPLL. Damping
factor is a func tion of both DAM P[2:0] a nd t he T4 DP LL ban dw idth (T4BW register). T he def ault value c orres ponds
to a damping factor of 5. See Section 7.7.4.
18Hz
35Hz
≥ 70Hz
001 =
1.2
1.2
1.2
010 =
2.5
2.5
2.5
011 =
5
5
5
100 =
5
10
10
101 =
5
10
20
000, 110, and 111 =
{unused valu es }
The gain peak for each damping factor is shown below:
DAMPING
FACTOR
GAIN PEAK (dB)
1.2
0.4
2.5
0.2
5
0.1
10
0.06
20
0.03
DS3105
91
Register Name:
T0CR2
Register Description:
T0 Configuratio n Register 2
Register Address:
6Bh
Bit #
7
6
5
4
3
2
1
0
Name
—
PD2G8K[2:0]
—
DAMP[2:0]
Default
0
0
0
1
0
0
1
1
Bits 6 to 4: Ph ase Det ecto r 2 Gain , 8kHz (PD 2G8K[ 2:0]) . This field sp ecif ies the ga in of the T 0 phase det ector 2
with an inpu t clock of 8kHz or les s. T his value is o nl y used if autom atic gain s election is ena bled b y setting PD2EN
= 1 in the T0CR3 r egister. See Sect ion 7.7.5.
Bits 2 to 0: Damping Factor (DAMP[2:0]). This field configures the damping factor of the T0 DPLL. Damping
factor is a function of both DAMP[2:0] and the T0 DPLL bandwidth (T0ABW and T0LBW). The default value
corresponds to a damping factor of 5. See Section 7.7.4.
18Hz
35Hz
≥ 70Hz
001 =
1.2
1.2
1.2
010 =
2.5
2.5
2.5
011 =
5
5
5
100 =
5
10
10
101 =
5
10
20
000, 110, and 111 =
{unused valu es }
The gain peak for each damping factor is shown below:
DAMPING
FACTOR
GAIN PEAK (dB)
1.2
0.4
2.5
0.2
5
0.1
10
0.06
20
0.03
DS3105
92
Register Name:
T4CR3
Register Description:
T4 Configuratio n Register 3
Register Address:
6Ch
Bit #
7
6
5
4
3
2
1
0
Name
PD2EN
—
—
—
—
PD2G[2:0]
Default
1
1
0
0
0
0
1
0
Bit 7: Phase D etector 2 Gain Enab le (PD2EN). W hen this bit is s et to 1, the T4 phase det ector 2 is enable d and
the gain is det ermined by the input lock ing freque ncy. If the frequenc y is greater than 8k Hz, the gain is set by the
PD2G field. If the frequency is less than or equal to 8kHz, the gain is set by the PD2G8K field in the T4CR2
register. See Section 7.7.5.
0 = Disable
1 = Enable
Bits 2 to 0: Phase Detecto r 2 Gain (PD2G [2:0]) . This field specif ies the gain of the T 4 phase detector 2 when the
input frequency is greater than 8kHz. This value is only used if automatic gain selection is enabled by setting
PD2EN = 1. See Section 7.7.5.
Register Name:
T0CR3
Register Description:
T0 Configuratio n Register 3
Register Address:
6Dh
Bit #
7
6
5
4
3
2
1
0
Name
PD2EN
—
—
—
—
PD2G[2:0]
Default
1
1
0
0
0
0
1
0
Bit 7: Phase D etector 2 Gain Enab le (PD2EN). W hen this bit is s et to 1, the T0 phase det ector 2 is enable d and
the gain is det ermined by the input lock ing frequency. If the frequency is great er than 8kHz, the gain is set by the
PD2G field. If the frequency is less than or equal to 8kHz, the gain is set by the PD2G8K field in the T0CR2
register. See Section 7.7.5.
0 = Disable
1 = Enable
Bits 2 to 0: Phase Detecto r 2 Gain (PD2G [2:0]) . This field specif ies the gain of the T 0 phase detector 2 when the
input frequency is greater than 8kHz. This value is only used if automatic gain selection is enabled by setting
PD2EN = 1. See Section 7.7.5.
DS3105
93
Register Name:
GPCR
Register Description:
GPIO Configuration Register
Register Address:
6Eh
Bit #
7
6
5
4
3
2
1
0
Name
GPIO4D
GPIO3D
GPIO2D
GPIO1D
GPIO4O
GPIO3O
GPIO2O
GPIO1O
Default
0
0
0
0
0
0
0
0
Bit 7: GPIO4 Direction (GPIO4D). This bit configures the data direction for the GPIO4 pin. When GPIO4 is an
input its current state can be read from GPSR:GPIO4. When GPIO4 is an output, its value is controlled by the
GPIO4O configuration bit.
0 = Input
1 = Output
Bit 6: GPIO3 Direction (GPIO3D). This bit configures the data direction for the GPIO3 pin. When GPIO3 is an
input its current state can be read from GPSR:GPIO3. When GPIO3 is an output, its value is controlled by the
GPIO3O configuration bit.
0 = Input
1 = Output
Bit 5: GPIO2 Direction (GPIO2D). This bit configures the data direction for the GPIO2 pin. When GPIO2 is an
input its current state can be read from GPSR:GPIO2. When GPIO2 is an output, its value is controlled by the
GPIO2O configuration bit.
0 = Input
1 = Output
Bit 4: GPIO1 Direction (GPIO1D). This bit configures the data direction for the GPIO1 pin. When GPIO1 is an
input its current state can be read from GPSR:GPIO1. When GPI13 is an output, its value is controlled by the
GPIO1O configuration bit.
0 = Input
1 = Output
Bit 3: GPIO4 Output Value (GPIO4O). When GPIO4 is configured as an output (GPIO4D = 1), this bit specifies
the output value.
0 = Low
1 = High
Bit 2: GPIO3 Output Value (GPIO3O). When GPIO3 is configured as an output (GPIO3D = 1), this bit specifies
the output value.
0 = Low
1 = High
Bit 1: GPIO2 Output Value (GPIO2O). When GPIO2 is configured as an output (GPIO2D = 1), this bit specifies
the output value.
0 = Low
1 = High
Bit 0: GPIO1 Output Value (GPIO1O). When GPIO1 is configured as an output (GPIO1D = 1), this bit specifies
the output value.
0 = Low
1 = High
DS3105
94
Register Name:
GPSR
Register Description:
GPIO Statu s Register
Register Address:
6Fh
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
GPIO4
GPIO3
GPIO2
GPIO1
Default
0
0
0
0
0
1
0
0
Bit 3: GPI O4 State (GPIO4). This bit indicates the current state of the GPIO4 pin.
0 = Low
1 = High
Bit 2: GPI O3 State (GPIO3). This bit indicates the current state of the GPIO3 pin.
0 = Low
1 = High
Bit 2: GPI O2 State (GPIO2). This bit indicates the current state of the GPIO2 pin.
0 = Low
1 = High
Bit 1: GPI O1 State (GPIO1). This bit indicates the current state of the GPIO1 pin.
0 = Low
1 = High
DS3105
95
Register Name:
OFFSET1
Register Description:
Phase Offset Register 1
Register Address:
70h
Bit #
7
6
5
4
3
2
1
0
Name
OFFSET[7:0]
Default
0
0
0
0
0
0
0
0
Note: The OFFSET1 and OFFSET2 registers must be read consecutively and written consecutiv ely. See Section 8.3.
Bits 7 to 0: Phase Offset (OFFSET[7:0]). The full 16-bit OF F SET [15:0] fiel d s pa ns t his r e gister and the OFFSET2
register. O FFSET is a two’ s-com plement signed integer that specif ies the desired ph ase off set between the output
clocks and the selected input reference. The phase offset in picoseconds is equal to OFFSET[15:0] ×
actual_internal_clock_period / 211. If the internal clock is at its nominal frequency of 77.76MHz, the phase offset
equation s implifies to OFFSET [15:0] × 6. 279ps. If , however, t he DPLL is lock ed to a refer ence whose frequ enc y is
+1ppm from ideal, for exam ple, then the actual intern al clock period is 1ppm shorter and the phase off set is 1ppm
smaller. When the OF FSE T field is wri tten , the p has e of the out put cl oc ks is autom atic ally ramped to the new of f s et
value to avoid loss of s ynchronizat ion. To a djust th e phas e off set without c hanging th e phase of the o utput c lock s,
use the recalibration process enabled by FSCR3:RECAL. The OFFSET field is ignored when phase build-out is
enabled (PBOEN = 1 in the MCR10 register) and when the DPLL is not locked. See Section 7.7.8.
Register Name:
OFFSET2
Register Description:
Phase Offset Register 2
Register Address:
71h
Bit #
7
6
5
4
3
2
1
0
Name
OFFSET[15:8]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Phase Offset (OFFSET[15:8]). See the OFFSET1 register description.
DS3105
96
Register Name:
PBOFF
Register Description:
Phase Build-Out Offset Register
Register Address:
72h
Bit #
7
6
5
4
3
2
1
0
Name
—
—
PBOFF[5:0]
Default
0
0
0
0
0
0
0
0
Bits 5 to 0: Phase Build-Out Offset Register (PBOFF[5:0]). An uncertainty of up to 5ns is introduced each time a
phase build-out event occurs. This uncertainty results in a phase hit on the output. Over a large num ber of phase
build-out events the mean error should be zero. The PBOFF f ield specifies a fixed of fset for each phase build-out
event to skew the average error toward zero. This field is a two’s-complement signed integer. The offset in
nanoseco nds is PBOF F[5:0] × 0.101. V alues great er than 1. 4ns or les s than -1.4 ns can cause in ternal m ath errors
and should not be used. See Section 7.7.7.2.
Register Name:
PHLIM1
Register Description:
Phase Limit Register 1
Register Address:
73h
Bit #
7
6
5
4
3
2
1
0
Name
FLEN
NALOL
1
—
—
FINELIM[2:0]
Default
1
0
1
0
0
0
1
0
Bit 7: Fine Phase Limit Enable (FLEN). This configuration bit enables the fine phase limit specified in the
FINELIM[2:0] field. The fine limit must be disabled for multi-UI jitter tolerance (see PHLIM2 fields). This field
controls both T0 and T4. See Section 7.7.6.
0 = Disabled
1 = Enabled
Bit 6: No Activity Loss-of-Lock (NALOL). T he T0 and the T4 DPLLs c an det ec t that an inp ut cloc k has no act ivit y
very quickly (within two clock cycles). When NALOL = 0, loss-of-lock is not declared when clock cycles are missing,
and nearest edge locking (±180°) is used when the clock recovers. This gives tolerance to missing cycles. When
NALOL = 1 , l oss -of-lock is indicated as soon as n o ac t i vity is detec ted, and the device s witc hes to phase/f requency
locking (±360°). This field controls both T0 and T4. See Sections 7.5.3 and 7.7.6.
0 = No activity does not trigger loss-of-lock.
1 = No activity does trigger loss-of-lock.
Bit 5: Leave set to 1 (test control).
Bits 2 to 0: Fine Phase Limit (FINELIM[2:0]). This field specifies the fine phase limit window, outside of which
loss-of-lock is declared. The FLEN bit enables this feature. The phase of the input clock has to be inside the fine
lim it w ind ow for two sec on d s before phase loc k is dec lared. Los s -of-lock is declared im mediatel y if the ph as e of the
input clock is outside the p hase limit window . The default value of 010 is approp riate for most s ituations. This f ield
controls both T0 and T4. See Section 7.7.6.
000 = Always indicates los s -of-phase lock—do not use
001 = Small phase limit window, ±45° to ±90°
010 = Normal phase limit window, ±90° to ±180° (default)
100, 101, 110, 111 = Propo rtiona tely larger phase limit window
DS3105
97
Register Name:
PHLIM2
Register Description:
Phase Limit Register 2
Register Address:
74h
Bit #
7
6
5
4
3
2
1
0
Name
CLEN
MCPDEN
USEMCPD
—
COARSELIM[3:0]
Default
1
0
0
0
0
1
0
1
Bit 7: Coarse Phase Limit Enable (CLEN). This configuration bit enables the coarse phase limit specified in the
COARSELIM[3:0] field. This field controls both T0 and T4. See Section 7.7.6.
0 = Disabled
1 = Enabled
Bit 6: Multicycle Phase D et ect or Enab le (MC PDEN). This conf igur at ion bit enables the m ultic yc le phase d et ector
and allows th e DPLL to tolerat e large-am plitude jitter and wander. T he range of this phas e detector is the sam e as
the coarse phase limit specified in the COARSELIM[3:0] field. This field controls both T0 and T4. See Section
7.7.5.
0 = Disabled
1 = Enabled
Bit 5: Use Multicycle Phase Detector in the DPLL Algorithm (USEMCPD). This configuration bit enables the
DPLL algor it hm to use the multic ycle phas e det ec tor s o that a l arge phase measurement drives faster D PLL pull -in.
When USEMCPD = 0, phase measurement is limited to ±360°, giving slower pull-in at higher frequencies but with
less over shoot. W hen US EMCPD = 1, phase meas urem ent is set as spec if ied in the CO ARS ELIM[3 :0] fie ld, giving
faster pull-in. MCPDEN should be set to 1 when USEMCPD = 1. This field controls both T0 and T4. See Section
7.7.5.
0 = Disabled
1 = Enabled
Bits 3 to 0: Coarse Phase Limit (COARSELIM[3:0]). This field specifies the coarse phase limit and the tracking
range of the multicycle phase detector. The CLEN bit enables this feature. If jitter tolerance greater than 0.5UI is
required and the input clock is a high-frequency signal, the DPLL can be configured to track phase errors over
many UI using the multicycle phase detector. This field controls both T0 and T4. See Section 7.7.5 and 7.7.6.
0000 = ±1UI
0001 = ±3UI
0010 = ±7UI
0011 = ±15UI
0100 = ±31UI
0101 = ±63UI
0110 = ±127UI
0111 = ±255UI
1000 = ±511UI
1001 = ±1023UI
1010 = ±2047UI
1011 = ±4095UI
1100–1111 = ±8191UI
DS3105
98
Register Name:
PHMON
Register Description:
Phase Monitor Register
Register Address:
76h
Bit #
7
6
5
4
3
2
1
0
Name
NW
—
—
—
—
—
—
—
Default
0
0
0
0
0
1
1
0
Bit 7: Low-Frequency Input Clock Noise Window (NW). For 2kHz, 4kH z, or 8k Hz input clock s, this conf iguration
bit enables a ±5% tolerance noise window centered around the expected clock edge location. Noise-induce d edges
outside th is windo w are ign ored, red ucin g the pos sibil ity of phas e hits on t he ou tput c lock s. This onl y applies to the
T0 DPLL a nd s h oul d b e e n abl ed o nly when the T0 DP LL is locked to an i nput an d the 180° phas e detector is being
used (TEST1.D180=0).
0 = All edges are recognized by the T0 DPLL.
1 = Only edges within the ±5% tolerance window are recognized by the T0 DPLL.
DS3105
99
Register Name:
PHASE1
Register Description:
Phase Register 1
Register Address:
77h
Bit #
7
6
5
4
3
2
1
0
Name
PHASE[7:0]
Default
0
0
0
0
0
0
0
0
Note: The PHASE1 and PHASE2 registers must be read consecutively. S ee Secti on 8.3.
Bits 7 to 0: Current DPLL Phase (PHASE[7:0]). The full 16-bit PHASE[15:0] field spans this register and the
PHASE2 register. PHASE is a two’s-complement signed integer that indicates the current value of the phase
detector. The value is the output of the phase averager. W hen T4T0 = 0 in the MCR11 register, PHASE indicates
the current phase of the T0 DPLL. When T4T0 = 1, PHASE indicates the current phase of the T4 DPLL. The
averaged phase difference in degrees is equal to PHASE × 0.707. See Section 7.7.10.
Register Name:
PHASE2
Register Description:
Phase Register 2
Register Address:
78h
Bit #
7
6
5
4
3
2
1
0
Name
PHASE[15:8]
Default
0
0
0
0
0
0
0
0
Bits 7 to 0: Current DPLL Phase (PHASE[15:8]). See the PHASE1 register description.
Register Name:
PHLKTO
Register Description:
Phase-Lock Timeout Register
Register Address:
79h
Bit #
7
6
5
4
3
2
1
0
Name
PHLKTOM[1:0]
PHLKTO[5:0]
Default
0
0
1
1
0
0
1
0
Bits 7 and 6: Phase-Lock Timeout Multiplier (PHLKTOM[1:0]). This field is an unsigned integer that specifies
the resolution of the phase-lock timeout field PHLKTO[5:0].
00 = 2 seconds
01 = 4 seconds
10 = 8 seconds
11 = 16 seconds
Bits 5 to 0: Phase-Lock Timeout (PHLKTO[5:0]). This field is an unsigned integer that, together with the
PHLKTOM[1:0] field, specifies the length of time that the T0 DPLL attempts to lock to an input clock before
declaring a phase-lock alarm (by setting the corresponding LOCK bit in the ISR registers). The timeout period in
seconds is PHLKTO[5:0] × 2^(PHLKTOM[1:0] + 1). The state machine remains in the prelocked, prelocked 2, or
phase-lost modes for the specified time before declaring a phase alarm on the selected input. See Section 7.7.1.
DS3105
100
Register Name:
FSCR1
Register Description:
Frame-Sync Configuration Register 1
Register Address:
7Ah
Bit #
7
6
5
4
3
2
1
0
Name
—
SYNCSRC[2:0]
8KINV
8KPUL
2KINV
2KPUL
Default
0
0
0
0
0
0
0
0
Bits 6 to 4: SYNC12 Source (SYNCSRC[2:0]). W hen external frame sync is configured for SYNC123 m ode, this
field specifies the input clocks to associate with the SYNC1 and SYNC2 pins. SYNC3 is always associated with
input clock IC9 in this mode. See Section 7.9.1.
0XX = SYNC1 pin associated with IC3 or IC5, SYNC2 pin associated with IC4 or IC6
1X0 = SYNC1 pin associat ed with IC 3, S YNC2 pin as soc iated with IC4
1X1 = SYNC1 pin assoc iat ed with IC5, S YNC 2 pin as s oc iated wit h IC6
Bit 3: 8kHz Invert (8KINV). When this bit is set to 1 the 8kHz signal on clock output FSYNC is inverted. See
Section 7.8.2.5.
0 = FSYNC not inverted
1 = FSYNC inverted
Bit 2: 8kHz Pulse (8K PUL) . W hen this bit is s et to 1, the 8k Hz signal on c lock output FSYNC is puls ed rather than
50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of FSYNC is equal to the
clock period of OC3. See Section 7.8.2.5.
0 = FSYNC not pulsed; 50% duty cycle
1 = FSYNC pulsed, with pulse width equal to OC3 period
Bit 1: 2kHz Invert (2KINV). When this bit is set to 1 the 2kHz signal on clock output MFSYNC is inverted. See
Section 7.8.2.5.
0 = MFSYNC not invert ed
1 = MFSYNC inverte d
Bit 0: 2kHz Pulse (2KPUL). When this bit is set to 1, the 2kHz signal on clock output MFSYNC is pulsed rather
than 50% duty c ycle. In this mode output clock OC3 m ust be enabled , and the pulse width of MFS YNC is equal to
the clock period of OC3. See Section 7.8.2.5.
0 = MFSYNC not pulsed; 50% duty cycle
1 = MFSYNC pulsed, with puls e wid th equa l to OC3 p eriod
DS3105
101
Register Name:
FSCR2
Register Description:
Frame-Sync Configuration Register 2
Register Address:
7Bh
Bit #
7
6
5
4
3
2
1
0
Name
INDEP
OCN
PHASE3[1:0]
PHASE2[1:0]
PHASE1[1:0]
Default
0
0
0
0
0
0
0
0
Bit 7: Independent Frame Sync and Multiframe Sync (INDEP). W hen th is bi t is s et to 0, the 8kHz fr am e sync on
FSYNC and the 2kHz multiframe sync on MFSYNC are aligned with the other output clocks when synchronized
with the SYNCn input. When this bit is 1, the frame sync and multifram e s ync are independent of the other output
clocks, and their edge position may change without disturbing the other output clocks. See Section 7.9.5.
0 = FSYNC and MFSYNC are aligned with other output clocks; all are synchronized by the SYNCn input.
1 = FSYNC and MFSYNC are independent of the other clock outputs; only FSYNC and MFSYNC are
synchron i zed by the SYNC n input.
Bit 6: Sync OC-N Rates (OCN). See Section 7.9.3.
0 = SYNCn is sampled with a 6.48MHz resolution; the selected reference must be 6.48MHz.
1 = If the selected reference is 19.44MHz, SYNCn is sampled at 19.44MHz. If the selected reference is
38.88MHz, SYNCn is sampled at 38.88MHz. The selected reference must be either 19.44MHz or
38.88MHz.
Bits 5 and 4: External Sync-Sampling Phase 3 (PHASE3[1:0]). This field adjusts the sampling of the SYNC3
input pin. Normally the falling edge of SYNC3 is aligned with the falling edge of the selected reference. All UI
numbers listed below are UI of the sampling clock. See Section 7.9.2.
00 = Coincident
01 = 0.5UI early
10 = 1UI late
11 = 0.5UI late
Bits 3 and 2: External Sync-Sampling Phase 2 (PHASE2[1:0]). This field adjusts the sampling of the SYNC2
input pin. Normally the falling edge of SYNC2 is aligned with the falling edge of the selected reference. All UI
numbers listed below are UI of the sampling clock. See Section 7.9.2.
00 = Coincident
01 = 0.5UI early
10 = 1UI late
11 = 0.5UI late
Bits 1 and 0: External Sync-Sampling Phase 1 (PHASE1[1:0]). This field adjusts the sampling of the SYNC1
input pin. Normally the falling edge of SYNC1 is aligned with the falling edge of the selected reference. All UI
numbers listed below are UI of the sampling clock. See Section 7.9.2.
00 = Coincident
01 = 0.5UI early
10 = 1UI late
11 = 0.5UI late
DS3105
102
Register Name:
FSCR3
Register Description:
Frame-Sync Configuration Register 3
Register Address:
7Ch
Bit #
7
6
5
4
3
2
1
0
Name
RECAL
MONLIM[2:0]
SOURCE[3:0]
Default
0
0
1
0
1
0
1
1
Bit 7: Phase Offset Recalibration (RECAL). When set to 1, this configuration bit causes a recalibration of the
phase off set bet ween the o utput cloc k s and the selec ted ref erenc e. This process puts the DPLL into m ini holdov er,
internall y ramps the phase offs et to zero, res ets all c lock dividers, r am ps the phase of fset to the val ue stored in the
OFFSET registers, and then switches the DPLL out of m ini-holdover. Unlike sim ply writing the OFFSET registers,
the RECAL process causes no change in the phase offset of the output clocks. RECAL is autom atically reset to 0
when recalibration is complete. See Section 7.7.8.
0 = Normal operation
1 = Phase offset recalibration
Bits 6 to 4: External Frame-Sync Monitor Limit (MONLIM[2:0]). When the external frame-sync signal is
misaligned with respect to the MFSYNC output by the specified number of resampling clock cycles, a frame-sync
monitor alarm is declared in the FSMON bit of the OPSTATE regis ter. See Sec t io n 7.9.6.
000 = ± 1UI
001 = ± 2UI
010 = ± 3UI
011 = ± 4UI
100 = ± 5UI
101 = ± 6UI
110 = ± 7UI
111 = ± 8UI
Bits 3 to 0: External Frame-Sync Reference Source (SOURCE[3:0]). When external frame sync is configured
for SYNC1 automatic mode, this field specifies the input clock to associate with the SYNC1 pin. See Section 7.9.1.
0000–0001 {unused values, undefined}
0011 = IC3
0100 = IC4
0101 = IC5
0110 = IC6
0111–1000 = {unused values, undefined}
1001 = IC9
1010–1011 = {unused value, undefined}
11XX = SYNC123 mode
DS3105
103
Register Name:
INTCR
Register Description:
Interrupt Configuration Register
Register Address:
7Dh
Bit #
7
6
5
4
3
2
1
0
Name
—
—
—
—
LOS
GPO
OD
POL
Default
0
0
0
0
0
0
1
0
Bit 3: INTREQ Pin Mode (LOS). When GPO = 0, this bit selects the function of the INTREQ pin.
0 = The INTREQ/LOS pin indicates interrupt requests
1 = The INTREQ/LOS pin indicates the real-time state of the selected reference activity monitor (see
Section 7.5.3). This function is most useful when external switching mode (Section 7.6.5) is enabled
(MCR10:EXTSW = 1).
Bit 2: INTREQ Pin General-Purpose Output Enable (GPO). When set to 1, this bit configures the interrupt
request pin to be a general-purpose out put whos e va lu e is set by the POL bit.
0 = INTREQ is function det ermined by the LOS bit.
1 = INTREQ is a general-purpose output.
Bit 1: INTREQ Pin Open-Dra in Enable (OD)
When GPO = 0:
0 = INTREQ is driven in both inactive and active states.
1 = INTREQ is driven high or low in the active state but is high impedance in the inactive state.
When GPO = 1:
0 = INTREQ is driven as specified by POL.
1 = INTREQ is high impedance and POL has no effect.
Bit 0: INTREQ Pin Polarity (POL)
When GPO = 0:
0 = INTREQ goes low to signal an interrupt request or LOS = 1 (active low).
1 = INTREQ goes high to signal interrupt request or LOS = 1 (active high).
When GPO = 1:
0 = INTREQ driven low.
1 = INTREQ driven high.
Register Name:
PROT
Register Description:
Protection Register
Register Address:
7Eh
Bit #
7
6
5
4
3
2
1
0
Name
PROT[7:0]
Default
1
0
0
0
0
1
0
1
Bits 7 to 0: Protection Control (PROT[7:0]). This field can be used to protect the rest of the register set from
inadvertent writes. In protected mode writes to all other registers are ignored. In single unprotected mode, one
register (ot her than P ROT) can be written , but after t hat write the device rever ts to protec ted mode (and the value
of PROT is internally changed to 00h). In full y unprotected mode all register can be written without limitation. See
Section 7.2.
1000 0101 = Fully unprotected mode
1000 0110 = Single unprotected mode
All other values = Protected mode
DS3105
104
9.
JTAG Tes t Access Por t and Boundary Scan
9.1
JTAG Description
The DS3105 supp or ts t he s tandard instr uc t ion co des S AM PL E/PR ELO AD, B YPASS, and EX T EST . Optiona l pub lic
instructio ns included are HI GHZ, CLAMP, and ID CODE. Figure 9-1 sho ws a block diagram. T he DS3105 contains
the follo wing items, which meet the r equir ements s et b y the I EE E 11 49. 1 St and a r d T es t Ac ces s Port and B o undary
Scan Architecture:
Test Access Port (TAP)
Bypass Register
TAP Controller
Boundary Scan Register
Instruction Register
Device Identification Register
The TAP has the necessar y interf ace pins, nam ely JTCLK, JTRST, JTDI, JT DO, and JTMS. Details on these pins
can be found in Table 6-5. Details about the boundary scan architecture and the TAP can be found in IEEE 1149.1-
1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
Figure 9-1. JTAG Block Diagram
BOUNDARY SCAN
REGISTER
DEVICE
IDENTIFICATION
REGISTER
BYPASS REGISTER
INSTRUCTION
REGISTER
TEST ACCESS PORT
CONTROLLER
MUX
SELECT
THREE-STATE
JTDI
50k
JTMS
50k
JTCLK
JTRST
50k
JTDO
DS3105
105
9.2
JTAG TAP Controller State Machine Description
This section discusses the operation of the TAP controller state machine. The TAP controller is a finite state
machine that responds to the logic level at JTMS on the rising edge of JTCLK. Each of the states denoted in
Figure 9-2 is described in the following paragraphs.
Test-Logic-Reset. Upon device power-up, the TAP controller starts in the Test-Logic-Reset state. The instruction
register contains the IDCODE instruction. All system logic on the device operates normally.
Run-Test-Idle. Run-Test-Idle is used between sc an operatio ns or dur ing specif ic tes ts. The inst ruction reg iste r and
all test registers remain idle.
Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the
controller into the Capture-DR state and initiates a scan sequence. JT MS high m oves the controller to th e Select-
IR-SCAN state.
Capture-DR. D ata can be parallel-lo aded into the test register selec ted by the cur rent instruction. If the instruction
does not c all for a p aralle l load or t he sel ected t est reg ister does not a llow para ll el loads, t he reg ister remains at its
current va lue. On the r ising edge of JTC LK, the contro ller goes to t he Shift -DR state if JTMS is lo w or to the Ex it1-
DR state if JTMS is high.
Shift-DR. The test register selected by the current instruction is connected between JTDI and JTDO and data is
shifted one stage toward the serial output on each rising edge of JTCLK. If a test register selected by the current
instruction is not placed in the serial path, it maintains its previous state.
Exit1-DR. W hile in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state,
which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Pause-DR
state.
Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction retain their previous state. The controller remains in this state while JTMS is low. A rising edge on
JTCLK with JTMS high puts the controller in the Exit2-DR state.
Exit2-DR. W hile in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state
and terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Shift-DR
state.
Update-DR. A falling edge on JT CLK while in the Update-DR state latches the data from the shift register path of
the test registers into the data output latches. T his prevents changes at the parallel output because of changes in
the shift regis ter. A rising e dge on JTCLK with JT MS low puts th e controller in th e Run-Test-Idle stat e. W ith JTMS
high, the controller enters the Select-DR-Scan state.
Select-IR-Scan. All test r egister s retai n th eir pre vi ous state. T he ins truc tio n r eg ister remains unc hange d during th is
state. With JTMS low, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan
sequence for the instruction register. JTMS high during a rising edge on JTCLK puts the controller back into the
Test-Logic-Reset state.
Capture-IR. The Cap tur e-I R s tate is us ed to lo ad t he s hif t regis ter in th e inst ruc ti on re gis ter with a f ix ed va lue. This
value is loa ded on the r ising edg e of JT CLK. If JT MS is high on the ris ing edge of JTCLK, the c ontroller ente rs the
Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller enters the Shift-IR state.
Shift-IR. In this state, the instruction register ’s shift register is connected between JTDI and JTDO and shifts data
one stage for every rising edge of JTCLK toward the serial output. The parallel register and the test registers
rem ain at their pr evious st ates. A r ising edg e on JT CLK with J TMS high m oves t he control ler to the Exit1-IR state.
A rising edge on JTCLK with JTMS low keeps the controller in the Shift-IR state, while moving data one stage
through the instruction shift register.
DS3105
106
Exit1-IR. A rising edge on JTCLK with JTMS low puts the controller in the Pause -IR state. If JT MS is high on the
rising edge of JTCLK, the controller enters the Update-IR state and terminates the scanning process.
Pause-IR. Shifting of the instruction register is halted temporarily. With JTMS high, a rising edge on JTCLK puts
the controller in the Exit2-I R state. T he controller rem ains in the Pause-IR state if JT MS is low during a risin g edge
on JTCLK.
Exit2-IR. A rising edge on JTCLK with JTMS high puts the controller in the Update-IR state. The controller loops
back to the Shift-IR state if JTMS is low during a rising edge of JTCLK in this state.
Update-IR. The instruction shifted into the instruction shift register is latched into the parallel output on the falling
edge of JT CLK as the controller e nters this state . Once latched, this instruction bec omes the curr ent instruction. A
rising edge on JT CLK with JTMS low puts the controller in the Run-Test-Idle state. W ith JTMS high, the controller
enters the Select-DR-Scan state.
Figure 9-2. JTAG TAP Controller State Machine
Test-Logic-Reset
Run-Test/Idle
Select
DR-Scan
1
0
Capture-DR
1
0
Shift-DR
0
1
Exit1- DR
1
0
Pause-DR
1
Exit2-DR
1
Update-DR
0
0
1
Select
IR-Scan
1
0
Capture-IR
0
Shift-IR
0
1
Exit1-IR
1
0
Pause-IR
1
Exit2-IR
1
Update-IR
0
0
1
0
0
1
0
1
0
1
DS3105
107
9.3
JTAG Instruction Register and Instructions
The instr uc tion re gist er c on tains a shif t r egister as w el l as a latc he d para ll el o utpu t and is 3 b its in len gth. When the
TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in
the Shift-IR state, a ris ing edge on J T CLK with JT MS lo w shifts data one s tage to ward the s erial o utput at J TDO. A
rising edg e on J T C LK in the Exit1-IR state or th e Exit2 -IR st ate with J T MS h ig h m oves t he c on tr ol ler to the Update-
IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction
parallel output. Table 9-1 shows the instructions supported by the DS3105 and their respective operational binar y
codes.
Table 9-1. JTAG Instruction Codes
INSTRUCTIONS
SELECTED REGISTER
INSTRUCTION CODES
SAMPLE/PRELOAD
Boundary Sc an
010
BYPASS
Bypass
111
EXTEST
Boundary Sc an
000
CLAMP
Bypass
011
HIGHZ
Bypass
100
IDCODE
Device Identification
001
SAMPLE/PRELOAD. SAMPLE/RELOAD is a mandatory instruction for the IEEE 1149.1 specification. This
instruction supports two functions. First, the digital I/Os of the device can be sampled at the boundary scan
register, using the Capture-DR state, without interfering with the device’s normal operation. Second, data can be
shifted into the boundary scan register through JTDI using the Shift-DR state.
EXTEST. EXTEST allows testing of the interc onnections to the device. W hen the EXTEST instruction is latched in
the instruction register, the following actions occur: (1) Once the EXTEST instruction is enabled through the
Update-IR state, the parallel outputs of the digital output pins are driven. (2) The boundary scan register is
connected between JTDI and JTDO. (3) The Capture-DR state samples all digital inputs into the boundary scan
register.
BYPASS. W hen the B YPASS instruc tion is latche d int o the paral lel ins tructio n re gister, J TDI is connected to JTDO
through the 1-b it b ypass r egister. T his allo ws data to p ass from JT DI to JTDO without aff ecting th e device ’s norm al
operation.
IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the device identification
register is selected. The device ID code is loaded into the device identification register on the rising edge of JTCLK,
following entry into the Capture-DR state. Shift-DR can be used to shift the ID code out serially through JTDO.
During Test-Logic-Reset, the ID code is forced into the instruction register’s parallel output.
HIGHZ. A ll dig ital o utputs are p laced into a h igh-impedance s tate. The b ypass reg ister is conn ected bet ween J TDI
and JTDO.
CLAMP. All digital output pins output data from the boundary scan parallel output while connecting the bypass
register between JTDI and JTDO. The outputs do not change during the CL AM P instr uction.
DS3105
108
9.4
JTAG Test Registers
IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An
optional tes t regis ter, the identific ation re gister, h as be en includ ed in the de vice d esign. It is used with the ID CODE
instruction and the Test-Logic-Reset state of the TAP controller.
Bypass Register. This is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions to
provide a short path between JTDI and JTDO.
Boundary Scan Register. T his regist er contains a shif t register path and a latch ed paral lel output f or co ntrol cells
and digital I/O cells. The BSDL file is available on the DS3105 page of Microsemi’s website.
Identification Register. This register contains a 32-bit shift register and a 32-bit latched parallel output. It is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. The device
identification code for the DS3105 is shown in Table 9-2.
Table 9-2. JTAG ID Code
DEVICE REVISION DEV ICE CODE MANUFACTURER CODE REQUIRED
DS3105 Consult factory 0000000010100011 00010100001 1
DS3105
109
10.
Electrical Char acteristics
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin with Respect to VSS (except VDD)…….………………………………………..-0.3V to +5.5V
Supply Voltage Range (VDD) with Respect to VSS…….………….………………………………………..-0.3V to +1.98V
Supply Voltage Range (VDDIO) with Respect to VSS…………….………………………………………….-0.3V to +3.63V
Ambient Operating Temperature Range………………………………………………………..…-40°C to +85°C (Note 1)
Junction Operating Temperature Range…………………………………………………………………..-40°C to +125°C
Storage Temperature Range………………………………………………………………………………..-55°C to +125°C
Lead Temperature (soldering 10s) .................................................................................................................... +300°C
Soldering Temperature (reflow)
Lead(Pb)-free .............................................................................................................................................. +260°C
Containing lead(Pb) ..................................................................................................................................... +240°C
Note 1:
Specifications to -40°C are guaranteed by design and not production tested.
Stresses beyond those listed under “Absolute Maximum Ratings” may caus e permanent damage to the device. Thes e are stress ratings only ,
and functional operation of the device at these or any other condit i ons beyond those indic ated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating condit i ons for extended periods may aff ect device. A mbient operati ng temperature range
when device is mounted on a four-layer JEDEC test board with no airflow.
Note: The typical values listed in the tables of Section 10 are not production tested.
10.1
DC Characteristics
Table 10-1. Recommended DC Operati ng Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage, Core
VDD
1.62
1.8
1.98
V
Supply Voltage, I/O
VDDIO
3.135
3.3
3.465
V
Ambient Temperature Range
TA
-40
+85
°C
Junction Temperature Range
TJ
-40
+125
°C
Table 10-2. DC Characteristics
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Current, Core IDD (Notes 2, 3) 151 192 mA
Supply Current, I/O IDDIO (Notes 2, 3) 39 52 mA
Supply Current from VDD_OC6 When
Output OC6 Enabled
IDDOC6 (Note 4) 16 mA
Input Capacitance CIN 5 pF
Output Capac ita nc e COUT 7 pF
Note 2:
12.800MHz clock appli ed to REFCLK and 19.44MHz clock applied to one CMOS/TTL input clock pin. Output clock pin OC3 at
19.44MHz driving 100pF load; all other inputs at V DDIO or grounded; all other outputs disabled and open.
Note 3:
TYP current measured at V
DD
= 1.8V and V
DDIO
= 3.3V, MAX current measured at V
DD
= 1.98V and V
DDIO
= 3.465V.
Note 4:
19.44MHz output clock frequency, drivi ng t he load s hown in Figure 10-1. Enabled means MCR8:OC6SF ≠ 00.
DS3105
110
Table 10-3. CMOS/TTL Pins
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2.0
5.5
V
Input Low Voltage
VIL
-0.3
+0.8
V
Input Leakage IIL (Note 1) -10 +10 µA
Input Leakage, Pins with Internal
Pullup Resistor (50kΩ typ)
IILPU (Note 1) -100 +10 µA
Input Leakage, Pins with Internal
Pulldown Resistor (50kΩ typ)
IILPD (Note 1) -10 +100 µA
Output Leak age (w hen Hig h-Z) ILO (Note 1) -10 +10 µA
Output High Voltage (IO = -4.0mA) VOH 2.4 VDDIO V
Output Low Volta ge (IO = +4.0mA) VOL 0 0.4 V
Note 1:
0V < V
IN
< V
DDIO
for all other digital inputs.
Table 10-4. LVDS/LVPECL Input Pins
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage Tolerance VTOL (Note 1) 0 VDDIO V
Input Voltage Range VIN VID = 100mV 0 2.4 V
Input Differential Voltage VID 0.1 1.4 V
Input Differential Logic Threshold VIDTH -100 +100 mV
Note 1:
The device can tolerate this range of voltages w.r.t. VSS on its ICxPOS and ICxNEG pins without bei ng damaged. Proper
operation of the different i al input circuit ry is onl y guaranteed when the other specificat i ons i n this table are met.
Table 10-5. LVDS Output Pins
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
VOHLVDS
(Note 1)
1.6
V
Output Low Volta ge
VOLLVDS
(Note 1)
0.9
V
Differential Output Voltage
VODLVDS
247
350
454
mV
Output Offset (Common Mode) Voltage
VOSLVDS
25°C (Note 1)
1.125
1.25
1.375
V
Difference in Magnitude of Output
Differential Voltage for Complementary
States
VDOSLVDS 25 mV
Note 1:
With 100Ω load across the differential outputs.
Note 2:
The differential outputs can easil y be interf aced t o LVDS, LVPECL, and CML inputs on neighboring ICs using a few external
passive components. See App Note HFAN-1.0 for details.
DS3105
111
Table 10-6. LVPECL Level-Compatible Output Pins
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Output Voltage
VODPECL
595
700
930
mV
Output Offset (Common Mode) Voltage
VOSPECL
25°C (Note 1)
0.8
V
Difference in Magnitude of Output
Differential Voltage for Complementary
States
VDOSPECL 50 mV
Note 1:
With 100Ω load across the differential outputs.
Note 2:
The differential outputs can easil y be interf aced t o LVDS, LVPECL, and CML inputs on neighboring ICs using a few external
passive components. See App Note HFAN-1.0 for details.
Figure 10-1. R ecom mended Termination for LVDS Pins
DS3105
LVDS
I/O
ICnPOS
ICnNEG
100Ω
(5%)
50Ω
50Ω
OC6POS
OC6NEG
50Ω
50Ω
100Ω
(5%)
LVDS
DRIVER
LVDS
RECEIVER
Figure 10-2. Recommended Termination for LVPECL Signals on LVDS Input Pins
DS3105
LVDS
INPUTS
ICnPOS
ICnNEG
130Ω
130Ω
82Ω
82Ω
50Ω
50Ω
GND
3.3V
LVPECL
DRIVER
DS3105
112
Figure 10-3. Recommended Termination for LVPECL-Compatible Output Pins
DS3105
LVPECL
LEVEL-
OUTPUTS
OC6POS
OC6NEG
50Ω
50Ω
82Ω
0.01µF
130Ω
130Ω
GND
3.3V
LVPECL
RECEIVER
82Ω
COMPATIBLE
DS3105
113
10.2
Input Clock Ti mi ng
Table 10-7. Input Clock Timing
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
MIN
TYP
MAX
Input Clock
Period CMOS/TTL Input Pins tCYC 8ns (125MHz) 500µs (2kHz)
LVDS/LVPECL Input Pins 6.4ns (156.25MHz) 500µs (2kHz)
Input Clock High, Low Time tH, tL 3ns or 30% of tCYC,
whichever is smaller
10.3
Output Clock Timing
Table 10-8. Input Clock to Output Clock Delay
INPUT
FREQUENCY OUTPUT
FREQUENCY
INPUT CLOCK EDGE TO
OUTPUT CLOCK EDGE
DELA Y (ns)
8kHz
8kHz
0 ± 1.5
6.48MHz
6.48MHz
0 ± 1.5
19.44MHz
19.44MHz
0 ± 1.5
25.92MHz
25.92MHz
0 ± 1.5
38.88MHz
38.88MHz
0 ± 1.5
51.84MHz
51.84MHz
0 ± 1.5
77.76MHz
77.76MHz
0 ± 1.5
155.52MHz
155.52MHz
0 ± 1.5
Table 10-9. Output Clock Phase Ali gnm ent, Frame-Sync Alignment Mode
OUTPUT
FREQUENCY
MFSYNC FALLING EDGE TO OUTPUT
CLOCK FALLING EDGE DELAY (ns)
8kHz (FSYNC)
0 ± 0.5
2kHz
0 ± 0.5
8kHz
0 ± 0.5
1.544MHz
0 ± 1.25
2.048MHz
0 ± 1.25
44.736MHz
-2.0 ± 1.25
34.368MHz
-2.0 ± 1.25
6.48MHz
-2.0 ± 1.25
19.44MHz
-2.0 ± 1.25
25.92MHz
-2.0 ± 1.25
38.88MHz
-2.0 ± 1.25
51.84MHz
-2.0 ± 1.25
77.76MHz
-2.0 ± 1.25
155.52MHz
-2.0 ± 1.25
311.04MHz
-2.0 ± 1.25
See Section 7.9 for details on frame-sy nc alignment and the SYNC[1:3] pins.
DS3105
114
10.4
SPI Interface Timing
Table 10-10. SPI Interface Timing
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C.) (See Figure 10-4.)
PARAMETER (Note 1)
SYMBOL
MIN
TYP
MAX
UNITS
SCLK Frequency f
BUS
6 MHz
SCLK Cycle Time tCYC 100 ns
CS Setup to First SCLK Edge tSUC 15 ns
CS Hold Time After Last SCLK Edge t
HDC
15 ns
SCLK High Time t
CLKH
50 ns
SCLK Low Time t
CLKL
50 ns
SDI Data Setup Time t
SUI
5 ns
SDI Data Hold Time t
HDI
15 ns
SDO Enable Time (High-Z to Output Active) t
EN
0 ns
SDO Disable Time (Output Active to High-Z) t
DIS
25 ns
SDO Data Valid Time t
DV
50 ns
SDO Data Hold Time After Update SCLK Edge t
HDO
5 ns
Note 1:
All timing is specifi ed with 100pF load on all SPI pins.
DS3105
115
Figure 10-4. SPI Interface Timing Diagram
CS
SCLK,
CPOL=0
SCLK,
CPOL=1
t
SUI
t
HDI
SDI
t
CYC
t
SUC
t
CLKH
t
CLKL
t
CLKL
t
CLKH
t
HDC
SDO t
EN
t
DV
t
HDO
t
DIS
CPHA = 0
CPHA = 1
CS
SCLK,
CPOL=0
SCLK,
CPOL=1
t
CYC
t
SUC
t
CLKH
t
CLKL
t
CLKL
t
HDC
t
SUI
t
HDI
SDI
SDO t
EN
t
DV
t
HDO
t
DIS
t
CLKH
DS3105
116
10.5
JTAG Interface Timing
Table 10-11. JTAG Interface Timing
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C.) (See Figure 10-5.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
JTCLK Clock Period t1 1000 ns
JTCLK Clock High/Low Time (Note 1) t2/t3 50 500 ns
JTCLK to JTDI, JTMS Setup Time t4 50 ns
JTCLK to JTDI, JTMS Hold Time t5 50 ns
JTCLK to JTDO Delay t6 2 50 ns
JTCLK to JTDO High-Z Delay (Note 2) t7 2 50 ns
JTRST Width Low Time t8 100 ns
Note 1:
Clock can be stopped high or low.
Note 2:
Not tested during production t est.
Figure 10-5. JTAG Timing Diagram
t1
JTDO
t4
t5
t2
t3
t7
JTDI, JTMS, JTRST
t6
JTRST
t8
JTCLK
DS3105
117
10.6
Reset Pi n Timing
Table 10-12. Reset Pin Timing
(VDD = 1.8V ±10%; VDDIO = 3.3 V ±5%, TA = -40°C to +85°C.) (See Figure 10-6.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
RST Low Time (Note 1) t1 1000 ns
SONSDH, SRCSW, O3F[2:0], O6F[2:0] Setup Time to RST t2
0 ns
SONSDH, SRCSW, O3F[2:0], O6F[2:0] Hold Time from RST t3 50 ns
Note 1:
RST should be held low while the REFCLK oscillator stabilizes. It is recommended to force RST low during power-up. The
1000ns minimum time appli es if the RST pulse is applied any time after the device has powered up and the osci llat or has
stabilized.
Figure 10-6. Reset Pin Timing Diagram
RST
SONSDH
OxF[2:0]
SRCSW
VALID
X
X
t2
t3
t1
DS3105
118
11.
Pin Ass ignments
Table 11-1 lists pin assignments sorted in alphabetical order by pin name. Figure 11-1 shows pin assignments
arranged by pin number.
Table 11-1. Pin Assignments Sorted b y Signal Name
PIN NAME PIN NUMBER PIN NAME PIN NUMBER
AVDD_DL
59
MFSYNC
18
AVDD_PLL1
4
O3F1/SRFAIL
38
AVDD_PLL2
7
O3F2/LOCK
36
AVDD_PLL3
9
O6F0/GPIO1
45
AVDD_PLL4
11
O6F1/GPIO2
46
AVSS_DL
55
O6F2/GPIO3
63
AVSS_PLL1
3
OC3
56
AVSS_PLL2
8
OC6NEG
20
AVSS_PLL3
10
OC6POS
19
AVSS_PLL4
12
REFCLK
6
CPHA
42
RST
48
CS
44
SCLK
47
FSYNC
17
SDI
43
IC3
29
SDO
52
IC4
30
SONSDH/GPIO4
64
IC5NEG
24
SRCSW
13
IC5POS
23
SYNC1
28
IC6NEG
26
SYNC2
33
IC6POS
25
SYNC3/O3F0
35
IC9
34
TEST
2
INTREQ/LOS
5
VDD
27, 39, 57, 58
JTCLK
49
VDDIO
14, 32, 54, 61
JTDI
51
VDD_OC6
22
JTDO
50
VSS 1, 15, 16, 31, 40, 53,
60, 62
JTMS
41
JTRST
37
VSS_OC6
21
DS3105
119
Figure 11-1. P in As sign me nt Diagr a m
DS3105
RST
SCLK
O6F1/GPIO2
O6F0/GPIO1
CS
SDI
CPHA
JTMS
VSS
VDD
O3F1/SRFAIL
JTRST
O3F2/LOCK
SYNC3/O3F0
IC9
SYNC2
SONSDH/GPIO4
O6F2/GPIO3
VSS
VDDIO
VSS
AVDD_DL
VDD
VDD
OC3
AVSS_DL
VDDIO
VSS
SDO
JTDI
JTDO
JTCLK
VSS
TEST
AVSS_PLL1
AVDD_PLL1
INTREQ/LOS
REFCLK
AVDD_PLL2
AVSS_PLL2
AVDD_PLL3
AVSS_PLL3
AVDD_PLL4
AVSS_PLL4
SRCSW
VDDIO
VSS
VSS
FSYNC
MFSYNC
OC6POS
OC6NEG
VSS_OC6
VDD_OC6
IC5POS
IC5NEG
IC6POS
IC6NEG
VDD
SYNC1
IC3
IC4
VSS
VDDIO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32 49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
DS3105
120
12.
Package Information
For the latest package outline information and land patterns, contact Microsemi timing products technical support.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
64 LQFP C64-1 21-0083 90-0141
DS3105
121
13.
Thermal I nformation
Table 13-1. LQFP Package Thermal Properties, Natural Convection
PARAMETER
MIN
TYP
MAX
Ambient Temperature (Note 1)
-40°C
+85°C
Junction Temperature
-40°C
+125°C
Theta-JA (θJA) (Note 2)
45.4°C/W
Psi-JB
23.8°C/W
Psi-JT
0.3°C/W
Note 1:
The package is mounted on a four-layer JEDEC standard test board with no airflow and dissipating maximum power.
Note 2:
Theta-JA (θ
JA
) is the junction to ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard
test board with no airflow and dissipating maximum power.
Table 13-2. LQFP Theta-JA (
θ
JA) vs. Airflow
FORCED AIR (METERS PER SECOND)
THETA-JA (θJA)
0
45.4°C/W
1
37.3°C/W
2.5
34.5°C/W
DS3105
122
14.
Acronyms and A bbreviati ons
AIS Alarm Indication Signal
AMI Alternate Mark Inversion
APLL Analog Phase-Locked Loop
BITS Building Integrated Timing Supply
BPV Bipolar Violation
DFS Digital Frequency Synthesis
DPLL Digital Phase-Locked Loop
ESF Ext end ed Su perf r am e
EXZ Excessive Zeros
GbE Gigab it Eth er net
I/O Input/Output
LOS Loss of Signal
LVDS Low-Voltage D if f erentia l Si gna l
LVPECL Low-Voltage Positi ve Emitter-Coup led Lo gic
MTIE Maximum Time Interval Error
OCXO Oven-Controlled Crystal Oscillator
OOF Out of Frame Alignment
PBO Phas e Buil d-Out
PFD Phas e/Fr e qu ency Detector
PLL Phase-Locked Loop
ppb Parts per Billion
ppm Parts per Million
pk-pk Peak-to-Peak
RMS Root-Mean-Square
RAI Remote Alarm Indication
RO Read-Only
R/W Read/Write
SDH Synchronous Digital Hierarchy
SEC SDH Equipment Clock
SETS Synchronous Equipment Timing Source
SF Superframe
SONET Synchronous Optical Network
SSM Synchronization Status Message
SSU Synchronization Supply Unit
STM Synchronous Transport Module
TDEV Time Deviation
TCXO Temperature-Compensated Crystal Oscillator
UI Unit Interva l
UIP-P Unit Interval, Peak -to-Peak
XO Crystal Oscillator
DS3105
123
15.
Data Sheet Rev ision Hi story
REVISION
DATE DESCRIPTION
120707 Initial data sheet release.
100108 In Section 7.7.12, corrected the PLL bandwidth range to have the correct range of 18kHz to 400Hz to match
the register descriptions for T0ABW and T0LBW.
030909
In Table 6-1
, in the IC5POS/NEG and IC6POS/NEG pin desc riptions, added text to say that if the pins are not
used they should be left unconnected.
Corrected several frequencies in T able 7-17 and Table 7-18 to match actual device operati o n.
5/09 In Section 8, added note indicating systems must be able to access entire address range 0-1FFh.
8/10
In Figure 9-1 corrected pullup resistors values to 50kΩ.
In PHMON.NW bit description, added "(TEST1.D180=0)".
In Table 6-3 edited SRFAIL pin description to indicate state is high im pedance when MCR10.SRFPIN=0.
Edited MCR10.SRFPIN decription to say this also.
In Section 7.7.6 delet ed sent e nce that said the hard and soft limits have hysteresis.
Replaced the term "floating" with "unconnected" in several places .
Updated soldering temperature information in Section 10.
2012-04 Reformatted for Microsemi. No content change.
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