INTEGRATED CIRCUITS DATA SHEET 74LVC162373A; 74LVCH162373A 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state Product specification File under Integrated Circuits, IC24 1999 Aug 05 Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series 74LVC162373A; termination resistors; 5 V input/output tolerant; 3-state 74LVCH162373A FEATURES DESCRIPTION * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V The 74LVC(H)162373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One latch enable (LE) input and one output enable (OE) are provide for each octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment. * 5 V tolerant input/output for interfacing with 5 V logic * Wide supply voltage range of 1.2 to 3.6 V * Complies with JEDEC standard no. 8-1A * CMOS low power consumption * MULTIBYTE flow-through standard pin-out architecture * Low inductance multiple power and ground pins for minimum noise and ground bounce * Direct interface with TTL levels * All data inputs have bus hold (74LVCH162373A only) The 74LVC(H)162373 consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state off latches. The 74LVCH162373A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs. The 74LVC(H)162373A is designed with 30 series termination resistors in both HIGH and LOW output stages to reduce line noise. * High impedance when VCC = 0 * Power off disables outputs, permitting live insertion. FUNCTION TABLE (per section of eight bits) See note 1. INPUTS Enable and read register (transparent mode) Latch and read register Latch register and disable outputs OE LE Dn L H L L L L H H H H L L l L L L L h H H H L l L Z H L h H Z Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. 1999 Aug 05 OUTPUTS INTERNAL LATCHES OPERATION MODES 2 Q0 to Q7 Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state 74LVC162373A; 74LVCH162373A QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH PARAMETER CONDITIONS propagation delay TYPICAL UNIT CL = 50 pF; VCC = 3.3 V Dn to Qn 3.2 ns LE to Qn 3.5 ns CI input capacitance CPD power dissipation capacitance per latch VCC = 3.3 V; note 1 5.0 pF 26.0 pF Note 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL x VCC2 x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. ORDERING INFORMATION PACKAGE OUTSIDE NORTH AMERICA NORTH AMERICA TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE -40 to +85 C 48 SSOP plastic SOT370-1 74LVC162373ADL VC162373A DL 74LVC162373ADGG VC162373A DGG 48 TSSOP plastic SOT362-1 74LVCH162373ADL VCH162373A DL 48 SSOP plastic SOT370-1 74LVCH162373ADGG VCH162373A DGG 48 TSSOP plastic SOT362-1 PINNING PIN SYMBOL DESCRIPTION 1 1OE output enable input (active LOW) 2, 3, 5, 6, 8, 9, 11, 12 1Q0 to 1Q7 data inputs/outputs 4, 10, 15, 21, 28, 34, 39, 45 GND ground (0 V) 7, 18, 31, 42 VCC DC supply voltage 13, 14, 16, 17, 19, 20, 22, 23 2Q0 to 2Q7 data inputs/outputs 24 2OE output enable input (active LOW) 25 2LE latch enable input (active HIGH) 36, 35, 33, 32, 30, 29, 27, 26 2D0 to 2D7 data inputs 47, 46, 44, 43, 41, 40, 38, 37 1D0 to 1D7 data inputs 48 latch enable input (active HIGH) 1999 Aug 05 1LE 3 Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state handbook, halfpage 1OE 1 48 1LE 1Q0 2 47 1D0 1Q1 3 46 1D1 GND 4 45 GND 1Q2 5 44 1D2 1Q3 6 43 1D3 VCC 7 42 VCC 1Q4 8 41 1D4 1Q5 9 40 1D5 74LVC162373A; 74LVCH162373A 1 24 1OE 2OE handbook, halfpage 47 1D0 1Q0 2 46 1D1 1Q1 3 44 1D2 1Q2 5 43 1D3 1Q3 6 8 GND 10 39 GND 41 1D4 1Q4 1Q6 11 38 1D6 40 1D5 1Q5 9 38 1D6 1Q6 11 37 1D7 1Q7 12 2Q0 13 162373A 2Q1 14 37 1D7 1Q7 12 36 2D0 36 2D0 2Q0 13 35 2D1 35 2D1 2Q1 14 33 2D2 2Q2 16 32 2D3 2Q3 17 30 2D4 2Q4 19 GND 15 34 GND 2Q2 16 33 2D2 2Q3 17 32 2D3 29 2D5 2Q5 20 VCC 18 31 VCC 27 2D6 2Q6 22 30 2D4 26 2D7 2Q7 23 2Q4 19 2Q5 20 29 2D5 GND 21 28 GND 2Q6 22 27 2D6 2Q7 23 26 2D7 2OE 24 25 2LE 1LE 2LE 48 25 MNA425 MNA424 Fig.1 Pin configuration. 1999 Aug 05 Fig.2 Logic symbol. 4 Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state 74LVC162373A; 74LVCH162373A handbook, full pagewidth 1D0 D 1Q0 Q 2D0 D LATCH 9 LE LE LE LE 1LE 2LE 1OE 2OE to 7 other channels 2Q0 Q LATCH 1 to 7 other channels MNA426 Fig.3 Logic diagram. handbook, halfpage 1OE 1LE 2OE 2LE 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1 48 24 25 47 1EN C3 2EN C4 3D 1 2 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 4D 2 13 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Q0 1Q1 1Q2 handbook, halfpage VCC 1Q3 1Q4 1Q5 input 1Q6 to internal circuit 1Q7 2Q0 MNA428 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 MNA427 Fig.4 IEC logic symbol. 1999 Aug 05 Fig.5 Bus hold circuit. 5 Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state 74LVC162373A; 74LVCH162373A RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS UNIT MIN. VCC MAX. DC supply voltage for max. speed performance 2.7 3.6 V for low-voltage applications 1.2 3.6 V 0 5.5 V VI DC input voltage range VO DC output voltage range output HIGH or LOW state 0 VCC V 3-state 0 5.5 V see DC and AC characteristics per device -40 +85 C VCC = 1.2 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V Tamb operating ambient temperature tr, tf input rise and fall times LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT -0.5 +6.5 V VI < 0 - -50 mA DC input voltage note 1 -0.5 +5.5 V IOK DC output diode current VO > VCC or VO < 0 - 50 mA VO DC output voltage output HIGH or LOW note 1 -0.5 VCC + 0.5 V output 3-state note 1 -0.5 +6.5 V VO = 0 to VCC - 50 mA - 100 mA -65 +150 C - 500 mW VCC DC supply voltage IIK DC input diode current VI IO DC output diode current ICC, IGND DC VCC or GND current Tstg storage temperature Ptot power dissipation plastic shrink mini-pack (SSOP and TSSOP) above 60 C derate linearly with 5.5 mW/K Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1999 Aug 05 6 Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state 74LVC162373A; 74LVCH162373A DC CHARACTERISTICS Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL -40 to +85 PARAMETER VCC (V) OTHER VIH Tamb (C) HIGH-level input voltage MIN. VOH VOL LOW-level input voltage - - - - - GND 2.7 to 3.6 - - 0.8 1.2 HIGH-level output voltage VI = VIH or VIL; IO = -6 mA LOW-level output voltage MAX. - 1.2 VCC 2.7 to 3.6 2.0 VIL TYP.(1) UNIT 2.7 VCC - 0.5 - - VI = VIH or VIL; IO = -100 A 3.0 VCC - 0.2 VCC - VI = VIH or VIL; IO = -12 mA 3.0 VCC - 0.8 - - VI = VIH or VIL; IO = 6 mA 2.7 - - 0.40 VI = VIH or VIL; IO = 100 A 3.0 - - 0.20 V V V V VI = VIH or VIL; IO = 12 mA 3.0 - - 0.55 II input leakage current VI = 5.5 V or GND; note 2 3.6 - 0.1 5 A IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 5.5 V or GND 3.6 - 0.1 5 A Ioff power off leakage supply VI or VO = 5.5 V 0.0 - 0.1 10 A ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 - 0.1 20 A ICC additional quiescent VI = VCC - 0.6 V; IO = 0 supply current per control pin 2.7 to 3.6 - 5 500 A IBHL bus hold LOW sustaining current VI = 0.8 V; notes 3, 4 and 5 3.0 75 - - A IBHH bus hold HIGH sustaining VI = 2.0 V; notes 3, 4 and 5 current 3.0 -75 - - A IBHLO bus hold LOW overdrive current VI = 0.8 V; notes 3, 4 and 6 3.6 500 - - A IBHHO bus hold HIGH overdrive current VI = 0.8 V; notes 3, 4 and 6 3.6 -500 - - A Notes 1. All typical values are at VCC = 3.3 V and Tamb = 25 C. 2. For bus hold parts, the bus hold circuit is switched off when VI exceeds VCC allowing 5.5 V on the input terminal. 3. Valid for data inputs of bus hold parts (LVCH162373-A) only. 4. For data inputs only, control inputs do not have a bus hold circuit. 5. The specified sustaining current at the data input holds the input below the specified VI level. 6. The specified overdrive current at the data input forces the data input to the opposite logic input state. 1999 Aug 05 7 Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state 74LVC162373A; 74LVCH162373A AC CHARACTERISTICS GND = 0 V; tr = tf 2.5 ns; Tamb = -40 to +85 C. LIMITS SYMBOL PARAMETER VCC = 3.3 V 0.3 V WAVEFORMS MIN. tPHL/tPLH TYP.(1) MAX. VCC = 2.7 V MIN. UNIT MAX. propagation delay nDn to nQn see Figs 6 and 10 1.5 3.3 5.4 1.5 6.4 ns nLE to nQn see Figs 7 and 10 1.5 3.5 5.8 1.5 6.8 ns tPZH/tPZL 3-state output enable time nOE to nQn see Figs 9 and 10 1.5 4.0 7.3 1.5 8.3 ns tPHZ/tPLZ 3-state output disable time see Figs 9 and 10 nOE to nQn 1.5 3.4 4.8 1.5 5.8 ns tW nLE pulse width HIGH see Fig.7 4.0 2.0 - 3 - ns tsu set-up time nDn to nLE see Fig.8 +2.0 -0.1 - 1.7 - ns th hold time nDn to nLE see Fig.8 1.5 0.1 - 1.2 - ns Note 1. Typical values at VCC = 3.3 V and Tamb = 25 C. 1999 Aug 05 8 Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state 74LVC162373A; 74LVCH162373A AC WAVEFORMS handbook, halfpage VI VM nDn INPUT GND tPLH tPHL VOH VM nQn OUTPUT VOL MNA429 Fig.6 The input (nDn) to output (nQn) propagation delay. VI handbook, full pagewidth nLE INPUT VM VM GND tW t PHL t PLH VOH VM nQn OUTPUT VOL MNA430 Fig.7 Latch enable input (nLE) pulse width, the latch enable input to output (nQn) propagation delays. 1999 Aug 05 9 Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state 74LVC162373A; 74LVCH162373A VI handbook, full pagewidth VM nDn INPUT GND th th t su t su VI VM nLE INPUT GND MNA431 The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.8 Data set-up and hold times for the nDn input to the nLE input. VI handbook, full pagewidth nOE INPUT VM GND t PLZ t PZL VCC nQn OUTPUT LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ VOH VY nQn OUTPUT HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled MNA432 Fig.9 3-state enable and disable times. 1999 Aug 05 10 Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state S1 handbook, full pagewidth VCC PULSE GENERATOR VI RL 500 VO 74LVC162373A; 74LVCH162373A 2 x VCC open GND D.U.T. CL 50 pF RT RL 500 MNA296 TEST Definitions for test circuit: RL = Load resistor; see Chapter "AC characteristics". CL = Load capacitance including jig and probe capacitance (see Chapter "AC characteristics"). RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. S1 VCC VI tPLH/tPHL open tPLZ/tPZL 2 x VCC <2.7 V VCC tPHZ/tPZH GND 2.7 - 3.6 V 2.7 V Fig.10 Load circuitry for switching times. 1999 Aug 05 11 Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state 74LVC162373A; 74LVCH162373A PACKAGE OUTLINES SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3) pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 1999 Aug 05 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-11-02 95-02-04 MO-118AA 12 o Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state 74LVC162373A; 74LVCH162373A TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 1999 Aug 05 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-02-03 95-02-10 MO-153ED 13 o Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state SOLDERING 74LVC162373A; 74LVCH162373A If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 1999 Aug 05 14 Philips Semiconductors Product specification 16-bit D-type transparent latch with 30 series termination resistors; 5 V input/output tolerant; 3-state 74LVC162373A; 74LVCH162373A Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable(2) suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 245004/01/pp16 Date of release: 1999 Aug 05 Document order number: 9397 750 05974