HCS12
Microcontrollers
freescale.com
MC9S12XS256
Reference Manual
Covers MC9S12XS Family
MC9S12XS256
MC9S12XS128
MC9S12XS64
MC9S12XS256RMV1
Rev. 1.12
07/2011
To provide the most up-to-date information, the document revision on the World Wide Web is the most
current.Aprintedcopymaybeanearlierrevision.Toverifyyouhavethelatestinformationavailable,refer
to: http://freescale.com/
This document contains information for the complete S12XS Family and thus includes a set of separate
flash (FTMR) module sections to cover the whole family. A full list of family members and options is
included in the appendices.
This document contains information for all constituent modules, with the exception of the CPU. For CPU
information please refer to CPU12XV1 in the CPU12/CPU12X Reference Manual.
Revision History
Date Revision
Level Description
May, 2010 1.10 Updated Chapter 2 Port Integration Module (S12XSPIMV1)
Updated Chapter 16 Timer Module (TIM16B8CV2)
BDM Alternate clock source defined in device overview
November,
2010 1.11
Updated Chapter 3 Memory Mapping Control (S12XMMCV4)
Updated Chapter 11 Freescale’s Scalable Controller Area Network
(S12MSCANV3)
Updated Chapter 14 Serial Communication Interface (S12SCIV5)
Updated footnotes on table 1-2
Updated note in Appendix F Ordering Information
Jul, 2011 1.12
Corrected API accuracy in feature list
Corrected name of pin #27 in 80QFP pinout (PE5->PE4)
Updated Chapter 2 Port Integration Module (S12XSPIMV1)
Updated Chapter 11 Freescale’s Scalable Controller Area Network
(S12MSCANV3)
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Chapter 1 Device Overview S12XS Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Chapter 2 Port Integration Module (S12XSPIMV1) . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Chapter 3 Memory Mapping Control (S12XMMCV4) . . . . . . . . . . . . . . . . . . . . . . . .127
Chapter 4 Interrupt (S12XINTV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Chapter 5 Background Debug Module (S12XBDMV2) . . . . . . . . . . . . . . . . . . . . . . .167
Chapter 6 S12X Debug (S12XDBGV3) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Chapter 7 Security (S12XS9SECV2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Chapter 8 S12XE Clocks and Reset Generator (S12XECRGV1) . . . . . . . . . . . . . . .235
Chapter 9 Pierce Oscillator (S12XOSCLCPV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
Chapter 10 Analog-to-Digital Converter (ADC12B16CV1) . . . . . . . . . . . . . . . . . . . . .269
Chapter 11 Freescale’s Scalable Controller Area Network (S12MSCANV3) . . . . . .295
Chapter 12 Periodic Interrupt Timer (S12PIT24B4CV1) . . . . . . . . . . . . . . . . . . . . . . .349
Chapter 13 Pulse-Width Modulator (S12PWM8B8CV1) . . . . . . . . . . . . . . . . . . . . . . .365
Chapter 14 Serial Communication Interface (S12SCIV5). . . . . . . . . . . . . . . . . . . . . .397
Chapter 15 Serial Peripheral Interface (S12SPIV5). . . . . . . . . . . . . . . . . . . . . . . . . . .435
Chapter 16 Timer Module (TIM16B8CV2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .461
Chapter 17 Voltage Regulator (S12VREGL3V3V1) . . . . . . . . . . . . . . . . . . . . . . . . . . .489
Chapter 18 256 KByte Flash Module (S12XFTMR256K1V1). . . . . . . . . . . . . . . . . . . .507
Chapter 19 128 KByte Flash Module (S12XFTMR128K1V1). . . . . . . . . . . . . . . . . . . .557
Chapter 20 64 KByte Flash Module (S12XFTMR64K1V1). . . . . . . . . . . . . . . . . . . . . .607
Appendix A Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .657
Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .698
Appendix C PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .708
Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .712
Appendix E Detailed Register Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .713
Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .735
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Chapter 1
Device Overview S12XS Family
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.1.4 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.1.5 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.1.6 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.1.7 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.2.2 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
1.3 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1.4.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1.4.2 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
1.4.3 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.6 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.6.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.6.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.6.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.7 ATD0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.7.1 External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.7.2 ATD0 Channel[17] Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.8 VREG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.8.1 Temperature Sensor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.9 BDM Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
1.10 Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Chapter 2
Port Integration Module (S12XSPIMV1)
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
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2.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
2.3.3 Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.3.4 Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.3.5 Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.3.6 Port B Data Direction Register (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2.3.7 PIM Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.3.8 Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.3.9 Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.3.10 Ports ABEK, BKGD pin Pull-up Control Register (PUCR) . . . . . . . . . . . . . . . . . . . . . . 79
2.3.11 Ports ABEK Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.3.12 ECLK Control Register (ECLKCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.3.13 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
2.3.14 IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.3.15 PIM Reserved Register PIMTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.3.16 Port K Data Register (PORTK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.3.17 Port K Data Direction Register (DDRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
2.3.18 Port T Data Register (PTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.3.19 Port T Input Register (PTIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.20 Port T Data Direction Register (DDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.21 Port T Reduced Drive Register (RDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.22 Port T Pull Device Enable Register (PERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.3.23 Port T Polarity Select Register (PPST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
2.3.24 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.3.25 Port T Routing Register (PTTRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.3.26 Port S Data Register (PTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
2.3.27 Port S Input Register (PTIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
2.3.28 Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
2.3.29 Port S Reduced Drive Register (RDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.3.30 Port S Pull Device Enable Register (PERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.3.31 Port S Polarity Select Register (PPSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.3.32 Port S Wired-Or Mode Register (WOMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.3.33 PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.3.34 Port M Data Register (PTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2.3.35 Port M Input Register (PTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2.3.36 Port M Data Direction Register (DDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
2.3.37 Port M Reduced Drive Register (RDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
2.3.38 Port M Pull Device Enable Register (PERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.3.39 Port M Polarity Select Register (PPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.3.40 Port M Wired-Or Mode Register (WOMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
2.3.41 Module Routing Register (MODRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
2.3.42 Port P Data Register (PTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
2.3.43 Port P Input Register (PTIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
2.3.44 Port P Data Direction Register (DDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.3.45 Port P Reduced Drive Register (RDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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2.3.46 Port P Pull Device Enable Register (PERP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.3.47 Port P Polarity Select Register (PPSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
2.3.48 Port P Interrupt Enable Register (PIEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
2.3.49 Port P Interrupt Flag Register (PIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
2.3.50 Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
2.3.51 Port H Input Register (PTIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.3.52 Port H Data Direction Register (DDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.3.53 Port H Reduced Drive Register (RDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
2.3.54 Port H Pull Device Enable Register (PERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
2.3.55 Port H Polarity Select Register (PPSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
2.3.56 Port H Interrupt Enable Register (PIEH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
2.3.57 Port H Interrupt Flag Register (PIFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
2.3.58 Port J Data Register (PTJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
2.3.59 Port J Input Register (PTIJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
2.3.60 Port J Data Direction Register (DDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
2.3.61 Port J Reduced Drive Register (RDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
2.3.62 Port J Pull Device Enable Register (PERJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
2.3.63 Port J Polarity Select Register (PPSJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
2.3.64 Port J Interrupt Enable Register (PIEJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
2.3.65 Port J Interrupt Flag Register (PIFJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
2.3.66 Port AD0 Data Register 0 (PT0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
2.3.67 Port AD0 Data Register 1 (PT1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
2.3.68 Port AD0 Data Direction Register 0 (DDR0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
2.3.69 Port AD0 Data Direction Register 1 (DDR1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
2.3.70 Port AD0 Reduced Drive Register 0 (RDR0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
2.3.71 Port AD0 Reduced Drive Register 1 (RDR1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
2.3.72 Port AD0 Pull Up Enable Register 0 (PER0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
2.3.73 Port AD0 Pull Up Enable Register 1 (PER1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
2.3.74 PIM Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
2.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
2.4.3 Pins and Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2.4.4 Pin interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
2.5 Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
2.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Chapter 3
Memory Mapping Control (S12XMMCV4)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
3.1.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
3.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
3.1.3 S12X Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
3.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
3.4.1 MCU Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
3.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
3.4.3 Chip Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
3.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
3.5.1 CALL and RTC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Chapter 4
Interrupt (S12XINTV2)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
4.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
4.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
4.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
4.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4.4.1 S12X Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.4.3 XGATE Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
4.4.4 Priority Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
4.4.5 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.4.6 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
4.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
4.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
4.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Chapter 5
Background Debug Module (S12XBDMV2)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
5.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
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5.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
5.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
5.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
5.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
5.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
5.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
5.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
5.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
5.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
5.4.11 Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Chapter 6
S12X Debug (S12XDBGV3) Module
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
6.4.1 S12XDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.4.3 Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
6.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
6.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Chapter 7
Security (S12XS9SECV2)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.1.3 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
7.1.4 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
7.1.5 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
7.1.6 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
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7.1.7 Complete Memory Erase (Special Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Chapter 8
S12XE Clocks and Reset Generator (S12XECRGV1)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
8.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
8.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
8.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
8.2.1 VDDPLL, VSSPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
8.2.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
8.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
8.4.1 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
8.4.2 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
8.4.3 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
8.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
8.5.1 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
8.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
8.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Chapter 9
Pierce Oscillator (S12XOSCLCPV2)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
9.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
9.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
9.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 266
9.2.2 EXTAL and XTAL — Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
9.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
9.4.1 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
9.4.2 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
9.4.3 Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
9.4.4 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Chapter 10
Analog-to-Digital Converter (ADC12B16CV1)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
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10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
10.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
10.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
10.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
10.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
10.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
10.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
10.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Chapter 11
Freescale’s Scalable Controller Area Network (S12MSCANV3)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
11.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
11.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
11.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
11.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
11.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
11.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
11.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
11.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
11.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
11.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
11.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
11.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
11.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
11.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
11.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
11.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
11.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
11.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Chapter 12
Periodic Interrupt Timer (S12PIT24B4CV1)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
12.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
12.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
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12.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
12.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
12.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
12.4.1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
12.4.2 Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
12.4.3 Hardware Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
12.5 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
12.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
12.5.2 Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
12.5.3 Flag Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
12.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Chapter 13
Pulse-Width Modulator (S12PWM8B8CV1)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
13.2.1 PWM7 — PWM Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.2.2 PWM6 — PWM Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.2.3 PWM5 — PWM Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.2.4 PWM4 — PWM Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.2.5 PWM3 — PWM Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.2.6 PWM3 — PWM Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.2.7 PWM3 — PWM Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.2.8 PWM3 — PWM Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
13.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
13.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Chapter 14
Serial Communication Interface (S12SCIV5)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
14.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
14.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
14.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
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14.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
14.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
14.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
14.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
14.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
14.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
14.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
14.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
14.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
14.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
14.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
14.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
14.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
14.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
14.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
14.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
14.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
14.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Chapter 15
Serial Peripheral Interface (S12SPIV5)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
15.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
15.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
15.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
15.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
15.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
15.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
15.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
15.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
15.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
15.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
15.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
15.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
15.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
15.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
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15.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Chapter 16
Timer Module (TIM16B8CV2)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
16.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
16.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
16.2.1 IOC7 — Input Capture and Output Compare Channel 7 Pin . . . . . . . . . . . . . . . . . . . . 465
16.2.2 IOC6 — Input Capture and Output Compare Channel 6 Pin . . . . . . . . . . . . . . . . . . . . 465
16.2.3 IOC5 — Input Capture and Output Compare Channel 5 Pin . . . . . . . . . . . . . . . . . . . . 465
16.2.4 IOC4 — Input Capture and Output Compare Channel 4 Pin . . . . . . . . . . . . . . . . . . . . 465
16.2.5 IOC3 — Input Capture and Output Compare Channel 3 Pin . . . . . . . . . . . . . . . . . . . . 465
16.2.6 IOC2 — Input Capture and Output Compare Channel 2 Pin . . . . . . . . . . . . . . . . . . . . 465
16.2.7 IOC1 — Input Capture and Output Compare Channel 1 Pin . . . . . . . . . . . . . . . . . . . . 466
16.2.8 IOC0 — Input Capture and Output Compare Channel 0 Pin . . . . . . . . . . . . . . . . . . . . 466
16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
16.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
16.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
16.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
16.4.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
16.4.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
16.4.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
16.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
16.6.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
16.6.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
16.6.3 Pulse Accumulator Overflow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
16.6.4 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
Chapter 17
Voltage Regulator (S12VREGL3V3V1)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
17.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
17.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
17.2.1 VDDR — Regulator Power Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
17.2.2 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
17.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 492
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17.2.4 VDDF — Regulator Output2 (NVM Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
17.2.5 VDDPLL, VSSPLL — Regulator Output3 (PLL) Pins . . . . . . . . . . . . . . . . . . . . . . . . . 493
17.2.6 VDDX — Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
17.2.7 VREGEN — Optional Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
17.2.8 VREG_API — Optional Autonomous Periodical Interrupt Output Pin . . . . . . . . . . . . . . 493
17.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
17.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
17.4.2 Regulator Core (REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
17.4.3 Low-Voltage Detect (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
17.4.4 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
17.4.5 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
17.4.6 HTD - High Temperature Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
17.4.7 Regulator Control (CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
17.4.8 Autonomous Periodical Interrupt (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
17.4.9 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
17.4.10Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
17.4.11Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Chapter 18
256 KByte Flash Module (S12XFTMR256K1V1)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
18.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
18.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
18.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
18.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
18.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
18.4.2 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
18.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
18.4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
18.4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
18.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
18.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
18.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 555
18.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 556
18.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
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Chapter 19
128 KByte Flash Module (S12XFTMR128K1V1)
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
19.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
19.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
19.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
19.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
19.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
19.4.2 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
19.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
19.4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
19.4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
19.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
19.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
19.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 605
19.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 606
19.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
Chapter 20
64 KByte Flash Module (S12XFTMR64K1V1)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
20.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
20.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
20.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
20.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
20.4.2 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
20.4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
20.4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
20.4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
20.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
20.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
20.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 655
20.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 656
20.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
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Appendix A
Electrical Characteristics
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
A.1.5 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
A.1.8 Power Dissipation and Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
A.2.1 ATD Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
A.2.2 Factors Influencing Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
A.3 NVM, Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
A.3.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
A.3.2 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
A.4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
A.5 Output Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
A.5.1 Resistive Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
A.5.2 Capacitive Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
A.5.3 Chip Power-up and Voltage Drops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
A.6 Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
A.6.1 Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
A.6.2 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
A.6.3 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
A.7 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
A.8 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
A.8.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
A.8.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Appendix B
Package Information
B.1 112-pin LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
B.2 80-Pin QFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
B.3 64-Pin LQFP Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Appendix C
PCB Layout Guidelines
C.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
C.1.1 112-Pin LQFP Recommended PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
S12XS Family Reference Manual, Rev. 1.12
18 Freescale Semiconductor
C.1.2 80-Pin QFP Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
C.1.3 64-Pin LQFP Recommended PCB Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
Appendix D
Derivative Differences
D.1 Memory Sizes and Package Options S12XS family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Appendix E
Detailed Register Address Map
E.1 Detailed Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Appendix F
Ordering Information
F.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 19
Chapter 1
Device Overview S12XS Family
1.1 Introduction
The new S12XS family of 16-bit micro controllers is a compatible, reduced version of the S12XE family.
These families provide an easy approach to develop common platforms from low-end to high-end
applications, minimizing the redesign of software and hardware.
Targeted at generic automotive applications and CAN nodes, some typical examples of these applications
are: Body Controllers, Occupant Detection, Door Modules, RKE Receivers, Smart Actuators, Lighting
Modules and Smart Junction Boxes amongst many others.
The S12XS family retains many of the features of the S12XE family including Error Correction Code
(ECC) on Flash memory, a separate Data-Flash Module for code or data storage, a Frequency Modulated
Locked Loop (IPLL) that improves the EMC performance and a fast ATD converter.
S12XS family delivers 32-bit performance with all the advantages and efficiencies of a 16-bit MCU while
retaining the low cost, power consumption, EMC and code-size efficiency advantages currently enjoyed
by users of Freescale’s existing 16-bit S12 and S12X MCU families. Like members of other S12X
families, the S12XS family runs 16-bit wide accesses without wait states for all peripherals and memories.
The S12XS family is available in 112-pin LQFP, 80-pin QFP, 64-pin LQFP package options and maintains
a high level of pin compatibility with the S12XE family. In addition to the I/O ports available in each
module, up to 18 further I/O ports are available with interrupt capability allowing Wake-Up from stop or
wait modes.
The peripheral set includes MSCAN, SPI, two SCIs, an 8-channel 24-bit periodic interrupt timer, 8-
channel 16-bit Timer, 8-channel PWM and up to 16- channel 12-bit ATD converter.
Software controlled peripheral-to-port routing enables access to a flexible mix of the peripheral modules
in the lower pin count package options.
1.1.1 Features
Features of the S12XS Family are listed here. Please see Table D-1 for memory options and Table D-2 for
the peripheral features that are available on the different family members.
• 16-bit CPU12X
— Upward compatible with S12 instruction set with the exception of five Fuzzy instructions
(MEM, WAV, WAVR, REV, REVW) which have been removed
— Enhanced indexed addressing
— Access to large data segments independent of PPAGE
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
20 Freescale Semiconductor
• INT (interrupt module)
— Seven levels of nested interrupts
— Flexible assignment of interrupt sources to each interrupt level.
— External non-maskable high priority interrupt (XIRQ)
— The following inputs can act as Wake-up Interrupts
– IRQ and non-maskable XIRQ
– CAN receive pins
– SCI receive pins
– Depending on the package option up to 20 pins on ports J, H and P configurable as rising or
falling edge sensitive
• MMC (module mapping control)
• DBG (debug module)
— Monitoring of CPU bus with tag-type or force-type breakpoint requests
— 64 x 64-bit circular trace buffer captures change-of-flow or memory access information
• BDM (background debug mode)
• OSC_LCP (oscillator)
— Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal
— Good noise immunity
— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal
— Transconductance sized for optimum start-up margin for typical crystals
• IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)
— No external components required
— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)
• CRG (clock and reset generation)
— COP watchdog
— Real time interrupt
— Clock monitor
— Fast wake up from STOP in self clock mode
• Memory Options
— 64K, 128K and 256K byte Flash
— Flash General Features
– 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure
correction and double fault detection
– Erase sector size 1024 bytes
– Automated program and erase algorithm
– Protection scheme to prevent accidental program or erase
– Security option to prevent unauthorized access
– Sense-amp margin level setting for reads
— 4K and 8K byte Data Flash space
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 21
– 16 data bits plus 6 syndrome ECC (Error Correction Code) bits allow single bit failure
correction and double fault detection
– Erase sector size 256 bytes
– Automated program and erase algorithm
— 4K, 8K and 12K byte RAM
• 16-channel, 12-bit Analog-to-Digital converter
— 8/10/12 Bit resolution
—3µs, 10-bit single conversion time
— Left or right justified result data
— External and internal conversion trigger capability
— Internal oscillator for conversion in Stop modes
— Wake from low power modes on analog comparison > or <= match
— Continuous conversion mode
— Multiplexer for 16 analog input channels
— Multiple channel scans
— Pins can also be used as digital I/O
• MSCAN (1 M bit per second, CAN 2.0 A, B software compatible module)
— 1 Mbit per second, CAN 2.0 A, B software compatible module
– Standard and extended data frames
– 0 - 8 bytes data length
– Programmable bit rate up to 1 Mbps
— Five receive buffers with FIFO storage scheme
— Three transmit buffers with internal prioritization
— Flexible identifier acceptance filter programmable as:
– 2 x 32-bit
– 4 x 16-bit
– 8 x 8-bit
— Wake-up with integrated low pass filter option
— Loop back for self test
— Listen-only mode to monitor CAN bus
— Bus-off recovery by software intervention or automatically
— 16-bit time stamp of transmitted/received messages
• TIM (standard timer module)
— 8 x 16-bit channels for input capture or output compare
— 16-bit free-running counter with 8-bit precision prescaler
— 1 x 16-bit pulse accumulator
• PIT (periodic interrupt timer)
— Up to four timers with independent time-out periods
— Time-out periods selectable between 1 and 224 bus clock cycles
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
22 Freescale Semiconductor
— Time-out interrupt and peripheral triggers
— Start of timers can be aligned
• Up to 8 channel x 8-bit or 4 channel x 16-bit Pulse Width Modulator
— Programmable period and duty cycle per channel
— Center- or left-aligned outputs
— Programmable clock select logic with a wide range of frequencies
• Serial Peripheral Interface Module (SPI)
— Configurable for 8 or 16-bit data size
— Full-duplex or single-wire bidirectional
— Double-buffered transmit and receive
— Master or Slave mode
— MSB-first or LSB-first shifting
— Serial clock phase and polarity options
• Two Serial Communication Interfaces (SCI)
— Full-duplex or single wire operation
— Standard mark/space non-return-to-zero (NRZ) format
— Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
— 13-bit baud rate selection
— Programmable character length
— Programmable polarity for transmitter and receiver
— Receive wakeup on active edge
— Break detect and transmit collision detect supporting LIN
• On-Chip Voltage Regulator
— Two parallel, linear voltage regulators with bandgap reference
— Low-voltage detect (LVD) with low-voltage interrupt (LVI)
— Power-on reset (POR) circuit
— Low-voltage reset (LVR)
• Low-power wake-up timer (API)
— Internal oscillator driving a down counter
— Trimmable to +/-5% accuracy
— Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution
• Input/Output
— Up to 91 general-purpose input/output (I/O) pins depending on the package option and 2 input-
only pins
— Hysteresis and configurable pull up/pull down device on all input pins
— Configurable drive strength on all output pins
• Package Options
— 112-pin low-profile quad flat-pack (LQFP)
— 80-pin quad flat-pack (QFP)
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 23
— 64-pin low-profile quad flat-pack (LQFP)
• Operating Conditions
— Wide single Supply Voltage range 3.135 V to 5.5 V at full performance
– Separate supply for internal voltage regulator and I/O allow optimized EMC filtering
— 40MHz maximum CPU bus frequency
— Ambient temperature range –40°C to 125°C
— Temperature Options:
– –40°C to 85°C
– –40°C to 105°C
– –40°C to 125°C
1.1.2 Modes of Operation
Operating modes:
• Normal single-chip mode
• Special single-chip mode with active background debug mode
NOTE
This chip family does not support external bus modes.
Low-power modes:
• System stop modes
— Pseudo stop mode
— Full stop mode with fast wake-up option
• System wait mode
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
24 Freescale Semiconductor
1.1.3 Block Diagram
Figure 1-1 shows a block diagram of the S12XS Family devices
Figure 1-1. S12XS Family Block Diagram
4K … 12K bytes RAM
RESET
EXTAL
XTAL
4K … 8K bytes Data Flash
BKGD
VDDR
Periodic Interrupt
Clock Monitor
Single-wire Background
TEST
Voltage Regulator
Debug Module
VDD
ATD
Multilevel
Interrupt Module
PTAD
SCI0
SS
SCK
PS3
PS0
PS1
PS2
MOSI
MISO
SPI0
PTS
AN[15:0] PAD[15:0]
VDDPLL
8/10/12-bit 16-channel
Analog-Digital Converter
16-bit 8 channel
Timer
TIM
Asynchronous Serial IF
8-bit 8 channel
Pulse Width Modulator
PWM
PIT
PB[7:0]
PTB
PA[7:0]
PTA
PK[7,5:0]
PTK
XIRQ
IRQ
ECLK
PE4
PE3
PE2
PE1
PE0
PE7
PE6
PE5
PTE
VDDF
64K … 256K bytes Flash
CPU12X
Amplitude Controlled
Low Power Pierce or
Full drive Pierce
Oscillator
COP Watchdog
PLL with Frequency
Modulation option
Debug Module
4 address breakpoints
2 data breakpoints
512 Byte Trace Buffer
Reset Generation
and Test Entry
RXD
TXD
SCI1
Asynchronous Serial IF
RXD
TXD
PS7
PS4
PS5
PS6
PH3
PH0
PH1
PH2
PTH (Wake-up Int)
PH7
PH4
PH5
PH6
CAN0
PM3
PM0
PM1
PM2
PTM
msCAN 2.0B
RXCAN
TXCAN
PM7
PM4
PM5
PM6
Synchronous Serial IF
Async. Periodic Int.
4ch 24-bit Timer
PTJ (Wake-up Int)
PJ7
PJ6
PT3
PT0
PT1
PT2
PTT
PT7
PT4
PT5
PT6
PP3
PP0
PP1
PP2
PTP (Wake-Up Int)
PP7
PP4
PP5
PP6
PWM3
PWM0
PWM1
PWM2
PWM7
PWM4
PWM5
PWM6
IOC3
IOC0
IOC1
IOC2
IOC7
IOC4
IOC5
IOC6
VDDA
VSSA
VRH
VRL
PJ1
PJ0
XCLKS/ECLKX2
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 25
1.1.4 Device Memory Map
Table 1-1 shows the device register memory map.
Table 1-1. Device Register Memory Map
Address Module Size
(Bytes)
0x0000–0x0009 PIM (port integration module)10
0x000A–0x000B MMC (memory map control) 2
0x000C–0x000D PIM (port integration module) 2
0x000E–0x000F Reserved 2
0x0010–0x0017 MMC (memory map control) 8
0x0018–0x0019 Reserved 2
0x001A–0x001B Device ID register 2
0x001C–0x001F PIM (port integration module) 4
0x0020–0x002F DBG (debug module) 16
0x0030–0x0031 Reserved 2
0x0032–0x0033 PIM (port integration module) 2
0x0034–0x003F ECRG (clock and reset generator) 12
0x0040–0x006F TIM (timer module) 48
0x0070–0x00C7 Reserved 88
0x00C8–0x00CF SCI0 (serial communications interface) 8
0x00D0–0x00D7 SCI1 (serial communications interface) 8
0x00D8–0x00DF SPI0 (serial peripheral interface) 8
0x00E0–0x00FF Reserved 32
0x0100–0x0113 FTMR control registers 20
0x0114–0x011F Reserved 12
0x0120–0x012F INT (interrupt module) 16
0x0130–0x013F Reserved 16
0x0140–0x017F CAN0 64
0x0180–0x023F Reserved 192
0x0240–0x027F PIM (port integration module) 64
0x0280–0x02BF Reserved 64
0x02C0–0x02EF ATD0 (analog-to-digital converter 12 bit 16-channel) 48
0x02F0–0x02F7 Voltage regulator 8
0x02F8–0x02FF Reserved 8
0x0300–0x0327 PWM (pulse-width modulator 8 channels) 40
0x0328–0x033F Reserved 24
0x0340–0x0367 PIT (periodic interrupt timer) 40
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
26 Freescale Semiconductor
NOTE
Reserved register space shown in Table 1-1 is not allocated to any module.
This register space is reserved for future use. Writing to these locations has
no effect. Read access to these locations returns zero.
1.1.5 Address Mapping
Figure 1-2 shows S12XS CPU and BDM local address translation to the global memory map. It indicates
also the location of the internal resources in the memory map.
0x0368–0x07FF Reserved 1176
Table 1-1. Device Register Memory Map (continued)
Address Module Size
(Bytes)
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 27
Figure 1-2. S12XS Family Global Memory Map
0x7F_FFFF
0x00_0000
0x13_FFFF
0x0F_FFFF
DFLASH
RAM
0x00_07FF
RPAGE
PPAGE 0x3F_FFFF
CPU and BDM
Local Memory Map Global Memory Map
FLASH
FLASHSIZE
Unimplemented
FLASH
0xFFFF Vectors
0xC000
0x8000
Unpaged
0x4000
0x1000
0x0000
16K FLASH window
0x2000
0x0800
8K RAM
4K RAM window
2K REGISTERS
16K FLASH
Unpaged
16K FLASH
2K REGISTERS
Unimplemented
RAM
Unimplemented
Space
RAM_LOW
FLASH_LOW
RAMSIZE
DF_HIGH
DFLASH
Resources
Reserved
EPAGE
1K DFLASH window
0x0C00
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
28 Freescale Semiconductor
Accessing the reserved area in the range of 0x0C00 to 0x0FFF will return undefined data values.
A CPU access to any unimplemented space causes an illegal address reset.
The range between 0x10_0000 and 0x13_FFFF is mapped to DFLASH (Data Flash). The DFLASH block
sizes are listed in Table 1-2.
Table 1-2. Derivative Dependent Memory Parameters of Device Internal Resources
1.1.6 Detailed Register Map
The detailed register map is listed in the appendix of the reference manual.
1.1.7 Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B).
The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned part ID
number and Mask Set number.
The Version ID is a word located in a flash information row at 0x40_00E8. The version ID number
indicates a specific version of internal NVM variables used to patch NVM errata. The default is no patch
(0xFFFF).
Device FLASH_LOW SIZE/
PPAGE1
1Number of 16K pages addressable via PPAGE register
RAM_LOW SIZE/
RPAGE2
2Number of 4K pages addressing the RAM via PPAGE register
DF_HIGH SIZE/
EPAGE3
3Number of 1K pages addressing the DFLASH via the EPAGE register starting upwards from 0x00
S12XS256 0x7C_0000 256K / 16 0x0F_D000 12K / 3 0x10_1FFF 8K / 8
S12XS128 0x7E_0000 128K / 8 0x0F_E000 8K / 2 0x10_1FFF 8K / 8
S12XS64 0x7F_0000 64K / 4 0x0F_F000 4K / 1 0x10_0FFF 4K / 4
Table 1-3. Assigned Part ID Numbers
Device Mask Set Number Part ID1
1The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-6: Minor family identifier
Bit 5-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor — non full — mask set revision
Version ID
MC9S12XS256 0M05M $C0C0 0xFFFF
MC9S12XS128 0M04M $C1C0 0xFFFF
1M04M $C1C1 0xFFFF
MC9S12XS64 0M04M $C1C0 0xFFFF
1M04M $C1C1 0xFFFF
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 29
1.2 Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the
individual IP blocks on the device.
1.2.1 Device Pinout
The XS family of devices offers pin-compatible packaged devices to assist with system development and
accommodate expansion of the application.
The S12XS family devices are offered in the following package options:
• 112-pin LQFP
• 80-pin QFP
• 64-pin LQFP
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
30 Freescale Semiconductor
Figure 1-3. S12XS Family Pin Assignments 112-pin LQFP Package
VRH
VDDA
PAD15/AN15
PAD07/AN07
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VSS2
VDD
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PP4/KWP4/PWM4
PP5/KPW5/PWM5
PP6/KWP6/PWM6
PP7/KWP7/PWM7
PK7
VDDX1
VSSX1
PM0/RXCAN0/RXD1
PM1/TXCAN0/TXD1
PM2/MISO0
PM3/SS0
PM4/MOSI0
PM5/SCK0
PJ6/KWJ6
PJ7/KWJ7
TEST
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
PM6
PM7
VSSA
VRL
PWM3/KWP3/PP3
TXD1/IOC2/PWM2/KWP2/PP2
IOC1/PWM1/KWP1/PP1
RXD1/IOC0/PWM0/KWP0/PP0
PK3
PK2
PK1
PK0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDDF
VSS1
PWM4/IOC4/PT4
VREG_API/PWM5/IOC5/PT5
PWM6/IOC6/PT6
PWM7/IOC7/PT7
PK5
PK4
KWJ1/PJ1
KWJ0/PJ0
MODC/BKGD
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
KWH7/PH7
KWH6/PH6
KWH5/PH5
KWH4/PH4
XCLKS/ECLKX2/PE7
PE6
PE5
ECLK/PE4
VSSX2
VDDX2
RESET
VDDR
VSS3
VSSPLL
EXTAL
XTAL
VDDPLL
KWH3/PH3
KWH2/PH2
KWH1/PH1
KWH0/PH0
PE3
PE2
IRQ/PE1
XIRQ/PE0
PinsshowninBOLDarenot
available on the 80 QFP
package
S12XS Family
112LQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 31
Figure 1-4. S12XS Family Pin Assignments 80-pin QFP Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
VRH
VDDA
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VSS2
VDD
PA7
PA6
PA5
PA4
PA 3
PA 2
PA 1
PA 0
PB5
PB6
PB7
XCLKS/ECLKX2/PE7
PE6
PE5
ECLK/PE4
VSSX2
VDDX2
RESET
VDDR
VSS3
VSSPLL
EXTAL
XTAL
VDDPLL
PE3
PE2
IRQ/PE1
XIRQ/PE0
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
S12XS Family
80QFP
PWM3/KWP3/PP3
TXD1/IOC2/PWM2/KWP2/PP2
IOC1/PWM1/KWP1/PP1
RXD1/IOC0/PWM0/KWP0/PP0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDDF
VSS1
PWM4/IOC4/PT4
VREG_API/PWM5/IOC5/PT5
PWM6/IOC6/PT6
PWM7/IOC7/PT7
MODC/BKGD
PB0
PB1
PB2
PB3
PB4
PP4/KWP4/PWM4
PP5/KPW5/PWM5
PP7/KPW7/PWM7
VDDX1
VSSX1
PM0/RXCAN0/RXD1
PM1/TXCAN0/TXD1
PM2/MISO0
PM3/SS0
PM4/MOSI0
PM5/SCK0
PJ6/KWJ6
PJ7/KWJ7
TEST
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
VSSA
VRL
Pins shown in BOLD are
not available on the 64
QFP package
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
32 Freescale Semiconductor
Figure 1-5. S12XS Family Pin Assignments 64-pin LQFP Package
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
S12XS Family
64LQFP
VRH
VDDA
PAD07/AN07
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VSS2
VDD
PA3
PA2
PA1
PA0
PB5
PB6
PB7
XCLKS/ECLKX2/PE7
ECLK/PE4
VSSX2
VDDX2
RESET
VDDR
VSS3
VSSPLL
EXTAL
XTAL
VDDPLL
IRQ/PE1
XIRQ/PE0
PWM3/KWP3/PP3
TXD1/IOC2/PWM2/KWP2/PP2
IOC1/PWM1/KWP1/PP1
RXD1/IOC0/PWM0/KWP0/PP0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDDF
VSS1
PWM4/IOC4/PT4
VREG_API/PWM5/IOC5/PT5
PWM6/IOC6/PT6
PWM7/IOC7/PT7
MODC/BKGD
PB0
PP5/KPW5/PWM5
PP7/KWP7/PWM7
VDDX1
VSSX1
PM0/RXCAN0/RXD1
PM1/TXCAN0/TXD1
PM2/MISO0
PM3/SS0
PM4/MOSI0
PM5/SCK0
TEST
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
VSSA/VRL
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 33
1.2.2 Pin Assignment Overview
Table 1-4 provides a summary of which ports are available for each package option. Routing of pin
functions is summarized in Table 1-5.
Table 1-4. Port Availability by Package Option
Port 112 LQFP 80 QFP 64 LQFP
Port AD/ADC Channels 16/16 8/8 8/8
Port A pins 8 8 4
Port B pins 8 8 4
Port E pins inc. IRQ/XIRQ input only 8 8 4
Port H 800
Port J 420
Port K 700
Port M 866
Port P 876
Port S 844
Port T 888
Sum of Ports 91 59 44
I/O Power Pairs VDDX/VSSX 2/2 2/2 2/2
Table 1-5. Peripheral - Port Routing Options1
1“X” denotes reset condition, “O” denotes a possible rerouting
under software control
SCI1 SPI0 PWM TIM
PM[1:0] O
PM[5:2] O
PP[2,0] O
PP[2:0] O
PP[7:4] X
PS[3:2] X
PS[7:4] X
PT[2:0] X
PT[7:4] O
S12XS Family Reference Manual, Rev. 1.12
34 Freescale Semiconductor
Device Overview S12XS Family
Table 1-6 provides a pin out summary listing the availability and functionality of individual pins for each package option.
Table 1-6. Pin-Out Summary1
Package Terminal Function Power
Supply
Internal Pull
Resistor Description
LQFP
112 QFP
80 LQFP
64 Pin 2nd
Func. 3rd
Func. 4th
Func. 5th
Func. CTRL Reset
State
1 1 1 PP3 KWP3 PWM3 — — VDDX PERP/PPSP Disabled Port P I/O, interrupt,
PWM channel
2 2 2 PP2 KWP2 PWM2 IOC2 TXD1 VDDX PERP/PPSP Disabled Port P I/O, interrupt,
PWM/TIMchannel,TXD
of SCI1
3 3 3 PP1 KWP1 PWM1 IOC1 — VDDX PERP/PPSP Disabled Port P I/O, interrupt,
PWM/TIM channel
4 4 4 PP0 KWP0 PWM0 IOC0 RXD1 VDDX PERP/PPSP Disabled Port P I/O, interrupt,
PWM/TIM channel,
RXD of SCI1
5 - - PK3 — — — — VDDX PUCR Up Port K I/O
6 - - PK2 — — — — VDDX PUCR Up Port K I/O
7 - - PK1 — — — — VDDX PUCR Up Port K I/O
8 - - PK0 — — — — VDDX PUCR Up Port K I/O
9 5 5 PT0 IOC0 — — — VDDX PERT/PPST Disabled Port T I/O, TIM channel
10 6 6 PT1 IOC1 — — — VDDX PERT/PPST Disabled Port T I/O, TIM channel
11 7 7 PT2 IOC2 — — — VDDX PERT/PPST Disabled Port T I/O, TIM channel
12 8 8 PT3 IOC3 — — — VDDX PERT/PPST Disabled Port T I/O, TIM channel
13 9 9 VDDF — — — — — — — —
14 10 10 VSS1 — — — — — — — —
15 11 11 PT4 IOC4 PWM4 — — VDDX PERT/PPST Disabled Port T I/O, PWM/TIM
channel
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 35
16 12 12 PT5 IOC5 PWM5 VREG_
API —V
DDX PERT/PPST Disabled Port T I/O, PWM/TIM
channel, API output
17 13 13 PT6 IOC6 PWM6 — — VDDX PERT/PPST Disabled Port T I/O, channel of
PWM/TIM
18 14 14 PT7 IOC7 PWM7 — — VDDX PERT/PPST Disabled Port T I/O, channel of
PWM/TIM
19 - - PK5 — — — — VDDX PUCR Up Port K I/O
20 - - PK4 — — — — VDDX PUCR Up Port K I/O
21 - - PJ1 KWJ1 — — — VDDX PERJ/PPSJ Up Port J I/O, interrupt
22 - - PJ0 KWJ0 — — — VDDX PERJ/PPSJ Up Port J I/O, interrupt
23 15 15 BKGD MODC — — — VDDX Always on Up Background debug
24 16 16 PB0 — — — — VDDX PUCR Disabled Port B I/O
25 17 - PB1 — — — — VDDX PUCR Disabled Port B I/O
26 18 - PB2 — — — — VDDX PUCR Disabled Port B I/O
27 19 - PB3 — — — — VDDX PUCR Disabled Port B I/O
28 20 - PB4 — — — — VDDX PUCR Disabled Port B I/O
29 21 17 PB5 — — — — VDDX PUCR Disabled Port B I/O
30 22 18 PB6 — — — — VDDX PUCR Disabled Port B I/O
31 23 19 PB7 — — — — VDDX PUCR Disabled Port B I/O
32 - - PH7 KWH7 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt
33 - - PH6 KWH6 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt
34 - - PH5 KWH5 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt
35 - - PH4 KWH4 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt
Table 1-6. Pin-Out Summary1 (continued)
Package Terminal Function Power
Supply
Internal Pull
Resistor Description
LQFP
112 QFP
80 LQFP
64 Pin 2nd
Func. 3rd
Func. 4th
Func. 5th
Func. CTRL Reset
State
S12XS Family Reference Manual, Rev. 1.12
36 Freescale Semiconductor
Device Overview S12XS Family
36 24 20 PE7 XCLKS ECLKX2 — — VDDX PUCR Up Port E I/O, system clock
output, clock select
input
37 25 - PE6 — — — — VDDX While RESET pin
is low: down2Port E I/O
38 26 - PE5 — — — — VDDX While RESET pin
is low: down2Port E I/O
39 27 21 PE4 ECLK — — — VDDX PUCR Up Port E I/O, bus clock
output
40 28 22 VSSX2 — — — — — — — —
41 29 23 VDDX2 — — — — — — — —
42 30 24 RESET — — — — VDDX PULLUP External reset
43 31 25 VDDR — — — — — — — —
44 32 26 VSS3 — — — — — — — —
45 33 27 VSSPLL — — — — — — — —
46 34 28 EXTAL — — — — VDDPLL NA NA Oscillator pin
47 35 29 XTAL — — — — VDDPLL NA NA Oscillator pin
48 36 30 VDDPLL — — — — — — — —
49 - - PH3 KWH3 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt
50 - - PH2 KWH2 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt
51 - - PH1 KWH1 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt
52 - - PH0 KWH0 — — — VDDX PERH/PPSH Disabled Port H I/O, interrupt
53 37 - PE3 — — — — VDDX PUCR Up Port E I/O
54 38 - PE2 — — — — VDDX PUCR Up Port E I/O
Table 1-6. Pin-Out Summary1 (continued)
Package Terminal Function Power
Supply
Internal Pull
Resistor Description
LQFP
112 QFP
80 LQFP
64 Pin 2nd
Func. 3rd
Func. 4th
Func. 5th
Func. CTRL Reset
State
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 37
55 39 31 PE1 IRQ — — — VDDX PUCR Up Port E Input, maskable
interrupt
56 40 32 PE0 XIRQ — — — VDDX PUCR Up Port E Input, non-
maskable interrupt
57 41 33 PA0 — — — — VDDX PUCR Disabled Port A I/O
58 42 34 PA1 — — — — VDDX PUCR Disabled Port A I/O
59 43 35 PA2 — — — — VDDX PUCR Disabled Port A I/O
60 44 36 PA3 — — — — VDDX PUCR Disabled Port A I/O
61 45 - PA4 — — — — VDDX PUCR Disabled Port A I/O
62 46 - PA5 — — — — VDDX PUCR Disabled Port A I/O
63 47 - PA6 — — — — VDDX PUCR Disabled Port A I/O
64 48 - PA7 — — — — VDDX PUCR Disabled Port A I/O
65 49 37 VDD — — — — — — — —
66 50 38 VSS2 — — — — — — — —
67 51 39 PAD00 AN00 — — — VDDA PER1AD Disabled Port AD I/O,
analog input of ATD
68 - - PAD08 AN08 — — — VDDA PER0AD Disabled Port AD I/O,
analog input of ATD
69 52 40 PAD01 AN01 — — — VDDA PER1AD Disabled Port AD I/O,
analog input of ATD
70 - - PAD09 AN09 — — — VDDA PER0AD Disabled Port AD I/O,
analog input of ATD
71 53 41 PAD02 AN02 — — — VDDA PER1AD Disabled Port AD I/O,
analog input of ATD
Table 1-6. Pin-Out Summary1 (continued)
Package Terminal Function Power
Supply
Internal Pull
Resistor Description
LQFP
112 QFP
80 LQFP
64 Pin 2nd
Func. 3rd
Func. 4th
Func. 5th
Func. CTRL Reset
State
S12XS Family Reference Manual, Rev. 1.12
38 Freescale Semiconductor
Device Overview S12XS Family
72 - - PAD10 AN10 — — — VDDA PER0AD Disabled Port AD I/O,
analog input of ATD
73 54 42 PAD03 AN03 — — — VDDA PER1AD Disabled Port AD I/O,
analog input of ATD
74 - - PAD11 AN11 — — — VDDA PER0AD Disabled Port AD I/O,
analog input of ATD
75 55 43 PAD04 AN04 — — — VDDA PER1AD Disabled Port AD I/O,
analog input of ATD
76 - - PAD12 AN12 — — — VDDA PER0AD Disabled Port AD I/O,
analog input of ATD
77 56 44 PAD05 AN05 — — — VDDA PER1AD Disabled Port AD I/O,
analog input of ATD
78 - - PAD13 AN13 — — — VDDA PER0AD Disabled Port AD I/O,
analog input of ATD
79 57 45 PAD06 AN06 — — — VDDA PER1AD Disabled Port AD I/O,
analog input of ATD
80 - - PAD14 AN14 — — — VDDA PER0AD Disabled Port AD I/O,
analog input of ATD
81 58 46 PAD07 AN07 — — — VDDA PER1AD Disabled Port AD I/O,
analog input of ATD
82 - - PAD15 AN15 — — — VDDA PER0AD Disabled Port AD I/O,
analog input of ATD
83 59 47 VDDA — — — — — — — —
84 60 48 VRH — — — — — — — —
85 61 49 VRL3————— — — —
86 62 49 VSSA — — — — — — — —
Table 1-6. Pin-Out Summary1 (continued)
Package Terminal Function Power
Supply
Internal Pull
Resistor Description
LQFP
112 QFP
80 LQFP
64 Pin 2nd
Func. 3rd
Func. 4th
Func. 5th
Func. CTRL Reset
State
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 39
87 - - PM7 — — — — VDDX PERM/PPSM Disabled Port M I/O
88 - - PM6 — — — — VDDX PERM/PPSM Disabled Port M I/O
89 63 50 PS0 RXD0 — — — VDDX PERS/PPSS Up Port S I/O, RXD of SCI0
90 64 51 PS1 TXD0 — — — VDDX PERS/PPSS Up Port S I/O, TXD of SCI0
91 65 52 PS2 RXD1 — — — VDDX PERS/PPSS Up Port S I/O, RXD of SCI1
92 66 53 PS3 TXD1 — — — VDDX PERS/PPSS Up Port S I/O, TXD of SCI1
93 - - PS4 MISO0 — — — VDDX PERS/PPSS Up Port S I/O, MISO of SPI0
94 - - PS5 MOSI0 — — — VDDX PERS/PPSS Up Port S I/O, MOSI of SPI0
95 - - PS6 SCK0 — — — VDDX PERS/PPSS Up Port S I/O, SCK of SPI0
96 - - PS7 SS0 — — — VDDX PERS/PPSS Up Port S I/O, SS of SPI0
97 67 54 TEST — — — — N.A. RESET pin DOWN Test input
98 68 - PJ7 KWJ7 — — — VDDX PERJ/PPSJ Up Port J I/O, interrupt
99 69 - PJ6 KWJ6 — — — VDDX PERJ/PPSJ Up Port J I/O, interrupt
100 70 55 PM5 SCK0 — — — VDDX PERM/PPSM Disabled Port M I/O, SCK of SPI0
101 71 56 PM4 MOSI0 — — — VDDX PERM/PPSM Disabled Port M I/O, MOSI of
SPI0
102 72 57 PM3 SS0 — — — VDDX PERM/PPSM Disabled Port M I/O, SS of SPI0
103 73 58 PM2 MISO0 — — — VDDX PERM/PPSM Disabled Port M I/O, MISO of
SPI0
104 74 59 PM1 TXCAN0 TXD1 — — VDDX PERM/PPSM Disabled Port M I/O, TX of CAN0,
TXD of SCI1
105 75 60 PM0 RXCAN0 RXD1 — — VDDX PERM/PPSM Disabled Port M I/O, RX of CAN0,
RXD of SCI1
Table 1-6. Pin-Out Summary1 (continued)
Package Terminal Function Power
Supply
Internal Pull
Resistor Description
LQFP
112 QFP
80 LQFP
64 Pin 2nd
Func. 3rd
Func. 4th
Func. 5th
Func. CTRL Reset
State
S12XS Family Reference Manual, Rev. 1.12
40 Freescale Semiconductor
Device Overview S12XS Family
106 76 61 VSSX1 — — — — — — — —
107 77 62 VDDX1 — — — — — — — —
108 - - PK7 — — — — VDDX PUCR Up Port K I/O
109 78 63 PP7 KWP7 PWM7 — — VDDX PERP/PPSP Disabled Port P I/O, interrupt,
PWM channel
110 - - PP6 KWP6 PWM6 — — VDDX PERP/PPSP Disabled Port P I/O, interrupt,
PWM channel
111 79 64 PP5 KWP5 PWM5 — — VDDX PERP/PPSP Disabled Port P I/O, interrupt,
PWM channel
112 80 - PP4 KWP4 PWM4 — — VDDX PERP/PPSP Disabled Port P I/O, interrupt,
PWM channel
1Table shows a superset of pin functions. Not all functions are available on all derivatives
2For compatibility to XE family
3VRL and VSSA share single pin on 64 package option
Table 1-6. Pin-Out Summary1 (continued)
Package Terminal Function Power
Supply
Internal Pull
Resistor Description
LQFP
112 QFP
80 LQFP
64 Pin 2nd
Func. 3rd
Func. 4th
Func. 5th
Func. CTRL Reset
State
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 41
1.2.3 Detailed Signal Descriptions
NOTE
The pin list of the largest package version of each S12XS Family derivative
gives the complete of interface signals that also exist on smaller package
options, although some of them are not bonded out. For devices assembled
in smaller packages all non-bonded out pins should be configured as outputs
after reset in order to avoid current drawn from floating inputs. Refer to
Table 1-6 for affected pins.
1.2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the oscillator output.
1.2.3.2 RESET — External Reset Pin
The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a
known start-up state. As an output it is driven low to indicate when any internal MCU reset source triggers.
The RESET pin has an internal pull-up device.
1.2.3.3 TEST — Test Pin
This input only pin is reserved for factory test. This pin has a pull-down device.
NOTE
The TEST pin must be tied to VSS in all applications.
1.2.3.4 BKGD / MODC — Background Debug and Mode Pin
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET. The BKGD pin has an internal pull-up device.
1.2.3.5 PAD[15:0] / AN[15:0] — Port AD Input Pins of ATD0
PAD[15:0] are general-purpose input or output pins and analog inputs AN[15:0] of the analog-to-digital
converter ATD0.
1.2.3.6 PA[7:0] — Port A I/O Pins
PA[7:0] are general-purpose input or output pins.
1.2.3.7 PB[7:0] — Port B I/O Pins
PB[7:0] are general-purpose input or output pins.
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
42 Freescale Semiconductor
1.2.3.8 PE7 / ECLKX2 / XCLKS — Port E I/O Pin 7
PE7 is a general-purpose input or output pin. ECLKX2 is a clock output of twice the internal bus
frequency. The XCLKS is an input signal which controls whether a crystal in combination with the internal
loop controlled Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is
used (refer to Section 1.10 Oscillator Configuration). An internal pull-up is enabled during reset.
1.2.3.9 PE[6:5] — Port E I/O Pin 6-5
PE[6:5] are a general-purpose input or output pins.
1.2.3.10 PE4 / ECLK — Port E I/O Pin 4
PE4 is a general-purpose input or output pin. It can be configured to output the internal bus clock ECLK.
ECLK can be used as a timing reference. The ECLK output has a programmable prescaler.
1.2.3.11 PE[3:2] — Port E I/O Pin 3
PE[3:2] are a general-purpose input or output pins.
1.2.3.12 PE1 / IRQ — Port E Input Pin 1
PE1 is a general-purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode.
1.2.3.13 PE0 / XIRQ — Port E Input Pin 0
PE0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode. The XIRQ
interrupt is level sensitive and active low. As XIRQ is level sensitive, while this pin is low the MCU will
not enter STOP mode.
1.2.3.14 PH[7:0] / KWH[7:0] — Port H I/O Pins
PH[7:0] are a general-purpose input or output pins. They can be configured as keypad wakeup inputs.
1.2.3.15 PJ[7:6] / KWJ[7:6] — PORT J I/O Pins 7-6
PJ[7:6] are a general-purpose input or output pins. They can be configured as keypad wakeup inputs.
1.2.3.16 PJ[1:0] / KWJ[1:0] — PORT J I/O Pins 1-0
PJ[1:0] are a general-purpose input or output pins. They can be configured as keypad wakeup inputs.
1.2.3.17 PK[7,5:0] — Port K I/O Pins 7 and 5-0
PK[7,5:0] are a general-purpose input or output pins.
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 43
1.2.3.18 PM[7:6] — Port M I/O Pins 7-6
PM[7:6] are a general-purpose input or output pins.
1.2.3.19 PM5 / SCK0 — Port M I/O Pin 5
PM5 is a general-purpose input or output pin. It can be configured as the serial clock pin SCK of the serial
peripheral interface 0 (SPI0).
1.2.3.20 PM4 / MOSI0 — Port M I/O Pin 4
PM4 is a general-purpose input or output pin. It can be configured as the master output (during master
mode) or slave input pin (during slave mode) MOSI for the serial peripheral interface 0 (SPI0).
1.2.3.21 PM3 / SS0 — Port M I/O Pin 3
PM3 is a general-purpose input or output pin. It can be configured as the slave select pin SS of the serial
peripheral interface 0 (SPI0).
1.2.3.22 PM2 / MISO0 — Port M I/O Pin 2
PM2 is a general-purpose input or output pin. It can be configured as the master input (during master
mode) or slave output pin (during slave mode) MISO for the serial peripheral interface 0 (SPI0).
1.2.3.23 PM1 / TXCAN0 / TXD1 — Port M I/O Pin 1
PM1 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the
scalable controller area network controller 0 (CAN0). It can be configured as the transmit pin TXD of
serial communication interface 1 (SCI1).
1.2.3.24 PM0 / RXCAN0 / RXD1 — Port M I/O Pin 0
PM0 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN of the
scalable controller area network controller 0 (CAN0). It can be configured as the receive pin RXD of serial
communication interface 1 (SCI1).
1.2.3.25 PP7 / KWP7 / PWM7 — Port P I/O Pin 7
PP7 is a general-purpose input or output pin. It can be configured as keypad wakeup input. It can be
configured as pulse width modulator (PWM) channel 7 output or emergency shutdown input.
1.2.3.26 PP[6:3] / KWP[6:3] / PWM[6:3] — Port P I/O Pins 6-3
PP[6:3] are a general-purpose input or output pins. They can be configured as keypad wakeup inputs. They
can be configured as pulse width modulator (PWM) channel 6-3 output.
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
44 Freescale Semiconductor
1.2.3.27 PP2 / KWP2 / PWM2 / TXD1 / IOC2 — Port P I/O Pin 2
PP2 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as pulse width modulator (PWM) channel 2 output, TIM channel 2 or as the transmit pin TXD
of serial communication interface 1 (SCI1).
1.2.3.28 PP1 / KWP1 / PWM1 / IOC1 — Port P I/O Pin 1
PP1 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as pulse width modulator (PWM) channel 1 output, TIM channel 1.
1.2.3.29 PP0 / KWP0 / PWM0 / RXD1 / IOC0 — Port P I/O Pin 0
PP0 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as pulse width modulator (PWM) channel 0 output, TIM channel 0 or as the receive pin RXD
of serial communication interface 1 (SCI1).
1.2.3.30 PS7 / SS0 — Port S I/O Pin 7
PS7 is a general-purpose input or output pin. It can be configured as the slave select pin SS of the serial
peripheral interface 0 (SPI0).
1.2.3.31 PS6 / SCK0 — Port S I/O Pin 6
PS6 is a general-purpose input or output pin. It can be configured as the serial clock pin SCK of the serial
peripheral interface 0 (SPI0).
1.2.3.32 PS5 / MOSI0 — Port S I/O Pin 5
PS5 is a general-purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the serial peripheral interface 0 (SPI0).
1.2.3.33 PS4 / MISO0 — Port S I/O Pin 4
PS4 is a general-purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI of the serial peripheral interface 0 (SPI0).
1.2.3.34 PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial
communication interface 1 (SCI1).
1.2.3.35 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial
communication interface 1 (SCI1).
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 45
1.2.3.36 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial
communication interface 0 (SCI0).
1.2.3.37 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial
communication interface 0 (SCI0).
1.2.3.38 PT[7:6] / IOC[7:6] / PWM[7:6] — Port T I/O Pins 7-6
PT[7:6] are general-purpose input or output pins. They can be configured as timer (TIM) channel 7-6 or
pulse width modulator (PWM) outputs 7-6
1.2.3.39 PT5 / IOC5 / VREG_API — Port T I/O Pin 5
PT[5] is a general-purpose input or output pin. It can be configured as timer (TIM) channel 5, pulse width
modulator (PWM) output 5 or as the VREG_API signal output.
1.2.3.40 PT4 / IOC4 / PWM4 — Port T I/O Pin 4
PT4 is a general-purpose input or output pin. It can be configured as timer (TIM) channel 4 or pulse width
modulator (PWM) output 4.
1.2.3.41 PT[3:0] / IOC[3:0] — Port T I/O Pin [3:0]
PT[3:0] are a general-purpose input or output pins. They can be configured as timer (TIM) channels 3-0.
1.2.4 Power Supply Pins
S12XS Family power and ground pins are described below.
Because fast signal transitions place high, short-duration current demands on the power supply, use bypass
capacitors with high-frequency characteristics and place them as close to the MCU as possible.
NOTE
All VSS pins must be connected together in the application.
1.2.4.1 VDDX[2:1], VSSX[2:1] — Power and Ground Pins for I/O Drivers
External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are
loaded. All VDDX pins are connected together internally. All VSSX pins are connected together internally.
1.2.4.2 VDDR — Power Pin for Internal Voltage Regulator
Power supply input to the internal voltage regulator.
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
46 Freescale Semiconductor
1.2.4.3 VDD, VSS2, VSS3 — Core Power Pins
The voltage supply of nominally 1.8 V is derived from the internal voltage regulator. The return current
path is through the VSS2 and VSS3 pins. No static external loading of these pins is permitted.
1.2.4.4 VDDF, VSS1 — NVM Power Pins
The voltage supply of nominally 2.8 V is derived from the internal voltage regulator. The return current
path is through the VSS1 pin. No static external loading of these pins is permitted.
1.2.4.5 VDDA, VSSA — Power Supply Pins for ATD and Voltage Regulator
These are the power supply and ground input pins for the analog-to-digital converters and the voltage
regulator.
1.2.4.6 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog-to-digital converter.
1.2.4.7 VDDPLL, VSSPLL — Power Supply Pins for PLL
These pins provide operating voltage and ground for the oscillator and the phased-locked loop. The voltage
supply of nominally 1.8 V is derived from the internal voltage regulator. This allows the supply voltage to
the oscillator and PLL to be bypassed independently. This voltage is generated by the internal voltage
regulator. No static external loading of these pins is permitted.
Table 1-7. Power and Ground Connection Summary
Mnemonic Nominal
Voltage Description
VDDR 5.0 V External power supply to internal voltage
regulator
VDDX[2:1] 5.0 V External power and ground, supply to pin
drivers
VSSX[2:1] 0 V
VDDA 5.0 V Operating voltage and ground for the
analog-to-digital converters and the
reference for the internal voltage regulator,
allows the supply voltage to the A/D to be
bypassed independently.
VSSA 0 V
VRL 0 V Referencevoltagesfor the analog-to-digital
converter.
VRH 5.0 V
VDD 1.8 V Internal power and ground generated by
internal regulator for the internal core.
VSS1, VSS2,
VSS3 0 V
VDDF 2.8 V Internal power and ground generated by
internal regulator for the internal NVM.
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
47 Freescale Semiconductor
VDDPLL 1.8 V Provides operating voltage and ground for
the phased-locked loop. This allows the
supply voltage to the PLL to be bypassed
independently. Internal power and ground
generated by internal regulator.
VSSPLL 0 V
Table 1-7. Power and Ground Connection Summary
Mnemonic Nominal
Voltage Description
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
48 Freescale Semiconductor
1.3 System Clock Description
The clock and reset generator module (CRG) provides the internal clock signals for the core and all
peripheral modules. Figure 1-6 shows the clock connections from the CRG to all modules.
Consult the S12XECRG section for details on clock generation.
NOTE
The XS family uses the XE family clock and reset generator module.
Therefore all CRG references are related to S12XECRG.
Figure 1-6. Clock Connections
The system clock can be supplied in several ways enabling a range of system operating frequencies to be
supported:
• The on-chip phase locked loop (PLL)
• the PLL self clocking
• the oscillator
SCI0 . . SCI 1
SPI0
ATD0
CAN0
CRG
Bus Clock
EXTAL
XTAL
Core Clock
Oscillator Clock
RAM S12X FLASH
PIT
TIM
PIM
PWM
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 49
The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and
bus clock. As shown in Figure 1-6, these system clocks are used throughout the MCU to drive the core,
the memories, and the peripherals.
The program Flash memory is supplied by the bus clock and the oscillator clock. The oscillator clock is
used as a time base to derive the program and erase times for the NVMs.
The CAN modules may be configured to have their clock sources derived either from the bus clock or
directly from the oscillator clock. This allows the user to select its clock based on the required jitter
performance.
In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the
output of the oscillator. The clock monitor can be configured to invoke the PLL self-clocking mode or to
generate a system reset if it is allowed to time out as a result of no oscillator clock being present.
In addition to the clock monitor, the MCU also provides a clock quality checker which performs a more
accurate check of the clock. The clock quality checker counts a predetermined number of clock edges
within a defined time window to insure that the clock is running. The checker can be invoked following
specific events such as on wake-up or clock monitor failure.
1.4 Modes of Operation
The MCU can operate in different modes. These are described in 1.4.1 Chip Configuration Summary.
The MCU can operate in different power modes to facilitate power saving when full system performance
is not required. These are described in 1.4.2 Power Modes.
Some modules feature a software programmable option to freeze the module status whilst the background
debug module is active to facilitate debugging. This is described in 1.4.3 Freeze Mode.
1.4.1 Chip Configuration Summary
The different modes and the security state of the MCU affect the debug features (enabled or disabled).
The operating mode out of reset is determined by the state of the MODC signal during reset (see Table 1-
8). The MODC bit in the MODE register shows the current operating mode and provides limited mode
switching during operation. The state of the MODC signal is latched into this bit on the rising edge of
RESET.
1.4.1.1 Normal Single-Chip Mode
This mode is intended for normal device operation. The opcode from the on-chip memory is being
executed after reset (requires the reset vector to be programmed correctly). The processor program is
executed from internal memory.
Table 1-8. Chip Modes
Chip Modes MODC
Normal single chip 1
Special single chip 0
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
50 Freescale Semiconductor
1.4.1.2 Special Single-Chip Mode
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The
background debug module BDM is active in this mode. The CPU executes a monitor program located in
an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin.
1.4.2 Power Modes
The MCU features two main low-power modes. Consult the respective section for module specific
behavior in system stop, system pseudo stop, and system wait mode. An important source of information
about the clock system is the Clock and Reset Generator section (CRG).
1.4.2.1 System Stop Modes
The system stop modes are entered if the CPU executes the STOP instruction unless an NVM command
is active. Depending on the state of the PSTP bit in the CLKSEL register the MCU goes into pseudo stop
mode or full stop mode. Please refer to CRG section. Asserting RESET, XIRQ, IRQ or any other interrupt
that is not masked exits system stop modes. System stop modes can be exited by CPU activity, depending
on the configuration of the interrupt request.
If the CPU executes the STOP instruction whilst an NVM command is being processed, then the system
clocks continue running until NVM activity is completed. If a non-masked interrupt occurs within this time
then the system does not effectively enter stop mode although the STOP instruction has been executed.
1.4.2.2 Full Stop Mode
The oscillator is stopped in this mode. By default all clocks are switched off and all counters and dividers
remain frozen. The Autonomous Periodic Interrupt (API) and ATD module may be enabled to self wake
the device. A Fast wake up mode is available to allow the device to wake from Full Stop mode immediately
on the PLL internal clock without starting the oscillator clock.
1.4.2.3 Pseudo Stop Mode
In this mode the system clocks are stopped but the oscillator is still running and the real time interrupt
(RTI) and watchdog (COP), API and ATD modules may be enabled. Other peripherals are turned off. This
mode consumes more current than system stop mode but, as the oscillator continues to run, the full speed
wake up time from this mode is significantly shorter.
1.4.2.4 Wait Mode
This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU clock is switched off. All peripherals can be active in system wait mode.
For further power consumption the peripherals can individually turn off their local clocks. Asserting
RESET, XIRQ, IRQ or any other interrupt that is not masked ends system wait mode.
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 51
1.4.2.5 Run Mode
Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save
power.
1.4.3 Freeze Mode
The timer module, pulse width modulator, analog-to-digital converters, and the periodic interrupt timer
provide a software programmable option to freeze the module status when the background debug module
is active. This is useful when debugging application software. For detailed description of the behavior of
the ATD, TIM, PWM, and PIT when the background debug module is active consult the corresponding
section.
1.5 Security
The MCU security mechanism prevents unauthorized access to the Flash memory. For a detailed
description of the security features refer to the S12XS9SEC section.
1.6 Resets and Interrupts
Consult the CPU12/CPU12X Reference Manual and the S12XINT section for information on exception
processing.
NOTE
When referring to the S12XINT section please be aware that the XS family
neither features an XGATE nor an MPU module.
1.6.1 Resets
Resets are explained in detail in the Clock Reset Generator (S12XECRG) section.
Table 1-9. Reset Sources and Vector Locations
1.6.2 Vectors
Table 1-10 lists all interrupt sources and vectors in the default order of priority. The interrupt module
(S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each
Vector Address Reset Source CCR
Mask Local Enable
$FFFE Power-On Reset (POR) None None
$FFFE Low Voltage Reset (LVR) None None
$FFFE External pin RESET None None
$FFFE Illegal Address Reset None None
$FFFC Clock monitor reset None PLLCTL (CME, SCME)
$FFFA COP watchdog reset None COP rate select
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
52 Freescale Semiconductor
I-bit maskable service request is a configuration register. It selects if the service request is enabled and the
service request priority level.
Table 1-10. Interrupt Vector Locations (Sheet 1 of 2)
Vector Address1Interrupt Source CCR
Mask Local Enable STOP
Wake up WAIT
Wake up
Vector base + $F8 Unimplemented instruction trap None None — —
Vector base+ $F6 SWI None None — —
Vector base+ $F4 XIRQ X Bit None Yes Yes
Vector base+ $F2 IRQ I bit IRQCR (IRQEN) Yes Yes
Vector base+ $F0 Real time interrupt I bit CRGINT (RTIE) Refer to CRG
interrupt section
Vector base+ $EE TIM timer channel 0 I bit TIE (C0I) No Yes
Vector base + $EC TIM timer channel 1 I bit TIE (C1I) No Yes
Vector base+ $EA TIM timer channel 2 I bit TIE (C2I) No Yes
Vector base+ $E8 TIM timer channel 3 I bit TIE (C3I) No Yes
Vector base+ $E6 TIM timer channel 4 I bit TIE (C4I) No Yes
Vector base+ $E4 TIM timer channel 5 I bit TIE (C5I) No Yes
Vector base + $E2 TIM timer channel 6 I bit TIE (C6I) No Yes
Vector base+ $E0 TIM timer channel 7 I bit TIE (C7I) No Yes
Vector base+ $DE TIM timer overflow I bit TSRC2 (TOF) No Yes
Vector base+ $DC TIM Pulse accumulator A overflow I bit PACTL (PAOVI) No Yes
Vector base + $DA TIM Pulse accumulator input edge I bit PACTL (PAI) No Yes
Vector base + $D8 SPI0 I bit SPI0CR1 (SPIE, SPTIE) No Yes
Vector base+ $D6 SCI0 I bit SCI0CR2
(TIE, TCIE, RIE, ILIE) Yes Yes
Vector base + $D4 SCI1 I bit SCI1CR2
(TIE, TCIE, RIE, ILIE) Yes Yes
Vector base + $D2 ATD0 I bit ATD0CTL2 (ASCIE) Yes Yes
Vector base + $D0 Reserved
Vector base + $CE Port J I bit PIEJ (PIEJ7-PIEJ0) Yes Yes
Vector base + $CC Port H I bit PIEH (PIEH7-PIEH0) Yes Yes
Vector base + $CA Reserved
Vector base + $C8 Reserved
Vector base + $C6 CRG PLL lock I bit CRGINT(LOCKIE) Refer to CRG
interrupt section
Vector base + $C4 CRG self-clock mode I bit CRGINT (SCMIE) Refer to CRG
interrupt section
Vector base + $C2
to
Vector base + $BC Reserved
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 53
1.6.3 Effects of Reset
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections
for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers.
Vector base + $BA FLASH Fault Detect I bit FCNFG2 (SFDIE, DFDIE) No No
Vector base + $B8 FLASH I bit FCNFG (CCIE) No Yes
Vector base + $B6 CAN0 wake-up I bit CAN0RIER (WUPIE) Yes Yes
Vector base + $B4 CAN0 errors I bit CAN0RIER (CSCIE,
OVRIE) No Yes
Vector base + $B2 CAN0 receive I bit CAN0RIER (RXFIE) No Yes
Vector base + $B0 CAN0 transmit I bit CAN0TIER (TXEIE[2:0]) No Yes
Vector base + $AE
to
Vector base + $90 Reserved
Vector base + $8E Port P Interrupt I bit PIEP (PIEP7-PIEP0) Yes Yes
Vector base+ $8C PWM emergency shutdown I bit PWMSDN (PWMIE) No Yes
Vector base + $8A
to
Vector base + $82 Reserved
Vector base + $80 Low-voltage interrupt (LVI) I bit VREGCTRL (LVIE) No Yes
Vector base + $7E Autonomous periodical interrupt (API) I bit VREGAPICTRL (APIE) Yes Yes
Vector base + $7C High Temperature Interrupt (HTI) I bit VREGHTCL (HTIE) No Yes
Vector base + $7A Periodic interrupt timer channel 0 I bit PITINTE (PINTE0) No Yes
Vector base + $78 Periodic interrupt timer channel 1 I bit PITINTE (PINTE1) No Yes
Vector base + $76 Periodic interrupt timer channel 2 I bit PITINTE (PINTE2) No Yes
Vector base + $74 Periodic interrupt timer channel 3 I bit PITINTE (PINTE3) No Yes
Vector base + $72
to
Vector base + $40 Reserved
Vector base + $3E ATD0 Compare Interrupt I bit ATD0CTL2 (ACMPIE) Yes Yes
Vector base + $3C
to
Vector base + $14 Reserved
Vector base + $12 System Call Interrupt (SYS) — None — —
Vector base + $10 Spurious interrupt — None — —
116 bits vector address based
Table 1-10. Interrupt Vector Locations (Sheet 2 of 2)
Vector Address1Interrupt Source CCR
Mask Local Enable STOP
Wake up WAIT
Wake up
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
54 Freescale Semiconductor
1.6.3.1 Flash Configuration Reset Sequence Phase
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the Flash module section.
1.6.3.2 Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.6.3.3 I/O Pins
Refer to the PIM section for reset configurations of all peripheral module ports.
1.6.3.4 Memory
The RAM arrays are not initialized out of reset.
1.6.3.5 COP Configuration
The COP time-out rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded from the Flash
register FOPT. See Table 1-11 and Table 1-12 for coding. The FOPT register is loaded from the Flash
configuration field byte at global address $7FFF0E during the reset sequence.
If the MCU is secured the COP time-out rate is always set to the longest period (CR[2:0] = 111) after any
reset into Special Single Chip mode.
Table 1-11. Initial COP Rate Configuration
NV[2:0] in
FOPT Register CR[2:0] in
COPCTL Register
000 111
001 110
010 101
011 100
100 011
101 010
110 001
111 000
Table 1-12. Initial WCOP Configuration
NV[3] in
FOPT Register WCOP in
COPCTL Register
10
01
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 55
1.7 ATD0 Configuration
1.7.1 External Trigger Input Connection
The ATD module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The
external trigger allows the user to synchronize ATD conversion to external trigger events. Table 1-13
shows the connection of the external trigger inputs.
Consult the ATD section for information about the analog-to-digital converter module. References to
freeze mode are equivalent to active BDM mode.
1.7.2 ATD0 Channel[17] Connection
Further to the 16 externally available channels, ATD0 features an extra channel[17] that is connected to
the internal temperature sensor at device level. To access this channel ATD0 must use the channel encoding
SC:CD:CC:CB:CA = 1:0:0:0:1 in ATDCTL5. For more temperature sensor information, please refer to
1.8.1 Temperature Sensor Configuration.
1.8 VREG Configuration
The device must be configured with the internal voltage regulator enabled. Operation in conjunction with
an external voltage regulator is not supported.
The API trimming register APITR is loaded from the Flash IFR option field at global address 0x40_00F0
bits[5:0] during the reset sequence. Currently factory programming of this IFR range is not supported.
Read access to reserved VREG register space returns “0”. Write accesses have no effect. This device does
not support access abort of reserved VREG register space.
1.8.1 Temperature Sensor Configuration
The VREG high temperature trimming register bits VREGHTTR[3:0] are loaded from the internal Flash
during the reset sequence. To use the high temperature interrupt within the specified limits (THTIA and
THTID) these bits must be loaded with 0x8. Currently factory programming is not supported.
The device temperature can be monitored on ATD0 channel[17]. The internal bandgap reference voltage
can also be mapped to ATD0 analog input channel[17]. The voltage regulator VSEL bit when set, maps
the bandgap and, when clear, maps the temperature sensor to ATD0 channel[17].
Table 1-13. ATD0 External Trigger Sources
ExternalTrigger
Input Connectivity
ETRIG0 Pulse width modulator channel 1
ETRIG1 Pulse width modulator channel 3
ETRIG2 Periodic interrupt timer hardware trigger 0
ETRIG3 Periodic interrupt timer hardware trigger 1
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
56 Freescale Semiconductor
1.9 BDM Clock Configuration
The BDM alternate clock source is the oscillator clock.
1.10 Oscillator Configuration
The XCLKS is an input signal which controls whether a crystal in combination with the internal loop
controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock
circuitry is used.
The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check
is ongoing. This is the case for:
• Power on reset or low-voltage reset
• Clock monitor reset
• Any reset while in self-clock mode or full stop mode
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 57
The selected oscillator configuration is frozen with the rising edge of the RESET pin in any of these above
described reset cases.
Figure 1-7. Loop Controlled Pierce Oscillator Connections (XCLKS = 1)
Figure 1-8. Full Swing Pierce Oscillator Connections (XCLKS = 0)
Figure 1-9. External Clock Connections (XCLKS = 0)
MCU
EXTAL
XTAL
VSSPLL
Crystal or
Ceramic Resonator
C2
C1
MCU
EXTAL
XTAL RS
RB
VSSPLL
Crystal or
Ceramic Resonator
C2
C1
RB=1MΩ ; RS specified by crystal vendor
MCU
EXTAL
XTAL
CMOS-Compatible
External Oscillator
Not Connected
Device Overview S12XS Family
S12XS Family Reference Manual, Rev. 1.12
58 Freescale Semiconductor
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 59
Chapter 2
Port Integration Module (S12XSPIMV1)
Revision History
2.1 Introduction
2.1.1 Overview
The S12XS family Port Integration Module establishes the interface between the peripheral modules and
the I/O pins for all ports. It controls the electrical pin properties as well as the signal prioritization and
multiplexing on shared pins.
This document covers:
• Port A, B and K used as general purpose I/O
• Port E associated with the IRQ, XIRQ interrupt inputs
• Port T associated with 1 timer module
• Port S associated with 2 SCI module and 1 SPI module
• Port M associated with 1 MSCAN
• Port P connected to the PWM - inputs can be used as an external interrupt source
• Port H and J used as general purpose I/O - inputs can be used as an external interrupt source
• Port AD associated with one 16-channel ATD module
Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and
select pull-up or pull-down devices.
Revision
Number Revision Date Sections
Affected Description of Changes
V01.06 18 Dec 2009 Table 2-1./2-61 • Corrected PP0, PM0 pin descriptions
• Added function independency to wired-or bit descriptions
• Minor corrections
V01.07 08 Feb 2011 2.3.55/2-111
2.3.56/2-111
2.3.57/2-112
• Corrected addresses of PPSH,PIEH and PIFH in Register Descriptions
V01.08 08 Jul 2011 Table 2-2./2-65 • Corrected typo in PPSP register name in register map
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
60 Freescale Semiconductor
NOTE
This document assumes the availability of all features (112-pin package
option). Some functions are not available on lower pin count package
options. Refer to the pin-out summary section.
2.1.2 Features
The Port Integration Module includes these distinctive registers:
• Data and data direction registers for Ports A, B, E, K, T, S, M, P, H, J, and AD when used as
general-purpose I/O
• Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P,
H, and J on per-pin basis
• Control registers to enable/disable pull-up devices on Port AD on per-pin basis
• Single control register to enable/disable pull-ups on Ports A, B, E, and K on per-port basis and on
BKGD pin
• Control registers to enable/disable reduced output drive on Ports T, S, M, P, H, J, and AD on per-pin
basis
• Single control register to enable/disable reduced output drive on Ports A, B, E, and K on per-port
basis
• Control registers to enable/disable open-drain (wired-or) mode on Ports S, and M
• Interrupt flag register for pin interrupts on Ports P, H, and J
• Control register to configure IRQ pin operation
• Routing registers to support module port relocation
• Free-running clock outputs
A standard port pin has the following minimum features:
• Input/output selection
• 5V output drive with two selectable drive strengths
• 5V digital and analog input
• Input with selectable pull-up or pull-down device
Optional features supported on dedicated pins:
• Open drain for wired-or connections
• Interrupt inputs with glitch filtering
2.2 External Signal Description
This section lists and describes the signals that connect off-chip.
Table shows all the pins and their functions that are controlled by the Port Integration Module. Refer to
the device definition for the availability of the individual pins in the different package options.
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 61
NOTE
If there is more than one function associated with a pin, the priority is
indicated by the position in the table from top (highest priority) to bottom
(lowest priority)
Table 2-1. Pin Functions and Priorities
Port Pin Name Pin Function
& Priority1I/O Description Pin Function
after Reset
- BKGD MODC 2I MODC input during RESET BKGD
BKGD I/O S12X_BDM communication pin
A PA[7:0] GPIO I/O General purpose GPIO
B PB[7:0] GPIO I/O General purpose GPIO
E PE[7] XCLKS 2I External clock selection input during RESET GPIO
ECLKX2 O Free-running clock at core clock rate (ECLK x 2)
GPIO I/O General purpose
PE[6:5] GPIO I/O General purpose
PE[4] ECLK O Free-running clock at bus clock rate or programmable
down-scaled bus clock
GPIO I/O General purpose
PE[3:2] GPIO I/O General purpose
PE[1] IRQ I Maskable level- or falling edge-sensitive interrupt
GPI I General-purpose
PE[0] XIRQ I Non-maskable level-sensitive interrupt
GPI I General-purpose
K PK[7,5:0] GPIO I/O General purpose GPIO
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
62 Freescale Semiconductor
T PT7 IOC7 I/O Timer Channel 7 GPIO
(PWM7) I/O Pulse Width Modulator channel 7; emergency shut-down
GPIO I/O General purpose
PT6 IOC6 I/O Timer Channel 6
(PWM6) O Pulse Width Modulator channel 6
GPIO I/O General purpose
PT5 IOC5 I/O Timer Channel 5
(PWM5) O Pulse Width Modulator channel 5
VREG_API O VREG Autonomous Periodical Interrupt Clock
GPIO I/O General purpose
PT4 IOC4 I/O Timer Channel 4
(PWM4) O Pulse Width Modulator channel 4
GPIO I/O General purpose
PT[3:0] IOC[3:0] I/O Timer Channel 3 - 0
GPIO I/O General purpose
S PS7 SS0 I/O Serial Peripheral Interface 0 slave select output in master mode,
input in slave mode or master mode. GPIO
GPIO I/O General purpose
PS6 SCK0 I/O Serial Peripheral Interface 0 serial clock pin
GPIO I/O General purpose
PS5 MOSI0 I/O Serial Peripheral Interface 0 master out/slave in pin
GPIO I/O General purpose
PS4 MISO0 I/O Serial Peripheral Interface 0 master in/slave out pin
GPIO I/O General purpose
PS3 TXD1 O Serial Communication Interface 1 transmit pin
GPIO I/O General purpose
PS2 RXD1 I Serial Communication Interface 1 receive pin
GPIO I/O General purpose
PS1 TXD0 O Serial Communication Interface 0 transmit pin
GPIO I/O General purpose
PS0 RXD0 I Serial Communication Interface 0 receive pin
GPIO I/O General purpose
Table 2-1. Pin Functions and Priorities (continued)
Port Pin Name Pin Function
& Priority1I/O Description Pin Function
after Reset
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 63
M PM[7:6] GPIO I/O General purpose GPIO
PM5 (SCK0) I/O Serial Peripheral Interface 0 serial clock pin
GPIO I/O General purpose
PM4 (MOSI0) I/O Serial Peripheral Interface 0 master out/slave in pin
GPIO I/O General purpose
PM3 (SS0) I/O Serial Peripheral Interface 0 slave select output in master mode,
input in slave mode or master mode.
GPIO I/O General purpose
PM2 (MISO0) I/O Serial Peripheral Interface 0 master in/slave out pin
GPIO I/O General purpose
PM1 TXCAN0 O MSCAN0 transmit pin
(TXD1) O Serial Communication Interface 1 transmit pin
GPIO I/O General purpose
PM0 RXCAN0 I MSCAN0 receive pin
(RXD1) I Serial Communication Interface 1 receive pin
GPIO I/O General purpose
Table 2-1. Pin Functions and Priorities (continued)
Port Pin Name Pin Function
& Priority1I/O Description Pin Function
after Reset
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
64 Freescale Semiconductor
2.3 Memory Map and Register Definition
This section provides a detailed description of all Port Integration Module registers.
P PP7 PWM7 I/O Pulse Width Modulator channel 7; emergency shut-down GPIO
GPIO/KWP7 I/O General purpose; with interrupt
PP[6:3] PWM[6:3] O Pulse Width Modulator channel 6 - 3
GPIO/KWP[6:3] I/O General purpose; with interrupt
PP2 PWM2 O Pulse Width Modulator channel 2
(IOC2) I/O Timer Channel 2
(TXD1) O Serial Communication Interface 1 transmit pin
GPIO/KWP2 I/O General purpose; with interrupt
PP1 PWM1 O Pulse Width Modulator channel 1
(IOC1) I/O Timer Channel 1
GPIO/KWP1 I/O General purpose; with interrupt
PP0 PWM0 O Pulse Width Modulator channel 0
(IOC0) I/O Timer Channel 0
(RXD1) I Serial Communication Interface 1 receive pin
GPIO/KWP0 I/O General purpose; with interrupt
H PH[7:0] GPIO/KWH[7:0] I/O General purpose; with interrupt GPIO
J PJ[7:6] GPIO/KWJ[7:6] I/O General purpose; with interrupt GPIO
PJ[1:0] GPIO/KWJ[1:0] I/O General purpose; with interrupt
AD PAD[15:0] GPIO I/O General purpose GPIO
AN[15:0] I ATD analog
1Signals in brackets denote alternative module routing pins.
2Function active when RESET asserted.
Table 2-1. Pin Functions and Priorities (continued)
Port Pin Name Pin Function
& Priority1I/O Description Pin Function
after Reset
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 65
2.3.1 Memory Map
Table 2-2 shows the register map of the Port Integration Module.
Table 2-2. Block Memory Map
Port Offset or
Address Register Access Reset Value Section/Page
A
B0x0000 PORTA—Port A Data Register R/W 0x00 2.3.3/2-75
0x0001 PORTB—Port B Data Register R/W 0x00 2.3.4/2-75
0x0002 DDRA—Port A Data Direction Register R/W 0x00 2.3.5/2-76
0x0003 DDRB—Port B Data Direction Register R/W 0x00 2.3.6/2-76
0x0004
:
0x0007
PIM Reserved R 0x00 2.3.7/2-77
E 0x0008 PORTE—Port E Data Register R/W10x00 2.3.8/2-77
0x0009 DDRE—Port E Data Direction Register R/W10x00 2.3.9/2-78
0x000A
:
0x000B
Non-PIM address range2- - -
A
B
E
K
0x000C PUCR—Pull-up Control Register R/W10xD0 2.3.10/2-79
0x000D RDRIV—Reduced Drive Register R/W10x00 2.3.11/2-80
0x000E
:
0x001B
Non-PIM address range2- - -
E 0x001C ECLKCTL—ECLK Control Register R/W10b3100_0000 2.3.12/2-81
0x001D PIM Reserved R 0x00 2.3.13/2-82
0x001E IRQCR—IRQ Control Register R/W10x40 2.3.14/2-83
0x001F PIM Reserved R 0x00 2.3.15/2-83
0x0020
:
0x0031
Non-PIM address range2- - -
K 0x0032 PORTK—Port K Data Register R/W 0x00 2.3.16/2-84
0x0033 DDRK—Port K Data Direction Register R/W 0x00 2.3.17/2-84
0x0034
:
0x023F
Non-PIM address range2- - -
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
66 Freescale Semiconductor
T 0x0240 PTT—Port T Data Register R/W 0x00 2.3.18/2-85
0x0241 PTIT—Port T Input Register R 42.3.19/2-86
0x0242 DDRT—Port T Data Direction Register R/W 0x00 2.3.20/2-87
0x0243 RDRT—Port T Reduced Drive Register R/W 0x00 2.3.21/2-87
0x0244 PERT—Port T Pull Device Enable Register R/W 0x00 2.3.22/2-88
0x0245 PPST—Port T Polarity Select Register R/W 0x00 2.3.23/2-88
0x0246 PIM Reserved R 0x00 2.3.24/2-89
0x0247 Port T Routing Register R/W 0x00 2.3.25/2-89
S 0x0248 PTS—Port S Data Register R/W 0x00 2.3.26/2-91
0x0249 PTIS—Port S Input Register R 42.3.27/2-92
0x024A DDRS—Port S Data Direction Register R/W 0x00 2.3.28/2-93
0x024B RDRS—Port S Reduced Drive Register R/W 0x00 2.3.29/2-94
0x024C PERS—Port S Pull Device Enable Register R/W 0xFF 2.3.30/2-94
0x024D PTPS—Port S Polarity Select Register R/W 0x00 2.3.31/2-95
0x024E WOMS—Port S Wired-Or Mode Register R/W 0x00 2.3.32/2-95
0x024F PIM Reserved R 0x00 2.3.33/2-96
M 0x0250 PTM—Port M Data Register R/W 0x00 2.3.34/2-96
0x0251 PTIM—Port M Input Register R 42.3.35/2-98
0x0252 DDRM—Port M Data Direction Register R/W 0x00 2.3.36/2-98
0x0253 RDRM—Port M Reduced Drive Register R/W 0x00 2.3.37/2-99
0x0254 PERM—Port M Pull Device Enable Register R/W 0x00 2.3.38/2-100
0x0255 PPSM—Port M Polarity Select Register R/W 0x00 2.3.39/2-100
0x0256 WOMM—Port M Wired-Or Mode Register R/W 0x00 2.3.40/2-101
0x0257 MODRR—Module Routing Register R/W 0x00 2.3.41/2-101
P 0x0258 PTP—Port P Data Register R/W 0x00 2.3.42/2-102
0x0259 PTIP—Port P Input Register R 42.3.43/2-104
0x025A DDRP—Port P Data Direction Register R/W 0x00 2.3.44/2-105
0x025B RDRP—Port P Reduced Drive Register R/W 0x00 2.3.45/2-106
0x025C PERP—Port P Pull Device Enable Register R/W 0x00 2.3.46/2-106
0x025D PPSP—Port P Polarity Select Register R/W 0x00 2.3.47/2-107
0x025E PIEP—Port P Interrupt Enable Register R/W 0x00 2.3.48/2-107
0x025F PIFP—Port P Interrupt Flag Register R/W 0x00 2.3.49/2-108
Table 2-2. Block Memory Map (continued)
Port Offset or
Address Register Access Reset Value Section/Page
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 67
H 0x0260 PTH—Port H Data Register R/W 0x00 2.3.50/2-108
0x0261 PTIH—Port H Input Register R 42.3.51/2-109
0x0262 DDRH—Port H Data Direction Register R/W 0x00 2.3.52/2-109
0x0263 RDRH—Port H Reduced Drive Register R/W 0x00 2.3.53/2-110
0x0264 PERH—Port H Pull Device Enable Register R/W 0x00 2.3.54/2-110
0x0265 PPSH—Port H Polarity Select Register R/W 0x00 2.3.55/2-111
0x0266 PIEH—Port H Interrupt Enable Register R/W 0x00 2.3.56/2-111
0x0267 PIFH—Port H Interrupt Flag Register R/W 0x00 2.3.57/2-112
J 0x0268 PTJ—Port J Data Register R/W 0x00 2.3.58/2-112
0x0269 PTIJ—Port J Input Register R 42.3.59/2-113
0x026A DDRJ—Port J Data Direction Register R/W 0x00 2.3.60/2-113
0x026B RDRJ—Port J Reduced Drive Register R/W 0x00 2.3.61/2-114
0x026C PERJ—Port J Pull Device Enable Register R/W 0xFF 2.3.62/2-114
0x026D PPSJ—Port J Polarity Select Register R/W 0x00 2.3.63/2-115
0x026E PIEJ—Port J Interrupt Enable Register R/W 0x00 2.3.64/2-115
0x026F PIFJ—Port J Interrupt Flag Register R/W 0x00 2.3.65/2-116
AD 0x0270 PT0AD0—Port AD0 Data Register 0 R/W 0x00 2.3.66/2-116
0x0271 PT1AD0—Port AD0 Data Register 1 R/W 0x00 2.3.67/2-117
0x0272 DDR0AD0—Port AD0 Data Direction Register 0 R/W 0x00 2.3.68/2-117
0x0273 DDR1AD0—Port AD0 Data Direction Register 1 R/W 0x00 2.3.69/2-118
0x0274 RDR0AD0—Port AD0 Reduced Drive Register 0 R/W 0x00 2.3.70/2-118
0x0275 RDR1AD0—Port AD0 Reduced Drive Register 1 R/W 0x00 2.3.71/2-119
0x0276 PER0AD0—Port AD0 Pull Up Enable Register 0 R/W 0x00 2.3.72/2-119
0x0277 PER1AD0—Port AD0 Pull Up Enable Register 1 R/W 0x00 2.3.73/2-120
0x0278
:
0x027F
PIM Reserved R 0x00 2.3.74/2-120
1Write access not applicable for one or more register bits. Refer to register description.
2Refer to memory map in SoC Guide to determine related module.
3Mode dependent.
4Read always returns logic level on pins.
Table 2-2. Block Memory Map (continued)
Port Offset or
Address Register Access Reset Value Section/Page
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
68 Freescale Semiconductor
Register
Name Bit 7 6 5 4 3 2 1 Bit 0
0x0000
PORTA RPA7PA6PA5PA4PA3PA2PA1PA0
W
0x0001
PORTB RPB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
W
0x0002
DDRA RDDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
W
0x0003
DDRB RDDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
W
0x0004
Reserved R00000000
W
0x0005
Reserved R00000000
W
0x0006
Reserved R00000000
W
0x0007
Reserved R00000000
W
0x0008
PORTE RPE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
W
0x0009
DDRE RDDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 00
W
0x000A
0x000B
Non-PIM
Address
Range
R
Non-PIM Address Range
W
0x000C
PUCR RPUPKE BKPUE 0PUPEE 00
PUPBE PUPAE
W
0x000D
RDRIV RRDPK 00
RDPE 00
RDPB RDPA
W
0x000E–
0x001B
Non-PIM
Address
Range
R
Non-PIM Address Range
W
= Unimplemented or Reserved
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 69
0x001C
ECLKCTL RNECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0
W
0x001D
Reserved R00000000
W
0x001E
IRQCR RIRQE IRQEN 000000
W
0x001F
Reserved
R00000000
W
0x0020–
0x0031
Non-PIM
Address
Range
R
Non-PIM Address Range
W
0x0032
PORTK RPK7 0PK5 PK4 PK3 PK2 PK1 PK0
W
0x0033
DDRK RDDRK7 0DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0
W
0x0034–
0x023F
Non-PIM
Address
Range
R
Non-PIM Address Range
W
0x0240
PTT RPTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
W
0x0241
PTIT R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0
W
0x0242
DDRT RDDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
W
0x0243
RDRT RRDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
W
0x0244
PERT RPERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
W
0x0245
PPST RPPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
W
Register
Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
70 Freescale Semiconductor
0x0246
Reserved R00000000
W
0x0247
PTTRR RPTTRR7 PTTRR6 PTTRR5 PTTRR4 0PTTRR2 PTTRR1 PTTRR0
W
0x0248
PTS RPTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0
W
0x0249
PTIS R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0
W
0x024A
DDRS RDDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
W
0x024B
RDRS RRDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
W
0x024C
PERS RPERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0
W
0x024D
PPSS RPPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0
W
0x024E
WOMS RWOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
W
0x024F
Reserved R00000000
W
0x0250
PTM RPTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0
W
0x0251
PTIM R PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0
W
0x0252
DDRM RDDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
W
0x0253
RDRM RRDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
W
0x0254
PERM RPERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
W
0x0255
PPSM RPPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
W
Register
Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 71
0x0256
WOMM RWOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
W
0x0257
MODRR RMODRR7 MODRR6 0MODRR4 0000
W
0x0258
PTP RPTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
W
0x0259
PTIP R PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0
W
0x025A
DDRP RDDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
W
0x025B
RDRP RRDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
W
0x025C
PERP RPERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0
W
0x025D
PPSP RPPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
W
0x025E
PIEP RPIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
W
0x025F
PIFP RPIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
W
0x0260
PTH RPTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0
W
0x0261
PTIH R PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0
W
0x0262
DDRH RDDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
W
0x0263
RDRH RRDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0
W
0x0264
PERH RPERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0
W
Register
Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
72 Freescale Semiconductor
0x0265
PPSH RPPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0
W
0x0266
PIEH RPIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0
W
0x0267
PIFH RPIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0
W
0x0268
PTJ RPTJ7 PTJ6 0000
PTJ1 PTJ0
W
0x0269
PTIJ R PTIJ7 PTIJ6 0 0 0 0 PTIJ1 PTIJ0
W
0x026A
DDRJ RDDRJ7 DDRJ6 0000
DDRJ1 DDRJ0
W
0x026B
RDRJ RRDRJ7 RDRJ6 0000
RDRJ1 RDRJ0
W
0x026C
PERJ RPERJ7 PERJ6 0000
PERJ1 PERJ0
W
0x026D
PPSJ RPPSJ7 PPSJ6 0000
PPSJ1 PPSJ0
W
0x026E
PIEJ RPIEJ7 PIEJ6 0000
PIEJ1 PIEJ0
W
0x026F
PIFJ RPIFJ7 PIFJ6 0000
PIFJ1 PIFJ0
W
0x0270
PT0AD0 RPT0AD07 PT0AD06 PT0AD05 PT0AD04 PT0AD03 PT0AD02 PT0AD01 PT0AD00
W
0x0271
PT1AD0 RPT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00
W
0x0272
DDR0AD0 RDDR0AD07 DDR0AD06 DDR0AD05 DDR0AD04 DDR0AD03 DDR0AD02 DDR0AD01 DDR0AD00
W
0x0273
DDR1AD0 RDDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00
W
0x0274
RDR0AD0 RRDR0AD07 RDR0AD06 RDR0AD05 RDR0AD04 RDR0AD03 RDR0AD02 RDR0AD01 RDR0AD00
W
Register
Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 73
2.3.2 Register Descriptions
The following table summarizes the effect of the various configuration bits, i.e. data direction (DDR),
output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS) on the pin function and pull
device activity.
The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt enabled.
2. Select either a pull-up or pull-down device if PE is active.
0x0275
RDR1AD0 RRDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00
W
0x0276
PER0AD0 RPER0AD07 PER0AD06 PER0AD05 PER0AD04 PER0AD03 PER0AD02 PER0AD01 PER0AD00
W
0x0277
PER1AD0 RPER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00
W
0x0278
Reserved R00000000
W
0x0279
Reserved R00000000
W
0x027A
Reserved R00000000
W
0x027B
Reserved R00000000
W
0x027C
Reserved R00000000
W
0x027D
Reserved R00000000
W
0x027E
Reserved R00000000
W
0x027F
Reserved R00000000
W
Register
Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
74 Freescale Semiconductor
Table 2-3. Pin Configuration Summary
NOTE
All register bits in this module are completely synchronous to internal
clocks during a register read.
NOTE
Figures of port data registers also display the alternative functions if
applicable on the related pin as defined in Table . Names in brackets denote
the availability of the function when using a specific routing option.
NOTE
Figures of module routing registers also display the module instance or
module channel associated with the related routing bit.
DDR IO RDR PE PS1
1Always “0” on Port A, B, E, K, and AD.
IE2
2Applicable only on Port P, H, and J.
Function Pull Device Interrupt
0 x x 0 x 0 Input Disabled Disabled
0 x x 1 0 0 Input Pull Up Disabled
0 x x 1 1 0 Input Pull Down Disabled
0 x x 0 0 1 Input Disabled Falling edge
0 x x 0 1 1 Input Disabled Rising edge
0 x x 1 0 1 Input Pull Up Falling edge
0 x x 1 1 1 Input Pull Down Rising edge
1 0 0 x x 0 Output, full drive to 0 Disabled Disabled
1 1 0 x x 0 Output, full drive to 1 Disabled Disabled
1 0 1 x x 0 Output, reduced drive to 0 Disabled Disabled
1 1 1 x x 0 Output, reduced drive to 1 Disabled Disabled
1 0 0 x 0 1 Output, full drive to 0 Disabled Falling edge
1 1 0 x 1 1 Output, full drive to 1 Disabled Rising edge
1 0 1 x 0 1 Output, reduced drive to 0 Disabled Falling edge
1 1 1 x 1 1 Output, reduced drive to 1 Disabled Rising edge
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 75
2.3.3 Port A Data Register (PORTA)
2.3.4 Port B Data Register (PORTB)
Address 0x0000 (PRR) Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RPA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
W
Reset 00000000
Figure 2-1. Port A Data Register (PORTA)
Table 2-4. PORTA Register Field Descriptions
Field Description
7-0
PA Port A general purpose input/output data—Data Register
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Address 0x0001 (PRR) Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RPB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
W
Reset 00000000
Figure 2-2. Port B Data Register (PORTB)
Table 2-5. PORTB Register Field Descriptions
Field Description
7-0
PB Port B general purpose input/output data—Data Register
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
76 Freescale Semiconductor
2.3.5 Port A Data Direction Register (DDRA)
2.3.6 Port B Data Direction Register (DDRB)
Address 0x0002 (PRR) Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RDDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
W
Reset 00000000
Figure 2-3. Port A Data Direction Register (DDRA)
Table 2-6. DDRA Register Field Descriptions
Field Description
7-0
DDRA Port A Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x0003 (PRR) Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RDDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
W
Reset 00000000
Figure 2-4. Port B Data Direction Register (DDRB)
Table 2-7. DDRB Register Field Descriptions
Field Description
7-0
DDRB Port B Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 77
2.3.7 PIM Reserved Registers
2.3.8 Port E Data Register (PORTE)
Address 0x0004 (PRR) to 0x0007 (PRR) Access: User read1
1Read: Always reads 0x00
Write: Unimplemented
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-5. PIM Reserved Registers
Address 0x0008 (PRR) Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RPE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
W
Altern.
Function XCLKS — — ECLK — — IRQ XIRQ
ECLKX2 ———————
Reset 000000—
2
2These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated
pin values.
—2
= Unimplemented or Reserved
Figure 2-6. Port E Data Register (PORTE)
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
78 Freescale Semiconductor
2.3.9 Port E Data Direction Register (DDRE)
Table 2-8. PORTE Register Field Descriptions
Field Description
7
PE Port E general purpose input/output data—Data Register, ECLKX2 output, XCLKS input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The ECLKX2 output function takes precedence over the general purpose I/O function if enabled.
• The external clock selection feature (XCLKS) is only active during RESET=0
6-5, 3-2
PE Port E general purpose input/output data—Data Register
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
4
PE Port E general purpose input/output data—Data Register, ECLK output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The ECLK output function takes precedence over the general purpose I/O function if enabled.
1
PE Port E general purpose input data and interrupt—Data Register, IRQ input.
This pin can be used as general purpose and IRQ input.
0
PE Port E general purpose input data and interrupt—Data Register, XIRQ input.
This pin can be used as general purpose and XIRQ input.
Address 0x0009 (PRR) Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RDDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 00
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-7. Port E Data Direction Register (DDRE)
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 79
2.3.10 Ports ABEK, BKGD pin Pull-up Control Register (PUCR)
Table 2-9. DDRE Register Field Descriptions
Field Description
7-2
DDRE Port E Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x000C (PRR) Access: User read/write1
1Read: Anytime in single-chip modes.
Write: Anytime, except BKPUE which is writable in Special Single-Chip Mode only.
76543210
RPUPKE BKPUE 0PUPEE 00
PUPBE PUPAE
W
Reset 11010000
= Unimplemented or Reserved
Figure 2-8. Ports ABEK, BKGD pin Pull-up Control Register (PUCR)
Table 2-10. PUCR Register Field Descriptions
Field Description
7
PUPKE Port K Pull-up Enable—Enable pull-up devices on all port input pins
This bit configures whether a pull-up device is activated on all associated port input pins. If a pin is used as output
this bit has no effect.
1 Pull-up device enabled
0 Pull-up device disabled
6
BKPUE BKGD pin pull-up Enable—Enable pull-up device on pin
This bit configures whether a pull-up device is activated, if the pin is used as input. If a pin is used as output this bit
has no effect.
1 Pull-up device enabled
0 Pull-up device disabled
4
PUPEE Port E Pull-up Enable—Enable pull-up devices on all port input pins except pins 5 and 6
This bit configures whether a pull-up device is activated on all associated port input pins. If a pin is used as output
this bit has no effect.
Pins 5 and 6 have pull-down devices enabled only during reset. This bit has no effect on these pins.
1 Pull-up device enabled
0 Pull-up device disabled
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
80 Freescale Semiconductor
2.3.11 Ports ABEK Reduced Drive Register (RDRIV)
This register is used to select reduced drive for the pins associated with ports A, B, E, and K. If enabled,
the pins drive at approx. 1/5 of the full drive strength.
1
PUPBE Port B Pull-up Enable—Enable pull-up devices on all port input pins
This bit configures whether a pull-up device is activated on all associated port input pins. If a pin is used as output
this bit has no effect.
1 Pull-up device enabled
0 Pull-up device disabled
0
PUPAE Port A Pull-up Enable—Enable pull-up devices on all port input pins
This bit configures whether a pull-up device is activated on all associated port input pins. If a pin is used as output
this bit has no effect.
1 Pull-up device enabled
0 Pull-up device disabled
Address 0x000D (PRR) Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RRDPK 00
RDPE 00
RDPB RDPA
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-9. Ports ABEK Reduced Drive Register (RDRIV)
Table 2-11. RDRIV Register Field Descriptions
Field Description
7
RDPK Port K reduced drive—Select reduced drive for output port
This bit configures the drive strength of all associated port output pins as either full or reduced. If a pin is used as
input this bit has no effect. The reduced drive function is independent of which function is being used on a particular
pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
4
RDPE Port E reduced drive—Select reduced drive for output port
This bit configures the drive strength of all associated port output pins as either full or reduced. If a pin is used as
input this bit has no effect. The reduced drive function is independent of which function is being used on a particular
pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Table 2-10. PUCR Register Field Descriptions (continued)
Field Description
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 81
2.3.12 ECLK Control Register (ECLKCTL)
1
RDPB Port B reduced drive—Select reduced drive for output port
This bit configures the drive strength of all associated port output pins as either full or reduced. If a pin is used as
input this bit has no effect. The reduced drive function is independent of which function is being used on a particular
pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
0
RDPA Port A reduced drive—Select reduced drive for output port
This bit configures the drive strength of all associated port output pins as either full or reduced. If a pin is used as
input this bit has no effect. The reduced drive function is independent of which function is being used on a particular
pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Address 0x001C (PRR) Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RNECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0
W
Reset: Mode
Depen-
dent 1000000
Special
single-chip 01000000
Normal
single-chip 11000000
= Unimplemented or Reserved
Figure 2-10. ECLK Control Register (ECLKCTL)
Table 2-11. RDRIV Register Field Descriptions (continued)
Field Description
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
82 Freescale Semiconductor
2.3.13 PIM Reserved Register
Table 2-12. ECLKCTL Register Field Descriptions
Field Description
7
NECLK No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin. This clock has a fixed rate equivalent to the
internal bus clock.
1 ECLK disabled
0 ECLK enabled
6
NCLKX2 No ECLKX2—Disable ECLKX2 output
This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal bus clock.
1 ECLKX2 disabled
0 ECLKX2 enabled
5
DIV16 Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
4-0
EDIV Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin.
00000 ECLK rate = bus clock rate
00001 ECLK rate = bus clock rate divided by 2
00010 ECLK rate = bus clock rate divided by 3, ...
11111 ECLK rate = bus clock rate divided by 32
Address 0x001D (PRR) Access: User read1
1Read: Always reads 0x00
Write: Unimplemented
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-11. PIM Reserved Register
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 83
2.3.14 IRQ Control Register (IRQCR)
2.3.15 PIM Reserved Register PIMTEST1
This register is reserved for factory testing of the PIM module and is not available in normal operation.
Writing to this register when in special modes can alter the pin functionality.
Address 0x001E Access: User read/write1
1Read: See individual bit descriptions below.
Write: See individual bit descriptions below.
76543210
RIRQE IRQEN 000000
W
Reset 01000000
= Unimplemented or Reserved
Figure 2-12. IRQ Control Register (IRQCR)
Table 2-13. IRQCR Register Field Descriptions
Field Description
7
IRQE IRQ select edge sensitive only—
Special mode: Read or write anytime.
Normal mode: Read anytime, write once.
1IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE=1
and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0IRQ configured for low level recognition.
6
IRQEN IRQ enable—
Read or write anytime.
1IRQ pin is connected to interrupt logic.
0IRQ pin is disconnected from interrupt logic.
1. Implementation pim_xe.01.01 and later
Address 0x001F Access: User read1
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-13. PIM Reserved Register
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
84 Freescale Semiconductor
2.3.16 Port K Data Register (PORTK)
2.3.17 Port K Data Direction Register (DDRK)
1Read: Always reads 0x00
Write: Unimplemented
Address 0x0032 (PRR) Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RPK7 0PK5 PK4 PK3 PK2 PK1 PK0
W
Reset 00000000
Figure 2-14. Port K Data Register (PORTK)
Table 2-14. PORTK Register Field Descriptions
Field Description
7,5-0
PK Port K general purpose input/output data—Data Register
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Address 0x0033 (PRR) Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RDDRK7 0DDRK5 DDRK4 DDRK3 DDRK2 DDRK1 DDRK0
W
Reset 00000000
Figure 2-15. Port K Data Direction Register (DDRK)
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 85
2.3.18 Port T Data Register (PTT)
Table 2-15. DDRK Register Field Descriptions
Field Description
7,5-0
DDRK Port K Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x0240 Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RPTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
W
Altern.
Function IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
(PWM7) (PWM6) (PWM5) (PWM4) ————
— — VREG_API —————
Reset 00000000
Figure 2-16. Port T Data Register (PTT)
Table 2-16. PTT Register Field Descriptions
Field Description
7-6, 4
PTT Port T general purpose input/output data—Data Register, TIM output, routed PWM output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The TIM output function takes precedence over the routed PWM and the general purpose I/O function if the
related channel is enabled.
• The routed PWM function takes precedence over the general purpose I/O function if the related channel is
enabled.
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
86 Freescale Semiconductor
2.3.19 Port T Input Register (PTIT)
5
PTT Port T general purpose input/output data—Data Register, TIM output, routed PWM output, VREG_API output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The TIM output function takes precedence over the routed PWM, VREG_API function and the general purpose
I/O function if the related channel is enabled.
• The routed PWM function takes precedence over VREG_API and the general purpose I/O function if the related
channel is enabled.
• The VREG_API takes precedence over the general purpose I/O function if enabled.
3-0
PTT Port T general purpose input/output data—Data Register, TIM output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The TIM output function takes precedence over the general purpose I/O function if the related channel is enabled.
Address 0x0241 Access: User read1
1Read: Anytime.
Write:Never, writes to this register have no effect.
76543210
R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0
W
Reset uuuuuuuu
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-17. Port T Input Register (PTIT)
Table 2-17. PTIT Register Field Descriptions
Field Description
7-0
PTIT Port T input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Table 2-16. PTT Register Field Descriptions (continued)
Field Description
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 87
2.3.20 Port T Data Direction Register (DDRT)
2.3.21 Port T Reduced Drive Register (RDRT)
Address 0x0242 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RDDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0
W
Reset 00000000
Figure 2-18. Port T Data Direction Register (DDRT)
Table 2-18. DDRT Register Field Descriptions
Field Description
7-6, 4
DDRT Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. In these cases the data direction bit will not
change.
1 Associated pin configured as output
0 Associated pin configured as input
5
DDRT Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. Else the VREG_API forces the I/O state to
be an output if enabled. In these cases the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
3-0
DDRT Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. In this case
the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x0243 Access: User read/write1
76543210
RRDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRT1 RDRT0
W
Reset 00000000
Figure 2-19. Port T Reduced Drive Register (RDRT)
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
88 Freescale Semiconductor
2.3.22 Port T Pull Device Enable Register (PERT)
2.3.23 Port T Polarity Select Register (PPST)
1Read: Anytime.
Write: Anytime.
Table 2-19. RDRT Register Field Descriptions
Field Description
7-0
RDRT Port T reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Address 0x0244 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0
W
Reset 00000000
Figure 2-20. Port T Pull Device Enable Register (PERT)
Table 2-20. PERT Register Field Descriptions
Field Description
7-0
PERT Port T pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Address 0x0245 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0
W
Reset 00000000
Figure 2-21. Port T Polarity Select Register (PPST)
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 89
2.3.24 PIM Reserved Register
2.3.25 Port T Routing Register (PTTRR)
This register configures the re-routing of PWM and TIM channels on alternative pins.
Table 2-21. PPST Register Field Descriptions
Field Description
7-0
PPST Port T pull device select—Configure pull device polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
1 A pull-down device selected
0 A pull-up device selected
Address 0x0246 Access: User read1
1Read: Always reads 0x00
Write: Unimplemented
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 2-22. PIM Reserved Register
Address 0x0247 Access: User read1
1Read: Anytime.
Write: Anytime.
76543210
RPTTRR7 PTTRR6 PTTRR5 PTTRR4 0PTTRR2 PTTRR1 PTTRR0
W
Routing
Option PWM7 PWM6 PWM5 PWM4 — IOC2 IOC1 IOC0
Reset 00000000
= Unimplemented or Reserved
Figure 2-23. Port T Routing Register (PTTRR)
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
90 Freescale Semiconductor
Table 2-22. PTTRR Register Field Descriptions
Field Description
7
PTTRR Port T peripheral routing—
This register controls the routing of PWM channel 7.
1 PWM7 routed to PT7
0 PWM7 routed to PP7
6
PTTRR Port T peripheral routing—
This register controls the routing of PWM channel 6.
1 PWM6 routed to PT6
0 PWM6 routed to PP6
5
PTTRR Port T peripheral routing—
This register controls the routing of PWM channel 5.
1 PWM5 routed to PT5
0 PWM5 routed to PP5
4
PTTRR Port T peripheral routing—
This register controls the routing of PWM channel 4.
1 PWM4 routed to PT4
0 PWM4 routed to PP4
2
PTTRR Port T peripheral routing—
This register controls the routing of TIM channel 2.
1 IOC2 routed to PP2
0 IOC2 routed to PT2
1
PTTRR Port T peripheral routing—
This register controls the routing of TIM channel 1.
1 IOC1 routed to PP1
0 IOC1 routed to PT1
0
PTTRR Port T peripheral routing—
This register controls the routing of TIM channel 0.
1 IOC0 routed to PP0
0 IOC0 routed to PT0
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 91
2.3.26 Port S Data Register (PTS)
Address 0x0248 Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RPTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0
W
Altern.
Function SS0 SCK0 MOSI0 MISO0 TXD1 RXD1 TXD0 RXD0
Reset 00000000
Figure 2-24. Port S Data Register (PTS)
Table 2-23. PTS Register Field Descriptions
Field Description
7
PTS Port S general purpose input/output data—Data Register, SPI0 SS input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SPI0 function takes precedence over the general purpose I/O function if enabled.
6
PTS Port S general purpose input/output data—Data Register, SPI0 SCK input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SPI0 function takes precedence over the general purpose I/O function if enabled.
5
PTS Port S general purpose input/output data—Data Register, SPI0 MOSI input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SPI0 function takes precedence over the general purpose I/O function if enabled.
4
PTS Port S general purpose input/output data—Data Register, SPI0 MISO input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SPI0 function takes precedence over the general purpose I/O function if enabled.
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
92 Freescale Semiconductor
2.3.27 Port S Input Register (PTIS)
3
PTS Port S general purpose input/output data—Data Register, SCI1 TXD output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SCI1 function takes precedence over the general purpose I/O function if enabled.
2
PTS Port S general purpose input/output data—Data Register, SCI1 RXD input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SCI1 function takes precedence over the general purpose I/O function if enabled.
1
PTS Port S general purpose input/output data—Data Register, SCI0 TXD output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SCI0 function takes precedence over the general purpose I/O function if enabled.
0
PTS Port S general purpose input/output data—Data Register, SCI0 RXD input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SCI0 function takes precedence over the general purpose I/O function if enabled.
Address 0x0249 Access: User read1
1Read: Anytime.
Write:Never, writes to this register have no effect.
76543210
R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0
W
Reset uuuuuuuu
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-25. Port S Input Register (PTIS)
Table 2-23. PTS Register Field Descriptions (continued)
Field Description
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 93
2.3.28 Port S Data Direction Register (DDRS)
Table 2-24. PTIS Register Field Descriptions
Field Description
7-0
PTIS Port S input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x0249 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RDDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0
W
Reset 00000000
Figure 2-26. Port S Data Direction Register (DDRS)
Table 2-25. DDRS Register Field Descriptions
Field Description
7-4
DDRS Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI0 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
3-2
DDRS Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI1 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
1-0
DDRS Port S data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SCI0 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
94 Freescale Semiconductor
2.3.29 Port S Reduced Drive Register (RDRS)
2.3.30 Port S Pull Device Enable Register (PERS)
Address 0x024A Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RRDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRS0
W
Reset 00000000
Figure 2-27. Port S Reduced Drive Register (RDRS)
Table 2-26. RDRS Register Field Descriptions
Field Description
7-0
RDRS Port S reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Address 0x024B Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0
W
Reset 11111111
Figure 2-28. Port S Pull Device Enable Register (PERS)
Table 2-27. PERS Register Field Descriptions
Field Description
7-0
PERS Port S pull device enable—Enable pull device on input pin or wired-or output pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
only effect if used in wired-or mode. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 95
2.3.31 Port S Polarity Select Register (PPSS)
2.3.32 Port S Wired-Or Mode Register (WOMS)
Address 0x024C Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0
W
Reset 00000000
Figure 2-29. Port S Polarity Select Register (PPSS)
Table 2-28. PPSS Register Field Descriptions
Field Description
7-0
PPSS Port S pull device select—Configure pull device polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
1 A pull-down device selected
0 A pull-up device selected
Address 0x024C Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RWOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0
W
Reset 00000000
Figure 2-30. Port S Wired-Or Mode Register (WOMS)
Table 2-29. WOMS Register Field Descriptions
Field Description
7-0
WOMS Port S wired-or mode—Enable open-drain functionality on output pin
This bit configures an output pin as wired-or (open-drain) or push-pull independent of the function used on the pins.
In wired-or mode a logic “0” is driven active low while a logic “1” remains undriven. This allows a multipoint
connection of several serial modules. The bit has no influence on pins used as input.
1 Output buffer operates as open-drain output.
0 Output buffer operates as push-pull output.
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
96 Freescale Semiconductor
2.3.33 PIM Reserved Register
2.3.34 Port M Data Register (PTM)
Address 0x024F Access: User read1
1Read: Always reads 0x00
Write: Unimplemented
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-31. PIM Reserved Register
Address 0x0250 Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RPTM7 PTM6 PTM5 PTM4 PTM3 PTM2 PTM1 PTM0
W
Altern.
Function — — (SCK0) (MOSI0) (SS0) (MISO0) TXCAN0 RXCAN0
——————(TXD1) (RXD1)
Reset 00000000
Figure 2-32. Port M Data Register (PTM)
Table 2-30. PTM Register Field Descriptions
Field Description
7-6
PTM Port M general purpose input/output data—Data Register
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
5
PTM Port M general purpose input/output data—Data Register, routed SPI0 SCK input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SPI0 function takes precedence over the general purpose I/O function if enabled.
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 97
4
PTM Port M general purpose input/output data—Data Register, routed SPI0 MOSI input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SPI0 function takes precedence over the general purpose I/O function if enabled.
3
PTM Port M general purpose input/output data—Data Register, routed SPI0 SS input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SPI0 function takes precedence over the general purpose I/O function if enabled.
2
PTM Port M general purpose input/output data—Data Register, routed SPI0 MISO input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The SPI0 function takes precedence over the general purpose I/O function if enabled.
1
PTM Port M general purpose input/output data—Data Register, CAN0 TXCAN output, SCI1 TXD output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The CAN0 function takes precedence over the general purpose I/O function if enabled.
• The SCI1 function takes precedence over the general purpose I/O function if enabled.
0
PTM Port M general purpose input/output data—Data Register, CAN0 RXCAN input, SCI1 RXD input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The CAN0 function takes precedence over the general purpose I/O function if enabled.
• The SCI1 function takes precedence over the general purpose I/O function if enabled.
Table 2-30. PTM Register Field Descriptions (continued)
Field Description
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
98 Freescale Semiconductor
2.3.35 Port M Input Register (PTIM)
2.3.36 Port M Data Direction Register (DDRM)
Address 0x0251 Access: User read1
1Read: Anytime.
Write:Never, writes to this register have no effect.
76543210
R PTIM7 PTIM6 PTIM5 PTIM4 PTIM3 PTIM2 PTIM1 PTIM0
W
Reset uuuuuuuu
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-33. Port M Input Register (PTIM)
Table 2-31. PTIM Register Field Descriptions
Field Description
7-0
PTIM Port M input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x0252 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RDDRM7 DDRM6 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRM0
W
Reset 00000000
Figure 2-34. Port M Data Direction Register (DDRM)
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 99
2.3.37 Port M Reduced Drive Register (RDRM)
Table 2-32. DDRM Register Field Descriptions
Field Description
7-6
DDRM Port M data direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
5-2
DDRM Port M data direction—
This bit determines whether the associated pin is an input or output.
Depending on the configuration of the enabled SPI0 the I/O state will be forced to be input or output. In this case the
data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
1
DDRM Port M data direction—
This bit determines whether the associated pin is an input or output.
The enabled CAN0 or SCI1 forces the I/O state to be an output. In this case the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
0
DDRM Port M data direction—
This bit determines whether the associated pin is an input or output.
The enabled CAN0 or SCI1 forces the I/O state to be an input. In this case the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x0253 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RRDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRM0
W
Reset 00000000
Figure 2-35. Port M Reduced Drive Register (RDRM)
Table 2-33. RDRM Register Field Descriptions
Field Description
7-0
RDRM Port M reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
100 Freescale Semiconductor
2.3.38 Port M Pull Device Enable Register (PERM)
2.3.39 Port M Polarity Select Register (PPSM)
Address 0x0254 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPERM7 PERM6 PERM5 PERM4 PERM3 PERM2 PERM1 PERM0
W
Reset 00000000
Figure 2-36. Port M Pull Device Enable Register (PERM)
Table 2-34. PERM Register Field Descriptions
Field Description
7-0
PERM Port M pull device enable—Enable pull device on input pin or wired-or output pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
only effect if used in wired-or mode. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Address 0x0255 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPPSM7 PPSM6 PPSM5 PPSM4 PPSM3 PPSM2 PPSM1 PPSM0
W
Reset 00000000
Figure 2-37. Port M Polarity Select Register (PPSM)
Table 2-35. PPSM Register Field Descriptions
Field Description
7-0
PPSM Port M pull device select—Configure pull device polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
If CAN0 is active the selection of a pull-down device on the RXCAN input will have no effect.
1 A pull-down device selected
0 A pull-up device selected
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 101
2.3.40 Port M Wired-Or Mode Register (WOMM)
2.3.41 Module Routing Register (MODRR)
This register configures the re-routing of SCI1 and SPI0 on alternative ports.
Address 0x0256 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RWOMM7 WOMM6 WOMM5 WOMM4 WOMM3 WOMM2 WOMM1 WOMM0
W
Reset 00000000
Figure 2-38. Port M Wired-Or Mode Register (WOMM)
Table 2-36. WOMM Register Field Descriptions
Field Description
7-0
WOMM Port M wired-or mode—Enable open-drain functionality on output pin
This bit configures an output pin as wired-or (open-drain) or push-pull independent of the function used on the pins.
In wired-or mode a logic “0” is driven active low while a logic “1” remains undriven. This allows a multipoint
connection of several serial modules. The bit has no influence on pins used as input.
1 Output buffer operates as open-drain output.
0 Output buffer operates as push-pull output.
Address 0x0257 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RMODRR7 MODRR6 0MODRR4 0000
W
Routing
Option SCI1 SCI1 — SPI0 ————
Reset 00000000
= Unimplemented or Reserved
Figure 2-39. Module Routing Register (MODRR)
Table 2-37. SCI1 Routing
MODRRx Related Pins
7 6 TXD RXD
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
102 Freescale Semiconductor
2.3.42 Port P Data Register (PTP)
0 0 PS3 PS2
0 1 PP2 PP0
1 0 PM1 PM0
1 1 Reserved1Reserved1
1Defaults to reset value
Table 2-38. SPI0 Routing
MODRRx Related Pins
4 MISO0 MOSI0 SCK0 SS0
0 PS4 PS5 PS6 PS7
1 PM2 PM4 PM5 PM3
Address 0x0258 Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RPTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0
W
Altern.
Function PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
—————(IOC2) (IOC1) (IOC0)
—————(TXD1) — (RXD1)
Reset 00000000
Figure 2-40. Port P Data Register (PTP)
Table 2-37. SCI1 Routing
MODRRx Related Pins
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 103
Table 2-39. PTP Register Field Descriptions
Field Description
7
PTP Port P general purpose input/output data—Data Register, PWM input/output, pin interrupt input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The PWM function takes precedence over the general purpose I/O function if the related channel or the
emergency shut-down feature is enabled.
• Pin interrupts can be generated if enabled in input or output mode.
6-3
PTP Port P general purpose input/output data—Data Register, PWM output, pin interrupt input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The PWM function takes precedence over the general purpose I/O function if the related channel is enabled.
• Pin interrupts can be generated if enabled in input or output mode.
2
PTP Port P general purpose input/output data—Data Register, PWM output, routed TIM output, routed SCI1 TXD
output, pin interrupt input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The PWM function takes precedence over the TIM, SCI1 and general purpose I/O function if the related channel
is enabled.
• The TIM function takes precedence over SCI1 and the general purpose I/O function if the related channel is
enabled.
• The SCI1 function takes precedence over the general purpose I/O function if enabled.
• Pin interrupts can be generated if enabled in input or output mode.
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
104 Freescale Semiconductor
2.3.43 Port P Input Register (PTIP)
1
PTP Port P general purpose input/output data—Data Register, PWM output, routed TIM output, pin interrupt
input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The PWM function takes precedence over the TIM and general purpose I/O function if the related channel is
enabled.
• The TIM function takes precedence over the general purpose I/O function if the related channel is enabled.
• Pin interrupts can be generated if enabled in input or output mode.
0
PTP Port P general purpose input/output data—Data Register, PWM output, routed TIM output, routed SCI1 RXD
output, pin interrupt input/output
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• The PWM function takes precedence over the TIM, SCI1 and general purpose I/O function if the related channel
is enabled.
• The TIM function takes precedence over SCI1 and the general purpose I/O function if the related channel is
enabled.
• The SCI1 function takes precedence over the general purpose I/O function if enabled.
• Pin interrupts can be generated if enabled in input or output mode.
Address 0x0259 Access: User read1
1Read: Anytime.
Write:Never, writes to this register have no effect.
76543210
R PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0
W
Reset uuuuuuuu
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-41. Port P Input Register (PTIP)
Table 2-40. PTIP Register Field Descriptions
Field Description
7-0
PTIP Port P input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Table 2-39. PTP Register Field Descriptions (continued)
Field Description
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 105
2.3.44 Port P Data Direction Register (DDRP)
Address 0x025A Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RDDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0
W
Reset 00000000
Figure 2-42. Port P Data Direction Register (DDRP)
Table 2-41. DDRP Register Field Descriptions
Field Description
7
DDRP Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. If the PWM shutdown feature is enabled this
pin is forced to be an input. In this case the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
6-3
DDRP Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. In this case the data direction bit will not
change.
1 Associated pin configured as output
0 Associated pin configured as input
2,0
DDRP Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. Else the TIM forces the I/O state to be an
output for a timer port associated with an enabled output compare. Else depending on the configuration of the
enabled SCI the I/O state will be forced to be input or output. In this case the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
1
DDRP Port P data direction—
This bit determines whether the associated pin is an input or output.
The PWM forces the I/O state to be an output for an enabled channel. Else the TIM forces the I/O state to be an
output for a timer port associated with an enabled output compare. In this case the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
106 Freescale Semiconductor
2.3.45 Port P Reduced Drive Register (RDRP)
2.3.46 Port P Pull Device Enable Register (PERP)
Address 0x025B Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RRDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRP1 RDRP0
W
Reset 00000000
Figure 2-43. Port P Reduced Drive Register (RDRP)
Table 2-42. RDRP Register Field Descriptions
Field Description
7-0
RDRP Port P reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Address 0x025C Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
W
Reset 00000000
Figure 2-44. Port P Pull Device Enable Register (PERP)
Table 2-43. PERP Register Field Descriptions
Field Description
7-0
PERP Port P pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 107
2.3.47 Port P Polarity Select Register (PPSP)
2.3.48 Port P Interrupt Enable Register (PIEP)
Read: Anytime.
Address 0x025D Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0
W
Reset 00000000
Figure 2-45. Port P Polarity Select Register (PPSP)
Table 2-44. PPSP Register Field Descriptions
Field Description
7-0
PPSP Port P pull device select—Configure pull device and pin interrupt edge polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 A pull-down device selected; rising edge selected
0 A pull-up device selected; falling edge selected
Address 0x025E Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0
W
Reset 00000000
Figure 2-46. Port P Interrupt Enable Register (PIEP)
Table 2-45. PIEP Register Field Descriptions
Field Description
7-0
PIEP Port P interrupt enable—
This bit enables or disables on the edge sensitive pin interrupt on the associated pin.
1 Interrupt enabled
0 Interrupt disabled (interrupt flag masked)
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
108 Freescale Semiconductor
2.3.49 Port P Interrupt Flag Register (PIFP)
2.3.50 Port H Data Register (PTH)
Address 0x025F Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0
W
Reset 00000000
Figure 2-47. Port P Interrupt Flag Register (PIFP)
Table 2-46. PIFP Register Field Descriptions
Field Description
7-0
PIFP Port P interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
Address 0x0260 Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RPTH7 PTH6 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0
W
Reset 00000000
Figure 2-48. Port H Data Register (PTH)
Table 2-47. PTH Register Field Descriptions
Field Description
7-0
PTH Port H general purpose input/output data—Data Register, pin interrupt input/output
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• Pin interrupts can be generated if enabled in input or output mode.
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 109
2.3.51 Port H Input Register (PTIH)
2.3.52 Port H Data Direction Register (DDRH)
Address 0x0261 Access: User read1
1Read: Anytime.
Write:Never, writes to this register have no effect.
76543210
R PTIH7 PTIH6 PTIH5 PTIH4 PTIH3 PTIH2 PTIH1 PTIH0
W
Reset uuuuuuuu
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-49. Port H Input Register (PTIH)
Table 2-48. PTIH Register Field Descriptions
Field Description
7-0
PTIH Port H input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x0262 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RDDRH7 DDRH6 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 DDRH0
W
Reset 00000000
Figure 2-50. Port H Data Direction Register (DDRH)
Table 2-49. DDRH Register Field Descriptions
Field Description
7-0
DDRH Port H data direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
110 Freescale Semiconductor
2.3.53 Port H Reduced Drive Register (RDRH)
2.3.54 Port H Pull Device Enable Register (PERH)
Address 0x0263 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RRDRH7 RDRH6 RDRH5 RDRH4 RDRH3 RDRH2 RDRH1 RDRH0
W
Reset 00000000
Figure 2-51. Port H Reduced Drive Register (RDRH)
Table 2-50. RDRH Register Field Descriptions
Field Description
7-0
RDRH Port H reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Address 0x0264 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERH1 PERH0
W
Reset 00000000
Figure 2-52. Port H Pull Device Enable Register (PERH)
Table 2-51. PERH Register Field Descriptions
Field Description
7-0
PERH Port H pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 111
2.3.55 Port H Polarity Select Register (PPSH)
2.3.56 Port H Interrupt Enable Register (PIEH)
Read: Anytime.
Address 0x0265 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPPSH7 PPSH6 PPSH5 PPSH4 PPSH3 PPSH2 PPSH1 PPSH0
W
Reset 00000000
Figure 2-53. Port H Polarity Select Register (PPSH)
Table 2-52. PPSH Register Field Descriptions
Field Description
7-0
PPSH Port H pull device select—Configure pull device and pin interrupt edge polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 A pull-down device selected; rising edge selected
0 A pull-up device selected; falling edge selected
Address 0x0266 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPIEH7 PIEH6 PIEH5 PIEH4 PIEH3 PIEH2 PIEH1 PIEH0
W
Reset 00000000
Figure 2-54. Port H Interrupt Enable Register (PIEH)
Table 2-53. PIEH Register Field Descriptions
Field Description
7-0
PIEH Port H interrupt enable—
This bit enables or disables on the edge sensitive pin interrupt on the associated pin.
1 Interrupt enabled
0 Interrupt disabled (interrupt flag masked)
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
112 Freescale Semiconductor
2.3.57 Port H Interrupt Flag Register (PIFH)
2.3.58 Port J Data Register (PTJ)
Address 0x0267 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPIFH7 PIFH6 PIFH5 PIFH4 PIFH3 PIFH2 PIFH1 PIFH0
W
Reset 00000000
Figure 2-55. Port H Interrupt Flag Register (PIFH)
Table 2-54. PIFH Register Field Descriptions
Field Description
7-0
PIFH Port H interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
Address 0x0268 Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RPTJ7 PTJ6 0000
PTJ1 PTJ0
W
Reset 00000000
Figure 2-56. Port J Data Register (PTJ)
Table 2-55. PTJ Register Field Descriptions
Field Description
7-6, 1-0
PTJ Port J general purpose input/output data—Data Register, pin interrupt input/output
The associated pin can be used as general purpose I/O. In general purpose output mode the register bit value is
driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
• Pin interrupts can be generated if enabled in input or output mode.
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 113
2.3.59 Port J Input Register (PTIJ)
2.3.60 Port J Data Direction Register (DDRJ)
Address 0x0269 Access: User read1
1Read: Anytime.
Write:Never, writes to this register have no effect.
76543210
R PTIJ7 PTIJ6 0000PTIJ1 PTIJ0
W
Reset uuuuuuuu
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-57. Port J Input Register (PTIJ)
Table 2-56. PTIJ Register Field Descriptions
Field Description
7-6, 1-0
PTIJ Port J input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x026A Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RDDRJ7 DDRJ6 0000
DDRJ1 DDRJ0
W
Reset 00000000
Figure 2-58. Port J Data Direction Register (DDRJ)
Table 2-57. DDRJ Register Field Descriptions
Field Description
7-6, 1-0
DDRJ Port J data direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
Port Integration Module (S12XSPIMV1)
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114 Freescale Semiconductor
2.3.61 Port J Reduced Drive Register (RDRJ)
2.3.62 Port J Pull Device Enable Register (PERJ)
Address 0x026B Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RRDRJ7 RDRJ6 0000
RDRJ1 RDRJ0
W
Reset 00000000
Figure 2-59. Port J Reduced Drive Register (RDRJ)
Table 2-58. RDRJ Register Field Descriptions
Field Description
7-6, 1-0
RDRJ Port J reduced drive—Select reduced drive for outputs
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength).
0 Full drive strength enabled.
Address 0x026C Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPERJ7 PERJ6 0000
PERJ1 PERJ0
W
Reset 11111111
Figure 2-60. Port J Pull Device Enable Register (PERJ)
Table 2-59. PERJ Register Field Descriptions
Field Description
7-6, 1-0
PERJ Port J pull device enable—Enable pull device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 115
2.3.63 Port J Polarity Select Register (PPSJ)
2.3.64 Port J Interrupt Enable Register (PIEJ)
Read: Anytime.
Address 0x026D Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPPSJ7 PPSJ6 0000
PPSJ1 PPSJ0
W
Reset 00000000
Figure 2-61. Port J Polarity Select Register (PPSJ)
Table 2-60. PPSJ Register Field Descriptions
Field Description
7-6, 1-0
PPSJ Port J pull device select—Configure pull device and pin interrupt edge polarity on input pin
This bit selects a pull-up or a pull-down device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 A pull-down device selected; rising edge selected
0 A pull-up device selected; falling edge selected
Address 0x026E Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPIEJ7 PIEJ6 0000
PIEJ1 PIEJ0
W
Reset 00000000
Figure 2-62. Port J Interrupt Enable Register (PIEJ)
Table 2-61. PIEJ Register Field Descriptions
Field Description
7-6, 1-0
PIEJ Port J interrupt enable—
This bit enables or disables on the edge sensitive pin interrupt on the associated pin.
1 Interrupt enabled
0 Interrupt disabled (interrupt flag masked)
Port Integration Module (S12XSPIMV1)
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116 Freescale Semiconductor
2.3.65 Port J Interrupt Flag Register (PIFJ)
2.3.66 Port AD0 Data Register 0 (PT0AD0)
Address 0x026F Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPIFJ7 PIFJ6 0000
PIFJ1 PIFJ0
W
Reset 00000000
Figure 2-63. Port J Interrupt Flag Register (PIFJ)
Table 2-62. PIFJ Register Field Descriptions
Field Description
7-6, 1-0
PIFJ Port J interrupt flag—
The flag bit is set after an active edge was applied to the associated input pin. This can be a rising or a falling edge
based on the state of the polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
Address 0x0270 Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RPT0AD07 PT0AD06 PT0AD05 PT0AD04 PT0AD03 PT0AD02 PT0AD01 PT0AD00
W
Altern.
Function AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8
Reset 00000000
Figure 2-64. Port AD0 Data Register 0 (PT0AD0)
Table 2-63. PT0AD0 Register Field Descriptions
Field Description
7-0
PT0AD0 Port AD0 general purpose input/output data—Data Register, ATD AN analog input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Port Integration Module (S12XSPIMV1)
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Freescale Semiconductor 117
2.3.67 Port AD0 Data Register 1 (PT1AD0)
2.3.68 Port AD0 Data Direction Register 0 (DDR0AD0)
Address 0x0271 Access: User read/write1
1Read: Anytime. The data source depends on the data direction value.
Write: Anytime.
76543210
RPT1AD07 PT1AD06 PT1AD05 PT1AD04 PT1AD03 PT1AD02 PT1AD01 PT1AD00
W
Altern.
Function AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0
Reset 00000000
Figure 2-65. Port AD0 Data Register 1 (PT1AD0)
Table 2-64. PT1AD0 Register Field Descriptions
Field Description
7-0
PT1AD0 Port AD0 general purpose input/output data—Data Register, ATD AN analog input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Address 0x0272 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RDDR0AD07 DDR0AD06 DDR0AD05 DDR0AD04 DDR0AD03 DDR0AD02 DDR0AD01 DDR0AD00
W
Reset 00000000
Figure 2-66. Port AD0 Data Direction Register 0 (DDR0AD0)
Table 2-65. DDR0AD0 Register Field Descriptions
Field Description
7-0
DDR0AD0 Port AD0 data direction—
This bit determines whether the associated pin is an input or output.
To use the digital input function the ATD Digital Input Enable Register (ATD0DIEN) has to be set to logic level “1”.
1 Associated pin configured as output
0 Associated pin configured as input
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118 Freescale Semiconductor
2.3.69 Port AD0 Data Direction Register 1 (DDR1AD0)
2.3.70 Port AD0 Reduced Drive Register 0 (RDR0AD0)
Address 0x0273 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RDDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00
W
Reset 00000000
Figure 2-67. Port AD0 Data Direction Register 1 (DDR1AD0)
Table 2-66. DDR1AD0 Register Field Descriptions
Field Description
7-0
DDR1AD0 Port AD0 data direction—
This bit determines whether the associated pin is an input or output.
To use the digital input function the ATD Digital Input Enable Register (ATD0DIEN) has to be set to logic level “1”.
1 Associated pin configured as output
0 Associated pin configured as input
Address 0x0274 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RRDR0AD07 RDR0AD06 RDR0AD05 RDR0AD04 RDR0AD03 RDR0AD02 RDR0AD01 RDR0AD00
W
Reset 00000000
Figure 2-68. Port AD0 Reduced Drive Register 0 (RDR0AD0)
Table 2-67. RDR0AD0 Register Field Descriptions
Field Description
7-0
RDR0AD0 Port AD0 reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 119
2.3.71 Port AD0 Reduced Drive Register 1 (RDR1AD0)
2.3.72 Port AD0 Pull Up Enable Register 0 (PER0AD0)
Address 0x0275 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RRDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00
W
Reset 00000000
Figure 2-69. Port AD0 Reduced Drive Register 1 (RDR1AD0)
Table 2-68. RDR1AD0 Register Field Descriptions
Field Description
7-0
RDR1AD0 Port AD0 reduced drive—Select reduced drive for output pin
This bit configures the drive strength of the associated output pin as either full or reduced. If a pin is used as input
this bit has no effect. The reduced drive function is independent of which function is being used on a particular pin.
1 Reduced drive selected (approx. 1/5 of the full drive strength)
0 Full drive strength enabled
Address 0x0276 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPER0AD07 PER0AD06 PER0AD05 PER0AD04 PER0AD03 PER0AD02 PER0AD01 PER0AD00
W
Reset 00000000
Figure 2-70. Port AD0 Pull Device Up Register 0 (PER0AD0)
Table 2-69. PER0AD0 Register Field Descriptions
Field Description
7-0
PER0AD0 Port AD0 pull device enable—Enable pull-up device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
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120 Freescale Semiconductor
2.3.73 Port AD0 Pull Up Enable Register 1 (PER1AD0)
2.3.74 PIM Reserved Registers
2.4 Functional Description
2.4.1 General
Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an
output or input of a peripheral module.
Address 0x0277 Access: User read/write1
1Read: Anytime.
Write: Anytime.
76543210
RPER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00
W
Reset 00000000
Figure 2-71. Port AD0 Pull Up Enable Register 1 (PER1AD0)
Table 2-70. PER1AD0 Register Field Descriptions
Field Description
7-0
PER1AD0 Port AD0 pull device enable—Enable pull-up device on input pin
This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has
no effect. The polarity is selected by the related polarity select register bit.
1 Pull device enabled
0 Pull device disabled
Address 0x0278-0x27F Access: User read1
1Read: Always reads 0x00
Write: Unimplemented
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved u = Unaffected by reset
Figure 2-72. PIM Reserved Registers
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 121
2.4.2 Registers
A set of configuration registers is common to all ports with exception of the ATD port (Table 2-71). All
registers can be written at any time, however a specific configuration might not become active.
For example selecting a pull-up device: This device does not become active while the port is used as a
push-pull output.
2.4.2.1 Data register (PORTx, PTx)
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This
is independent of any other configuration (Figure 2-73).
2.4.2.2 Input register (PTIx)
This is a read-only register and always returns the buffered state of the pin (Figure 2-73).
2.4.2.3 Data direction register (DDRx)
This register defines whether the pin is used as a input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-73).
Independent of the pin usage with a peripheral module this register determines the source of data when
reading the associated data register address (2.4.2.1/2-121).
Table 2-71. Register availability per port1
1Each cell represents one register with individual configuration bits
Port Data Input Data
Direction Reduced
Drive Pull
Enable Polarity
Select Wired-
Or Mode Interrupt
Enable Interrupt
Flag Routing
Ayes-yesyesyes-----
Byes-yes -----
Eyes-yes -----
Kyes-yes -----
T yes yes yes yes yes yes - - - yes
S yes yes yes yes yes yes yes - - -
M yes yes yes yes yes yes yes - - yes
P yes yes yes yes yes yes - yes yes -
H yes yes yes yes yes yes - yes yes -
J yes yes yes yes yes yes - yes yes -
ADyes-yesyesyes-----
Port Integration Module (S12XSPIMV1)
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122 Freescale Semiconductor
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on port data or port input registers, when
changing the data direction register.
Figure 2-73. Illustration of I/O pin functionality
2.4.2.4 Reduced drive register (RDRx)
If the pin is used as an output this register allows the configuration of the drive strength independent of the
use with a peripheral module.
2.4.2.5 Pull device enable register (PERx)
This register turns on a pull-up or pull-down device on the related pins determined by the associated
polarity select register (2.4.2.5/2-122).
The pull device becomes active only if the pin is used as an input or as a wired-or output. Some peripheral
modules only allow certain configurations of pull devices to become active. Refer to the respective bit
descriptions.
2.4.2.6 Polarity select register (PPSx)
This register selects either a pull-up or pull-down device if enabled.
It only becomes active if the pin is used as an input. A pull-up device can be activated if the pin is used as
a wired-or output.
PT
DDR
output enable
module enable
1
0
1
1
0
0
PIN
PTI
data out
Module
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 123
2.4.2.7 Wired-or mode register (WOMx)
If the pin is used as an output this register turns off the active high drive. This allows wired-or type
connections of outputs.
2.4.2.8 Interrupt enable register (PIEx)
If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable
the interrupt.
2.4.2.9 Interrupt flag register (PIFx)
If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event.
2.4.2.10 Module routing registers (MODRR, PTTRR)
These registers allow software re-configuration of the pinouts of the different package options for specific
peripherals:
• MODRR supports the re-routing of the SCI1 and SPI0 pins to alternative ports
• PTTRR supports the re-routing of the PWM and TIM channels to alternative ports
2.4.3 Pins and Ports
NOTE
Please refer to the device pinout section to determine the pin availability in
the different package options.
2.4.3.1 BKGD pin
The BKGD pin is associated with the BDM module.
During reset, the BKGD pin is used as MODC input.
2.4.3.2 Port A, B
Port A pins PA[7:0] and Port B pins PB[7:0] can be used for general-purpose I/O.
2.4.3.3 Port E
Port E is associated with the free-running clock outputs ECLK, ECLKX2 and interrupt inputs IRQ and
XIRQ.
Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions.
Port E pin PE[7] an be used for either general-purpose I/O or as the free-running clock ECLKX2 output
running at the core clock rate.
Port E pin PE[4] an be used for either general-purpose I/O or as the free-running clock ECLK output
running at the bus clock rate or at the programmed divided clock rate.
Port Integration Module (S12XSPIMV1)
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124 Freescale Semiconductor
Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ
interrupt input. IRQ will be enabled by setting the IRQEN configuration bit (2.3.14/2-83) and clearing the
I-bit in the CPU condition code register. It is inhibited at reset so this pin is initially configured as a simple
input with a pull-up.
PortEpin PE[0] can beusedfor either general-purpose inputoras the level-sensitiveXIRQinterrupt input.
XIRQ can be enabled by clearing the X-bit in the CPU condition code register. It is inhibited at reset so
this pin is initially configured as a high-impedance input with a pull-up.
2.4.3.4 Port K
Port K pins PK[7,5:0] can be used for general-purpose I/O.
2.4.3.5 Port T
This port is associated with TIM and PWM.
Port T pins PT[7:4] can be used for either general-purpose I/O, or with the PWM or with the channels of
the standard Timer subsystem.
Port T pins PT[3:0] can be used for either general-purpose I/O, or with the channels of the standard Timer
subsystem.
The TIM pins IOC2-0 can be re-routed.
2.4.3.6 Port S
This port is associated with SPI0, SCI0 and SCI1.
Port S pins PS[7:4] can be used either for general-purpose I/O, or with the SPI0 subsystem.
Port S pins PS[3:2] can be used either for general-purpose I/O, or with the SCI1 subsystem.
Port S pins PS[1:0] can be used either for general-purpose I/O, or with the SCI0 subsystem.
The SPI0 and SCI1 pins can be re-routed.
2.4.3.7 Port M
This port is associated with CAN0 and SCI1.
Port M pins PM[7:6] can be used for either general purpose I/O.
Port M pins PM[1:0] can be used for either general purpose I/O, or with the CAN0 or with the SCI1
subsystem.
Port M pins PM[5:2] can be used for general purpose I/O.
2.4.3.8 Port P
This port is associated with the PWM, TIM and SCI1.
Port Integration Module (S12XSPIMV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 125
Port P pins PP[7:3] can be used for either general purpose I/O with pin interrupt capability, or with the
PWM or with the channels of the standard Timer.subsystem.
Port P pins PP[2,0] can be used for either general purpose I/O, or with the PWM or with the TIM or with
the SCI1 subsystem.
Port P pin PP[1] can be used for either general purpose I/O, or with the PWM or with the TIM subsystem.
2.4.3.9 Port H
Port H pins PH[7:0] can be used for general purpose I/O with pin interrupt capability.
2.4.3.10 Port J
Port J pins PJ[7,6,1,0] can be used for general purpose I/O with pin-interrupt capability.
2.4.3.11 Port AD
This port is associated with the ATD.
Port AD pins PAD[15:0] can be used for either general purpose I/O, or with the ATD0 subsystem.
2.4.4 Pin interrupts
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or
falling edges can be individually configured on a per-pin basis. All bits/pins in a port share the same
interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses (Figure 2-75) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-74 and
Table 2-72).
Figure 2-74. Interrupt Glitch Filter on Port P, H and J (PPS=0)
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
tpign
tpval
uncertain
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Table 2-72. Pulse Detection Criteria
Figure 2-75. Pulse Illustration
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4
consecutive samples of an active level directly or indirectly.
The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock
is generated by an RC-oscillator in the Port Integration Module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin individually:
Sample count <= 4 and interrupt enabled (PIE=1) and interrupt flag not set (PIF=0).
2.5 Initialization Information
2.5.1 Port Data and Data Direction Register writes
It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins
from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data
register before enabling the outputs.
Pulse
Mode
STOP STOP1
1These values include the spread of the oscillator frequency over tempera-
ture, voltage and process.
Unit
Ignored tpulse ≤ 3 bus clocks tpulse ≤ tpign
Uncertain 3 < tpulse < 4 bus clocks tpign < tpulse < tpval
Valid tpulse ≥ 4 bus clocks tpulse ≥ tpval
tpulse
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Chapter 3
Memory Mapping Control (S12XMMCV4)
Revision History
3.1 Introduction
This section describes the functionality of the module mapping control (MMC) sub-block of the S12X
platform. The block diagram of the MMC is shown in Figure 3-1.
The MMC module controls the multi-master priority accesses, the selection of internal resources . Internal
buses, including internal memories and peripherals, are controlled in this module. The local address space
for each master is translated to a global memory space.
Rev. No.
(Item No.) Date (Submitted
By) Sections
Affected Substantial Change(s)
v04.09 01-Feb-08 - Minor changes
v04.10 17-Feb-09 - Minor changes
v04.11 30-Jun-10 3.3.2.7/3-139 - Removed confusing statements in EPAGE description
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3.1.1 Terminology
3.1.2 Features
The main features of this block are:
• Paging capability to support a global 8MB memory address space
• Bus arbitration between the masters CPU, BDM
• Simultaneous accesses to different resources1 (internal, and peripherals) (see Figure 3-1 )
• Resolution of target bus access collision
• MCU operation mode control
• MCU security control
• Separate memory map schemes for each master CPU, BDM
• ROM control bits to enable the on-chip FLASH or ROM selection
• Generation of system reset when CPU accesses an unimplemented address (i.e., an address which
does not belong to any of the on-chip modules) in single-chip modes
Table 3-1. Acronyms and Abbreviations
Logic level “1” Voltage that corresponds to Boolean true state
Logic level “0” Voltage that corresponds to Boolean false state
0x Represents hexadecimal number
x Represents logic level ’don’t care’
Byte 8-bit data
word 16-bit data
local address based on the 64KB Memory Space (16-bit address)
global address based on the 8MB Memory Space (23-bit address)
Aligned address Address on even boundary
Mis-aligned address Address on odd boundary
Bus Clock System Clock. Refer to CRG Block Guide.
single-chip modes Normal Single-Chip Mode
Special Single-Chip Mode
normal modes Normal Single-Chip Mode
special modes Special Single-Chip Mode
NS Normal Single-Chip Mode
SS Special Single-Chip Mode
Unimplemented areas Areas which are accessible by the pages (RPAGE,PPAGE,EPAGE) and not implemented
PRR Port Replacement Registers
PRU Port Replacement Unit located on the emulator side
MCU MicroController Unit
NVM Non-volatile Memory; Flash, Data FLASH or ROM
IFR Information Row sector located on the top of NVM. For Test purposes.
1. Resources are also called targets.
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3.1.3 S12X Memory Mapping
The S12X architecture implements a number of memory mapping schemes including
• a CPU 8MB global map, defined using a global page (GPAGE) register and dedicated 23-bit
address load/store instructions.
• a BDM 8MB global map, defined using a global page (BDMGPR) register and dedicated 23-bit
address load/store instructions.
• a (CPU or BDM) 64KB local map, defined using specific resource page (RPAGE, EPAGE and
PPAGE) registers and the default instruction set. The 64KB visible at any instant can be considered
as the local map accessed by the 16-bit (CPU or BDM) address.
The MMC module performs translation of the different memory mapping schemes to the specific global
(physical) memory implementation.
3.1.4 Modes of Operation
This subsection lists and briefly describes all operating modes supported by the MMC.
3.1.4.1 Power Saving Modes
• Run mode
MMC is functional during normal run mode.
• Wait mode
MMC is functional during wait mode.
• Stop mode
MMC is inactive during stop mode.
3.1.4.2 Functional Modes
• Single chip modes
In normal and special single chip mode the internal memory is used.
3.1.5 Block Diagram
Figure 3-1 shows a block diagram of the MMC.
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Figure 3-1. MMC Block Diagram
3.2 External Signal Description
The user is advised to refer to the SoC Guide for port configuration and location of external bus signals.
Some pins may not be bonded out in all implementations.
Table 3-2 outlines the pin names and functions. It also provides a brief description of their operation.
Table 3-2. External Input Signals Associated with the MMC
Signal I/O Description Availability
MODC I Mode input Latched after
RESET (active low)
CPU
BDM
Target Bus Controller
DBG
MMC
Address Decoder & Priority
Peripherals
PGMFLASHData FLASH RAM
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3.3 Memory Map and Registers
3.3.1 Module Memory Map
A summary of the registers associated with the MMC block is shown in Figure 3-2. Detailed descriptions
of the registers and bits are given in the subsections that follow.
3.3.2 Register Descriptions
Address Register
Name Bit 7 6 5 4 3 2 1 Bit 0
0x000A Reserved R 0 0 0 0 0 0 0 0
W
0x000B MODE R MODC 0000000
W
0x0010 GPAGE R 0 GP6 GP5 GP4 GP3 GP2 GP1 GP0
W
0x0011 DIRECT R DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8
W
0x0012 Reserved R 0 0 0 0 0 0 0 0
W
0x0013 MMCCTL1 R MGRAMON 0DFIFRON PGMIFRON 0000
W
0x0014 Reserved R 0 0 0 0 0 0 0 0
W
0x0015 PPAGE R PIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
W
0x0016 RPAGE R RP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0
W
0x0017 EPAGE R EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0
W
= Unimplemented or Reserved
Figure 3-2. MMC Register Summary
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3.3.2.1 Mode Register (MODE)
Read: Anytime. Write: Only if a transition is allowed (see Figure 3-5).
The MODE bits of the MODE register are used to establish the MCU operating mode.
Figure 3-4.
Figure 3-5. Mode Transition Diagram when MCU is Unsecured
Address: 0x000B PRR
76543210
RMODC 0000000
W
Reset MODC10000000
1. External signal (see Table 3-2).
= Unimplemented or Reserved
Figure 3-3. Mode Register (MODE)
Table 3-3. MODE Field Descriptions
Field Description
7
MODC Mode Select Bit — This bit controls the current operating mode during RESET high (inactive). The external
mode pin MODC determines the operating mode during RESET low (active). The state of the pin is latched into
the respective register bit after the RESET signal goes inactive (see Figure 3-3).
Write restrictions exist to disallow transitions between certain modes. Figure 3-5 illustrates all allowed mode
changes. Attempting non authorized transitions will not change the MODE bits, but it will block further writes to
these register bits except in special modes.
Write accesses to the MODE register are blocked when the device is secured.
Normal
Single-Chip
1
Special
Single-Chip
0
RESET
(SS) 0
RESET 1(NS)
RESET
Transition done by external pins (MODC)
Transition done by write access to the MODE register
1
State
State
State
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3.3.2.2 Global Page Index Register (GPAGE)
Read: Anytime
Write: Anytime
The global page index register is used to construct a 23 bit address in the global map format. It is only used
when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX,
GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide). The generated global
address is the result of concatenation of the CPU local address [15:0] with the GPAGE register [22:16] (see
Figure 3-7).
Figure 3-7. GPAGE Address Mapping
Example 3-1. This example demonstrates usage of the GPAGE register
LDX #0x5000 ;Set GPAGE offset to the value of 0x5000
MOVB #0x14, GPAGE ;Initialize GPAGE register with the value of 0x14
GLDAA X ;Load Accu A from the global address 0x14_5000
Address: 0x0010
76543210
R0 GP6 GP5 GP4 GP3 GP2 GP1 GP0
W
Reset 00000000
= Unimplemented or Reserved
Figure 3-6. Global Page Index Register (GPAGE)
Table 3-4. GPAGE Field Descriptions
Field Description
6–0
GP[6:0] Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64KB pages is to be
accessed.
Bit16 Bit 0Bit15Bit22
CPU Address [15:0]GPAGE Register [6:0]
Global Address [22:0]
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3.3.2.3 Direct Page Register (DIRECT)
Read: Anytime
Write: anytime in special modes, one time only in other modes.
This register determines the position of the 256B direct page within the memory map.It is valid for both
global and local mapping scheme.
Figure 3-9. DIRECT Address Mapping
Bits [22:16] of the global address will be formed by the GPAGE[6:0] bits in case the CPU executes a global
instruction in direct addressing mode or by the appropriate local address to the global address expansion
(refer to Section 3.4.2.1.1, “Expansion of the Local Address Map).
Example 3-2. This example demonstrates usage of the Direct Addressing Mode
MOVB #0x80,DIRECT ;Set DIRECT register to 0x80. Write once only.
;Global data accesses to the range 0xXX_80XX can be direct.
;Logical data accesses to the range 0x80XX are direct.
LDY <00 ;Load the Y index register from 0x8000 (direct access).
;< operator forces direct access on some assemblers but in
;many cases assemblers are “direct page aware” and can
;automatically select direct mode.
Address: 0x0011
76543210
RDP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8
W
Reset 00000000
Figure 3-8. Direct Register (DIRECT)
Table 3-5. DIRECT Field Descriptions
Field Description
7–0
DP[15:8] Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct
addressing mode. The bits from this register form bits [15:8] of the address (see Figure 3-9).
Bit15 Bit0
Bit7
Bit22
CPU Address [15:0]
Global Address [22:0]
Bit8
Bit16
DP [15:8]
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3.3.2.4 MMC Control Register (MMCCTL1)
Read: Anytime. .
Write: Refer to each bit description.
3.3.2.5 Program Page Index Register (PPAGE)
Read: Anytime
Address: 0x0013 PRR
76543210
RMGRAMON 0DFIFRON PGMIFRON 0000
W
Reset 00000000
= Unimplemented or Reserved
Figure 3-10. MMC Control Register (MMCCTL1)
Table 3-6. MMCCTL1 Field Descriptions
Field Description
7
MGRAMON Flash Memory Controller SCRATCH RAM visible in the global memory map
Write: Anytime
This bit is used to made the Flash Memory Controller SCRATCH RAM visible in the global memory map.
0 Not visible in the global memory map.
1 Visible in the global memory map.
5
DFIFRON Data Flash Information Row (IFR) visible in the global memory map
Write: Anytime
This bit is used to made the IFR sector of the Data Flash visible in the global memory map.
0 Not visible in the global memory map.
1 Visible in the global memory map.
4
PGMIFRON Program Flash Information Row (IFR) visible in the global memory map
Write: Anytime
Thisbit is used to map the IFR sector of theProgram Flash to address range 0x40_000-0x40_3FFF of the global
memory map.
0 Not visible in the global memory map.
1 Visible in the global memory map.
Address: 0x0015
76543210
RPIX7 PIX6 PIX5 PIX4 PIX3 PIX2 PIX1 PIX0
W
Reset 11111110
Figure 3-11. Program Page Index Register (PPAGE)
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Write: Anytime
These eight index bits are used to page 16KB blocks into the Flash page window located in the local (CPU
or BDM) memory map from address 0x8000 to address 0xBFFF (see Figure 3-12). This supports
accessing up to 4MB of Flash (in the Global map) within the 64KB Local map. The PPAGE register is
effectively used to construct paged Flash addresses in the Local map format. The CPU has special access
to read and write this register directly during execution of CALL and RTC instructions..
Figure 3-12. PPAGE Address Mapping
NOTE
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
The reset value of 0xFE ensures that there is linear Flash space available between addresses 0x4000 and
0xFFFF out of reset.
The fixed 16K page from 0xC000-0xFFFF is the page number 0xFF.
3.3.2.6 RAM Page Index Register (RPAGE)
Table 3-7. PPAGE Field Descriptions
Field Description
7–0
PIX[7:0] Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM
array pages is to be accessed in the Program Page Window.
Address: 0x0016
76543210
RRP7 RP6 RP5 RP4 RP3 RP2 RP1 RP0
W
Reset 11111101
Figure 3-13. RAM Page Index Register (RPAGE)
Bit14 Bit0
1
Address [13:0]
PPAGE Register [7:0]
Global Address [22:0]
Bit13
Bit21
Address: CPU Local Address
or BDM Local Address
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Read: Anytime
Write: Anytime
These eight index bits are used to page 4KB blocks into the RAM page window located in the local (CPU
or BDM) memory map from address 0x1000 to address 0x1FFF (see Figure 3-14). This supports accessing
up to 1022KB of RAM (in the Global map) within the 64KB Local map. The RAM page index register is
effectively used to construct paged RAM addresses in the Local map format.
Figure 3-14. RPAGE Address Mapping
NOTE
Because RAM page 0 has the same global address as the register space, it is
possible to write to registers through the RAM space when RPAGE = 0x00.
The reset value of 0xFD ensures that there is a linear RAM space available between addresses 0x1000 and
0x3FFF out of reset.
The fixed 4K page from 0x2000–0x2FFF of RAM is equivalent to page 254 (page number 0xFE).
The fixed 4K page from 0x3000–0x3FFF of RAM is equivalent to page 255 (page number 0xFF).
NOTE
The page 0xFD (reset value) contains unimplemented area in the range not
occupied by RAM if RAMSIZE is less than 12KB (Refer to Section 3.4.2.3,
“Implemented Memory Map).
Table 3-8. RPAGE Field Descriptions
Field Description
7–0
RP[7:0] RAM Page Index Bits 7–0 — These page index bits are used to select which of the 256 RAM array pages is to
be accessed in the RAM Page Window.
Bit18 Bit0
Bit11
0
Address [11:0]
RPAGE Register [7:0]
Global Address [22:0]
Bit12
Bit19
0
Address: CPU Local Address
or BDM Local Address
0
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3.3.2.7 Data FLASH Page Index Register (EPAGE)
Read: Anytime
Write: Anytime
These eight index bits are used to page 1KB blocks into the Data FLASH page window located in the local
(CPU or BDM) memory map from address 0x0800 to address 0x0BFF (see Figure 3-16). This supports
accessing up to 256KB of Data FLASH (in the Global map) within the 64KB Local map. The Data FLASH
page index register is effectively used to construct paged Data FLASH addresses in the Local map format.
Figure 3-16. EPAGE Address Mapping
Address: 0x0017
76543210
REP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0
W
Reset 11111110
Figure 3-15. Data FLASH Page Index Register (EPAGE)
Table 3-9. EPAGE Field Descriptions
Field Description
7–0
EP[7:0] Data FLASH Page Index Bits 7–0 — These page index bits are used to select which of the 256 Data FLASH
array pages is to be accessed in the Data FLASH Page Window.
Bit16 Bit0
Bit9
Address [9:0]
EPAGE Register [7:0]
Global Address [22:0]
Bit10
Bit17
00 100
Address: CPU Local Address
or BDM Local Address
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3.4 Functional Description
The MMC block performs several basic functions of the S12X sub-system operation: MCU operation
modes, priority control, address mapping, select signal generation and access limitations for the system.
Each aspect is described in the following subsections.
3.4.1 MCU Operating Mode
• Normal single-chip mode
There is no external bus in this mode. The MCU program is executed from the internal memory
and no external accesses are allowed.
• Special single-chip mode
This mode is generally used for debugging single-chip operation, boot-strapping or security related
operations. The active background debug mode is in control of the CPU code execution and the
BDM firmware is waiting for serial commands sent through the BKGD pin. There is no external
bus in this mode.
3.4.2 Memory Map Scheme
3.4.2.1 CPU and BDM Memory Map Scheme
The BDM firmware lookup tables and BDM register memory locations share addresses with other
modules; however they are not visible in the global memory map during user’s code execution. The BDM
memory resources are enabled only during the READ_BD and WRITE_BD access cycles to distinguish
between accesses to the BDM memory area and accesses to the other modules. (Refer to BDM Block
Guide for further details).
When the MCU enters active BDM mode, the BDM firmware lookup tables and the BDM registers
become visible in the local memory map in the range 0xFF00-0xFFFF (global address 0x7F_FF00 -
0x7F_FFFF) and the CPU begins execution of firmware commands or the BDM begins execution of
hardware commands. The resources which share memory space with the BDM module will not be visible
in the global memory map during active BDM mode.
Please note that after the MCU enters active BDM mode the BDM firmware lookup tables and the BDM
registers will also be visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value
of 0xFF.
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Figure 3-17. Expansion of the Local Address Map
0x7F_FFFF
0x00_0000
0x14_0000
0x10_0000
0x00_0800
EPAGE
RPAGE
PPAGE
CPU and BDM
Local Memory Map Global Memory Map
0xFFFF Reset Vectors
0xC000
0x8000
Unpaged
0x4000
0x1000
0x0000
16KB FLASH window
0x0C00
0x2000
0x0800
8KB RAM
4KB RAM window
Reserved
2KB REGISTERS
1KB Data Flash window
16KB FLASH
Unpaged
16KB FLASH
2KB REGISTERS
2KB RAM
253*4KB paged
RAM
256*1KB paged
Data FLASH
253 *16KB paged
FLASH
16KB FLASH
(PPAGE 0xFD)
8KB RAM
16KB FLASH
(PPAGE 0xFE)
16KB FLASH
(PPAGE 0xFF)
0x00_1000
0x0F_E000
0x13_FC00
0x40_0000
0x7F_4000
0x7F_8000
0x7F_C000
1M minus 2KB
256KB
4MB 2.75MB
Unimplemented
Space
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3.4.2.1.1 Expansion of the Local Address Map
Expansion of the CPU Local Address Map
The program page index register in MMC allows accessing up to 4MB of FLASH or ROM in the global
memory map by using the eight page index bits to page 256 16KB blocks into the program page window
located from address 0x8000 to address 0xBFFF in the local CPU memory map.
The page value for the program page window is stored in the PPAGE register. The value of the PPAGE
register can be read or written by normal memory accesses as well as by the CALL and RTC instructions
(see Section 3.5.1, “CALL and RTC Instructions).
Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the
64KB local CPU address space.
The starting address of an interrupt service routine must be located in unpaged memory unless the user is
certain that the PPAGE register will be set to the appropriate value when the service routine is called.
However an interrupt service routine can call other routines that are in paged memory. The upper 16KB
block of the local CPU memory space (0xC000–0xFFFF) is unpaged. It is recommended that all reset and
interrupt vectors point to locations in this area or to the other unpaged sections of the local CPU memory
map.
The RAM page index register allows accessing up to 1MB minus 2KB of RAM in the global memory map
by using the eight RPAGE index bits to page 4KB blocks into the RAM page window located in the local
CPU memory space from address 0x1000 to address 0x1FFF. The Data FLASH page index register
EPAGE allows accessing up to 256KB of Data Flash in the system by using the eight EPAGE index bits to
page 1KB blocks into the Data FLASH page window located in the local CPU memory space from address
0x0800 to address 0x0BFF.
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Expansion of the BDM Local Address Map
PPAGE, RPAGE, and EPAGE registers are also used for the expansion of the BDM local address to the
global address. These registers can be read and written by the BDM.
The BDM expansion scheme is the same as the CPU expansion scheme.
3.4.2.2 Global Addresses Based on the Global Page
CPU Global Addresses Based on the Global Page
The seven global page index bits allow access to the full 8MB address map that can be accessed with 23
address bits. This provides an alternative way to access all of the various pages of FLASH, RAM and Data
FLASH.
The GPAGE Register is used only when the CPU is executing a global instruction (see Section 3.3.2.2,
“Global Page Index Register (GPAGE)). The generated global address is the result of concatenation of the
CPU local address [15:0] with the GPAGE register [22:16] (see Figure 3-7).
BDM Global Addresses Based on the Global Page
The seven BDMGPR Global Page index bits allow access to the full 8MB address map that can be accessed
with 23 address bits. This provides an alternative way to access all of the various pages of FLASH, RAM
and Data FLASH.
The BDM global page index register (BDMGPR) is used only in the case the CPU is executing a firmware
command which uses a global instruction (like GLDD, GSTD) or by a BDM hardware command (like
WRITE_W, WRITE_BYTE, READ_W, READ_BYTE). See the BDM Block Guide for further details.
The generated global address is a result of concatenation of the BDM local address with the BDMGPR
register [22:16] in the case of a hardware command or concatenation of the CPU local address and the
BDMGPR register [22:16] in the case of a firmware command (see Figure 3-18).
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Figure 3-18. BDMGPR Address Mapping
3.4.2.3 Implemented Memory Map
The global memory spaces reserved for the internal resources (RAM, Data FLASH, and FLASH) are not
determined by the MMC module. Size of the individual internal resources are however fixed in the design
of the device cannot be changed by the user. Please refer to the SoC Guide for further details. Figure 3-19
and Table 3-10 show the memory spaces occupied by the on-chip resources. Please note that the memory
spaces have fixed top addresses.
Table 3-10. Global Implemented Memory Space
Internal Resource $Address
RAM RAM_LOW = 0x10_0000 minus RAMSIZE1
1RAMSIZE is the hexadecimal value of RAM SIZE in Bytes
Data FLASH DF_HIGH = 0x10_0000 plus DFLASHSIZE2
2DFLASHSIZE is the hexadecimal value of DFLASH SIZE in Bytes
FLASH FLASH_LOW = 0x80_0000 minus FLASHSIZE3
3FLASHSIZE is the hexadecimal value of FLASH SIZE in Bytes
Bit16 Bit0Bit15Bit22
BDM Local Address
BDMGPR Register [6:0]
Global Address [22:0]
Bit16 Bit0Bit15Bit22
CPU Local Address
BDMGPR Register [6:0]
Global Address [22:0]
BDM HARDWARE COMMAND
BDM FIRMWARE COMMAND
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In single-chip modes accesses by the CPU (except for firmware commands) to any of the unimplemented
areas (see Figure 3-19) will result in an illegal access reset (system reset) in case of no MPU error. BDM
accesses to the unimplemented areas are allowed but the data will be undefined.No misaligned word access
from the BDM module will occur; these accesses are blocked in the BDM module (Refer to BDM Block
Guide).
Misaligned word access to the last location of RAM is performed but the data will be undefined.
Misaligned word access to the last location of any global page (64KB) by any global instruction, is
performed by accessing the last byte of the page and the first byte of the same page, considering the above
mentioned misaligned access cases.
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Figure 3-19. S12X CPU & BDM Global Address Mapping
0x7F_FFFF
0x00_0000
0x13_FFFF
0x0F_FFFF
Data FLASH
RAM
0x00_07FF
EPAGE
RPAGE
PPAGE 0x3F_FFFF
CPU and BDM
Local Memory Map Global Memory Map
FLASHSIZE RAMSIZE
0xFFFF Reset Vectors
0xC000
0x8000
Unpaged
0x4000
0x1000
0x0000
16K FLASH window
0x0C00
0x2000
0x0800
8K RAM
4K RAM window
Reserved
2K REGISTERS
1K Data Flash window
16K FLASH
Unpaged
16K FLASH
2K REGISTERS
Unimplemented
RAM
RAM_LOW
FLASH
FLASH_LOW
Unimplemented
FLASH
Unimplemented
Space
DF_HIGH Data FLASH
Resources
DFLASHSIZE
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3.4.3 Chip Bus Control
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM )
with the rest of the system (master buses). In addition the MMC handles all CPU read data bus swapping
operations. All internal resources are connected to specific target buses (see Figure 3-20).
Figure 3-20. MMC Block Diagram
CPU
BDM
Target Bus Controller
DBG
MMC
Address Decoder & Priority
Peripherals
PGMFLASHData FLASH RAM
S12X1 S12X0
XBUS0
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3.4.3.1 Master Bus Prioritization regarding access conflicts on Target Buses
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
• CPU always has priority over BDM .
• BDM has priority over CPU when its access is stalled for more than 128 cycles. In the later case
the suspect master will be stalled after finishing the current operation and the BDM will gain access
to the bus.
3.5 Initialization/Application Information
3.5.1 CALL and RTC Instructions
CALL and RTC instructions are uninterruptible CPU instructions that automate page switching in the
program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is
called can be located anywhere in the local address space or in any Flash or ROM page visible through the
program page window. The CALL instruction calculates and stacks a return address, stacks the current
PPAGE value and writes a new instruction-supplied value to the PPAGE register. The PPAGE value
controls which of the 256 possible pages is visible through the 16KB program page window in the 64KB
local CPU memory map. Execution then begins at the address of the called subroutine.
During the execution of the CALL instruction, the CPU performs the following steps:
1. Writes the current PPAGE value into an internal temporary register and writes the new instruction-
supplied PPAGE value into the PPAGE register
2. Calculates the address of the next instruction after the CALL instruction (the return address) and
pushes this 16-bit value onto the stack
3. Pushes the temporarily stored PPAGE value onto the stack
4. Calculates the effective address of the subroutine, refills the queue and begins execution at the new
address
This sequence is uninterruptible. There is no need to inhibit interrupts during the CALL instruction
execution. A CALL instruction can be performed from any address to any other address in the local CPU
memory space.
The PPAGE value supplied by the instruction is part of the effective address of the CPU. For all addressing
mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand
in the instruction. In indexed-indirect variations of the CALL instruction a pointer specifies memory
locations where the new page value and the address of the called subroutine are stored. Using indirect
addressing for both the new page value and the address within the page allows usage of values calculated
at run time rather than immediate values that must be known at the time of assembly.
The RTC instruction terminates subroutines invoked by a CALL instruction. The RTC instruction unstacks
the PPAGE value and the return address and refills the queue. Execution resumes with the next instruction
after the CALL instruction.
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During the execution of an RTC instruction the CPU performs the following steps:
1. Pulls the previously stored PPAGE value from the stack
2. Pulls the 16-bit return address from the stack and loads it into the PC
3. Writes the PPAGE value into the PPAGE register
4. Refills the queue and resumes execution at the return address
This sequence is uninterruptible. The RTC can be executed from anywhere in the local CPU memory
space.
The CALL and RTC instructions behave like JSR and RTS instruction, they however require more
execution cycles. Usage of JSR/RTS instructions is therefore recommended when possible and
CALL/RTC instructions should only be used when needed. The JSR and RTS instructions can be used to
access subroutines that are already present in the local CPU memory map (i.e. in the same page in the
program memory page window for example). However calling a function located in a different page
requires usage of the CALL instruction. The function must be terminated by the RTC instruction. Because
the RTC instruction restores contents of the PPAGE register from the stack, functions terminated with the
RTC instruction must be called using the CALL instruction even when the correct page is already present
in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time
of the RTC instruction execution.
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Chapter 4
Interrupt (S12XINTV2)
4.1 Introduction
The XINT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to either the CPU or the XGATE module. The XINT module supports:
• I bit and X bit maskable interrupt requests
• One non-maskable unimplemented op-code trap
• One non-maskable software interrupt (SWI) or background debug mode request
• One non-maskable system call interrupt (SYS)
• Three non-maskable access violation interrupt
• One spurious interrupt vector request
• Three system reset vector requests
Each of the I bit maskable interrupt requests can be assigned to one of seven priority levels supporting a
flexible priority scheme. For interrupt requests that are configured to be handled by the CPU, the priority
scheme can be used to implement nested interrupt capability where interrupts from a lower level are
automatically blocked if a higher level interrupt is being processed. Interrupt requests configured to be
handled by the XGATE module can be nested one level deep.
NOTE
The HPRIO register and functionality of the original S12 interrupt module
is no longer supported, since it is superseded by the 7-level interrupt request
priority scheme.
Table 4-1. Revision History
Revision
Number Revision Date Sections
Affected Description of Changes
V02.00 01 Jul 2005 4.1.2/4-152 Initial V2 release, added new features:
- XGATE threads can be interrupted.
- SYS instruction vector.
- Access violation interrupt vectors.
V02.04 11 Jan 2007 4.3.2.2/4-157
4.3.2.4/4-158 - Added Notes for devices without XGATE module.
V02.05 20 Mar 2007 4.4.6/4-164 - Fixed priority definition for software exceptions.
V02.06 07 Jan 2008 4.5.3.1/4-166 - Added clarification of “Wake-up from STOP or WAIT by XIRQ with X bit set”
feature.
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4.1.1 Glossary
The following terms and abbreviations are used in the document.
4.1.2 Features
• Interrupt vector base register (IVBR)
• One spurious interrupt vector (at address vector base1 + 0x0010).
• One non-maskable system call interrupt vector request (at address vector base + 0x0012).
• Three non-maskable access violation interrupt vector requests (at address vector base + 0x0014−
0x0018).
• 2–109 I bit maskable interrupt vector requests (at addresses vector base + 0x001A–0x00F2).
• Each I bit maskable interrupt request has a configurable priority level and can be configured to be
handled by either the CPU or the XGATE module2.
• I bit maskable interrupts can be nested, depending on their priority levels.
• One X bit maskable interrupt vector request (at address vector base + 0x00F4).
• One non-maskable software interrupt request (SWI) or background debug mode vector request (at
address vector base + 0x00F6).
• One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).
• Three system reset vectors (at addresses 0xFFFA–0xFFFE).
• Determines the highest priority XGATE and interrupt vector requests, drives the vector to the
XGATE module or to the bus on CPU request, respectively.
• Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or
whenever XIRQ is asserted, even if X interrupt is masked.
• XGATE can wake up and execute code, even with the CPU remaining in stop or wait mode.
Table 4-2. Terminology
Term Meaning
CCR Condition Code Register (in the S12X CPU)
DMA Direct Memory Access
INT Interrupt
IPL Interrupt Processing Level
ISR Interrupt Service Routine
MCU Micro-Controller Unit
XGATE refers to the XGATE co-processor; XGATE is an optional feature
IRQ refers to the interrupt request associated with the IRQ pin
XIRQ refers to the interrupt request associated with the XIRQ pin
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
as upper byte) and 0x00 (used as lower byte).
2. The IRQ interrupt can only be handled by the CPU
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4.1.3 Modes of Operation
• Run mode
This is the basic mode of operation.
• Wait mode
In wait mode, the XINT module is frozen. It is however capable of either waking up the CPU if an
interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to
Section 4.5.3, “Wake Up from Stop or Wait Mode” for details.
• Stop Mode
In stop mode, the XINT module is frozen. It is however capable of either waking up the CPU if an
interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to
Section 4.5.3, “Wake Up from Stop or Wait Mode” for details.
• Freeze mode (BDM active)
In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please
refer to Section 4.3.2.1, “Interrupt Vector Base Register (IVBR)” for details.
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4.1.4 Block Diagram
Figure 4-1 shows a block diagram of the XINT module.
Figure 4-1. XINT Block Diagram
4.2 External Signal Description
The XINT module has no external signals.
Wake Up
Current
RQST
IVBR
One Set Per Channel
XGATE
Interrupts
XGATE
Requests
Interrupt
Requests
Interrupt Requests CPU
Vector
Address
New
IPL
IPL
(Up to 108 Channels)
RQST XGATE Request Route,
PRIOLVLn Priority Level
= bits from the channel configuration
in the associated configuration register
INT_XGPRIO = XGATE Interrupt Priority
IVBR = Interrupt Vector Base
IPL = Interrupt Processing Level
PRIOLVL0
PRIOLVL1
PRIOLVL2
INT_XGPRIO
Peripheral
Vector
ID
To XGATE Module
Priority
Decoder
To CPU
Priority
Decoder
Non I Bit Maskable
Channels
Wake up
XGATE
IRQ Channel
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4.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the XINT module.
4.3.1 Module Memory Map
Table 4-3 gives an overview over all XINT module registers.
Table 4-3. XINT Memory Map
Address Use Access
0x0120 RESERVED —
0x0121 Interrupt Vector Base Register (IVBR) R/W
0x0122–0x0125 RESERVED —
0x0126 XGATE Interrupt Priority Configuration Register
(INT_XGPRIO) R/W
0x0127 Interrupt Request Configuration Address Register
(INT_CFADDR) R/W
0x0128 Interrupt Request Configuration Data Register 0
(INT_CFDATA0) R/W
0x0129 Interrupt Request Configuration Data Register 1
(INT_CFDATA1) R/W
0x012A Interrupt Request Configuration Data Register 2
(INT_CFDATA2 R/W
0x012B Interrupt Request Configuration Data Register 3
(INT_CFDATA3) R/W
0x012C Interrupt Request Configuration Data Register 4
(INT_CFDATA4) R/W
0x012D Interrupt Request Configuration Data Register 5
(INT_CFDATA5) R/W
0x012E Interrupt Request Configuration Data Register 6
(INT_CFDATA6) R/W
0x012F Interrupt Request Configuration Data Register 7
(INT_CFDATA7) R/W
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4.3.2 Register Descriptions
This section describes in address order all the XINT module registers and their individual bits.
Address Register
Name Bit 7 654321Bit 0
0x0121 IVBR R IVB_ADDR[7:0]7
W
0x0126 INT_XGPRIO R 00000 XILVL[2:0]
W
0x0127 INT_CFADDR R INT_CFADDR[7:4] 0000
W
0x0128 INT_CFDATA0 R RQST 0000 PRIOLVL[2:0]
W
0x0129 INT_CFDATA1 R RQST 0000 PRIOLVL[2:0]
W
0x012A INT_CFDATA2 R RQST 0000 PRIOLVL[2:0]
W
0x012B INT_CFDATA3 R RQST 0000 PRIOLVL[2:0]
W
0x012C INT_CFDATA4 R RQST 0000 PRIOLVL[2:0]
W
0x012D INT_CFDATA5 R RQST 0000 PRIOLVL[2:0]
W
0x012E INT_CFDATA6 R RQST 0000 PRIOLVL[2:0]
W
0x012F INT_CFDATA7 R RQST 0000 PRIOLVL[2:0]
W
= Unimplemented or Reserved
Figure 4-2. XINT Register Summary
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4.3.2.1 Interrupt Vector Base Register (IVBR)
Read: Anytime
Write: Anytime
4.3.2.2 XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Read: Anytime
Write: Anytime
Address: 0x0121
76543210
RIVB_ADDR[7:0]
W
Reset 1 1 1 11111
Figure 4-3. Interrupt Vector Base Register (IVBR)
Table 4-4. IVBR Field Descriptions
Field Description
7–0
IVB_ADDR[7:0] Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of
reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to
previous S12 microcontrollers.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine
the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset
vectors (0xFFFA–0xFFFE).
Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of
IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”.
Address: 0x0126
76543210
R00000 XILVL[2:0]
W
Reset 0 0 0 00001
= Unimplemented or Reserved
Figure 4-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Table 4-5. INT_XGPRIO Field Descriptions
Field Description
2–0
XILVL[2:0] XGATE Interrupt Priority Level — The XILVL[2:0] bits configure the shared interrupt level of the XGATE
interrupts coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”).
Note: If the XGATE module is not available on the device, write accesses to this register are ignored and read
accesses to this register will return all 0.
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4.3.2.3 Interrupt Request Configuration Address Register (INT_CFADDR)
Read: Anytime
Write: Anytime
4.3.2.4 Interrupt Request Configuration Data Registers (INT_CFDATA0–7)
The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the
block of eight interrupt requests (out of 128) selected by the interrupt configuration address register
(INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt configuration data register
of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt
configuration data register of the vector with the highest address, respectively.
Table 4-6. XGATE Interrupt Priority Levels
Priority XILVL2 XILVL1 XILVL0 Meaning
0 0 0 Interrupt request is disabled
low 0 0 1 Priority level 1
0 1 0 Priority level 2
0 1 1 Priority level 3
1 0 0 Priority level 4
1 0 1 Priority level 5
1 1 0 Priority level 6
high 1 1 1 Priority level 7
Address: 0x0127
76543210
RINT_CFADDR[7:4] 0000
W
Reset 0 0 0 10000
= Unimplemented or Reserved
Figure 4-5. Interrupt Configuration Address Register (INT_CFADDR)
Table 4-7. INT_CFADDR Field Descriptions
Field Description
7–4
INT_CFADDR[7:4] Interrupt Request Configuration Data Register Select Bits — These bits determine which of the 128
configuration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal
valuewritten to thisregister corresponds tothe upper nibbleofthe lowerbyteof theaddress of theinterrupt
vector, i.e.,writing0xE0 to this register selectstheconfiguration data registerblock forthe 8 interrupt vector
requests starting with vector at address (vector base + 0x00E0) to be accessible as INT_CFDATA0–7.
Note: Writing all 0s selects non-existing configuration registers. In this case write accesses to
INT_CFDATA0–7 will be ignored and read accesses will return all 0.
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Address: 0x0128
76543210
RRQST 0000 PRIOLVL[2:0]
W
Reset 0 0 0 00001
1
1Please refer to the notes following the PRIOLVL[2:0] description below.
= Unimplemented or Reserved
Figure 4-6. Interrupt Request Configuration Data Register 0 (INT_CFDATA0)
Address: 0x0129
76543210
RRQST 0000 PRIOLVL[2:0]
W
Reset 0 0 0 00001
1
1Please refer to the notes following the PRIOLVL[2:0] description below.
= Unimplemented or Reserved
Figure 4-7. Interrupt Request Configuration Data Register 1 (INT_CFDATA1)
Address: 0x012A
76543210
RRQST 0000 PRIOLVL[2:0]
W
Reset 0 0 0 00001
1
1Please refer to the notes following the PRIOLVL[2:0] description below.
= Unimplemented or Reserved
Figure 4-8. Interrupt Request Configuration Data Register 2 (INT_CFDATA2)
Address: 0x012B
76543210
RRQST 0000 PRIOLVL[2:0]
W
Reset 0 0 0 00001
1
1Please refer to the notes following the PRIOLVL[2:0] description below.
= Unimplemented or Reserved
Figure 4-9. Interrupt Request Configuration Data Register 3 (INT_CFDATA3)
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Read: Anytime
Write: Anytime
Address: 0x012C
76543210
RRQST 0000 PRIOLVL[2:0]
W
Reset 0 0 0 00001
1
1Please refer to the notes following the PRIOLVL[2:0] description below.
= Unimplemented or Reserved
Figure 4-10. Interrupt Request Configuration Data Register 4 (INT_CFDATA4)
Address: 0x012D
76543210
RRQST 0000 PRIOLVL[2:0]
W
Reset 0 0 0 00001
1
1Please refer to the notes following the PRIOLVL[2:0] description below.
= Unimplemented or Reserved
Figure 4-11. Interrupt Request Configuration Data Register 5 (INT_CFDATA5)
Address: 0x012E
76543210
RRQST 0000 PRIOLVL[2:0]
W
Reset 0 0 0 00001
1
1Please refer to the notes following the PRIOLVL[2:0] description below.
= Unimplemented or Reserved
Figure 4-12. Interrupt Request Configuration Data Register 6 (INT_CFDATA6)
Address: 0x012F
76543210
RRQST 0000 PRIOLVL[2:0]
W
Reset 0 0 0 00001
1
1Please refer to the notes following the PRIOLVL[2:0] description below.
= Unimplemented or Reserved
Figure 4-13. Interrupt Request Configuration Data Register 7 (INT_CFDATA7)
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4.4 Functional Description
The XINT module processes all exception requests to be serviced by the CPU module. These exceptions
include interrupt vector requests and reset vector requests. Each of these exception types and their overall
priority level is discussed in the subsections below.
Table 4-8. INT_CFDATA0–7 Field Descriptions
Field Description
7
RQST XGATE Request Enable — This bit determines if the associated interrupt request is handled by the CPU or by
the XGATE module.
0 Interrupt request is handled by the CPU
1 Interrupt request is handled by the XGATE module
Note: The IRQ interrupt cannot be handled by the XGATE module. For this reason, the configuration register
for vector (vector base + 0x00F2) = IRQ vector address) does not contain a RQST bit. Writing a 1 to the
location of the RQST bit in this register will be ignored and a read access will return 0.
Note: If the XGATE module is not available on the device, writing a 1 to the location of the RQST bit in this
register will be ignored and a read access will return 0.
2–0
PRIOLVL[2:0] Interrupt Request Priority Level Bits — The PRIOLVL[2:0] bits configure the interrupt request priority level of
the associated interrupt request. Out of reset all interrupt requests are enabled at the lowest active level (“1”)
to provide backwards compatibility with previous S12 interrupt controllers. Please also refer to Table 4-9 for
available interrupt request priority levels.
Note: Write accesses to configuration data registers of unused interrupt channels will be ignored and read
accesses will return all 0. For information about what interrupt channels are used in a specific MCU,
please refer to the Device Reference Manual of that MCU.
Note: When vectors (vector base + 0x00F0–0x00FE) are selected by writing 0xF0 to INT_CFADDR, writes to
INT_CFDATA2–7 (0x00F4–0x00FE) will be ignored and read accesses will return all 0s. The
corresponding vectors do not have configuration data registers associated with them.
Note: When vectors (vector base + 0x0010–0x001E) are selected by writing 0x10 to INT_CFADDR, writes to
INT_CFDATA1–INT_CFDATA4(0x0012–0x0018)will be ignored andreadaccesses will returnall 0s. The
corresponding vectors do not have configuration data registers associated with them.
Note: Write accesses to the configuration register for the spurious interrupt vector request
(vector base + 0x0010) will be ignored and read accesses will return 0x07 (request is handled by the
CPU, PRIOLVL = 7).
Table 4-9. Interrupt Priority Levels
Priority PRIOLVL2 PRIOLVL1 PRIOLVL0 Meaning
0 0 0 Interrupt request is disabled
low 0 0 1 Priority level 1
0 1 0 Priority level 2
0 1 1 Priority level 3
1 0 0 Priority level 4
1 0 1 Priority level 5
1 1 0 Priority level 6
high 1 1 1 Priority level 7
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4.4.1 S12X Exception Requests
The CPU handles both reset requests and interrupt requests. The XINT module contains registers to
configure the priority level of each I bit maskable interrupt request which can be used to implement an
interrupt priority scheme. This also includes the possibility to nest interrupt requests. A priority decoder
is used to evaluate the priority of a pending interrupt request.
4.4.2 Interrupt Prioritization
After system reset all interrupt requests with a vector address lower than or equal to (vector base + 0x00F2)
are enabled, are set up to be handled by the CPU and have a pre-configured priority level of 1. Exceptions
to this rule are the non-maskable interrupt requests and the spurious interrupt vector request at (vector base
+ 0x0010) which cannot be disabled, are always handled by the CPU and have a fixed priority levels. A
priority level of 0 effectively disables the associated I bit maskable interrupt request.
If more than one interrupt request is configured to the same interrupt priority level the interrupt request
with the higher vector address wins the prioritization.
The following conditions must be met for an I bit maskable interrupt request to be processed.
1. The local interrupt enabled bit in the peripheral module must be set.
2. The setup in the configuration register associated with the interrupt request channel must meet the
following conditions:
a) The XGATE request enable bit must be 0 to have the CPU handle the interrupt request.
b) The priority level must be set to non zero.
c) The priority level must be greater than the current interrupt processing level in the condition
code register (CCR) of the CPU (PRIOLVL[2:0] > IPL[2:0]).
3. The I bit in the condition code register (CCR) of the CPU must be cleared.
4. There is no access violation interrupt request pending.
5. There is no SYS, SWI, BDM, TRAP, or XIRQ request pending.
NOTE
All non I bit maskable interrupt requests always have higher priority than
I bit maskable interrupt requests. If an I bit maskable interrupt request is
interrupted by a non I bit maskable interrupt request, the currently active
interrupt processing level (IPL) remains unaffected. It is possible to nest
non I bit maskable interrupt requests, e.g., by nesting SWI or TRAP calls.
4.4.2.1 Interrupt Priority Stack
The current interrupt processing level (IPL) is stored in the condition code register (CCR) of the CPU. This
way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The
new IPL is copied to the CCR from the priority level of the highest priority active interrupt request channel
which is configured to be handled by the CPU. The copying takes place when the interrupt vector is
fetched. The previous IPL is automatically restored by executing the RTI instruction.
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4.4.3 XGATE Requests
If the XGATE module is implemented on the device, the XINT module is also used to process all exception
requests to be serviced by the XGATE module. The overall priority level of those exceptions is discussed
in the subsections below.
4.4.3.1 XGATE Request Prioritization
An interrupt request channel is configured to be handled by the XGATE module, if the RQST bit of the
associated configuration register is set to 1 (please refer to Section 4.3.2.4, “Interrupt Request
Configuration Data Registers (INT_CFDATA0–7)”). The priority level configuration (PRIOLVL) for this
channel becomes the XGATE priority which will be used to determine the highest priority XGATE request
to be serviced next by the XGATE module. Additionally, XGATE interrupts may be raised by the XGATE
module by setting one or more of the XGATE channel interrupt flags (by using the SIF instruction). This
will result in an CPU interrupt with vector address vector base + (2 * channel ID number), where the
channel ID number corresponds to the highest set channel interrupt flag, if the XGIE and channel RQST
bits are set.
The shared interrupt priority for the XGATE interrupt requests is taken from the XGATE interrupt priority
configuration register (please refer to Section 4.3.2.2, “XGATE Interrupt Priority Configuration Register
(INT_XGPRIO)”). If more than one XGATE interrupt request channel becomes active at the same time,
the channel with the highest vector address wins the prioritization.
4.4.4 Priority Decoders
The XINT module contains priority decoders to determine the priority for all interrupt requests pending
for the respective target.
There are two priority decoders, one for each interrupt request target, CPU or XGATE. The function of
both priority decoders is basically the same with one exception: the priority decoder for the XGATE
module does not take the current XGATE thread processing level into account. Instead, XGATE requests
are handed to the XGATE module including a 1-bit priority identifier. The XGATE module uses this
additional information to decide if the new request can interrupt a currently running thread. The 1-bit
priority identifier corresponds to the most significant bit of the priority level configuration of the requesting
channel. This means that XGATE requests with priority levels 4, 5, 6 or 7 can interrupt running XGATE
threads with priority levels 1, 2 and 3.
A CPU interrupt vector is not supplied until the CPU requests it. Therefore, it is possible that a higher
priority interrupt request could override the original exception which caused the CPU to request the vector.
In this case, the CPU will receive the highest priority vector and the system will process this exception
instead of the original request.
If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive
after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the
CPU will default to that of the spurious interrupt vector.
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NOTE
Care must be taken to ensure that all exception requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not get processed at all or the result may be a
spurious interrupt request (vector at address (vector base + 0x0010)).
4.4.5 Reset Exception Requests
The XINT module supports three system reset exception request types (for details please refer to the Clock
and Reset Generator module (CRG)):
1. Pin reset, power-on reset, low-voltage reset, or illegal address reset
2. Clock monitor reset request
3. COP watchdog reset request
4.4.6 Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the XINT module upon
request by the CPU is shown in Table 4-10. Generally, all non-maskable interrupts have higher priorities
than maskable interrupts. Please note that between the three software interrupts (Unimplemented op-code
trap request, SWI/BGND request, SYS request) there is no real priority defined because they cannot occur
simultaneously (the S12XCPU executes one instruction at a time).
Table 4-10. Exception Vector Map and Priority
Vector Address1
116 bits vector address based
Source
0xFFFE Pin reset, power-on reset, low-voltage reset, illegal address reset
0xFFFC Clock monitor reset
0xFFFA COP watchdog reset
(Vector base + 0x00F8) Unimplemented op-code trap
(Vector base + 0x00F6) Software interrupt instruction (SWI) or BDM vector request
(Vector base + 0x0012) System call interrupt instruction (SYS)
(Vector base + 0x0018) (reserved for future use)
(Vector base + 0x0016) XGATE Access violation interrupt request2
2only implemented if device features both a Memory Protection Unit (MPU) and an XGATE co-processor
(Vector base + 0x0014) CPU Access violation interrupt request3
3only implemented if device features a Memory Protection Unit (MPU)
(Vector base + 0x00F4) XIRQ interrupt request
(Vector base + 0x00F2) IRQ interrupt request
(Vector base +
0x00F0–0x001A) Device specific I bit maskable interrupt sources (priority determined by the associated
configuration registers, in descending order)
(Vector base + 0x0010) Spurious interrupt
Interrupt (S12XINTV2)
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Freescale Semiconductor 165
4.5 Initialization/Application Information
4.5.1 Initialization
After system reset, software should:
• Initialize the interrupt vector base register if the interrupt vector table is not located at the default
location (0xFF10–0xFFF9).
• Initialize the interrupt processing level configuration data registers (INT_CFADDR,
INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request
target (CPU or XGATE module). It might be a good idea to disable unused interrupt requests.
• If the XGATE module is used, setup the XGATE interrupt priority register (INT_XGPRIO) and
configure the XGATE module (please refer the XGATE Block Guide for details).
• Enable I maskable interrupts by clearing the I bit in the CCR.
• Enable the X maskable interrupt by clearing the X bit in the CCR (if required).
4.5.2 Interrupt Nesting
The interrupt request priority level scheme makes it possible to implement priority based interrupt request
nesting for the I bit maskable interrupt requests handled by the CPU.
• I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority,
so that there can be up to seven nested I bit maskable interrupt requests at a time (refer to Figure 4-
14 for an example using up to three nested interrupt requests).
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per
default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the
I bit in the CCR (CLI). After clearing the I bit, I bit maskable interrupt requests with higher priority can
interrupt the current ISR.
An ISR of an interruptible I bit maskable interrupt request could basically look like this:
• Service interrupt, e.g., clear interrupt flags, copy data, etc.
• Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with
higher priority)
• Process data
• Return from interrupt by executing the instruction RTI
Interrupt (S12XINTV2)
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166 Freescale Semiconductor
Figure 4-14. Interrupt Processing Example
4.5.3 Wake Up from Stop or Wait Mode
4.5.3.1 CPU Wake Up from Stop or Wait Mode
Every I bit maskable interrupt request which is configured to be handled by the CPU is capable of waking
the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualified to wake
up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode:
• If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU.
• An I bit maskable interrupt is ignored if it is configured to a priority level below or equal to the
current IPL in CCR.
• I bit maskable interrupt requests which are configured to be handled by the XGATE module are not
capable of waking up the CPU.
The X bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the
X bit in CCR is set. If the X bit maskable interrupt request is used to wake-up the MCU with the X bit in
the CCR set, the associated ISR is not called. The CPU then resumes program execution with the
instruction following the WAI or STOP instruction. This features works following the same rules like any
interrupt request, i.e. care must be taken that the X interrupt request used for wake-up remains active at
least until the system begins execution of the instruction following the WAI or STOP instruction;
otherwise, wake-up may not occur.
4.5.3.2 XGATE Wake Up from Stop or Wait Mode
Interrupt request channels which are configured to be handled by the XGATE module are capable of
waking up the XGATE module. Interrupt request channels handled by the XGATE module do not affect
the state of the CPU.
0
Reset
4
0
7
6
5
4
3
2
1
0
L4
7
0
4
L1 (Pending)
L7
L3 (Pending)
RTI
4
0
3
0
RTI
RTI
1
0
0
RTI
Stacked IPL
Processing Levels
IPL in CCR
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 167
Chapter 5
Background Debug Module (S12XBDMV2)
5.1 Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the
HCS12X core platform.
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
The BDM has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate
and a handshake signal to indicate when an operation is complete. The system is backwards compatible to
the BDM of the S12 family with the following exceptions:
• TAGGO command no longer supported by BDM
• External instruction tagging feature now part of DBG module
• BDM register map and register content extended/modified
• Global page access functionality
• Enabled but not active out of reset in emulation modes (if modes available)
• CLKSW bit set out of reset in emulation modes (if modes available).
• Family ID readable from firmware ROM at global address 0x7FFF0F (value for HCS12X devices
is 0xC1)
5.1.1 Features
The BDM includes these distinctive features:
• Single-wire communication with host development system
• Enhanced capability for allowing more flexibility in clock rates
• SYNC command to determine communication rate
• GO_UNTIL command
• Hardware handshake protocol to increase the performance of the serial communication
Table 5-1. Revision History
Revision
Number Revision Date Sections
Affected Description of Changes
V02.00 07 Mar 2006 - First version of S12XBDMV2
V02.01 14 May 2008 - Introduced standardized Revision History Table
Background Debug Module (S12XBDMV2)
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168 Freescale Semiconductor
• Active out of reset in special single chip mode
• Nine hardware commands using free cycles, if available, for minimal CPU intervention
• Hardware commands not requiring active BDM
• 14 firmware commands execute from the standard BDM firmware lookup table
• Software control of BDM operation during wait mode
• Software selectable clocks
• Global page access functionality
• Enabled but not active out of reset in emulation modes (if modes available)
• CLKSW bit set out of reset in emulation modes (if modes available).
• When secured, hardware commands are allowed to access the register space in special single chip
mode, if the non-volatile memory erase test fail.
• Family ID readable from firmware ROM at global address 0x7FFF0F (value for HCS12X devices
is 0xC1)
• BDM hardware commands are operational until system stop mode is entered (all bus masters are
in stop mode)
5.1.2 Modes of Operation
BDM is available in all operating modes but must be enabled before firmware commands are executed.
Some systems may have a control bit that allows suspending thefunction during background debug mode.
5.1.2.1 Regular Run Modes
All of these operations refer to the part in run mode and not being secured. The BDM does not provide
controls to conserve power during run mode.
• Normal modes
General operation of the BDM is available and operates the same in all normal modes.
• Special single chip mode
In special single chip mode, background operation is enabled and active out of reset. This allows
programming a system with blank memory.
• Emulation modes (if modes available)
In emulation mode, background operation is enabled but not active out of reset. This allows
debugging and programming a system in this mode more easily.
5.1.2.2 Secure Mode Operation
If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run
mode operation. Secure operation prevents BDM and CPU accesses to non-volatile memory (Flash and/or
EEPROM) other than allowing erasure. For more information please see Section 5.4.1, “Security”.
Background Debug Module (S12XBDMV2)
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Freescale Semiconductor 169
5.1.2.3 Low-Power Modes
The BDM can be used until all bus masters (e.g., CPU or XGATE or others depending on which masters
are available on the SOC) are in stop mode. When CPU is in a low power mode (wait or stop mode) all
BDM firmware commands as well as the hardware BACKGROUND command can not be used
respectively are ignored. In this case the CPU can not enter BDM active mode, and only hardware read and
write commands are available. Also the CPU can not enter a low power mode during BDM active mode.
If all bus masters are in stop mode, the BDM clocks are stopped as well. When BDM clocks are disabled
and one of the bus masters exits from stop mode the BDM clocks will restart and BDM will have a soft
reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM
is now ready to receive a new command.
5.1.3 Block Diagram
A block diagram of the BDM is shown in Figure 5-1.
Figure 5-1. BDM Block Diagram
5.2 External Signal Description
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate
with the BDM system. During reset, this pin is a mode select input which selects between normal and
special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
background debug mode.
ENBDM
CLKSW
BDMACT
TRACE
SDV
16-Bit Shift Register
BKGD
Host
System Serial
Interface Data
Control
UNSEC
Register Block
Register
BDMSTS
Instruction Code
and
Execution
Standard BDM Firmware
LOOKUP TABLE
Secured BDM Firmware
LOOKUP TABLE
Bus Interface
and
Control Logic
Address
Data
Control
Clocks
Background Debug Module (S12XBDMV2)
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170 Freescale Semiconductor
5.3 Memory Map and Register Definition
5.3.1 Module Memory Map
Table 5-2 shows the BDM memory map when BDM is active.
5.3.2 Register Descriptions
A summary of the registers associated with the BDM is shown in Figure 5-2. Registers are accessed by
host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
Table 5-2. BDM Memory Map
Global Address Module Size
(Bytes)
0x7FFF00–0x7FFF0B BDM registers 12
0x7FFF0C–0x7FFF0E BDM firmware ROM 3
0x7FFF0F Family ID (part of BDM firmware ROM) 1
0x7FFF10–0x7FFFFF BDM firmware ROM 240
Global
Address Register
Name Bit 7 6 5 4 3 2 1 Bit 0
0x7FFF00 Reserved R X X X X X X 0 0
W
0x7FFF01 BDMSTS R ENBDM BDMACT 0 SDV TRACE CLKSW UNSEC 0
W
0x7FFF02 Reserved R X X X X X X X X
W
0x7FFF03 Reserved R X X X X X X X X
W
0x7FFF04 Reserved R X X X X X X X X
W
0x7FFF05 Reserved R X X X X X X X X
W
0x7FFF06 BDMCCRL R CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
W
= Unimplemented, Reserved = Implemented (do not alter)
X = Indeterminate 0 = Always read zero
Figure 5-2. BDM Register Summary
Background Debug Module (S12XBDMV2)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 171
5.3.2.1 BDM Status Register (BDMSTS)
Figure 5-3. BDM Status Register (BDMSTS)
0x7FFF07 BDMCCRH R 0 0 0 0 0 CCR10 CCR9 CCR8
W
0x7FFF08 BDMGPR R BGAE BGP6 BGP5 BGP4 BGP3 BGP2 BGP1 BGP0
W
0x7FFF09 Reserved R 0 0 0 0 0 0 0 0
W
0x7FFF0A Reserved R 0 0 0 0 0 0 0 0
W
0x7FFF0B Reserved R 0 0 0 0 0 0 0 0
W
Register Global Address 0x7FFF01
7 6 543 2 1 0
RENBDM BDMACT 0SDVTRACE CLKSW UNSEC 0
W
Reset
Special Single-Chip Mode 01
1ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but
fully erased (non-volatile memory). This is because the ENBDM bit is set by the standard firmware before a BDM command
can be fully transmitted and executed.
1000 0 03
3UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,
else it is 0 and can only be read if not secure (see also bit description).
0
Emulation Modes
(if modes available) 1 0 000 12
2CLKSW is read as 1 by a debugging environment in emulation modes when the device is not secured and read as 0 when
secured if emulation modes available.
0 0
All Other Modes 0 0 000 0 0 0
= Unimplemented, Reserved = Implemented (do not alter)
0 = Always read zero
Global
Address Register
Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented, Reserved = Implemented (do not alter)
X = Indeterminate 0 = Always read zero
Figure 5-2. BDM Register Summary (continued)
Background Debug Module (S12XBDMV2)
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172 Freescale Semiconductor
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured, but subject to the following:
— ENBDM should only be set via a BDM hardware command if the BDM firmware commands
are needed. (This does not apply in special single chip and emulation modes).
— BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by
the standard BDM firmware lookup table upon exit from BDM active mode.
— CLKSW can only be written via BDM hardware WRITE_BD commands.
— All other bits, while writable via BDM hardware or standard BDM firmware write commands,
should only be altered by the BDM hardware or standard firmware lookup table as part of BDM
command execution.
Table 5-3. BDMSTS Field Descriptions
Field Description
7
ENBDM Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made
active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM
hardware commands are still allowed.
0 BDM disabled
1 BDM enabled
Note: ENBDM is set by the firmware out of reset in special single chip mode. In emulation modes (if modes
available) the ENBDM bit is set by BDM hardware out of reset. In special single chip mode with the device
secured, this bit will not be set by the firmware until after the non-volatile memory erase verify tests are
complete. In emulation modes (if modes available) with the device secured, the BDM operations are
blocked.
6
BDMACT BDM Active Status — This bit becomes set upon entering BDM. The standard BDM firmware lookup table is
then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the
standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from
the map.
0 BDM not active
1 BDM active
4
SDV Shift Data Valid — This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as
part of a firmware or hardware read command or after data has been received as part of a firmware or hardware
write command. It is cleared when the next BDM command has been received or BDM is exited. SDV is used
by the standard BDM firmware to control program flow execution.
0 Data phase of command not complete
1 Data phase of command is complete
3
TRACE TRACE1 BDM Firmware Command is Being Executed — This bit gets set when a BDM TRACE1 firmware
command is first recognized. It will stay set until BDM firmware is exited by one of the following BDM commands:
GO or GO_UNTIL.
0 TRACE1 command is not being executed
1 TRACE1 command is being executed
Background Debug Module (S12XBDMV2)
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Freescale Semiconductor 173
2
CLKSW Clock Switch — The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware
BDM command. A minimum delay of 150 cycles at the clock speed that is active during the data portion of the
command send to change the clock source should occur before the next command can be send. The delay
should be obtained no matter which bit is modified to effectively change the clock source (either PLLSEL bit or
CLKSW bit). This guarantees that the start of the next BDM command uses the new clock for timing subsequent
BDM communications.
Table 5-4 shows the resulting BDM clock source based on the CLKSW and the PLLSEL (PLL select in the CRG
module, the bit is part of the CLKSEL register) bits.
Note: The BDM alternate clock source can only be selected when CLKSW = 0 and PLLSEL = 1. The BDM serial
interface is now fully synchronized to the alternate clock source, when enabled. This eliminates frequency
restriction on the alternate clock which was required on previous versions. Refer to the device
specification to determine which clock connects to the alternate clock source input.
Note: If the acknowledge function is turned on, changing the CLKSW bit will cause the ACK to be at the new
rate for the write command which changes it.
Note: In emulation modes (if modes available), the CLKSW bit will be set out of RESET.
1
UNSEC Unsecure — If the device is secured this bit is only writable in special single chip mode from the BDM secure
firmware. It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled
and put into the memory map overlapping the standard BDM firmware lookup table.
The secure BDM firmware lookup table verifies that the non-volatile memories (e.g. on-chip EEPROM and/or
Flash EEPROM) are erased. This being the case, the UNSEC bit is set and the BDM program jumps to the start
of the standard BDM firmware lookup table and the secure BDM firmware lookup table is turned off. If the erase
test fails, the UNSEC bit will not be asserted.
0 System is in a secured mode.
1 System is in a unsecured mode.
Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip
Flash EEPROM. Note that if the user does not change the state of the bits to “unsecured” mode, the
system will be secured again when it is next taken out of reset.After reset this bit has no meaning or effect
when the security byte in the Flash EEPROM is configured for unsecure mode.
Table 5-4. BDM Clock Sources
PLLSEL CLKSW BDMCLK
0 0 Bus clock dependent on oscillator
0 1 Bus clock dependent on oscillator
1 0 Alternate clock (refer to the device specification to determine the alternate clock source)
1 1 Bus clock dependent on the PLL
Table 5-3. BDMSTS Field Descriptions (continued)
Field Description
Background Debug Module (S12XBDMV2)
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174 Freescale Semiconductor
5.3.2.2 BDM CCR LOW Holding Register (BDMCCRL)
Figure 5-4. BDM CCR LOW Holding Register (BDMCCRL)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
NOTE
When BDM is made active, the CPU stores the content of its CCRLregister
in the BDMCCRL register. However, out of special single-chip reset, the
BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the
CCRL register in this CPU mode. Out of reset in all other modes the
BDMCCRL register is read zero.
When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte
of the condition code register of the user’s program. It is also used for temporary storage in the standard
BDM firmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.
5.3.2.3 BDM CCR HIGH Holding Register (BDMCCRH)
Figure 5-5. BDM CCR HIGH Holding Register (BDMCCRH)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR HIGH holding register is used to save the high
byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be
written to modify the CCR value.
Register Global Address 0x7FFF06
7 6 5 4 3 2 1 0
RCCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
W
Reset
Special Single-Chip Mode 1 1 0 0 1 0 0 0
All Other Modes 0 0 0 0 0 0 0 0
Register Global Address 0x7FFF07
76543210
R 0 0 0 0 0 CCR10 CCR9 CCR8
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Background Debug Module (S12XBDMV2)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 175
5.3.2.4 BDM Global Page Index Register (BDMGPR)
Figure 5-6. BDM Global Page Register (BDMGPR)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
5.3.3 Family ID Assignment
The family ID is a 8-bit value located in the firmware ROM (at global address: 0x7FFF0F). The read-only
value is a unique family ID which is 0xC1 for S12X devices.
5.4 Functional Description
The BDM receives and executes commands from a host via a single wire serial interface. There are two
types of BDM commands: hardware and firmware commands.
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode, see Section 5.4.3, “BDM Hardware Commands”. Target system memory
includes all memory that is accessible by the CPU.
Firmware commands are used to read and write CPU resources and to exit from active background debug
mode, see Section 5.4.4, “Standard BDM Firmware Commands”. The CPU resources referred to are the
accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC).
Hardware commands can be executed at any time and in any mode excluding a few exceptions as
highlighted (see Section 5.4.3, “BDM Hardware Commands”) and in secure mode (see Section 5.4.1,
“Security”). Firmware commands can only be executed when the system is not secure and is in active
background debug mode (BDM).
Register Global Address 0x7FFF08
7 6 5 4 3 2 1 0
RBGAE BGP6 BGP5 BGP4 BGP3 BGP2 BGP1 BGP0
W
Reset 0 0 0 0 0 0 0 0
Table 5-5. BDMGPR Field Descriptions
Field Description
7
BGAE BDM Global Page Access Enable Bit — BGAE enables global page access for BDM hardware and firmware
read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD_ and
WRITE_BD_) can not be used for global accesses even if the BGAE bit is set.
0 BDM Global Access disabled
1 BDM Global Access enabled
6–0
BGP[6:0] BDM Global Page Index Bits 6–0 — These bits define the extended address bits from 22 to 16. For more
detailed information regarding the global page window scheme, please refer to the S12X_MMC Block Guide.
Background Debug Module (S12XBDMV2)
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176 Freescale Semiconductor
5.4.1 Security
If the user resets into special single chip mode with the system secured, a secured mode BDM firmware
lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table.
The secure BDM firmware verifies that the on-chip non-volatile memory (e.g. EEPROM and Flash
EEPROM) is erased. This being the case, the UNSEC and ENBDM bit will get set. The BDM program
jumps to the start of the standard BDM firmware and the secured mode BDM firmware is turned off and
all BDM commands are allowed. If the non-volatile memory does not verify as erased, the BDM firmware
sets the ENBDM bit, without asserting UNSEC, and the firmware enters a loop. This causes the BDM
hardware commands to become enabled, but does not enable the firmware commands. This allows the
BDM hardware to be used to erase the non-volatile memory.
BDM operation is not possible in any other mode than special single chip mode when the device is secured.
The device can be unsecured via BDM serial interface in special single chip mode only. For more
information regarding security, please see the S12X_9SEC Block Guide.
5.4.2 Enabling and Activating BDM
The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated
only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS)
register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire
interface, using a hardware command such as WRITE_BD_BYTE.
After being enabled, BDM is activated by one of the following1:
• Hardware BACKGROUND command
• CPU BGND instruction
• External instruction tagging mechanism2
• Breakpoint force or tag mechanism2
When BDM is activated, the CPU finishes executing the current instruction and then begins executing the
firmware in the standard BDM firmware lookup table. When BDM is activated by a breakpoint, the type
of breakpoint used determines if BDM becomes active before or after execution of the next instruction.
NOTE
If an attempt is made to activate BDM before being enabled, the CPU
resumes normal instruction execution after a brief delay. If BDM is not
enabled, any hardware BACKGROUND commands issued are ignored by
the BDM and the CPU is not delayed.
In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses
0x7FFF00 to 0x7FFFFF. BDM registers are mapped to addresses 0x7FFF00 to 0x7FFF0B. The BDM uses
these registers which are readable anytime by the BDM. However, these registers are not readable by user
programs.
1. BDM is enabled and active immediately out of special single-chip reset.
2. This method is provided by the S12X_DBG module.
Background Debug Module (S12XBDMV2)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 177
5.4.3 BDM Hardware Commands
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode. Target system memory includes all memory that is accessible by the CPU on the
SOC which can be on-chip RAM, non-volatile memory (e.g. EEPROM, Flash EEPROM), I/O and control
registers, and all external memory.
Hardware commands are executed with minimal or no CPU intervention and do not require the system to
be in active BDM for execution, although, they can still be executed in this mode. When executing a
hardware command, the BDM sub-block waits for a free bus cycle so that the background access does not
disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is
momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation
does not intrude on normal CPU operation provided that it can be completed in a single cycle. However,
if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the
BDM found a free cycle.
The BDM hardware commands are listed in Table 5-6.
The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations
are not normally in the system memory map but share addresses with the application in memory. To
distinguish between physical memory locations that share the same address, BDM memory resources are
enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM
locations unobtrusively, even if the addresses conflict with the application memory map.
Table 5-6. Hardware Commands
Command Opcode
(hex) Data Description
BACKGROUND 90 None Enter background mode if firmware is enabled. If enabled, an ACK will be
issued when the part enters active background mode.
ACK_ENABLE D5 None Enable Handshake. Issues an ACK pulse after the command is executed.
ACK_DISABLE D6 None Disable Handshake. This command does not issue an ACK pulse.
READ_BD_BYTE E4 16-bit address
16-bit data out Read from memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
READ_BD_WORD EC 16-bit address
16-bit data out Read from memory with standard BDM firmware lookup table in map.
Must be aligned access.
READ_BYTE E0 16-bit address
16-bit data out Read from memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
READ_WORD E8 16-bit address
16-bit data out Read from memory with standard BDM firmware lookup table out of map.
Must be aligned access.
WRITE_BD_BYTE C4 16-bit address
16-bit data in Write to memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
WRITE_BD_WORD CC 16-bit address
16-bit data in Write to memory with standard BDM firmware lookup table in map.
Must be aligned access.
WRITE_BYTE C0 16-bit address
16-bit data in Write to memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
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5.4.4 Standard BDM Firmware Commands
Firmware commands are used to access and manipulate CPU resources. The system must be in active
BDM to execute standard BDM firmware commands, see Section 5.4.2, “Enabling and Activating BDM”.
Normal instruction execution is suspended while the CPU executes the firmware located in the standard
BDM firmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM.
As the system enters active BDM, the standard BDM firmware lookup table and BDM registers become
visible in the on-chip memory map at 0x7FFF00–0x7FFFFF, and the CPU begins executing the standard
BDM firmware. The standard BDM firmware watches for serial commands and executes them as they are
received.
The firmware commands are shown in Table 5-7.
WRITE_WORD C8 16-bit address
16-bit data in Write to memory with standard BDM firmware lookup table out of map.
Must be aligned access.
NOTE:
If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is
complete for all BDM WRITE commands.
Table 5-6. Hardware Commands (continued)
Command Opcode
(hex) Data Description
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5.4.5 BDM Command Structure
Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a
16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte
or word implication in the command name.
8-bit reads return 16-bits of data, of which, only one byte will contain valid
data. If reading an even address, the valid data will appear in the MSB. If
reading an odd address, the valid data will appear in the LSB.
Table 5-7. Firmware Commands
Command1
1If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is
complete for all BDM WRITE commands.
Opcode
(hex) Data Description
READ_NEXT2
2When the firmware command READ_NEXT or WRITE_NEXT is used to access the BDM address space the BDM resources
are accessed rather than user code. Writing BDM firmware is not possible.
62 16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to.
READ_PC 63 16-bit data out Read program counter.
READ_D 64 16-bit data out Read D accumulator.
READ_X 65 16-bit data out Read X index register.
READ_Y 66 16-bit data out Read Y index register.
READ_SP 67 16-bit data out Read stack pointer.
WRITE_NEXT<f-
helvetica><st-
superscript>
42 16-bit data in Increment X index register by 2 (X = X + 2), then write word to location
pointed to by X.
WRITE_PC 43 16-bit data in Write program counter.
WRITE_D 44 16-bit data in Write D accumulator.
WRITE_X 45 16-bit data in Write X index register.
WRITE_Y 46 16-bit data in Write Y index register.
WRITE_SP 47 16-bit data in Write stack pointer.
GO 08 none Go to user program. If enabled, ACK will occur when leaving active
background mode.
GO_UNTIL3
3System stop disables the ACK function and ignored commands will not have an ACK-pulse (e.g., CPU in stop or wait mode).
The GO_UNTIL command will not get an Acknowledge if CPU executes the wait or stop instruction before the “UNTIL”
condition (BDM active again) is reached (see Section 5.4.7, “Serial Interface Hardware Handshake Protocol” last Note).
0C none Go to user program. If enabled, ACK will occur upon returning to active
background mode.
TRACE1 10 none Execute one user instruction then return to active BDM. If enabled,
ACK will occur upon returning to active background mode.
TAGGO -> GO 18 none (Previous enable tagging and go to user program.)
This command will be deprecated and should not be used anymore.
Opcode will be executed as a GO command.
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16-bit misaligned reads and writes are generally not allowed. If attempted
by BDM hardware command, the BDM will ignore the least significant bit
of the address and will assume an even address from the remaining bits.
For devices with external bus:
The following cycle count information is only valid when the external wait
function is not used (see wait bit of EBI sub-block). During an external wait
the BDM can not steal a cycle. Hence be careful with the external wait
function if the BDM serial interface is much faster than the bus, because of
the BDM soft-reset after time-out (see Section 5.4.11, “Serial
Communication Time Out”).
For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending
the address before attempting to obtain the read data. This is to be certain that valid data is available in the
BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait
150 bus clock cycles after sending the data to be written before attempting to send a new command. This
is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle
delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a
free cycle before stealing a cycle.
For firmware read commands, the external host should wait at least 48 bus clock cycles after sending the
command opcode and before attempting to obtain the read data. This includes the potential of extra cycles
when the access is external and stretched (+1 to maximum +7 cycles) or to registers of the PRU (port
replacement unit) in emulation modes (if modes available). The 48 cycle wait allows enough time for the
requested data to be made available in the BDM shift register, ready to be shifted out.
NOTE
This timing has increased from previous BDM modules due to the new
capability in which the BDM serial interface can potentially run faster than
the bus. On previous BDM modules this extra time could be hidden within
the serial time.
For firmware write commands, the external host must wait 36 bus clock cycles after sending the data to be
written before attempting to send a new command. This is to avoid disturbing the BDM shift register
before the write has been completed.
The external host should wait at least for 76 bus clock cycles after a TRACE1 or GO command before
starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM
firmware lookup table and resume execution of the user code. Disturbing the BDM shift register
prematurely may adversely affect the exit from the standard BDM firmware lookup table.
NOTE
If the bus rate of the target processor is unknown or could be changing or the
external wait function is used, it is recommended that the ACK
(acknowledge function) is used to indicate when an operation is complete.
When using ACK, the delay times are automated.
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Figure 5-7 represents the BDM command structure. The command blocks illustrate a series of eight bit
times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles
in the high state. The time for an 8-bit command is 8 × 16 target clock cycles.1
Figure 5-7. BDM Command Structure
5.4.6 BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode
select input which selects between normal and special modes of operation. After reset, this pin becomes
the dedicated serial interface pin for the BDM.
The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see
Section 5.3.2.1, “BDM Status Register (BDMSTS)”. This clock will be referred to as the target clock in
the following explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on
the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per
bit. The interface times out if 512 clock cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically
drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide
brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host
for transmit cases and the target for receive cases.
1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 5.4.6, “BDM Serial Interface”
and Section 5.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected.
Hardware
Hardware
Firmware
Firmware
GO,
48-BC
BC = Bus Clock Cycles
Command Address
150-BC
Delay
Next
DELAY
8 Bits
AT ~16 TC/Bit
16 Bits
AT ~16 TC/Bit
16 Bits
AT ~16 TC/Bit
Command Address Data Next
Data
Read
Write
Read
Write
TRACE
Command Next
Command Data
76-BC
Delay
Next
Command
150-BC
Delay
36-BC
DELAY
Command
Command
Command
Command
Data
Next
Command
TC = Target Clock Cycles
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The timing for host-to-target is shown in Figure 5-8 and that of target-to-host in Figure 5-9 and
Figure 5-10. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since
the host and target are operating from separate clocks, it can take the target system up to one full clock
cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the
host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle
earlier. Synchronization between the host and target is established in this manner at the start of every bit
time.
Figure 5-8 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a
target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten
target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic
requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1
transmission.
Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven
signals.
Figure 5-8. BDM Host-to-Target Serial Bit Timing
The receive cases are more complicated. Figure 5-9 shows the host receiving a logic 1 from the target
system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the host-
generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
Target Senses Bit
10 Cycles
Synchronization
Uncertainty
BDM Clock
(Target MCU)
Host
Transmit 1
Host
Transmit 0
Perceived
Start of Bit Time Earliest
Start of
Next Bit
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Figure 5-9. BDM Target-to-Host Serial Bit Timing (Logic 1)
High-Impedance
Earliest
Start of
Next Bit
R-C Rise
10 Cycles
10 Cycles
Host Samples
BKGD Pin
Perceived
Start of Bit Time
BKGD Pin
BDM Clock
(Target MCU)
Host
Drive to
BKGD Pin
Target System
Speedup
Pulse
High-Impedance
High-Impedance
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Figure 5-10 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target,
there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit
time as perceived by the target. The host initiates the bit time but the target finishes it. Since the target
wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives
it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting
the bit time.
Figure 5-10. BDM Target-to-Host Serial Bit Timing (Logic 0)
5.4.7 Serial Interface Hardware Handshake Protocol
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM
clock source can be asynchronously related to the bus frequency, when CLKSW = 0, it is very helpful to
provide a handshake protocol in which the host could determine when an issued command is executed by
the CPU. The alternative is to always wait the amount of time equal to the appropriate number of cycles at
the slowest possible rate the clock could be running. This sub-section will describe the hardware
handshake protocol.
The hardware handshake protocol signals to the host controller when an issued command was successfully
executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a
brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued
by the host, has been successfully executed (see Figure 5-11). This pulse is referred to as the ACK pulse.
After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read
command, or start a new command if the last command was a write command or a control command
(BACKGROUND, GO, GO_UNTIL or TRACE1). The ACK pulse is not issued earlier than 32 serial clock
cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick
of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also
that, there is no upper limit for the delay between the command and the related ACK pulse, since the
command execution depends upon the CPU bus frequency, which in some cases could be very slow
Earliest
Start of
Next Bit
BDM Clock
(Target MCU)
Host
Drive to
BKGD Pin
BKGD Pin
Perceived
Start of Bit Time
10 Cycles
10 Cycles
Host Samples
BKGD Pin
Target System
Drive and
Speedup Pulse
Speedup Pulse
High-Impedance
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compared to the serial communication rate. This protocol allows a great flexibility for the POD designers,
since it does not rely on any accurate time measurement or short response time to any event in the serial
communication.
Figure 5-11. Target Acknowledge Pulse (ACK)
NOTE
If the ACK pulse was issued by the target, the host assumes the previous
command was executed. If the CPU enters wait or stop prior to executing a
hardware command, the ACK pulse will not be issued meaning that the
BDM command was not executed. After entering wait or stop mode, the
BDM command is no longer pending.
Figure 5-12 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE
instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the
address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed
(free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the
BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved.
After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form
of a word and the host needs to determine which is the appropriate byte based on whether the address was
odd or even.
Figure 5-12. Handshake Protocol at Command Level
16 Cycles
BDM Clock
(Target MCU)
Target
Transmits
ACK Pulse High-Impedance
BKGD Pin
Minimum Delay
From the BDM Command
32 Cycles
Earliest
Start of
Next Bit
Speedup Pulse
16th Tick of the
Last Command Bit
High-Impedance
READ_BYTE
BDM Issues the
BKGD Pin Byte Address
BDM Executes the
READ_BYTE Command
Host Target
HostTarget
BDM Decodes
the Command
ACK Pulse (out of scale)
Host Target
(2) Bytes are
Retrieved New BDM
Command
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Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK
handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware
handshake protocol in Figure 5-11 specifies the timing when the BKGD pin is being driven, so the host
should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin.
NOTE
The only place the BKGD pin can have an electrical conflict is when one
side is driving low and the other side is issuing a speedup pulse (high). Other
“highs” are pulled rather than driven. However, at low rates the time of the
speedup pulse can become lengthy and so the potential conflict time
becomes longer as well.
The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not
acknowledge by an ACK pulse, the host needs to abort the pending command first in order to be able to
issue a new BDM command. When the CPU enters wait or stop while the host issues a hardware command
(e.g., WRITE_BYTE), the target discards the incoming command due to the wait or stop being detected.
Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be
issued in this case. After a certain time the host (not aware of stop or wait) should decide to abort any
possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol
provides a mechanism in which a command, and its corresponding ACK, can be aborted.
NOTE
The ACK pulse does not provide a time out. This means for the GO_UNTIL
command that it can not be distinguished if a stop or wait has been executed
(command discarded and ACK not issued) or if the “UNTIL” condition
(BDM active) is just not reached yet. Hence in any case where the ACK
pulse of a command is not issued the possible pending command should be
aborted before issuing a new command. See the handshake abort procedure
described in Section 5.4.8, “Hardware Handshake Abort Procedure”.
5.4.8 Hardware Handshake Abort Procedure
The abort procedure is based on the SYNC command. In order to abort a command, which had not issued
the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving
it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a
speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol,
see Section 5.4.9, “SYNC — Request Timed Reference Pulse”, and assumes that the pending command
and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been
completed the host is free to issue new BDM commands. For Firmware READ or WRITE commands it
can not be guaranteed that the pending command is aborted when issuing a SYNC before the
corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins
until it is finished and the corresponding ACK pulse is issued. The latency time depends on the firmware
READ or WRITE command that is issued and if the serial interface is running on a different clock rate
than the bus. When the SYNC command starts during this latency time the READ or WRITE command
will not be aborted, but the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or
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GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the
SYNC command.
Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in
the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command.
The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin. The short
abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the negative
edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending
command will be aborted along with the ACK pulse. The potential problem with this abort procedure is
when there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not
perceive the abort pulse. The worst case is when the pending command is a read command (i.e.,
READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new
command after the abort pulse was issued, while the target expects the host to retrieve the accessed
memory byte. In this case, host and target will run out of synchronism. However, if the command to be
aborted is not a read command the short abort pulse could be used. After a command is aborted the target
assumes the next negative edge, after the abort pulse, is the first bit of a new BDM command.
NOTE
The details about the short abort pulse are being provided only as a reference
for the reader to better understand the BDM internal behavior. It is not
recommended that this procedure be used in a real application.
Since the host knows the target serial clock frequency, the SYNC command (used to abort a command)
does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC
very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to
assure the SYNC pulse will not be misinterpreted by the target. See Section 5.4.9, “SYNC — Request
Timed Reference Pulse”.
Figure 5-13 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE
command. Note that, after the command is aborted a new command could be issued by the host computer.
Figure 5-13. ACK Abort Procedure at the Command Level
NOTE
Figure 5-13 does not represent the signals in a true timing scale
Figure 5-14 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could
occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.
READ_BYTE READ_STATUSBKGD Pin Memory Address New BDM Command
New BDM Command
Host Target Host Target Host Target
SYNC Response
From the Target
(Out of Scale)
BDM Decode
and Starts to Execute
the READ_BYTE Command
READ_BYTE CMD is Aborted
by the SYNC Request
(Out of Scale)
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Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being
connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this
case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not
a probable situation, the protocol does not prevent this conflict from happening.
Figure 5-14. ACK Pulse and SYNC Request Conflict
NOTE
This information is being provided so that the MCU integrator will be aware
that such a conflict could eventually occur.
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE
BDM commands. This provides backwards compatibility with the existing POD devices which are not
able to execute the hardware handshake protocol. It also allows for new POD devices, that support the
hardware handshake protocol, to freely communicate with the target device. If desired, without the need
for waiting for the ACK pulse.
The commands are described as follows:
• ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse
when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the
ACK pulse as a response.
• ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst
case delay time at the appropriate places in the protocol.
The default state of the BDM after reset is hardware handshake protocol disabled.
All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then
ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data
has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See
Section 5.4.3, “BDM Hardware Commands” and Section 5.4.4, “Standard BDM Firmware Commands”
for more information on the BDM commands.
BDM Clock
(Target MCU)
Target MCU
Drives to
BKGD Pin
BKGD Pin
16 Cycles
Speedup Pulse
High-Impedance
Host
Drives SYNC
To BKGD Pin
ACK Pulse
Host SYNC Request Pulse
At Least 128 Cycles
Electrical Conflict
Host and
Target Drive
to BKGD Pin
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The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be
used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is
issued in response to this command, the host knows that the target supports the hardware handshake
protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In
this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid
command.
The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to
background mode. The ACK pulse related to this command could be aborted using the SYNC command.
The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse
related to this command could be aborted using the SYNC command.
The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this
case, is issued when the CPU enters into background mode. This command is an alternative to the GO
command and should be used when the host wants to trace if a breakpoint match occurs and causes the
CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which
could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related
to this command could be aborted using the SYNC command.
The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode
after one instruction of the application program is executed. The ACK pulse related to this command could
be aborted using the SYNC command.
5.4.9 SYNC — Request Timed Reference Pulse
The SYNC command is unlike other BDM commands because the host does not necessarily know the
correct communication speed to use for BDM communications until after it has analyzed the response to
the SYNC command. To issue a SYNC command, the host should perform the following steps:
1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication
frequency (the lowest serial communication frequency is determined by the crystal oscillator or the
clock chosen by CLKSW.)
2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically
one cycle of the host clock.)
3. Remove all drive to the BKGD pin so it reverts to high impedance.
4. Listen to the BKGD pin for the sync response pulse.
Upon detecting the SYNC request from the host, the target performs the following steps:
1. Discards any incomplete command received or bit retrieved.
2. Waits for BKGD to return to a logic one.
3. Delays 16 cycles to allow the host to stop driving the high speedup pulse.
4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency.
5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD.
6. Removes all drive to the BKGD pin so it reverts to high impedance.
The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed
for subsequent BDM communications. Typically, the host can determine the correct communication speed
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within a few percent of the actual target speed and the communication protocol can easily tolerate speed
errors of several percent.
As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is
discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the
SYNC response, the target will consider the next negative edge (issued by the host) as the start of a new
BDM command or the start of new SYNC request.
Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the
same as in a regular SYNC command. Note that one of the possible causes for a command to not be
acknowledged by the target is a host-target synchronization problem. In this case, the command may not
have been understood by the target and so an ACK response pulse will not be issued.
5.4.10 Instruction Tracing
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM
firmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to
return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the
TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or
tracing through the user code one instruction at a time.
If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but
no user instruction is executed. Once back in standard BDM firmware execution, the program counter
points to the first instruction in the interrupt service routine.
Be aware when tracing through the user code that the execution of the user code is done step by step but
all peripherals are free running. Hence possible timing relations between CPU code execution and
occurrence of events of other peripherals no longer exist.
Do not trace the CPU instruction BGND used for soft breakpoints. Tracing the BGND instruction will
result in a return address pointing to BDM firmware address space.
When tracing through user code which contains stop or wait instructions the following will happen when
the stop or wait instruction is traced:
The CPU enters stop or wait mode and the TRACE1 command can not be finished before leaving
the low power mode. This is the case because BDM active mode can not be entered after CPU
executed the stop instruction. However all BDM hardware commands except the BACKGROUND
command are operational after tracing a stop or wait instruction and still being in stop or wait
mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is
operational.
As soon as stop or wait mode is exited the CPU enters BDM active mode and the saved PC value
points to the entry of the corresponding interrupt service routine.
In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command
will be discarded when tracing a stop or wait instruction. Hence there is no ACK pulse when BDM
active mode is entered as part of the TRACE1 command after CPU exited from stop or wait mode.
All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or
wait mode will have an ACK pulse. The handshake feature becomes disabled only when system
Background Debug Module (S12XBDMV2)
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Freescale Semiconductor 191
stop mode has been reached. Hence after a system stop mode the handshake feature must be
enabled again by sending the ACK_ENABLE command.
5.4.11 Serial Communication Time Out
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If
BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command
was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the
SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any
time-out limit.
Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as
a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge
marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock
cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting
memory or the operating mode of the MCU. This is referred to as a soft-reset.
If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will
occur causing the command to be disregarded. The data is not available for retrieval after the time-out has
occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider the
behavior where the BDM is running in a frequency much greater than the CPU frequency. In this case, the
command could time out before the data is ready to be retrieved. In order to allow the data to be retrieved
even with a large clock frequency mismatch (between BDM and CPU) when the hardware handshake
protocol is enabled, the time out between a read command and the data retrieval is disabled. Therefore, the
host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued
read command. However, once the handshake pulse (ACK pulse) is issued, the time-out feature is re-
activated, meaning that the target will time out after 512 clock cycles. Therefore, the host needs to retrieve
the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After that period,
the read command is discarded and the data is no longer available for retrieval. Any negative edge in the
BKGD pin after the time-out period is considered to be a new command or a SYNC request.
Note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the
serial communication is active. This means that if a time frame higher than 512 serial clock cycles is
observed between two consecutive negative edges and the command being issued or data being retrieved
is not complete, a soft-reset will occur causing the partially received command or data retrieved to be
disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the
target as the start of a new BDM command, or the start of a SYNC request pulse.
Background Debug Module (S12XBDMV2)
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Chapter 6
S12X Debug (S12XDBGV3) Module
Table 6-1. Revision History
6.1 Introduction
The S12XDBG module provides an on-chip trace buffer with flexible triggering capability to allow non-
intrusive debug of application software. The S12XDBG module is optimized for the S12X 16-bit
architecture and allows debugging of CPU12X module operations.
Typically the S12XDBG module is used in conjunction with the S12XBDM module, whereby the user
configures the S12XDBG module for a debugging session over the BDM interface. Once configured the
S12XDBG module is armed and the device leaves BDM Mode returning control to the user program,
which is then monitored by the S12XDBG module. Alternatively the S12XDBG module can be configured
over a serial interface using SWI routines.
6.1.1 Glossary
Revision
Number Revision Date Sections
Affected Description of Changes
V03.20 14 Sep 2007 6.3.2.7/6-203 - Clarified reserved State Sequencer encodings.
V03.21 23 Oct 2007 6.4.2.2/6-216
6.4.2.4/6-217 - Added single databyte comparison limitation information
- Added statement about interrupt vector fetches whilst tagging.
V03.22 12 Nov 2007 6.4.5.2/6-221
6.4.5.5/6-225 - Removed LOOP1 tracing restriction NOTE.
- Added pin reset effect NOTE.
V03.23 13 Nov 2007 General - Text readability improved, typo removed.
V03.24 04 Jan 2008 6.4.5.3/6-223 - Corrected bit name.
V03.25 14 May 2008 - Updated Revision History Table format. Corrected other paragraph formats.
Table 6-2. Glossary Of Terms
Term Definition
COF Change Of Flow.
Change in the program flow due to a conditional branch, indexed jump or interrupt
BDM Background Debug Mode
DUG Device User Guide, describing the features of the device into which the DBG is integrated
WORD 16 bit data entity
Data Line 64 bit data entity
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6.1.2 Overview
The comparators monitor the bus activity of the CPU12X. When a match occurs the control logic can
trigger the state sequencer to a new state. On a transition to the Final State, bus tracing is triggered and/or
a breakpoint can be generated.
Independent of comparator matches a transition to Final State with associated tracing and breakpoint can
be triggered by writing to the TRIG control bit.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads. Tracing is disabled when the MCU system is secured.
6.1.3 Features
• Four comparators (A, B, C, and D)
— Comparators A and C compare the full address bus and full 16-bit data bus
— Comparators A and C feature a data bus mask register
— Comparators B and D compare the full address bus only
— Each comparator can be configured to monitor CPU12X buses
— Each comparator features selection of read or write access cycles
— Comparators B and D allow selection of byte or word access cycles
— Comparisons can be used as triggers for the state sequencer
• Three comparator modes
— Simple address/data comparator match mode
— Inside address range mode, Addmin ≤ Address ≤Addmax
— Outside address range match mode, Address <Addmin or Address > Addmax
• Two types of triggers
— Tagged — This triggers just before a specific instruction begins execution
— Force — This triggers on the first instruction boundary after a match occurs.
• The following types of breakpoints
— CPU12X breakpoint entering BDM on breakpoint (BDM)
— CPU12X breakpoint executing SWI on breakpoint (SWI)
• TRIG Immediate software trigger independent of comparators
• Four trace modes
— Normal: change of flow (COF) PC information is stored (see Section 6.4.5.2.1) for change of
flow definition.
CPU CPU12X module
Tag Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the
execution stage a tag hit occurs.
Table 6-2. Glossary Of Terms (continued)
Term Definition
S12X Debug (S12XDBGV3) Module
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— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
— Pure PC: All program counter addresses are stored.
• 4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin, End, and Mid alignment of tracing to trigger
6.1.4 Modes of Operation
The S12XDBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU12X monitoring is disabled.
Thus breakpoints, comparators, and CPU12X bus tracing are disabled . When the CPU12X enters active
BDM Mode through a BACKGROUND command, with the S12XDBG module armed, the S12XDBG
remains armed.
The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be
generated if the MCU is secure.
Table 6-3. Mode Dependent Restriction Summary
BDM
Enable BDM
Active MCU
Secure Comparator
Matches Enabled Breakpoints
Possible Tagging
Possible Tracing
Possible
x x 1 Yes Yes Yes No
0 0 0 Yes Only SWI Yes Yes
0 1 0 Active BDM not possible when not enabled
1 0 0 Yes Yes Yes Yes
110 No No No No
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6.1.5 Block Diagram
Figure 6-1. Debug Module Block Diagram
6.2 External Signal Description
The S12XDBG sub-module features no external signals.
6.3 Memory Map and Registers
6.3.1 Module Memory Map
A summary of the registers associated with the S12XDBG sub-block is shown in Table 6-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
Address Name Bit 7 6 5 4 3 2 1 Bit 0
0x0020 DBGC1 RARM 0reserved BDM DBGBRK reserved COMRV
W TRIG
0x0021 DBGSR R TBF 0 0 0 0 SSF2 SSF1 SSF0
W
0x0022 DBGTCR Rreserved TSOURCE TRANGE TRCMOD TALIGN
W
0x0023 DBGC2 R0000 CDCM ABCM
W
Figure 6-2. Quick Reference to S12XDBG Registers
S12XCPU BUS
TRACE BUFFER
BUS INTERFACE
TRIGGER
MATCH0
STATE
COMPARATOR B
COMPARATOR C
COMPARATOR D
COMPARATOR A
STATE SEQUENCER
MATCH1
MATCH2
MATCH3
TRACE
READ TRACE DATA (DBG READ DATA BUS)
CONTROL
SECURE
BREAKPOINT REQUESTS
COMPARATOR
MATCH CONTROL
TRIGGER
TAG &
TRIGGER
CONTROL
LOGIC
TAGS
TAGHITS
STATE
S12XCPU
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6.3.2 Register Descriptions
This section consists of the S12XDBG control and trace buffer register descriptions in address order. Each
comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F
in the S12XDBG module register address map. When ARM is set in DBGC1, the only bits in the
S12XDBG module registers that can be written are ARM, TRIG, and COMRV[1:0]
0x0024 DBGTBH R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
0x0025 DBGTBL R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
0x0026 DBGCNT R 0 CNT
W
0x0027 DBGSCRX R0000
SC3 SC2 SC1 SC0
W
0x0027 DBGMFR R 0 0 0 0 MC3 MC2 MC1 MC0
W
0x00281DBGXCTL
(COMPA/C) R0 NDB TAG BRK RW RWE reserved COMPE
W
0x00282DBGXCTL
(COMPB/D) RSZE SZ TAG BRK RW RWE reserved COMPE
W
0x0029 DBGXAH R0 Bit 22 21 20 19 18 17 Bit 16
W
0x002A DBGXAM RBit 15 14 13 12 11 10 9 Bit 8
W
0x002B DBGXAL RBit 7 6 5 4 3 2 1 Bit 0
W
0x002C DBGXDH RBit 15 14 13 12 11 10 9 Bit 8
W
0x002D DBGXDL RBit 7 6 5 4 3 2 1 Bit 0
W
0x002E DBGXDHM RBit 15 14 13 12 11 10 9 Bit 8
W
0x002F DBGXDLM RBit 7 6 5 4 3 2 1 Bit 0
W
1This represents the contents if the Comparator A or C control register is blended into this address.
2This represents the contents if the Comparator B or D control register is blended into this address
Address Name Bit 7 6 5 4 3 2 1 Bit 0
Figure 6-2. Quick Reference to S12XDBG Registers
S12X Debug (S12XDBGV3) Module
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6.3.2.1 Debug Control Register 1 (DBGC1)
Read: Anytime
Write: Bits 7, 1, 0 anytime
Bit 6 can be written anytime but always reads back as 0.
Bits 5:2 anytime S12XDBG is not armed.
NOTE
If a write access to DBGC1 with the ARM bit position set occurs
simultaneously to a hardware disarm from an internal trigger event, then the
ARM bit is cleared due to the hardware disarm.
NOTE
When disarming the S12XDBG by clearing ARM with software, the
contents of bits[5:2] are not affected by the write, since up until the write
operation, ARM = 1 preventing these bits from being written. These bits
must be cleared using a second write if required.
Address: 0x0020
76543210
RARM 0reserved BDM DBGBRK reserved COMRV
W TRIG
Reset 00000000
Figure 6-3. Debug Control Register (DBGC1)
Table 6-4. DBGC1 Field Descriptions
Field Description
7
ARM Arm Bit — The ARM bit controls whether the S12XDBG module is armed. This bit can be set and cleared by
user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with
tracing not enabled. On setting this bit the state sequencer enters State1.
0 Debugger disarmed
1 Debugger armed
6
TRIG Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of
comparator signal status. When tracing is complete a forced breakpoint may be generated depending upon
DBGBRK and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no effect. If TSOURCE
is clear no tracing is carried out. If tracing has already commenced using BEGIN- or MID trigger alignment, it
continues until the end of the tracing session as defined by the TALIGN bit settings, thus TRIG has no affect. In
secure mode tracing is disabled and writing to this bit has no effect.
0 Do not trigger until the state sequencer enters the Final State.
1 Trigger immediately .
5
reserved This bit is reserved, setting it has no meaning or effect.
4
BDM Background Debug Mode Enable — This bit determines if an S12X breakpoint causes the system to enter
Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled
by the ENBDM bit in the BDM module, then breakpoints default to SWI.
0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI
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6.3.2.2 Debug Status Register (DBGSR)
Read: Anytime
Write: Never
3
DBGBRK S12XDBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint
to S12XCPU upon reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated
on completion of the tracing session. If tracing is not enabled, the breakpoint is generated immediately. Please
refer to Section 6.4.7 for further details.
0 No breakpoint on trigger.
1 Breakpoint on trigger
1–0
COMRV Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the
8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these
bits determine which register is visible at the address 0x0027. See Table 6-5.
Table 6-5. COMRV Encoding
COMRV Visible Comparator Visible Register at 0x0027
00 Comparator A DBGSCR1
01 Comparator B DBGSCR2
10 Comparator C DBGSCR3
11 Comparator D DBGMFR
Address: 0x0021
76543210
R TBF 0 0 0 0 SSF2 SSF1 SSF0
W
Reset
POR —
00
00
00
00
00
00
00
0
= Unimplemented or Reserved
Figure 6-4. Debug Status Register (DBGSR)
Table 6-6. DBGSR Field Descriptions
Field Description
7
TBF Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0].
The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset
initialization. Other system generated resets have no affect on this bit
2–0
SSF[2:0] State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During
a debug session on each transition to a new state these bits are updated. If the debug session is ended by
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer
before disarming. If a debug session is ended by an internal trigger, then the state sequencer returns to state0
andthese bits are cleared to indicate that state0 wasentered during thesession. On arming the module the state
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 6-7.
Table 6-4. DBGC1 Field Descriptions (continued)
Field Description
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6.3.2.3 Debug Trace Control Register (DBGTCR)
Read: Anytime
Write: Bits 7:6 only when S12XDBG is neither secure nor armed.
Bits 5:0 anytime the module is disarmed.
WARNING
DBGTCR[7] is reserved. Setting this bit maps the tracing to an unimplemented bus, thus
preventing proper operation.
Table 6-7. SSF[2:0] — State Sequence Flag Bit Encoding
SSF[2:0] Current State
000 State0 (disarmed)
001 State1
010 State2
011 State3
100 Final State
101,110,111 Reserved
Address: 0x0022
76543210
Rreserved TSOURCE TRANGE TRCMOD TALIGN
W
Reset 00000000
Figure 6-5. Debug Trace Control Register (DBGTCR)
Table 6-8. DBGTCR Field Descriptions
Field Description
6
TSOURCE Trace Source Control Bits — The TSOURCE enables the tracing session. If the MCU system is secured, this
bit cannot be set and tracing is inhibited.
0 No tracing selected
1 Tracing selected
5–4
TRANGE Trace Range Bits — The TRANGE bits allow filtering of trace information from a selected address range when
tracing from the CPU12X in Detail Mode. To use a comparator for range filtering, the corresponding COMPE
bits must remain cleared. If the COMPE bit is not clear then the comparator will also be used to generate state
sequence triggers. See Table 6-9.
3–2
TRCMOD Trace Mode Bits — See Section 6.4.5.2 for detailed Trace Mode descriptions. In Normal Mode, change of flow
information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace
memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. See
Table 6-10.
1–0
TALIGN Trigger Align Bits — These bits control whether the trigger is aligned to the beginning, end or the middle of a
tracing session. See Table 6-11.
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Freescale Semiconductor 201
6.3.2.4 Debug Control Register2 (DBGC2)
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
Table 6-9. TRANGE Trace Range Encoding
TRANGE Tracing Range
00 Trace from all addresses (No filter)
01 Trace only in address range from $00000 to Comparator D
10 Trace only in address range from Comparator C to $7FFFFF
11 Trace only in range from Comparator C to Comparator D
Table 6-10. TRCMOD Trace Mode Bit Encoding
TRCMOD Description
00 Normal
01 Loop1
10 Detail
11 Pure PC
Table 6-11. TALIGN Trace Alignment Encoding
TALIGN Description
00 Trigger at end of stored data
01 Trigger before storing data
10 Trace buffer entries before and after trigger
11 Reserved
Address: 0x0023
76543210
R0000 CDCM ABCM
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-6. Debug Control Register2 (DBGC2)
Table 6-12. DBGC2 Field Descriptions
Field Description
3–2
CDCM[1:0] C and D Comparator Match Control — These bits determine the C and D comparator match mapping as
described in Table 6-13.
1–0
ABCM[1:0] A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in Table 6-14.
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6.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL)
Read: Only when unlocked AND not secured AND not armed AND with the TSOURCE bit set.
Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer
contents.
Table 6-13. CDCM Encoding
CDCM Description
00 Match2 mapped to comparator C match....... Match3 mapped to comparator D match.
01 Match2 mapped to comparator C/D inside range....... Match3 disabled.
10 Match2 mapped to comparator C/D outside range....... Match3 disabled.
11 Reserved1
1Currently defaults to Match2 mapped to comparator C : Match3 mapped to comparator D
Table 6-14. ABCM Encoding
ABCM Description
00 Match0 mapped to comparator A match....... Match1 mapped to comparator B match.
01 Match 0 mapped to comparator A/B inside range....... Match1 disabled.
10 Match 0 mapped to comparator A/B outside range....... Match1 disabled.
11 Reserved1
1Currently defaults to Match0 mapped to comparator A : Match1 mapped to comparator B
Address: 0x0024, 0x0025
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
PORXXXXXXXXXXXXXXXX
Other
Resets ————————————————
Figure 6-7. Debug Trace Buffer Register (DBGTB)
Table 6-15. DBGTB Field Descriptions
Field Description
15–0
Bit[15:0] Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 64-bit wide data lines of the
Trace Buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer
which points to the next address to be read. When the ARM bit is written to 1 the trace buffer is locked to prevent
reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when
the module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned
access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace
buffer address. The same is true for word reads while the debugger is armed. The POR state is undefined Other
resets do not affect the trace buffer contents. .
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6.3.2.6 Debug Count Register (DBGCNT)
Read: Anytime
Write: Never
6.3.2.7 Debug State Control Registers
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if
transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the
Address: 0x0026
76543210
R 0 CNT
W
Reset
POR 0
0—
0—
0—
0—
0—
0—
0—
0
= Unimplemented or Reserved
Figure 6-8. Debug Count Register (DBGCNT)
Table 6-16. DBGCNT Field Descriptions
Field Description
6–0
CNT[6:0] Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the Trace Buffer.
Table 6-17 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer.
When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-
trigger or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The
DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus
should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of
valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when
reading from the trace buffer.
Table 6-17. CNT Decoding Table
TBF (DBGSR) CNT[6:0] Description
0 0000000 No data valid
0 0000001 32 bits of one line valid
0 0000010
0000100
0000110
..
1111100
1 line valid
2 lines valid
3 lines valid
..
62 lines valid
0 1111110 63 lines valid
1 0000000 64 lines valid; if using Begin trigger alignment,
ARM bit will be cleared and the tracing session ends.
1 0000010
..
..
1111110
64 lines valid,
oldest data has been overwritten by most recent data
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next state for the state sequencer following a match. The three debug state control registers are located at
the same address in the register address map (0x0027). Each register can be accessed using the COMRV
bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register
(DBGMFR).
6.3.2.7.1 Debug State Control Register 1 (DBGSCR1)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the
targeted next state whilst in State1. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 6-1 and described in Section 6.3.2.8.1”. Comparators must be enabled
by setting the comparator enable bit in the associated DBGXCTL control register.
Table 6-18. State Control Register Access Encoding
COMRV Visible State Control Register
00 DBGSCR1
01 DBGSCR2
10 DBGSCR3
11 DBGMFR
Address: 0x0027
76543210
R0000
SC3 SC2 SC1 SC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-9. Debug State Control Register 1 (DBGSCR1)
Table 6-19. DBGSCR1 Field Descriptions
Field Description
3–0
SC[3:0] These bits select the targeted next state whilst in State1, based upon the match event.
Table 6-20. State1 Sequencer Next State Selection
SC[3:0] Description
0000 Any match triggers to state2
0001 Any match triggers to state3
0010 Any match triggers to Final State
0011 Match2 triggers to State2....... Other matches have no effect
0100 Match2 triggers to State3....... Other matches have no effect
0101 Match2 triggers to Final State....... Other matches have no effect
0110 Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect
S12X Debug (S12XDBGV3) Module
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The trigger priorities described in Table 6-39 dictate that in the case of simultaneous matches, the match
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
6.3.2.7.2 Debug State Control Register 2 (DBGSCR2)
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state whilst in State2. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 6-1 and described in Section 6.3.2.8.1”. Comparators must be enabled
by setting the comparator enable bit in the associated DBGXCTL control register.
0111 Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
1000 Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect
1001 Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
1010 Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect
1011 Match3 triggers to State3....... Match1 triggers to Final State....... Other matches have no effect
1100 Match3 has no effect....... All other matches (M0,M1,M2) trigger to State2
1101 Reserved. (No match triggers state sequencer transition)
1110 Reserved. (No match triggers state sequencer transition)
1111 Reserved. (No match triggers state sequencer transition)
Address: 0x0027
76543210
R0000
SC3 SC2 SC1 SC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-10. Debug State Control Register 2 (DBGSCR2)
Table 6-21. DBGSCR2 Field Descriptions
Field Description
3–0
SC[3:0] These bits select the targeted next state whilst in State2, based upon the match event.
Table 6-22. State2 —Sequencer Next State Selection
SC[3:0] Description
0000 Any match triggers to state1
0001 Any match triggers to state3
0010 Any match triggers to Final State
0011 Match3 triggers to State1....... Other matches have no effect
0100 Match3 triggers to State3....... Other matches have no effect
Table 6-20. State1 Sequencer Next State Selection (continued)
SC[3:0] Description
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The trigger priorities described in Table 6-39 dictate that in the case of simultaneous matches, the match
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
6.3.2.7.3 Debug State Control Register 3 (DBGSCR3)
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 6-1 and described in Section 6.3.2.8.1”. Comparators must be enabled
by setting the comparator enable bit in the associated DBGXCTL control register.
0101 Match3 triggers to Final State....... Other matches have no effect
0110 Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect
0111 Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
1000 Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect
1001 Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
1010 Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect
1011 Match3 triggers to State3....... Match1 triggers Final State....... Other matches have no effect
1100 Match2 triggers to State1..... Match3 trigger to Final State
1101 Match2 has no affect, all other matches (M0,M1,M3) trigger to Final State
1110 Reserved. (No match triggers state sequencer transition)
1111 Reserved. (No match triggers state sequencer transition)
Address: 0x0027
76543210
R0000
SC3 SC2 SC1 SC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-11. Debug State Control Register 3 (DBGSCR3)
Table 6-23. DBGSCR3 Field Descriptions
Field Description
3–0
SC[3:0] These bits select the targeted next state whilst in State3, based upon the match event.
Table 6-24. State3 — Sequencer Next State Selection
SC[3:0] Description
0000 Any match triggers to state1
0001 Any match triggers to state2
Table 6-22. State2 —Sequencer Next State Selection (continued)
SC[3:0] Description
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The trigger priorities described in Table 6-39 dictate that in the case of simultaneous matches, the match
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
6.3.2.7.4 Debug Match Flag Register (DBGMFR)
Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features four flag bits each mapped directly
to a channel. Should a match occur on the channel during the debug session, then the corresponding flag
is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents
are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they
are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag
is set, further triggers on the same channel have no affect.
6.3.2.8 Comparator Register Descriptions
Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG
module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare
registers, two data bus compare registers, two data bus mask registers and a control register).
0010 Any match triggers to Final State
0011 Match0 triggers to State1....... Other matches have no effect
0100 Match0 triggers to State2....... Other matches have no effect
0101 Match0 triggers to Final State.......Match1 triggers to State1...Other matches have no effect
0110 Match1 triggers to State1....... Other matches have no effect
0111 Match1 triggers to State2....... Other matches have no effect
1000 Match1 triggers to Final State....... Other matches have no effect
1001 Match2 triggers to State2....... Match0 triggers to Final State....... Other matches have no effect
1010 Match1 triggers to State1....... Match3 triggers to State2....... Other matches have no effect
1011 Match3 triggers to State2....... Match1 triggers to Final State....... Other matches have no effect
1100 Match2 triggers to Final State....... Other matches have no effect
1101 Match3 triggers to Final State....... Other matches have no effect
1110 Reserved. (No match triggers state sequencer transition)
1111 Reserved. (No match triggers state sequencer transition)
Address: 0x0027
76543210
R0000MC3MC2MC1MC0
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-12. Debug Match Flag Register (DBGMFR)
Table 6-24. State3 — Sequencer Next State Selection
SC[3:0] Description
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Comparators B and D consist of four register bytes (three address bus compare registers and a control
register).
Each set of comparator registers is accessible in the same 8-byte window of the register address map and
can be accessed using the COMRV bits in the DBGC1 register. If the Comparators B or D are accessed
through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with
data bus and data bus masking read as zero and cannot be written. Furthermore the control registers for
comparators B and D differ from those of comparators A and C.
6.3.2.8.1 Debug Comparator Control Register (DBGXCTL)
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map.
Read: Anytime. See Table 6-26 for visible register encoding.
Write: If DBG not armed. See Table 6-26 for visible register encoding.
WARNING
DBGXCTL[1] is reserved. Setting this bit maps the corresponding comparator to an
Table 6-25. Comparator Register Layout
0x0028 CONTROL Read/Write Comparators A,B,C,D
0x0029 ADDRESS HIGH Read/Write Comparators A,B,C,D
0x002A ADDRESS MEDIUM Read/Write Comparators A,B,C,D
0x002B ADDRESS LOW Read/Write Comparators A,B,C,D
0x002C DATA HIGH COMPARATOR Read/Write Comparator A and C only
0x002D DATA LOW COMPARATOR Read/Write Comparator A and C only
0x002E DATA HIGH MASK Read/Write Comparator A and C only
0x002F DATA LOW MASK Read/Write Comparator A and C only
Address: 0x0028
76543210
R0 NDB TAG BRK RW RWE reserved COMPE
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-13. Debug Comparator Control Register (Comparators A and C)
Address: 0x0028
76543210
RSZE SZ TAG BRK RW RWE reserved COMPE
W
Reset 00000000
Figure 6-14. Debug Comparator Control Register (Comparators B and D)
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unimplemented bus, thus preventing proper operation.
The DBGC1_COMRV bits determine which comparator control, address, data and datamask registers are
visible in the 8-byte window from 0x0028 to 0x002F as shown in Section Table 6-26.
Table 6-26. Comparator Address Register Visibility
COMRV Visible Comparator
00 DBGACTL, DBGAAH ,DBGAAM, DBGAAL, DBGADH, DBGADL, DBGADHM, DBGADLM
01 DBGBCTL, DBGBAH, DBGBAM, DBGBAL
10 DBGCCTL, DBGCAH, DBGCAM, DBGCAL, DBGCDH, DBGCDL, DBGCDHM, DBGCDLM
11 DBGDCTL, DBGDAH, DBGDAM, DBGDAL
Table 6-27. DBGXCTL Field Descriptions
Field Description
7
SZE
(Comparators
B and D)
Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the
associated comparator. This bit is ignored if the TAG bit in the same register is set.
0 Word/Byte access size is not used in comparison
1 Word/Byte access size is used in comparison
6
NDB
(Comparators
A and C
Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator
register value or when the data bus differs from the register value. Furthermore data bus bits can be
individually masked using the comparator data mask registers. This bit is only available for comparators A
and C. This bit is ignored if the TAG bit in the same register is set. This bit position has an SZ functionality for
comparators B and D.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
6
SZ
(Comparators
B and D)
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the
associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
This bit position has NDB functionality for comparators A and C
0 Word access size will be compared
1 Byte access size will be compared
5
TAG Tag Select — This bit controls whether the comparator match will cause a trigger or tag the opcode at the
matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue.
0 Trigger immediately on match
1 On match, tag the opcode. If the opcode is about to be executed a trigger is generated
4
BRK Break — This bit controls whether a channel match terminates a debug session immediately, independent
of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled
using DBGBRK.
0 The debug session termination is dependent upon the state sequencer and trigger conditions.
1 A match on this channel terminates the debug session immediately; breakpoints if active are generated,
tracing, if active, is terminated and the module disarmed.
3
RW Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
associated comparator . The RW bit is not used if RWE = 0.
0 Write cycle will be matched
1 Read cycle will be matched
2
RWE Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
associated comparator. This bit is not used for tagged operations.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
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Table 6-28 shows the effect for RWE and RW on the comparison conditions. These bits are not useful for
tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the
instruction queue. Thus these bits are ignored if tagged triggering is selected.
6.3.2.8.2 Debug Comparator Address High Register (DBGXAH)
Read: Anytime. See Table 6-26 for visible register encoding.
Write: If DBG not armed. See Table 6-26 for visible register encoding.
0
COMPE Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled for state sequence triggers or tag generation
Table 6-28. Read or Write Comparison Logic Table
RWE Bit RW Bit RW Signal Comment
0 x 0 RW not used in comparison
0 x 1 RW not used in comparison
1 0 0 Write
1 0 1 No match
1 1 0 No match
1 1 1 Read
Address: 0x0029
76543210
R0 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16
W
Reset 00000000
= Unimplemented or Reserved
Figure 6-15. Debug Comparator Address High Register (DBGXAH)
Table 6-29. DBGXAH Field Descriptions
Field Description
6–0
Bit[22:16] Comparator Address High Compare Bits — The Comparator address high compare bits control whether the
selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. .
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Table 6-27. DBGXCTL Field Descriptions (continued)
Field Description
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6.3.2.8.3 Debug Comparator Address Mid Register (DBGXAM)
Read: Anytime. See Table 6-26 for visible register encoding.
Write: If DBG not armed. See Table 6-26 for visible register encoding.
6.3.2.8.4 Debug Comparator Address Low Register (DBGXAL)
Read: Anytime. See Table 6-26 for visible register encoding.
Write: If DBG not armed. See Table 6-26 for visible register encoding.
Address: 0x002A
76543210
RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 6-16. Debug Comparator Address Mid Register (DBGXAM)
Table 6-30. DBGXAM Field Descriptions
Field Description
7–0
Bit[15:8] Comparator Address Mid Compare Bits— The Comparator address mid compare bits control whether the
selected comparator will compare the address bus bits [15:8] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Address: 0x002B
76543210
RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 00000000
Figure 6-17. Debug Comparator Address Low Register (DBGXAL)
Table 6-31. DBGXAL Field Descriptions
Field Description
7–0
Bits[7:0] Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the
selected comparator will compare the address bus bits [7:0] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
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6.3.2.8.5 Debug Comparator Data High Register (DBGXDH)
Read: Anytime. See Table 6-26 for visible register encoding.
Write: If DBG not armed. See Table 6-26 for visible register encoding.
6.3.2.8.6 Debug Comparator Data Low Register (DBGXDL)
Read: Anytime. See Table 6-26 for visible register encoding.
Write: If DBG not armed. See Table 6-26 for visible register encoding.
Address: 0x002C
76543210
RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 6-18. Debug Comparator Data High Register (DBGXDH)
Table 6-32. DBGXAH Field Descriptions
Field Description
7–0
Bits[15:8] Comparator Data High Compare Bits — The Comparator data high compare bits control whether the selected
comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparators A and C.
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
Address: 0x002D
76543210
RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 00000000
Figure 6-19. Debug Comparator Data Low Register (DBGXDL)
Table 6-33. DBGXDL Field Descriptions
Field Description
7–0
Bits[7:0] Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected
comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparators A and C.
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
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6.3.2.8.7 Debug Comparator Data High Mask Register (DBGXDHM)
Read: Anytime. See Table 6-26 for visible register encoding.
Write: If DBG not armed. See Table 6-26 for visible register encoding.
6.3.2.8.8 Debug Comparator Data Low Mask Register (DBGXDLM)
Read: Anytime. See Table 6-26 for visible register encoding.
Write: If DBG not armed. See Table 6-26 for visible register encoding.
6.4 Functional Description
This section provides a complete functional description of the S12XDBG module. If the part is in secure
mode, the S12XDBG module can generate breakpoints but tracing is not possible.
Address: 0x002E
76543210
RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 6-20. Debug Comparator Data High Mask Register (DBGXDHM)
Table 6-34. DBGXDHM Field Descriptions
Field Description
7–0
Bits[15:8] Comparator Data High Mask Bits — The Comparator data high mask bits control whether the selected
comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. This register
is available only for comparators A and C.
0 Do not compare corresponding data bit
1 Compare corresponding data bit
Address: 0x002F
76543210
RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 00000000
Figure 6-21. Debug Comparator Data Low Mask Register (DBGXDLM)
Table 6-35. DBGXDLM Field Descriptions
Field Description
7–0
Bits[7:0] Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected
comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. This register
is available only for comparators A and C.
0 Do not compare corresponding data bit
1 Compare corresponding data bit
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6.4.1 S12XDBG Operation
Arming the S12XDBG module by setting ARM in DBGC1 allows triggering, and storing of data in the
trace buffer and can be used to cause breakpoints to the CPU12X . The DBG module is made up of four
main blocks, the comparators, control logic, the state sequencer, and the trace buffer.
The comparators monitor the bus activity of the CPU12X . Comparators can be configured to monitor
address and databus. Comparators can also be configured to mask out individual data bus bits during a
compare and to use R/W and word/byte access qualification in the comparison. When a match with a
comparator register value occurs the associated control logic can trigger the state sequencer to another state
(see Figure 6-22). Either forced or tagged triggers are possible. Using a forced trigger, the trigger is
generated immediately on a comparator match. Using a tagged trigger, at a comparator match, the
instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction queue
is a trigger generated. In the case of a transition to Final State, bus tracing is triggered and/or a breakpoint
can be generated.
Independent of the state sequencer, a breakpoint can be triggered by writing to the TRIG bit in the DBGC1
control register.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads.
6.4.2 Comparator Modes
The S12XDBG contains four comparators, A, B, C, and D. Each comparator compares the selected address
bus with the address stored in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparators A and C
also compare the data buses to the data stored in DBGXDH, DBGXDL and allow masking of individual
data bus bits.
S12X comparator matches are disabled in BDM and during BDM accesses.
The comparator match control logic configures comparators to monitor the buses for an exact address or
an address range. The comparator configuration is controlled by the control register contents and the range
control by the DBGC2 contents.
On a match a trigger can initiate a transition to another state sequencer state (see Section 6.4.3”). The
comparator control register also allows the type of access to be included in the comparison through the use
of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled
for the associated comparator and the RW bit selects either a read or write access for a valid match.
Similarly the SZE and SZ bits allows the size of access (word or byte) to be considered in the compare.
Only comparators B and D feature SZE and SZ.
The TAG bit in each comparator control register is used to determine the triggering condition. By setting
TAG, the comparator will qualify a match with the output of opcode tracking logic and a trigger occurs
before the tagged instruction executes (tagged-type trigger). Whilst tagging, the RW, RWE, SZE, and SZ
bits are ignored and the comparator register must be loaded with the exact opcode address.
If the TAG bit is clear (forced type trigger) a comparator match is generated when the selected address
appears on the system address bus. If the selected address is an opcode address, the match is generated
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when the opcode is fetched from the memory. This precedes the instruction execution by an indefinite
number of cycles due to instruction pipe lining. For a comparator match of an opcode at an odd address
when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an
opcode at odd address (n), the comparator register must contain address (n–1).
Once a successful comparator match has occurred, the condition that caused the original match is not
verified again on subsequent matches. Thus if a particular data value is verified at a given address, this
address may not still contain that data value when a subsequent match occurs.
Comparators C and D can also be used to select an address range to trace from. This is determined by the
TRANGE bits in the DBGTCR register. The TRANGE encoding is shown in Table 6-9. If the TRANGE
bits select a range definition using comparator D, then comparator D is configured for trace range
definition and cannot be used for address bus comparisons. Similarly if the TRANGE bits select a range
definition using comparator C, then comparator C is configured for trace range definition and cannot be
used for address bus comparisons.
Match[0, 1, 2, 3] map directly to Comparators[A, B, C, D] respectively, except in range modes (see
Section 6.3.2.4”). Comparator priority rules are described in the trigger priority section (Section 6.4.3.4”).
6.4.2.1 Exact Address Comparator Match (Comparators A and C)
With range comparisons disabled, the match condition is an exact equivalence of address/data bus with the
value stored in the comparator address/data registers. Further qualification of the type of access (R/W,
word/byte) is possible.
Comparators A and C do not feature SZE or SZ control bits, thus the access size is not compared. Table 6-
37 lists access considerations without data bus compare. Table 6-36 lists access considerations with data
bus comparison. To compare byte accesses DBGxDH must be loaded with the data byte, the low byte must
be masked out using the DBGxDLM mask register. On word accesses the data byte of the lower address
is mapped to DBGxDH.
Code may contain various access forms of the same address, i.e. a word access of ADDR[n] or byte access
of ADDR[n+1] both access n+1. At a word access of ADDR[n], address ADDR[n+1] does not appear on
the address bus and so cannot cause a comparator match if the comparator contains ADDR[n]. Thus it is
not possible to monitor all data accesses of ADDR[n+1] with one comparator.
To detect an access of ADDR[n+1] through a word access of ADDR[n] the comparator can be configured
to ADDR[n], DBGxDL is loaded with the data pattern and DBGxDHM is cleared so only the data[n+1] is
compared on accesses of ADDR[n].
Table 6-36. Comparator A and C Data Bus Considerations
Access Address DBGxDH DBGxDL DBGxDHM DBGxDLM Example Valid Match
Word ADDR[n] Data[n] Data[n+1] $FF $FF MOVW #$WORD ADDR[n] config1
Byte ADDR[n] Data[n] x $FF $00 MOVB #$BYTE ADDR[n] config2
Word ADDR[n] Data[n] x $FF $00 MOVW #$WORD ADDR[n] config2
Word ADDR[n] x Data[n+1] $00 $FF MOVW #$WORD ADDR[n] config3
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NOTE
Using this configuration, a byte access of ADDR[n] can cause a comparator match if the databus low byte
by chance contains the same value as ADDR[n+1] because the databus comparator does not feature access
size comparison and uses the mask as a “don’t care” function. Thus masked bits do not prevent a match.
Comparators A and C feature an NDB control bit to determine if a match occurs when the data bus differs
to comparator register contents or when the data bus is equivalent to the comparator register contents.
6.4.2.2 Exact Address Comparator Match (Comparators B and D)
Comparators B and D feature SZ and SZE control bits. If SZE is clear, then the comparator address match
qualification functions the same as for comparators A and C.
If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the
specified type of access causes a match. Thus if configured for a byte access of a particular address, a word
access covering the same address does not lead to match.
6.4.2.3 Data Bus Comparison NDB Dependency
Comparators A and C each feature an NDB control bit, which allows data bus comparators to be configured
to either trigger on equivalence or trigger on difference. This allows monitoring of a difference in the
contents of an address location from an expected value.
When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by
clearing the corresponding mask bit (DBGxDHM/DBGxDLM), so that it is ignored in the comparison. A
match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register
bits are clear, then a match is based on the address bus only, the data bus is ignored.
When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any
data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored
and prevents a match because no difference can be detected. In this case address bus equivalence does not
cause a match.
Table 6-37. Comparator Access Size Considerations
Comparator Address SZE SZ8 Condition For Valid Match
Comparators
A and C ADDR[n] — — Word and byte accesses of ADDR[n]1
MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
1A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address used in the code.
Comparators
B and D ADDR[n] 0 X Word and byte accesses of ADDR[n]1
MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
Comparators
B and D ADDR[n] 1 0 Word accesses of ADDR[n]1
MOVW #$WORD ADDR[n]
Comparators
B and D ADDR[n] 1 1 Byte accesses of ADDR[n]
MOVB #$BYTE ADDR[n]
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6.4.2.4 Range Comparisons
When using the AB comparator pair for a range comparison, the data bus can also be used for qualification
by using the comparator A data and data mask registers. Furthermore the DBGACTL RW and RWE bits
can be used to qualify the range comparison on either a read or a write access. The corresponding
DBGBCTL bits are ignored. Similarly when using the CD comparator pair for a range comparison, the
data bus can also be used for qualification by using the comparator C data and data mask registers.
Furthermore the DBGCCTL RW and RWE bits can be used to qualify the range comparison on either a
read or a write access if tagging is not selected. The corresponding DBGDCTL bits are ignored. The SZE
and SZ control bits are ignored in range mode. The comparator A and C TAG bits are used to tag range
comparisons for the AB and CD ranges respectively. The comparator B and D TAG bits are ignored in
range modes. In order for a range comparison using comparators A and B, both COMPEA and COMPEB
must be set; to disable range comparisons both must be cleared. Similarly for a range CD comparison, both
COMPEC and COMPED must be set. The comparator A and C BRK bits are used for the AB and CD
ranges respectively, the comparator B and D BRK bits are ignored in range mode. When configured for
range comparisons and tagging, the ranges are accurate only to word boundaries.
6.4.2.4.1 Inside Range (CompAC_Addr ≤ address ≤ CompBD_Addr)
In the Inside Range comparator mode, either comparator pair A and B or comparator pair C and D can be
configured for range comparisons by the control register (DBGC2). The match condition requires that a
valid match for both comparators happens on the same bus cycle. A match condition on only one
comparator is not valid. An aligned word access which straddles the range boundary will cause a trigger
only if the aligned address is inside the range.
6.4.2.4.2 Outside Range (address < CompAC_Addr or address > CompBD_Addr)
In the Outside Range comparator mode, either comparator pair A and B or comparator pair C and D can
be configured for range comparisons. A single match condition on either of the comparators is recognized
as valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned
address is outside the range.
Outside range mode in combination with tagged triggers can be used to detect if the opcode fetches are
from an unexpected range. In forced trigger modes the outside range trigger would typically be activated
at any interrupt vector fetch or register access. This can be avoided by setting the upper or lower range limit
to $7FFFFF or $000000 respectively. Interrupt vector fetches do not cause taghits
Table 6-38. NDB and MASK bit dependency
NDB DBGxDHM[n] /
DBGxDLM[n] Comment
0 0 Do not compare data bus bit.
0 1 Compare data bus bit. Match on equivalence.
1 0 Do not compare data bus bit.
1 1 Compare data bus bit. Match on difference.
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6.4.3 Trigger Modes
Trigger modes are used as qualifiers for a state sequencer change of state. The control logic determines the
trigger mode and provides a trigger to the state sequencer. The individual trigger modes are described in
the following sections.
6.4.3.1 Forced Trigger On Comparator Match
If a forced trigger comparator match occurs, the trigger immediately initiates a transition to the next state
sequencer state whereby the corresponding flags in DBGSR are set. The state control register for the
current state determines the next state for each trigger. Forced triggers are generated as soon as the
matching address appears on the address bus, which in the case of opcode fetches occurs several cycles
before the opcode execution. For this reason a forced trigger at an opcode address precedes a tagged trigger
at the same address by several cycles.
6.4.3.2 Trigger On Comparator Related Taghit
If a CPU12X taghit occurs, a transition to another state sequencer state is initiated and the corresponding
DBGSR flags are set. For a comparator related taghit to occur, the S12XDBG must first generate tags based
on comparator matches. When the tagged instruction reaches the execution stage of the instruction queue
a taghit is generated by the CPU12X. The state control register for the current state determines the next
state for each trigger.
6.4.3.3 TRIG Immediate Trigger
Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing
the TRIG bit in DBGC1 to a logic “1”. If configured for begin or mid aligned tracing, this triggers the state
sequencer into the Final State, if configured for end alignment, setting the TRIG bit disarms the module,
ending the session. If breakpoints are enabled, a forced breakpoint request is issued immediately (end
alignment) or when tracing has completed (begin or mid alignment).
6.4.3.4 Trigger Priorities
In case of simultaneous triggers, the priority is resolved according to Table 6-39. The lower priority trigger
is suppressed. It is thus possible to miss a lower priority trigger if it occurs simultaneously with a trigger
of a higher priority. The trigger priorities described in Table 6-39 dictate that in the case of simultaneous
matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that
a match leading to final state has priority over all other matches in each state sequencer state. When
configured for range modes a simultaneous match of comparators A and C generates an active match0
whilst match2 is suppressed.
If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm
from an internal trigger event, then the ARM bit is cleared due to the hardware disarm.
Table 6-39. Trigger Priorities
Priority Source Action
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6.4.4 State Sequence Control
Figure 6-22. State Sequencer Diagram
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the
trace buffer. Once the S12XDBG module has been armed by setting the ARM bit in the DBGC1 register,
then state1 of the state sequencer is entered. Further transitions between the states are then controlled by
the state control registers and depend upon a selected trigger mode condition being met. From Final State
the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is
not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current
state.
Alternatively by setting the TRIG bit in DBGSC1, the state machine can be triggered to state0 or Final
State depending on tracing alignment.
Independent of the state sequencer, each comparator channel can be individually configured to generate an
immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers.
Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer
transition can be initiated by a match on other channels. If a debug session is ended by a trigger on a
channel with BRK = 1, the state sequencer transitions through Final State for a clock cycle to state0. This
is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state
sequencer enters state0 and the debug module is disarmed.
Highest TRIG Trigger immediately to final state (begin or mid aligned tracing enabled)
Trigger immediately to state 0 (end aligned or no tracing enabled)
Match0 (force or tag hit) Trigger to next state as defined by state control registers
Match1 (force or tag hit) Trigger to next state as defined by state control registers
Match2 (force or tag hit) Trigger to next state as defined by state control registers
Lowest Match3 (force or tag hit) Trigger to next state as defined by state control registers
Table 6-39. Trigger Priorities
State1
Final State State3
ARM = 1
Session Complete
(Disarm)
State2
State 0
(Disarmed) ARM = 0
ARM = 0
ARM = 0
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6.4.4.1 Final State
On entering Final State a trigger may be issued to the trace buffer according to the trace position control
as defined by the TALIGN field (see Section 6.3.2.3”). If TSOURCE in the trace control register DBGTCR
is cleared then the trace buffer is disabled and the transition to Final State can only generate a breakpoint
request. In this case or upon completion of a tracing session when tracing is enabled, the ARM bit in the
DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled, a breakpoint
request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled then when
the final state is reached it returns automatically to state0 and the debug module is disarmed.
6.4.5 Trace Buffer Operation
The trace buffer is a 64 lines deep by 64-bits wide RAM array. The S12XDBG module stores trace
information in the RAM array in a circular buffer format. The RAM array can be accessed through a
register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 64-bit trace
buffer line is read, an internal pointer into the RAM is incremented so that the next read will receive fresh
information. Data is stored in the format shown in Table 6-40. After each store the counter register bits
DBGCNT[6:0] are incremented. Tracing of CPU12X activity is disabled when the BDM is active. Reading
the trace buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not
incremented.
6.4.5.1 Trace Trigger Alignment
Using the TALIGN bits (see Section 6.3.2.3”) it is possible to align the trigger with the end, the middle, or
the beginning of a tracing session.
If End or Mid tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered.
The transition to Final State if End is selected signals the end of the tracing session. The transition to Final
State if Mid is selected signals that another 32 lines will be traced before ending the tracing session.
Tracing with Begin-Trigger starts at the opcode of the trigger.
6.4.5.1.1 Storing with Begin-Trigger
Storing with Begin-Trigger, data is not stored in the Trace Buffer until the Final State is entered. Once the
trigger condition is met the S12XDBG module will remain armed until 64 lines are stored in the Trace
Buffer. If the trigger is at the address of the change-of-flow instruction the change of flow associated with
the trigger will be stored in the Trace Buffer. Using Begin-trigger together with tagging, if the tagged
instruction is about to be executed then the trace is started. Upon completion of the tracing session the
breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary.
6.4.5.1.2 Storing with Mid-Trigger
Storing with Mid-Trigger, data is stored in the Trace Buffer as soon as the S12XDBG module is armed.
When the trigger condition is met, another 32 lines will be traced before ending the tracing session,
irrespective of the number of lines stored before the trigger occurred, then the S12XDBG module is
disarmed and no more data is stored. Using Mid-trigger with tagging, if the tagged instruction is about to
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be executed then the trace is continued for another 32 lines. Upon tracing completion the breakpoint is
generated, thus the breakpoint does not occur at the tagged instruction boundary.
6.4.5.1.3 Storing with End-Trigger
Storing with End-Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point
the S12XDBG module will become disarmed and no more data will be stored. If the trigger is at the
address of a change of flow instruction the trigger event will not be stored in the Trace Buffer.
6.4.5.2 Trace Modes
The S12XDBG module can operate in four trace modes. The mode is selected using the TRCMOD bits in
the DBGTCR register. The modes are described in the following subsections. The trace buffer organization
is shown in Table 6-40.
6.4.5.2.1 Normal Mode
In Normal Mode, change of flow (COF) program counter (PC) addresses will be stored.
COF addresses are defined as follows :
• Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
• Destination address of indexed JMP, JSR, and CALL instruction
• Destination address of RTI, RTS, and RTC instructions.
• Vector address of interrupts, except for SWI and BDM vectors
LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as
change of flow and are not stored in the trace buffer.
Change-of-flow addresses stored include the full 23-bit address bus of CPU12X and an information byte,
which contains a source/destination bit to indicate whether the stored address was a source address or
destination address.
NOTE
When an CPU12X COF instruction with destination address is executed, the
destination address is stored to the trace buffer on instruction completion,
indicating the COF has taken place. If an interrupt occurs simultaneously
then the next instruction carried out is actually from the interrupt service
routine. The instruction at the destination address of the original program
flow gets exectuted after the interrupt service routine.
In the following example an IRQ interrupt occurs during execution of the
indexed JMP at address MARK1. The BRN at the destination (SUB_1) is
not executed until after the IRQ service routine but the destination address
is entered into the trace buffer to indicate that the indexed JMP COF has
taken place.
LDX #SUB_1
MARK1 JMP 0,X ; IRQ interrupt occurs during execution of this
MARK2 NOP ;
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SUB_1 BRN * ; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
NOP ;
ADDR1 DBNE A,PART5 ; Source address TRACE BUFFER ENTRY 4
IRQ_ISR LDAB #$F0 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
STAB VAR_C1
RTI ;
The execution flow taking into account the IRQ is as follows
LDX #SUB_1
MARK1 JMP 0,X ;
IRQ_ISR LDAB #$F0 ;
STAB VAR_C1
RTI ;
SUB_1 BRN *
NOP ;
ADDR1 DBNE A,PART5 ;
6.4.5.2.2 Loop1 Mode
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it
however allows the filtering out of redundant information.
The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate
information from a looping construct such as delays using the DBNE instruction or polling loops using
BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the
S12XDBG module writes this value into a background register. This prevents consecutive duplicate
address entries in the Trace Buffer resulting from repeated branches.
Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in
most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector
addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the
S12XDBG module is designed to help find.
6.4.5.2.3 Detail Mode
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This
mode also features information byte entries to the trace buffer, for each address byte entry. The information
byte indicates the size of access (word or byte) and the type of access (read or write).
When tracing CPU12X activity in Detail Mode, all cycles are traced except those when the CPU12X is
either in a free or opcode fetch cycle, the address range can be limited to a range specified by the TRANGE
bits in DBGTCR. This function uses comparators C and D to define an address range inside which
CPU12X activity should be traced (see Table 6-40). Thus the traced CPU12X activity can be restricted to
particular register range accesses.
6.4.5.2.4 Pure PC Mode
In Pure PC Mode, tracing from the CPU the PC addresses of all executed opcodes, including illegal
opcodes, are stored.
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6.4.5.3 Trace Buffer Organization
Referring to Table 6-40. ADRH, ADRM, ADRL denote address high, middle and low byte respectively.
INF bytes contain control information (R/W, S/D etc.). The numerical suffix indicates which tracing step.
The information format for Loop1 Mode and PurePC Mode is the same as that of Normal Mode. Whilst
tracing in Normal or Loop1 modes each array line contains 2 data entries, thus in this case the DBGCNT[0]
is incremented after each separate entry. In Detail mode DBGCNT[0] remains cleared whilst the other
DBGCNT bits are incremented on each trace buffer entry.
When a COF occurs a trace buffer entry is made and the corresponding CDV bit is set.
Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (CDATAL )
and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to
trace buffer byte3 and the byte at the higher address is stored to byte2
Table 6-40. Trace Buffer Organization
Mode 8-Byte Wide Word Buffer
76543210
S12XCPU
Detail CXINF1 CADRH1 CADRM1 CADRL1 CDATAH1 CDATAL1
CXINF2 CADRH2 CADRM2 CADRL2 CDATAH2 CDATAL2
CPU12X
Other Modes CINF1 CPCH1 CPCM1 CPCL1 CINF0 CPCH0 CPCM0 CPCL0
CINF3 CPCH3 CPCM3 CPCL3 CINF2 CPCH2 CPCM2 CPCL2
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6.4.5.3.1 Information Byte Organization
The format of the control information byte is dependent upon the active trace mode as described below.
In Normal, Loop1, or Pure PC modes tracing of CPU12X activity, CINF is used to store control
information. In Detail Mode, CXINF contains the control information
CPU12X Information Byte
CXINF Information Byte
This describes the format of the information byte used only when tracing in Detail Mode. When tracing
from the CPU12X in Detail Mode, information is stored to the trace buffer on all cycles except opcode
fetch and free cycles. In this case the CSZ and CRW bits indicate the type of access being made by the
CPU12X.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CSD CVA 0 CDV 0 0 0 0
Figure 6-23. CPU12X Information Byte CINF
Table 6-41. CINF Field Descriptions
Field Description
7
CSD Source Destination Indicator —Thisbitindicates if the corresponding storedaddressis a source ordestination
address. This is only used in Normal and Loop1 mode tracing.
0 Source address
1 Destination address
6
CVA Vector Indicator — This bit indicates if the corresponding stored address is a vector address.. Vector addresses
are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This is only used in Normal
and Loop1 mode tracing. This bit has no meaning in Pure PC mode.
0 Indexed jump destination address
1 Vector destination address
4
CDV Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in Normal, Loop1 and Pure PC modes, to indicate that the CPU12X trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CSZ CRW
Figure 6-24. Information Byte CXINF
Table 6-42. CXINF Field Descriptions
Field Description
6
CSZ Access Type Indicator — This bit indicates if the access was a byte or word size access.This bit only contains
valid information when tracing CPU12X activity in Detail Mode.
0 Word Access
1 Byte Access
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6.4.5.4 Reading Data from Trace Buffer
The data stored in the Trace Buffer can be read using either the background debug module (BDM) module
or the CPU12X provided the S12XDBG module is not armed, is configured for tracing and the system not
secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer
can only be unlocked for reading by an aligned word write to DBGTB when the module is disarmed.
The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or
misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer
address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of
valid 64-bit lines can be determined. DBGCNT will not decrement as data is read.
Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the
pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0,
otherwise it points to the line with the oldest entry. The pointer is initialized by each aligned write to
DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be
easily restarted from the oldest data entry.
The least significant word of each 64-bit wide array line is read out first. This corresponds to the bytes 1
and 0 of Table 6-40. The bytes containing invalid information (shaded in Table 6-40) are also read out.
Reading the Trace Buffer while the S12XDBG module is armed will return invalid data and no shifting of
the RAM pointer will occur.
6.4.5.5 Trace Buffer Reset State
The Trace Buffer contents are not initialized by a system reset. Thus should a system reset occur, the trace
session information from immediately before the reset occurred can be read out. The DBGCNT bits are
not cleared by a system reset. Thus should a reset occur, the number of valid lines in the trace buffer is
indicated by DBGCNT. The internal pointer to the current trace buffer address is initialized by unlocking
the trace buffer thus points to the oldest valid data even if a reset occurred during the tracing session.
Generally debugging occurrences of system resets is best handled using mid or end trigger alignment since
the reset may occur before the trace trigger, which in the begin trigger alignment case means no
information would be stored in the trace buffer.
NOTE
An external pin RESET that occurs simultaneous to a trace buffer entry can,
in very seldom cases, lead to either that entry being corrupted or the first
entry of the session being corrupted. In such cases the other contents of the
trace buffer still contain valid tracing information. The case occurs when the
reset assertion coincides with the trace buffer entry clock edge.
5
CRW Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access. This bit only contains valid information when tracing CPU12X activity in Detail Mode.
0 Write Access
1 Read Access
Table 6-42. CXINF Field Descriptions (continued)
Field Description
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6.4.6 Tagging
A tag follows program information as it advances through the instruction queue. When a tagged instruction
reaches the head of the queue a tag hit occurs and triggers the state sequencer.
Each comparator control register features a TAG bit, which controls whether the comparator match will
cause a trigger immediately or tag the opcode at the matched address. If a comparator is enabled for tagged
comparisons, the address stored in the comparator match address registers must be an opcode address for
the trigger to occur.
Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the
transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started.
Only upon completion of the tracing session can a breakpoint be generated. Similarly using Mid trigger
with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32
lines. Upon tracing completion the breakpoint is generated. Using End trigger, when the tagged instruction
is about to be executed and the next transition is to Final State then a breakpoint is generated immediately,
before the tagged instruction is carried out.
Read/Write (R/W), access size (SZ) monitoring and data bus monitoring is not useful if tagged triggering
is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data
bus nor on the type of access. Thus these bits are ignored if tagged triggering is selected.
When configured for range comparisons and tagging, the ranges are accurate only to word boundaries.
S12X tagging is disabled when the BDM becomes active.
6.4.7 Breakpoints
Breakpoints can be generated as follows.
• From comparator channel triggers to final state.
• Using software to write to the TRIG bit in the DBGC1 register.
Breakpoints generated via the BDM BACKGROUND command have no affect on the CPU12X in STOP
or WAIT mode.
6.4.7.1 Breakpoints From Internal Comparator Channel Final State Triggers
Breakpoints can be generated when internal comparator channels trigger the state sequencer to the Final
State. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the
execution stage of the instruction queue.
If a tracing session is selected by TSOURCE, breakpoints are requested when the tracing session has
completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on
completion of the subsequent trace (see Table 6-43). If no tracing session is selected, breakpoints are
requested immediately.
If the BRK bit is set on the triggering channel, then the breakpoint is generated immediately independent
of tracing trigger alignment.
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6.4.7.2 Breakpoints Generated Via The TRIG Bit
If a TRIG triggers occur, the Final State is entered. If a tracing session is selected by TSOURCE,
breakpoints are requested when the tracing session has completed, thus if Begin or Mid aligned triggering
is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 6-43). If no
tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible even if
the S12XDBG module is disarmed.
6.4.7.3 S12XDBG Breakpoint Priorities
If a TRIG trigger occurs after Begin or Mid aligned tracing has already been triggered by a comparator
instigated transition to Final State, then TRIG no longer has an effect. When the associated tracing session
is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent trigger from a
comparator channel, it has no effect, since tracing has already started.
6.4.7.3.1 S12XDBG Breakpoint Priorities And BDM Interfacing
Breakpoint operation is dependent on the state of the S12XBDM module. If the S12XBDM module is
active, the CPU12X is executing out of BDM firmware and S12X breakpoints are disabled. In addition,
while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active, the
breakpoint will give priority to BDM requests over SWI requests if the breakpoint coincides with a SWI
instruction in the user’s code. On returning from BDM, the SWI from user code gets executed.
Table 6-43. Breakpoint Setup
BRK TALIGN DBGBRK Breakpoint Alignment
0 00 0 Fill Trace Buffer until trigger
(no breakpoints — keep running)
0 00 1 Fill Trace Buffer until trigger, then breakpoint request occurs
0 01 0 Start Trace Buffer at trigger
(no breakpoints — keep running)
0 01 1 Start Trace Buffer at trigger
A breakpoint request occurs when Trace Buffer is full
0 10 0 Store a further 32 Trace Buffer line entries after trigger
(no breakpoints — keep running)
0 10 1 Store a further 32 Trace Buffer line entries after trigger
Request breakpoint after the 32 further Trace Buffer entries
1 00,01,10 1 Terminate tracing and generate breakpoint immediately on trigger
1 00,01,10 0 Terminate tracing immediately on trigger
x 11 x Reserved
Table 6-44. Breakpoint Mapping Summary
DBGBRK
(DBGC1[3]) BDM Bit
(DBGC1[4]) BDM
Enabled BDM
Active S12X Breakpoint
Mapping
0 X X X No Breakpoint
1 0 X 0 Breakpoint to SWI
1 0 X 1 No Breakpoint
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BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via
a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU12X actually
executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If not serviced
by the monitor then the breakpoint is re-asserted when the BDM returns to normal CPU12X flow.
If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code
and DBG breakpoint could occur simultaneously. The CPU12X ensures that BDM requests have a higher
priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid re
triggering a breakpoint.
NOTE
When program control returns from a tagged breakpoint using an RTI or
BDM GO command without program counter modification it will return to
the instruction whose tag generated the breakpoint. To avoid re triggering a
breakpoint at the same location reconfigure the S12XDBG module in the
SWI routine, if configured for an SWI breakpoint, or over the BDM
interface by executing a TRACE command before the GO to increment the
program flow past the tagged instruction.
1 1 0 X Breakpoint to SWI
1 1 1 0 Breakpoint to BDM
1 1 1 1 No Breakpoint
Table 6-44. Breakpoint Mapping Summary
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Chapter 7
Security (S12XS9SECV2)
7.1 Introduction
This specification describes the function of the security mechanism in the S12XS chip family (9SEC).
NOTE
No security feature is absolutely secure. However, Freescale’s strategy is to
make reading or copying the FLASH and/or EEPROM difficult for
unauthorized users.
7.1.1 Features
The user must be reminded that part of the security must lie with the application code. An extreme example
would be application code that dumps the contents of the internal memory. This would defeat the purpose
of security. At the same time, the user may also wish to put a backdoor in the application program. An
example of this is the user downloads a security key through the SCI, which allows access to a
programming routine that updates parameters stored in another section of the Flash memory.
The security features of the S12XS chip family (in secure mode) are:
• Protect the content of non-volatile memories (Flash, EEPROM)
• Execution of NVM commands is restricted
• Disable access to internal memory via background debug module (BDM)
Table 7-2 gives an overview over availability of security relevant features in unsecure and secure modes.
Table 7-1. Revision History
Version
Number Revision
Date Effective
Date Author Description of Changes
02.00 27 Aug
2004 08 Sep
2004 reviewed and updated for S12XD architecture
02.01 21 Feb
2007 21 Feb
2007 added S12XE, S12XF and S12XS architectures
02.02 19 Apr
2007 19 Apr
2007 correctedstatementaboutBackdoorkeyaccessviaBDM onXE,XF,
XS
Table 7-2. Feature Availability in Unsecure and Secure Modes on S12XS
Unsecure Mode Secure Mode
NS SS NX ES EX ST NS SS NX ES EX ST
Flash Array Access ✔✔ ✔✔
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7.1.2 Modes of Operation
7.1.3 Securing the Microcontroller
Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the
security bits located in the options/security byte in the Flash memory array. These non-volatile bits will
keep the device secured through reset and power-down.
The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory
array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used
for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte
is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this
byte are copied into the Flash security register (FSEC) during a reset sequence.
The meaning of the bits KEYEN[1:0] is shown in Table 7-3. Please refer to Section 7.1.5.1, “Unsecuring
the MCU Using the Backdoor Key Access” for more information.
The meaning of the security bits SEC[1:0] is shown in Table 7-4. For security reasons, the state of device
security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to
EEPROM Array Access ✔✔ ✔✔
NVM Commands ✔1✔ ✔1✔1
BDM ✔✔ —✔2
DBG Module Trace ✔✔ ——
1Restricted NVM command set only. Please refer to the NVM wrapper block guides for detailed information.
2BDM hardware commands restricted to peripheral registers only.
76543210
0xFF0F KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0
Figure 7-1. Flash Options/Security Byte
Table 7-3. Backdoor Key Access Enable Bits
KEYEN[1:0] Backdoor Key
Access Enabled
00 0 (disabled)
01 0 (disabled)
10 1 (enabled)
11 0 (disabled)
Table 7-2. Feature Availability in Unsecure and Secure Modes on S12XS
Unsecure Mode Secure Mode
NS SS NX ES EX ST NS SS NX ES EX ST
Security (S12XS9SECV2)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 231
SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put
the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’.
NOTE
Please refer to the Flash block guide for actual security configuration (in
section “Flash Module Security”).
7.1.4 Operation of the Secured Microcontroller
By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented.
However, it must be understood that the security of the EEPROM and Flash memory contents also depends
on the design of the application program. For example, if the application has the capability of downloading
code through a serial port and then executing that code (e.g. an application containing bootloader code),
then this capability could potentially be used to read the EEPROM and Flash memory contents even when
the microcontroller is in the secure state. In this example, the security of the application could be enhanced
by requiring a challenge/response authentication before any code can be downloaded.
Secured operation has the following effects on the microcontroller:
Table 7-4. Security Bits
SEC[1:0] Security State
00 1 (secured)
01 1 (secured)
10 0 (unsecured)
11 1 (secured)
Security (S12XS9SECV2)
S12XS Family Reference Manual, Rev. 1.12
232 Freescale Semiconductor
7.1.4.1 Normal Single Chip Mode (NS)
• Background debug module (BDM) operation is completely disabled.
• Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for
details.
• Tracing code execution using the DBG module is disabled.
7.1.4.2 Special Single Chip Mode (SS)
• BDM firmware commands are disabled.
• BDM hardware commands are restricted to the register space.
• Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for
details.
• Tracing code execution using the DBG module is disabled.
Special single chip mode means BDM is active after reset. The availability of BDM firmware commands
depends on the security state of the device. The BDM secure firmware first performs a blank check of both
the Flash memory and the EEPROM. If the blank check succeeds, security will be temporarily turned off
and the state of the security bits in the appropriate Flash memory location can be changed If the blank
check fails, security will remain active, only the BDM hardware commands will be enabled, and the
accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used
to erase the EEPROM and Flash memory without giving access to their contents. After erasing both Flash
memory and EEPROM, another reset into special single chip mode will cause the blank check to succeed
and the options/security byte can be programmed to “unsecured” state via BDM.
While the BDM is executing the blank check, the BDM interface is completely blocked, which means that
all BDM commands are temporarily blocked.
Security (S12XS9SECV2)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 233
7.1.5 Unsecuring the Microcontroller
Unsecuring the microcontroller can be done by three different methods:
1. Backdoor key access
2. Reprogramming the security bits
3. Complete memory erase (special modes)
7.1.5.1 Unsecuring the MCU Using the Backdoor Key Access
In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key
access method. This method requires that:
• The backdoor key at 0xFF00–0xFF07 (= global addresses 0x7F_FF00–0x7F_FF07) has been
programmed to a valid value.
• The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’.
• In single chip mode, the application program programmed into the microcontroller must be
designed to have the capability to write to the backdoor key locations.
The backdoor key values themselves would not normally be stored within the application data, which
means the application program would have to be designed to receive the backdoor key values from an
external source (e.g. through a serial port).
The backdoor key access method allows debugging of a secured microcontroller without having to erase
the Flash. This is particularly useful for failure analysis.
NOTE
No word of the backdoor key is allowed to have the value 0x0000 or
0xFFFF.
7.1.6 Reprogramming the Security Bits
In normal single chip mode (NS), security can also be disabled by erasing and reprogramming the security
bits within Flash options/security byte to the unsecured value. Because the erase operation will erase the
entire sector from 0xFE00–0xFFFF (0x7F_FE00–0x7F_FFFF), the backdoor key and the interrupt vectors
will also be erased; this method is not recommended for normal single chip mode. The application
software can only erase and program the Flash options/security byte if the Flash sector containing the Flash
options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of
preventing this method. The microcontroller will enter the unsecured state after the next reset following
the programming of the security bits to the unsecured value.
This method requires that:
• The application software previously programmed into the microcontroller has been designed to
have the capability to erase and program the Flash options/security byte, or security is first disabled
using the backdoor key method, allowing BDM to be used to issue commands to erase and program
the Flash options/security byte.
• The Flash sector containing the Flash options/security byte is not protected.
Security (S12XS9SECV2)
S12XS Family Reference Manual, Rev. 1.12
234 Freescale Semiconductor
7.1.7 Complete Memory Erase (Special Modes)
The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory
contents.
When a secure microcontroller is reset into special single chip mode (SS), the BDM firmware verifies
whether the EEPROM and Flash memory are erased. If any EEPROM or Flash memory address is not
erased, only BDM hardware commands are enabled. BDM hardware commands can then be used to write
to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks.
When next reset into special single chip mode, the BDM firmware will again verify whether all EEPROM
and Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash
options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash
security register will indicate the unsecure state following the next reset.
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 235
Chapter 8
S12XE Clocks and Reset Generator (S12XECRGV1)
8.1 Introduction
This specification describes the function of the Clocks and Reset Generator (S12XECRG).
8.1.1 Features
The main features of this block are:
• Phase Locked Loop (IPLL) frequency multiplier with internal filter
— Reference divider
— Post divider
— Configurable internal filter (no external pin)
— Optional frequency modulation for defined jitter and reduced emission
— Automatic frequency lock detector
— Interrupt request on entry or exit from locked condition
— Self Clock Mode in absence of reference clock
• System Clock Generator
— Clock Quality Check
— User selectable fast wake-up from Stop in Self-Clock Mode for power saving and immediate
program execution
— Clock switch for either Oscillator or PLL based system clocks
• Computer Operating Properly (COP) watchdog timer with time-out clear window.
• System Reset generation from the following possible sources:
— Power on reset
Table 8-1. Revision History
Revision
Number Revision
Date Sections
Affected Description of Changes
V01.00 26 Oct. 2005 Initial release
V01.01 02 Nov 2006 8.4.1.1/8-252 Table “Examples of IPLL Divider settings”: corrected $32 to $31
V01.02 4 Mar. 2008 8.4.1.4/8-255
8.4.3.3/8-259 Corrected details
V01.03 1 Sep. 2008 Table 8-14 added 100MHz example for PLL
V01.04 20 Nov. 2008 8.3.2.4/8-241 S12XECRG Flags Register: corrected address to Module Base + 0x0003
V01.05 19. Sep 2009 8.5.1/8-261 Modified Note below Table 8-17./8-261
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual, Rev. 1.12
236 Freescale Semiconductor
— Low voltage reset
— Illegal address reset
— COP reset
— Loss of clock reset
— External pin reset
• Real-Time Interrupt (RTI)
8.1.2 Modes of Operation
This subsection lists and briefly describes all operating modes supported by the S12XECRG.
• Run Mode
All functional parts of the S12XECRG are running during normal Run Mode. If RTI or COP
functionality is required the individual bits of the associated rate select registers (COPCTL,
RTICTL) have to be set to a non zero value.
• Wait Mode
In this mode the IPLL can be disabled automatically depending on the PLLWAI bit.
• Stop Mode
Depending on the setting of the PSTP bit Stop Mode can be differentiated between Full Stop Mode
(PSTP = 0) and Pseudo Stop Mode (PSTP = 1).
— Full Stop Mode
The oscillator is disabled and thus all system and core clocks are stopped. The COP and the
RTI remain frozen.
— Pseudo Stop Mode
The oscillator continues to run and most of the system and core clocks are stopped. If the
respective enable bits are set the COP and RTI will continue to run, else they remain frozen.
• Self Clock Mode
Self Clock Mode will be entered if the Clock Monitor Enable Bit (CME) and the Self Clock Mode
Enable Bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of
clock. As soon as Self Clock Mode is entered the S12XECRG starts to perform a clock quality
check. Self Clock Mode remains active until the clock quality check indicates that the required
quality of the incoming clock signal is met (frequency and amplitude). Self Clock Mode should be
used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock
is causing severe system conditions.
8.1.3 Block Diagram
Figure 8-1 shows a block diagram of the S12XECRG.
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual Rev. 1.12
Freescale Semiconductor 237
Figure 8-1. Block diagram of S12XECRG
8.2 Signal Description
This section lists and describes the signals that connect off chip.
8.2.1 VDDPLL, VSSPLL
These pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the IPLL circuitry. This allows
the supply voltage to the IPLL to be independently bypassed. Even if IPLL usage is not required VDDPLL
and VSSPLL must be connected to properly.
8.2.2 RESET
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been
triggered.
ICRG
Registers
COP
RESET
RTI
IPLL
VDDPLL
VSSPLL
EXTAL
XTAL
Bus Clock
System Reset
Oscillator Clock
PLLCLK
OSCCLK
Core Clock
CM Fail
XCLKS
Power on Reset
Low Voltage Reset
COP Timeout
Real Time Interrupt
PLL Lock Interrupt
Self Clock Mode
Interrupt
S12X_MMC Illegal Address Reset
Reset
Generator
Clock Quality
Checker
Clock and Reset Control
Voltage
Regulator
Clock
Monitor
Oscillator
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual, Rev. 1.12
238 Freescale Semiconductor
8.3 Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12XECRG.
8.3.1 Module Memory Map
Figure 8-2 gives an overview on all S12XECRG registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Address Name Bit 7 6 5 4 3 2 1 Bit 0
0x0000 SYNR RVCOFRQ[1:0] SYNDIV[5:0]
W
0x0001 REFDV RREFFRQ[1:0] REFDIV[5:0]
W
0x0002 POSTDIV R0 0 0 POSTDIV[4:0]
W
0x0003 CRGFLG RRTIF PORF LVRF LOCKIF LOCK ILAF SCMIF SCM
W
0x0004 CRGINT RRTIE 00
LOCKIE 00
SCMIE 0
W
0x0005 CLKSEL RPLLSEL PSTP XCLKS 0 PLLWAI 0RTIWAI COPWAI
W
0x0006 PLLCTL RCME PLLON FM1 FM0 FSTWKP PRE PCE SCME
W
0x0007 RTICTL RRTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
0x0008 COPCTL RWCOP RSBCK 000
CR2 CR1 CR0
W WRTMASK
0x0009 FORBYP2R0 0 0 000 0 0
W
0x000A CTCTL2R0 0 0 000 0 0
W
0x000B ARMCOP R0 0 0 000 0 0
W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2. FORBYP and CTCTL are intended for factory test purposes only.
= Unimplemented or Reserved
Figure 8-2. CRG Register Summary
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual Rev. 1.12
Freescale Semiconductor 239
8.3.2 Register Descriptions
This section describes in address order all the S12XECRG registers and their individual bits.
8.3.2.1 S12XECRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range.
Read: Anytime
Write: Anytime except if PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit.
NOTE
fVCO must be within the specified VCO frequency lock range. F.BUS (Bus
Clock) must not exceed the specified maximum. If POSTDIV = $00 then
fPLL is same as fVCO (divide by one).
The VCOFRQ[1:0] bit are used to configure the VCO gain for optimal stability and lock time. For correct
IPLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in Table 8-2. Setting the VCOFRQ[1:0] bits wrong can result in a non functional IPLL
(no locking and/or insufficient stability).
Module Base + 0x0000
76543210
RVCOFRQ[1:0] SYNDIV[5:0]
W
Reset 0 0 0 00000
Figure 8-3. S12XECRG Synthesizer Register (SYNR)
Table 8-2. VCO Clock Frequency Selection
VCOCLK Frequency Ranges VCOFRQ[1:0]
32MHz <= fVCO<= 48MHz 00
48MHz < fVCO<= 80MHz 01
Reserved 10
80MHz < fVCO <= 120MHz 11
fVCO 2f
OSC
×SYNDIV 1+()
REFDIV 1+()
-------------------------------------
×=
fPLL
fVCO
2 POSTDIV×
------------------------------------=
fBUS
fPLL
2
-------------=
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual, Rev. 1.12
240 Freescale Semiconductor
8.3.2.2 S12XECRG Reference Divider Register (REFDV)
The REFDV register provides a finer granularity for the IPLL multiplier steps.
Read: Anytime
Write: Anytime except when PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit.
The REFFRQ[1:0] bit are used to configure the internal PLL filter for optimal stability and lock time. For
correct IPLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in Figure 8-3. Setting the REFFRQ[1:0] bits wrong can result in a non functional IPLL
(no locking and/or insufficient stability).
8.3.2.3 S12XECRG Post Divider Register (POSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and PLLCLK. The count in the
final divider divides VCOCLK frequency by 1 or 2*POSTDIV. Note that if POSTDIV = $00 fPLL= fVCO
(divide by one).
Module Base + 0x0001
76543210
RREFFRQ[1:0] REFDIV[5:0]
W
Reset 0 0 0 00000
Figure 8-4. S12XECRG Reference Divider Register (REFDV)
Table 8-3. Reference Clock Frequency Selection
REFCLK Frequency Ranges REFFRQ[1:0]
1MHz <= fREF <= 2MHz 00
2MHz < fREF <= 6MHz 01
6MHz < fREF <= 12MHz 10
fREF >12MHz 11
fREF
fOSC
REFDIV 1+()
------------------------------------=
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual Rev. 1.12
Freescale Semiconductor 241
Read: Anytime
Write: Anytime except if PLLSEL = 1
NOTE
If POSTDIV = $00 then fPLL is identical to fVCO (divide by one).
8.3.2.4 S12XECRG Flags Register (CRGFLG)
This register provides S12XECRG status bits and flags.
Read: Anytime
Write: Refer to each bit for individual write conditions
Module Base + 0x0002
76543210
R000 POSTDIV[4:0]
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 8-5. S12XECRG Post Divider Register (POSTDIV)
Module Base + 0x0003
76543210
RRTIF PORF LVRF LOCKIF LOCK ILAF SCMIF SCM
W
Reset 0 Note 1 Note 2 Note 3 0000
1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by system reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset.
= Unimplemented or Reserved
Figure 8-6. S12XECRG Flags Register (CRGFLG)
fPLL
fVCO
2xPOSTDIV()
--------------------------------------=
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual, Rev. 1.12
242 Freescale Semiconductor
8.3.2.5 S12XECRG Interrupt Enable Register (CRGINT)
This register enables S12XECRG interrupt requests.
Table 8-4. CRGFLG Field Descriptions
Field Description
7
RTIF Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
6
PORF Power on Reset Flag —PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 Power on reset has not occurred.
1 Power on reset has occurred.
5
LVRF Low Voltage Reset Flag —LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
4
LOCKIF IPLL Lock Interrupt Flag —LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared
by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
3
LOCK Lock Status Bit —LOCK reflects the current state of IPLL lock condition. This bit is cleared in Self Clock Mode.
Writes have no effect.
0 VCOCLK is not within the desired tolerance of the target frequency.
1 VCOCLK is within the desired tolerance of the target frequency.
2
ILAF Illegal Address Reset Flag —ILAF is set to 1 when an illegal address reset occurs. Refer to S12XMMC Block
Guide for details. This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Illegal address reset has not occurred.
1 Illegal address reset has occurred.
1
SCMIF Self Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be
cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request.
0 No change in SCM bit.
1 SCM bit has changed.
0
SCM Self Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect.
0 MCU is operating normally with OSCCLK available.
1 MCU is operating in Self Clock Mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK
running at its minimum frequency fSCM.
Module Base + 0x0004
76543210
RRTIE 00
LOCKIE 00
SCMIE 0
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 8-7. S12XECRG Interrupt Enable Register (CRGINT)
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual Rev. 1.12
Freescale Semiconductor 243
Read: Anytime
Write: Anytime
8.3.2.6 S12XECRG Clock Select Register (CLKSEL)
This register controls S12XECRG clock selection. Refer toFigure 8-16 for more details on the effect of each
bit.
Read: Anytime
Write: Refer to each bit for individual write conditions
Table 8-5. CRGINT Field Descriptions
Field Description
7
RTIE Real Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
1 Interrupt will be requested whenever RTIF is set.
4
LOCKIE Lock Interrupt Enable Bit
0 LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
1
SCMIE Self Clock Mode Interrupt Enable Bit
0 SCM interrupt requests are disabled.
1 Interrupt will be requested whenever SCMIF is set.
Module Base + 0x0005
76543210
RPLLSEL PSTP XCLKS 0 PLLWAI 0RTIWAI COPWAI
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 8-8. S12XECRG Clock Select Register (CLKSEL)
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual, Rev. 1.12
244 Freescale Semiconductor
8.3.2.7 S12XECRG IPLL Control Register (PLLCTL)
This register controls the IPLL functionality.
Table 8-6. CLKSEL Field Descriptions
Field Description
7
PLLSEL PLL Select Bit
Write: Anytime.
Writing a one when LOCK=0 has no effect. This prevents the selection of an unstable PLLCLK as SYSCLK.
PLLSEL bit is cleared when the MCU enters Self Clock Mode, Stop Mode or Wait Mode with PLLWAI bit set.
It is recommended to read back the PLLSEL bit to make sure PLLCLK has really been selected as
SYSCLK, as LOCK status bit could theoretically change at the very moment writing the PLLSEL bit.
0 System clocks are derived from OSCCLK (fBUS = fOSC / 2).
1 System clocks are derived from PLLCLK (fBUS = fPLL / 2).
6
PSTP Pseudo Stop Bit
Write: Anytime
This bit controls the functionality of the oscillator during Stop Mode.
0 Oscillator is disabled in Stop Mode.
1 Oscillator continues to run in Stop Mode (Pseudo Stop).
Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the
resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.
5
XCLKS Oscillator Configuration Status Bit — This read-only bit shows the oscillator configuration status.
0 Loop controlled Pierce Oscillator is selected.
1 External clock / full swing Pierce Oscillator is selected.
3
PLLWAI PLL Stops in Wait Mode Bit
Write: Anytime
If PLLWAI is set, the S12XECRG will clear the PLLSEL bit before entering Wait Mode. The PLLON bit remains
set during Wait Mode but the IPLL is powered down. Upon exiting Wait Mode, the PLLSEL bit has to be set
manually if PLL clock is required.
0 IPLL keeps running in Wait Mode.
1 IPLL stops in Wait Mode.
1
RTIWAI RTI Stops in Wait Mode Bit
Write: Anytime
0 RTI keeps running in Wait Mode.
1 RTI stops and initializes the RTI dividers whenever the part goes into Wait Mode.
0
COPWAI COP Stops in Wait Mode Bit
Normal modes: Write once
Special modes: Write anytime
0 COP keeps running in Wait Mode.
1 COP stops and initializes the COP counter whenever the part goes into Wait Mode.
Module Base + 0x0006
76543210
RCME PLLON FM1 FM0 FSTWKP PRE PCE SCME
W
Reset 1 1 0 00001
Figure 8-9. S12XECRG IPLL Control Register (PLLCTL)
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual Rev. 1.12
Freescale Semiconductor 245
Read: Anytime
Write: Refer to each bit for individual write conditions
Table 8-7. PLLCTL Field Descriptions
Field Description
7
CME Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1.
0 Clock monitor is disabled.
1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or Self Clock
Mode.
Note: Operating with CME=0 will not detect any loss of clock. In case of poor clock quality this could cause
unpredictable operation of the MCU!
In Stop Mode (PSTP=0) the clock monitor is disabled independently of the CME bit setting and any loss
of external clock will not be detected.
Also after wake-up from stop mode (PSTP = 0) with fast wake-up enabled (FSTWKP = 1) the clock monitor
is disabled independently of the CME bit setting and any loss of external clock will not be detected.
6
PLLON Phase Lock Loop On Bit — PLLON turns on the IPLL circuitry. In Self Clock Mode, the IPLL is turned on, but
the PLLON bit reads the last written value. Write anytime except when PLLSEL = 1.
0 IPLL is turned off.
1 IPLL is turned on.
5, 4
FM1, FM0 IPLL Frequency Modulation Enable Bit — FM1 and FM0 enable additional frequency modulation on the
VCOCLK. This is to reduce noise emission. The modulation frequency is fref divided by 16. Write anytime except
when PLLSEL = 1. See Table 8-8 for coding.
3
FSTWKP Fast Wake-up from Full Stop Bit — FSTWKP enables fast wake-up from full stop mode. Write anytime. If Self-
Clock Mode is disabled (SCME = 0) this bit has no effect.
0 Fast wake-up from full stop mode is disabled.
1 Fast wake-up from full stop mode is enabled. When waking up from full stop mode the system will immediately
resume operation in Self-Clock Mode (see Section 8.4.1.4, “Clock Quality Checker”). The SCMIF flag will not
be set. The system will remain in Self-Clock Mode with oscillator and clock monitor disabled until FSTWKP bit
is cleared. The clearing of FSTWKP will start the oscillator, the clock monitor and the clock quality check. If
the clock quality check is successful, the S12XECRG will switch all system clocks to OSCCLK. The SCMIF
flag will be set. See application examples in Figure 8-19 and Figure 8-20.
2
PRE RTI Enable During Pseudo Stop Bit — PRE enables the RTI during Pseudo Stop Mode.
Write anytime.
0 RTI stops running during Pseudo Stop Mode.
1 RTI continues running during Pseudo Stop Mode.
Note: If the PRE bit is cleared the RTI dividers will go static while Pseudo Stop Mode is active. The RTI dividers
will not initialize like in Wait Mode with RTIWAI bit set.
1
PCE COP Enable During Pseudo Stop Bit — PCE enables the COP during Pseudo Stop Mode.
Write anytime.
0 COP stops running during Pseudo Stop Mode
1 COP continues running during Pseudo Stop Mode
Note: If the PCE bit is cleared the COP dividers will go static while Pseudo Stop Mode is active. The COP
dividers will not initialize like in Wait Mode with COPWAI bit set.
0
SCME Self Clock Mode Enable Bit
Normal modes: Write once
Special modes: Write anytime
SCME can not be cleared while operating in Self Clock Mode (SCM = 1).
0 Detection of crystal clock failure causes clock monitor reset (see Section 8.5.1.1, “Clock Monitor Reset”).
1 Detection of crystal clock failure forces the MCU in Self Clock Mode (see Section 8.4.2.2, “Self Clock Mode”).
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual, Rev. 1.12
246 Freescale Semiconductor
8.3.2.8 S12XECRG RTI Control Register (RTICTL)
This register selects the timeout period for the Real Time Interrupt.
Read: Anytime
Write: Anytime
NOTE
A write to this register initializes the RTI counter.
Table 8-8. FM Amplitude selection
FM1 FM0 FM Amplitude /
fVCO Variation
0 0 FM off
01 ±1%
10 ±2%
11 ±4%
Module Base + 0x0007
76543210
RRTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0
W
Reset 0 0 0 00000
Figure 8-10. S12XECRG RTI Control Register (RTICTL)
Table 8-9. RTICTL Field Descriptions
Field Description
7
RTDEC Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See Table 8-10
1 Decimal based divider value. See Table 8-11
6–4
RTR[6:4] Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 8-
10 and Table 8-11.
3–0
RTR[3:0] Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.Table 8-10 and Table 8-11 show all possible divide values selectable by the
RTICTL register. The source clock for the RTI is OSCCLK.
Table 8-10. RTI Frequency Divide Rates for RTDEC = 0
RTR[3:0]
RTR[6:4] =
000
(OFF) 001
(210)010
(211)011
(212)100
(213)101
(214)110
(215)111
(216)
0000 (÷1) OFF1210 211 212 213 214 215 216
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Freescale Semiconductor 247
0001 (÷2) OFF 2x210 2x211 2x212 2x213 2x214 2x215 2x216
0010 (÷3) OFF 3x210 3x211 3x212 3x213 3x214 3x215 3x216
0011 (÷4) OFF 4x210 4x211 4x212 4x213 4x214 4x215 4x216
0100 (÷5) OFF 5x210 5x211 5x212 5x213 5x214 5x215 5x216
0101 (÷6) OFF 6x210 6x211 6x212 6x213 6x214 6x215 6x216
0110 (÷7) OFF 7x210 7x211 7x212 7x213 7x214 7x215 7x216
0111 (÷8) OFF 8x210 8x211 8x212 8x213 8x214 8x215 8x216
1000 (÷9) OFF 9x210 9x211 9x212 9x213 9x214 9x215 9x216
1001 (÷10) OFF 10x210 10x211 10x212 10x213 10x214 10x215 10x216
1010 (÷11) OFF 11x210 11x211 11x212 11x213 11x214 11x215 11x216
1011 (÷12) OFF 12x210 12x211 12x212 12x213 12x214 12x215 12x216
1100 (÷13) OFF 13x210 13x211 13x212 13x213 13x214 13x215 13x216
1101 (÷14) OFF 14x210 14x211 14x212 14x213 14x214 14x215 14x216
1110 (÷15) OFF 15x210 15x211 15x212 15x213 15x214 15x215 15x216
1111 (÷16) OFF 16x210 16x211 16x212 16x213 16x214 16x215 16x216
1Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.
Table 8-11. RTI Frequency Divide Rates for RTDEC=1
RTR[3:0]
RTR[6:4] =
000
(1x103)001
(2x103)010
(5x103)011
(10x103)100
(20x103)101
(50x103)110
(100x103)111
(200x103)
0000 (÷1) 1x1032x1035x10310x10320x10350x103100x103200x103
0001 (÷2) 2x1034x10310x10320x10340x103100x103200x103400x103
0010 (÷3) 3x1036x10315x10330x10360x103150x103300x103600x103
0011 (÷4) 4x1038x10320x10340x10380x103200x103400x103800x103
0100 (÷5) 5x10310x10325x10350x103100x103250x103500x1031x106
0101 (÷6) 6x10312x10330x10360x103120x103300x103600x1031.2x106
Table 8-10. RTI Frequency Divide Rates for RTDEC = 0
RTR[3:0]
RTR[6:4] =
000
(OFF) 001
(210)010
(211)011
(212)100
(213)101
(214)110
(215)111
(216)
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248 Freescale Semiconductor
8.3.2.9 S12XECRG COP Control Register (COPCTL)
This register controls the COP (Computer Operating Properly) watchdog.
Read: Anytime
Write:
1. RSBCK: anytime in special modes; write to “1” but not to “0” in all other modes
2. WCOP, CR2, CR1, CR0:
— Anytime in special modes
— Write once in all other modes
– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
– Writing WCOP to “0” has no effect, but counts for the “write once” condition.
0110 (÷7) 7x10314x10335x10370x103140x103350x103700x1031.4x106
0111 (÷8) 8x10316x10340x10380x103160x103400x103800x1031.6x106
1000 (÷9) 9x10318x10345x10390x103180x103450x103900x1031.8x106
1001 (÷10) 10 x10320x10350x103100x103200x103500x1031x1062x106
1010 (÷11) 11 x10322x10355x103110x103220x103550x1031.1x1062.2x106
1011 (÷12) 12x10324x10360x103120x103240x103600x1031.2x1062.4x106
1100 (÷13) 13x10326x10365x103130x103260x103650x1031.3x1062.6x106
1101 (÷14) 14x10328x10370x103140x103280x103700x1031.4x1062.8x106
1110 (÷15) 15x10330x10375x103150x103300x103750x1031.5x1063x106
1111 (÷16) 16x10332x10380x103160x103320x103800x1031.6x1063.2x106
Module Base + 0x0008
76543210
RWCOP RSBCK 000
CR2 CR1 CR0
W WRTMASK
Reset100000000
1. Refer to Device User Guide (Section: S12XECRG) for reset values of WCOP, CR2, CR1 and CR0.
= Unimplemented or Reserved
Figure 8-11. S12XECRG COP Control Register (COPCTL)
Table 8-11. RTI Frequency Divide Rates for RTDEC=1
RTR[3:0]
RTR[6:4] =
000
(1x103)001
(2x103)010
(5x103)011
(10x103)100
(20x103)101
(50x103)110
(100x103)111
(200x103)
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Freescale Semiconductor 249
The COP time-out period is restarted if one these two conditions is true:
1. Writing a non zero value to CR[2:0] (anytime in special modes, once in all other modes) with
WRTMASK = 0.
or
2. Changing RSBCK bit from “0” to “1”.
Table 8-12. COPCTL Field Descriptions
Field Description
7
WCOP Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected
period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during
this window, $55 can be written as often as desired. Once $AA is written after the $55, the time-out logic restarts
and the user must wait until the next window before writing to ARMCOP. Table 8-13 shows the duration of this
window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
6
RSBCK COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in Active BDM mode.
1 Stops the COP and RTI counters whenever the part is in Active BDM mode.
5
WRTMASK Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits
while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of
WCOP and CR[2:0].
0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL
1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL.
(Does not count for “write once”.)
2–0
CR[2:0] COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 8-13). Writing a
nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out
causes a system reset. This can be avoided by periodically (before time-out) reinitialize the COP counter via the
ARMCOP register.
While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at
highest time-out period (224 cycles) in normal COP mode (Window COP mode disabled):
1) COP is enabled (CR[2:0] is not 000)
2) BDM mode active
3) RSBCK = 0
4) Operation in emulation or special modes
Table 8-13. COP Watchdog Rates1
CR2 CR1 CR0 OSCCLK
Cycles to Timeout
0 0 0 COP disabled
001 2
14
010 2
16
011 2
18
100 2
20
101 2
22
110 2
23
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250 Freescale Semiconductor
8.3.2.10 Reserved Register (FORBYP)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special
modes can alter the S12XECRG’s functionality.
Read: Always read $00 except in special modes
Write: Only in special modes
8.3.2.11 Reserved Register (CTCTL)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special test
modes can alter the S12XECRG’s functionality.
Read: Always read $00 except in special modes
111 2
24
1OSCCLK cycles are referenced from the previous COP time-out reset
(writing $55/$AA to the ARMCOP register)
Module Base + 0x0009
76543210
R00000000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 8-12. Reserved Register (FORBYP)
Module Base + 0x000A
76543210
R00000000
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 8-13. Reserved Register (CTCTL)
Table 8-13. COP Watchdog Rates1
CR2 CR1 CR0 OSCCLK
Cycles to Timeout
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Freescale Semiconductor 251
Write: Only in special modes
8.3.2.12 S12XECRG COP Timer Arm/Reset Register (ARMCOP)
This register is used to restart the COP time-out period.
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period
you must write $55 followed by a write of $AA. Other instructions may be executed between these
writes but the sequence ($55, $AA) must be completed prior to COP end of time-out period to
avoid a COP reset. Sequences of $55 writes or sequences of $AA writes are allowed. When the
WCOP bit is set, $55 and $AA writes must be done in the last 25% of the selected time-out period;
writing any value in the first 75% of the selected period will cause a COP reset.
Module Base + 0x000B
76543210
R00000000
W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset 0 0 0 00000
Figure 8-14. S12XECRG ARMCOP Register Diagram
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252 Freescale Semiconductor
8.4 Functional Description
8.4.1 Functional Blocks
8.4.1.1 Phase Locked Loop with Internal Filter (IPLL)
The IPLL is used to run the MCU from a different time base than the incoming OSCCLK. Figure 8-15
shows a block diagram of the IPLL.
Figure 8-15. IPLL Functional Diagram
For increased flexibility, OSCCLK can be divided in a range of 1 to 64 to generate the reference frequency
REFCLK using the REFDIV[5:0] bits. This offers a finer multiplication granularity. Based on the
SYNDIV[5:0] bits the IPLL generates the VCOCLK by multiplying the reference clock by a multiple of 2,
4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,4,6,8,... to
62 to generate the PLLCLK.
.
NOTE
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
If (PLLSEL = 1) then fBUS = fPLL / 2.
IF POSTDIV = $00 the fPLL is identical to fVCO (divide by one)
Several examples of IPLL divider settings are shown in Table 8-14. Shaded rows indicated that these
settings are not recommended. The following rules help to achieve optimum stability and shortest lock
time:
• Use lowest possible fVCO / fREF ratio (SYNDIV value).
• Use highest possible REFCLK frequency fREF.
REDUCED
CONSUMPTION
OSCILLATOR
EXTAL
XTAL
OSCCLK
PLLCLK
REFERENCE
PROGRAMMABLE
DIVIDER PDET
PHASE
DETECTOR
REFDIV[5:0]
LOOP
PROGRAMMABLE
DIVIDER
SYNDIV[5:0]
VCO
LOCK
UP
DOWN
LOCK
DETECTOR
REFCLK
FBCLK
VDDPLL/VSSPLL
CLOCK
MONITOR
VDDPLL/VSSPLL
VDD/VSS
Supplied by:
CPUMP
AND
FILTER
POST
PROGRAMMABLE
DIVIDER
POSTDIV[4:0]
VCOCLK
fPLL 2f
OSC
SYNDIV 1+
REFDIV 1+[]2 POSTDIV×[]
------------------------------------------------------------------------------
××=
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Freescale Semiconductor 253
8.4.1.1.1 IPLL Operation
The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is
divided in a range of 1 to 64 (REFDIV+1) to output the REFCLK. The VCO output clock, (VCOCLK) is
fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2
x (SYNDIV +1)] to output the FBCLK. The VCOCLK is fed to the final programmable divider and is
divided in a range of 1,2,4,6,8,... to 62 (2*POSTDIV) to output the PLLCLK. See Figure 8-15.
The phase detector then compares the FBCLK, with the REFCLK. Correction pulses are generated based
on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the
internal filter capacitor, based on the width and direction of the correction pulse.
The user must select the range of the REFCLK frequency and the range of the VCOCLK frequency to
ensure that the correct IPLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK, and the REFCLK. Therefore, the speed of the
lock detector is directly proportional to the reference clock frequency. The circuit determines the lock
condition based on this comparison.
If IPLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check
the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during IPLL
start-up, usually) or at periodic intervals. In either case, only when the LOCK bit is set, the PLLCLK can
be selected as the source for the system and core clocks. If the IPLL is selected as the source for the system
and core clocks and the LOCK bit is clear, the IPLL has suffered a severe noise hit and the software must
take appropriate action, depending on the application.
• The LOCK bit is a read-only indicator of the locked state of the IPLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆Lock, and is cleared
when the VCO frequency is out of a certain tolerance, ∆unl.
• Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling
the LOCK bit.
Table 8-14. Examples of IPLL Divider Settings
fOSC REFDIV[5:0] fREF REFFRQ[1:0] SYNDIV[5:0] fVCO VCOFRQ[1:0] POSTDIV[4:0] fPLL fBUS
4MHz $01 2MHz 01 $18 100MHz 11 $00 100MHz 50 MHz
8MHz $03 2MHz 01 $18 100MHz 11 $00 100MHz 50 MHz
4MHz $00 4MHz 01 $09 80MHz 01 $00 80MHz 40MHz
8MHz $00 8MHz 10 $04 80MHz 01 $00 80MHz 40MHz
4MHz $00 4MHz 01 $03 32MHz 00 $01 16MHz 8MHz
4MHz $01 2MHz 01 $18 100MHz 11 $01 50MHz 25MHz
4MHz $03 1MHz 00 $18 50MHz 01 $00 50MHz 25MHz
4MHz $03 1MHz 00 $31 100MHz 11 $01 50MHz 25MHz
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254 Freescale Semiconductor
8.4.1.2 System Clocks Generator
Figure 8-16. System Clocks Generator
The clock generator creates the clocks used in the MCU (see Figure 8-16). The gating condition placed on
top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the
setting of the respective configuration bits.
The peripheral modules use the Bus Clock. Some peripheral modules also use the Oscillator Clock. If the
MCU enters Self Clock Mode (see Section 8.4.2.2, “Self Clock Mode”) Oscillator clock source is switched
to PLLCLK running at its minimum frequency fSCM. The Bus Clock is used to generate the clock visible at
the ECLK pin. The Core Clock signal is the clock for the CPU. The Core Clock is twice the Bus Clock. But
note that a CPU cycle corresponds to one Bus Clock.
IPLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the IPLL output clock
drives SYSCLK for the main system including the CPU and peripherals. The IPLL cannot be turned off by
clearing the PLLON bit, if the IPLL clock is selected. When PLLSEL is changed, it takes a maximum of 4
OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and CPU
activity ceases.
OSCILLATOR
PHASE
LOCK
LOOP (IIPLL)
EXTAL
XTAL
SYSCLK
RTI
OSCCLK
PLLCLK
CLOCK PHASE
GENERATOR Bus Clock
Clock
Monitor
1
0
PLLSEL or SCM
÷2
Core Clock
COP
Oscillator
= Clock Gate
Gating
Condition
WAIT(RTIWAI),
STOP(PSTP, PRE),
RTI ENABLE
WAIT(COPWAI),
STOP(PSTP, PCE),
COP ENABLE
STOP
1
0
SCM
Clock
STOP
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Freescale Semiconductor 255
8.4.1.3 Clock Monitor (CM)
If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block
generates a clock monitor fail event. The S12XECRG then asserts self clock mode or generates a system
reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is
detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by
the CME control bit.
8.4.1.4 Clock Quality Checker
The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker
provides a more accurate check in addition to the clock monitor.
A clock quality check is triggered by any of the following events:
• Power on reset (POR)
• Low voltage reset (LVR)
• Wake-up from Full Stop Mode (exit full stop)
• Clock Monitor fail indication (CM fail)
A time window of 50000 PLLCLK cycles1 is called check window.
A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that
osc ok immediately terminates the current check window. See Figure 8-17 as an example.
Figure 8-17. Check Window Example
1. IPLL is running at self clock mode frequency fSCM.
12 49999 50000
PLLCLK
CHECK WINDOW
12345
4095
4096
3
OSCCLK
OSC OK
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256 Freescale Semiconductor
The Sequence for clock quality check is shown in Figure 8-18.
Figure 8-18. Sequence for Clock Quality Check
NOTE
Remember that in parallel to additional actions caused by Self Clock Mode
or Clock Monitor Reset1 handling the clock quality checker continues to
check the OSCCLK signal.
NOTE
The Clock Quality Checker enables the IPLL and the voltage regulator
(VREG) anytime a clock check has to be performed. An ongoing clock
quality check could also cause a running IPLL (fSCM) and an active VREG
during Pseudo Stop Mode.
1. A Clock Monitor Reset will always set the SCME bit to logical’1’.
CHECK WINDOW
OSC OK
?
SCM
ACTIVE?
SWITCH TO OSCCLK
EXIT SCM
CLOCK OK
NUM = 50
NUM > 0
?
NUM = NUM-1
YES
NO
YES
SCME = 1
?
NO
ENTER SCM
SCM
ACTIVE?
YES
CLOCK MONITOR RESET
NO
YES
NO
NUM = 0
YES
NO
POR
EXIT FULL STOP
CM FAIL
LVR
SCME=1 &
?
FSTWKP=1
YES
NO
?
FSTWKP = 0
NO
NUM = 0 ENTER SCM
YES
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Freescale Semiconductor 257
8.4.1.5 Computer Operating Properly Watchdog (COP)
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. When the COP is being used, software is responsible for keeping the COP from
timing out. If the COP times out it is an indication that the software is no longer being executed in the
intended sequence; thus a system reset is initiated (see Section 8.4.1.5, “Computer Operating Properly
Watchdog (COP)”). The COP runs with a gated OSCCLK. Three control bits in the COPCTL register
allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this order) to the ARMCOP register
during the selected time-out period. Once this is done, the COP time-out period is restarted. If the
program fails to do this and the COP times out, the part will reset. Also, if any value other than $55 or $AA
is written, the part is immediately reset.
Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to
the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period.
A premature write will immediately reset the part.
If PCE bit is set, the COP will continue to run in Pseudo Stop Mode.
8.4.1.6 Real Time Interrupt (RTI)
The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting
RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated
OSCCLK. At the end of the RTI time-out period the RTIF flag is set to one and a new RTI time-out period
starts immediately.
A write to the RTICTL register restarts the RTI time-out period.
If the PRE bit is set, the RTI will continue to run in Pseudo Stop Mode.
8.4.2 Operation Modes
8.4.2.1 Normal Mode
The S12XECRG block behaves as described within this specification in all normal modes.
8.4.2.2 Self Clock Mode
If the external clock frequency is not available due to a failure or due to long crystal start-up time, the Bus
Clock and the Core Clock are derived from the PLLCLK running at self clock mode frequency fSCM; this
mode of operation is called Self Clock Mode. This requires CME = 1 and SCME = 1, which is the default
after reset. If the MCU was clocked by the PLLCLK prior to entering Self Clock Mode, the PLLSEL bit will
be cleared. If the external clock signal has stabilized again, the S12XECRG will automatically select
OSCCLK to be the system clock and return to normal mode. See Section 8.4.1.4, “Clock Quality Checker”
for more information on entering and leaving Self Clock Mode.
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258 Freescale Semiconductor
NOTE
In order to detect a potential clock loss the CME bit should always be
enabled (CME = 1).
If CME bit is disabled and the MCU is configured to run on PLLCLK, a loss
of external clock (OSCCLK) will not be detected and will cause the system
clock to drift towards lower frequencies. As soon as the external clock is
available again the system clock ramps up to its IPLL target frequency. If
the MCU is running on external clock any loss of clock will cause the
system to go static.
8.4.3 Low Power Options
This section summarizes the low power options available in the S12XECRG.
8.4.3.1 Run Mode
This is the default mode after reset.
The RTI can be stopped by setting the associated rate select bits to zero.
The COP can be stopped by setting the associated rate select bits to zero.
8.4.3.2 Wait Mode
The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of
the individual bits in the CLKSEL register. All individual Wait Mode configuration bits can be superposed.
This provides enhanced granularity in reducing the level of power consumption during Wait Mode.
Table 8-15 lists the individual configuration bits and the parts of the MCU that are affected in Wait Mode.
After executing the WAI instruction the core requests the S12XECRG to switch MCU into Wait Mode.
The S12XECRG then checks whether the PLLWAI bit is asserted. Depending on the configuration the
S12XECRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit and disables the
IPLL.
There are two ways to restart the MCU from Wait Mode:
1. Any reset
2. Any interrupt
Table 8-15. MCU Configuration During Wait Mode
PLLWAI RTIWAI COPWAI
IPLL Stopped — —
RTI — Stopped —
COP — — Stopped
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8.4.3.3 Stop Mode
All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE and PSTP bit. The
oscillator is disabled in STOP mode unless the PSTP bit is set. If the PRE or PCE bits are set, the RTI or
COP continues to run in Pseudo Stop Mode. In addition to disabling system and core clocks the
S12XECRG requests other functional units of the MCU (e.g. voltage-regulator) to enter their individual
power saving modes (if available).
If the PLLSEL bit is still set when entering Stop Mode, the S12XECRG will switch the system and core
clocks to OSCCLK by clearing the PLLSEL bit. Then the S12XECRG disables the IPLL, disables the core
clock and finally disables the remaining system clocks.
If Pseudo Stop Mode is entered from Self-Clock Mode the S12XECRG will continue to check the clock
quality until clock check is successful. In this case the IPLL and the voltage regulator (VREG) will remain
enabled. If Full Stop Mode (PSTP = 0) is entered from Self-Clock Mode the ongoing clock quality check
will be stopped. A complete timeout window check will be started when Stop Mode is left again.
There are two ways to restart the MCU from Stop Mode:
1. Any reset
2. Any interrupt
If the MCU is woken-up from Full Stop Mode by an interrupt and the fast wake-up feature is enabled
(FSTWKP=1 and SCME=1), the system will immediately (no clock quality check) resume operation in
Self-Clock Mode (see Section 8.4.1.4, “Clock Quality Checker”). The SCMIF flag will not be set for this
special case. The system will remain in Self-Clock Mode with oscillator disabled until FSTWKP bit is
cleared. The clearing of FSTWKP will start the oscillator and the clock quality check. If the clock quality
check is successful, the S12XECRG will switch all system clocks to oscillator clock. The SCMIF flag will be
set. See application examples in Figure 8-19 and Figure 8-20.
Because the IPLL has been powered-down during Stop Mode the PLLSEL bit is cleared and the MCU runs
on OSCCLK after leaving Stop-Mode. The software must manually set the PLLSEL bit again, in order to
switch system and core clocks to the PLLCLK.
NOTE
In Full Stop Mode or Self-Clock Mode caused by the fast wake-up feature
the clock monitor and the oscillator are disabled.
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual, Rev. 1.12
260 Freescale Semiconductor
Figure 8-19. Fast Wake-up from Full Stop Mode: Example 1
.
Figure 8-20. Fast Wake-up from Full Stop Mode: Example 2
8.5 Resets
All reset sources are listed in Table 8-16. Refer to MCU specification for related vector addresses and
priorities. Table 8-16. Reset Summary
Reset Source Local Enable
Power on Reset None
Low Voltage Reset None
External Reset None
Illegal Address Reset None
Clock Monitor Reset PLLCTL (CME=1, SCME=0)
Oscillator Clock
PLL Clock
Core Clock
Instruction STOP IRQ service
FSTWKP=1 IRQ service STOP STOP IRQ service
Oscillator Disabled
Power Saving
Self-Clock Mode
SCME=1
CPU resumes program execution immediately
Interrupt Interrupt Interrupt
Oscillator Clock
PLL Clock
Core Clock
Instruction
Clock Quality Check
STOP IRQ Service
FSTWKP=1 IRQ Interrupt FSTWKP=0 SCMIE=1
Osc StartupOscillator Disabled
CPU resumes program execution immediately
Self-Clock Mode
SCME=1
Frequent Uncritical
Instructions Frequent Critical
Instructions Possible
SCM Interrupt
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual Rev. 1.12
Freescale Semiconductor 261
8.5.1 Description of Reset Operation
The reset sequence is initiated by any of the following events:
• Low level is detected at the RESET pin (External Reset).
• Power on is detected.
• Low voltage is detected.
• Illegal Address Reset is detected (see S12XMMC Block Guide for details).
• COP watchdog times out.
• Clock monitor failure is detected and Self-Clock Mode was disabled (SCME=0).
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles (see
Figure 8-21). Since entry into reset is asynchronous it does not require a running SYSCLK. However, the
internal reset circuit of the S12XECRG cannot sequence out of current reset condition without a running
SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6 additional SYSCLK cycles
depending on the internal synchronization latency. After 128+n SYSCLK cycles the RESET pin is released.
The reset generator of the S12XECRG waits for additional 64 SYSCLK cycles and then samples the RESET
pin to determine the originating source. Table 8-17 shows which vector will be fetched.
NOTE
External circuitry connected to the RESET pin should be able to raise the
signal to a valid logic one within 64 SYSCLK cycles after the low drive is
released by the MCU. If this requirement is not adhered to the reset source
will always be recognized as “External Reset” even if the reset was initially
caused by an other reset source.
COP Watchdog Reset COPCTL (CR[2:0] nonzero)
Table 8-17. Reset Vector Selection
Sampled RESET Pin
(64 cycles after release) Clock Monitor
Reset Pending COP
Reset Pending Vector Fetch
1 0 0 POR / LVR /
Illegal Address Reset/
External Reset
1 1 X Clock Monitor Reset
1 0 1 COP Reset
0 X X POR / LVR /
Illegal Address Reset/ External Reset
with rise of RESET pin
Table 8-16. Reset Summary
Reset Source Local Enable
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual, Rev. 1.12
262 Freescale Semiconductor
The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long
reset sequence. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles
(External Reset), the internal reset remains asserted longer.
Figure 8-21. RESET Timing
8.5.1.1 Clock Monitor Reset
The S12XECRG generates a Clock Monitor Reset in case all of the following conditions are true:
• Clock monitor is enabled (CME = 1)
• Loss of clock is detected
• Self-Clock Mode is disabled (SCME = 0).
The reset event asynchronously forces the configuration registers to their default settings. In detail the
CME and the SCME are reset to logical ‘1’ (which changes the state of the SCME bit. As a consequence the
S12XECRG immediately enters Self Clock Mode and starts its internal reset sequence. In parallel the clock
quality check starts. As soon as clock quality check indicates a valid Oscillator Clock the S12XECRG
switches to OSCCLK and leaves Self Clock Mode. Since the clock quality checker is running in parallel to
the reset generator, the S12XECRG may leave Self Clock Mode while still completing the internal reset
sequence.
8.5.1.2 Computer Operating Properly Watchdog (COP) Reset
When COP is enabled, the S12XECRG expects sequential write of $55 and $AA (in this order) to the
ARMCOP register during the selected time-out period. Once this is done, the COP time-out period
restarts. If the program fails to do this the S12XECRG will generate a reset.
8.5.1.3 Power On Reset, Low Voltage Reset
The on-chip voltage regulator detects when VDD to the MCU has reached a certain level and asserts power
on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the
) ( ) (
)(
)
SYSCLK
128+n cycles 64 cycles
with nbeing
min 3 / max 6
cycles depending
on internal
synchronization
delay
ICRG drives RESET pin low
possibly
SYSCLK
not
running
possibly
RESET
driven low
externally
)(
(
RESET
RESET pin
released
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual Rev. 1.12
Freescale Semiconductor 263
S12XECRG performs a quality check on the incoming clock signal. As soon as clock quality check indicates
a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50 check windows
the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts using Self-Clock
Mode.
Figure 8-22 and Figure 8-23 show the power-up sequence for cases when the RESET pin is tied to VDD and
when the RESET pin is held low.
Figure 8-22. RESET Pin Tied to VDD (by a Pull-up Resistor)
Figure 8-23. RESET Pin Held Low Externally
8.6 Interrupts
The interrupts/reset vectors requested by the S12XECRG are listed in Table 8-18. Refer to MCU
specification for related vector addresses and priorities.
Table 8-18. S12XECRG Interrupt Vectors
Interrupt Source CCR
Mask Local Enable
Real time interrupt I bit CRGINT (RTIE)
LOCK interrupt I bit CRGINT (LOCKIE)
SCM interrupt I bit CRGINT (SCMIE)
RESET
Internal POR
128 SYSCLK
64 SYSCLK
Internal RESET
Clock Quality Check
(no Self-Clock Mode)
) (
) (
) (
Clock Quality Check
RESET
Internal POR
Internal RESET
128 SYSCLK
64 SYSCLK
(no Self Clock Mode)
) (
) (
) (
S12XE Clocks and Reset Generator (S12XECRGV1)
S12XS Family Reference Manual, Rev. 1.12
264 Freescale Semiconductor
8.6.1 Description of Interrupt Operation
8.6.1.1 Real Time Interrupt
The S12XECRG generates a real time interrupt when the selected interrupt time period elapses. RTI
interrupts are locally disabled by setting the RTIE bit to zero. The real time interrupt flag (RTIF) is set to1
when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit.
The RTI continues to run during Pseudo Stop Mode if the PRE bit is set to 1. This feature can be used for
periodic wakeup from Pseudo Stop if the RTI interrupt is enabled.
8.6.1.2 IPLL Lock Interrupt
The S12XECRG generates a IPLL Lock interrupt when the LOCK condition of the IPLL has changed,
either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting
the LOCKIE bit to zero. The IPLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has
changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
8.6.1.3 Self Clock Mode Interrupt
The S12XECRG generates a Self Clock Mode interrupt when the SCM condition of the system has
changed, either entered or exited Self Clock Mode. SCM conditions are caused by a failing clock quality
check after power on reset (POR) or low voltage reset (LVR) or recovery from Full Stop Mode (PSTP = 0)
or Clock Monitor failure. For details on the clock quality check refer to Section 8.4.1.4, “Clock Quality
Checker”. If the clock monitor is enabled (CME = 1) a loss of external clock will also cause a SCM
condition (SCME = 1).
SCM interrupts are locally disabled by setting the SCMIE bit to zero. The SCM interrupt flag (SCMIF) is
set to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 265
Chapter 9
Pierce Oscillator (S12XOSCLCPV2)
9.1 Introduction
The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source. The
module will be operated from the VDDPLL supply rail (1.8 V nominal) and require the minimum number
of external components. It is designed for optimal start-up margin with typical crystal oscillators.
9.1.1 Features
The XOSC will contain circuitry to dynamically control current gain in the output amplitude. This ensures
a signal with low harmonic distortion, low power and good noise immunity.
• High noise immunity due to input hysteresis
• Low RF emissions with peak-to-peak swing limited dynamically
• Transconductance (gm) sized for optimum start-up margin for typical oscillators
• Dynamic gain control eliminates the need for external current limiting resistor
• Integrated resistor eliminates the need for external bias resistor in loop controlled Pierce mode.
• Low power consumption:
— Operates from 1.8 V (nominal) supply
— Amplitude control limits power
• Clock monitor
9.1.2 Modes of Operation
Two modes of operation exist:
1. Loop controlled Pierce (LCP) oscillator
2. External square wave mode featuring also full swing Pierce (FSP) without internal bias resistor
The oscillator mode selection is described in the Device Overview section, subsection Oscillator
Configuration.
Table 9-1. Revision History
Revision
Number Revision
Date Sections
Affected Description of Changes
V01.05 19 Jul 2006 - All xclks info was removed
V02.00 04 Aug 2006 - Incremented revision to match the design system spec revision
Pierce Oscillator (S12XOSCLCPV2)
S12XS Family Reference Manual, Rev. 1.12
266 Freescale Semiconductor
9.1.3 Block Diagram
Figure 9-1 shows a block diagram of the XOSC.
Figure 9-1. XOSC Block Diagram
9.2 External Signal Description
This section lists and describes the signals that connect off chip
9.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins
Theses pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the XOSC circuitry. This
allows the supply voltage to the XOSC to use an independent bypass capacitor.
9.2.2 EXTAL and XTAL — Input and Output Pins
These pins provide the interface for either a crystal or a 1.8V CMOS compatible clock to control the
internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator
amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal system clock is derived
EXTAL XTAL
Gain Control
VDDPLL = 1.8 V
Rf
OSCCLK
Monitor_Failure
Clock
Monitor
Peak
Detector
Pierce Oscillator (S12XOSCLCPV2)
S12XS Family Reference Manual Rev. 1.12
Freescale Semiconductor 267
from the EXTAL input frequency. In full stop mode (PSTP = 0), the EXTAL pin is pulled down by an
internal resistor of typical 200 kΩ.
NOTE
Freescale recommends an evaluation of the application board and chosen
resonator or crystal by the resonator or crystal supplier.
Loop controlled circuit is not suited for overtone resonators and crystals.
Figure 9-2. Loop Controlled Pierce Oscillator Connections (LCP mode selected)
NOTE
Full swing Pierce circuit is not suited for overtone resonators and crystals
without a careful component selection.
Figure 9-3. Full Swing Pierce Oscillator Connections (FSP mode selected)
Figure 9-4. External Clock Connections (FSP mode selected)
MCU
EXTAL
XTAL
VSSPLL
Crystal or
Ceramic Resonator
C2
C1
* Rs can be zero (shorted) when use with higher frequency crystals.
Refer to manufacturer’s data.
MCU
EXTAL
XTAL RS*
RB
VSSPLL
Crystal or
Ceramic Resonator
C2
C1
MCU
EXTAL
XTAL Not Connected
CMOS Compatible
External Oscillator
(VDDPLL Level)
Pierce Oscillator (S12XOSCLCPV2)
S12XS Family Reference Manual, Rev. 1.12
268 Freescale Semiconductor
9.3 Memory Map and Register Definition
The CRG contains the registers and associated bits for controlling and monitoring the oscillator module.
9.4 Functional Description
The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal
level which is determined by the amount of hysteresis being used and the maximum oscillation range.
The oscillator block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is
intended to be connected to either a crystal or an external clock source. The XTAL pin is an output signal
that provides crystal circuit feedback.
A buffered EXTAL signal becomes the internal clock. To improve noise immunity, the oscillator is
powered by the VDDPLL and VSSPLL power supply pins.
9.4.1 Gain Control
In LCP mode a closed loop control system will be utilized whereby the amplifier is modulated to keep the
output waveform sinusoidal and to limit the oscillation amplitude. The output peak to peak voltage will be
kept above twice the maximum hysteresis level of the input buffer. Electrical specification details are
provided in the Electrical Characteristics appendix.
9.4.2 Clock Monitor
The clock monitor circuit is based on an internal RC time delay so that it can operate without any MCU
clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates failure
which asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock
monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function
is enabled/disabled by the CME control bit, described in the CRG block description chapter.
9.4.3 Wait Mode Operation
During wait mode, XOSC is not impacted.
9.4.4 Stop Mode Operation
XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled.
During pseudo-stop mode, XOSC is not impacted.
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 269
Chapter 10
Analog-to-Digital Converter (ADC12B16CV1)
Revision History
10.1 Introduction
The ADC12B16C is a 16-channel, 12-bit, multiplexed input successive approximation analog-to-digital
converter. Refer to device electrical specifications for ATD accuracy.
10.1.1 Features
• 8-, 10-, or 12-bit resolution.
• Conversion in Stop Mode using internally generated clock
• Automatic return to low power after conversion sequence
• Automatic compare with interrupt for higher than or less/equal than programmable value
• Programmable sample time.
• Left/right justified result data.
• External trigger control.
• Sequence complete interrupt.
• Analog input multiplexer for 16 analog input channels.
• Special conversions for VRH, VRL, (VRL+VRH)/2.
• 1-to-16 conversion sequence lengths.
• Continuous conversion mode.
• Multiple channel scans.
• Configurable external trigger functionality on any AD channel or any of four additional trigger
inputs. The four additional trigger inputs can be chip external or internal. Refer to device
specification for availability and connectivity.
Version
Number Revision
Date Effective
Date Author Description of Changes
V01.00 13 Oct. 2005 13 Oct. 2005 Initial version
V01.01 4 Mar. 2008 4 Mar. 2008 correchted reference that DJM bit is in ATDCTL3
Analog-to-Digital Converter (ADC12B16CV1)
S12XS Family Reference Manual, Rev. 1.12
270 Freescale Semiconductor
• Configurable location for channel wrap around (when converting multiple channels in a sequence).
Analog-to-Digital Converter (ADC12B16CV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 271
10.1.2 Modes of Operation
10.1.2.1 Conversion Modes
There is software programmable selection between performing single or continuous conversion on a
single channel or multiple channels.
10.1.2.2 MCU Operating Modes
• Stop Mode
—ICLKSTP=0 (in ATDCTL2 register)
Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted
restarts it after exiting stop mode. This has the same effect/consequences as starting a
conversion sequence with write to ATDCTL5. So after exiting from stop mode with a
previously aborted sequence all flags are cleared etc.
—ICLKSTP=1 (in ATDCTL2 register)
A/D conversion sequence seamless continues in Stop Mode based on the internally generated
clock ICLK as ATD clock. For conversions during transition from Run to Stop Mode or vice
versa the result is not written to the results register, no CCF flag is set and no compare is done.
When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is
required to switch back to bus clock based ATDCLK when leaving Stop Mode. Do not access
ATD registers during this time.
•Wait Mode
ADC12B16C behaves same in Run and Wait Mode. For reduced power consumption continuos
conversions should be aborted before entering Wait mode.
•Freeze Mode
In Freeze Mode the ADC12B16C will either continue or finish or stop converting according to the
FRZ1 and FRZ0 bits. This is useful for debugging and emulation.
Analog-to-Digital Converter (ADC12B16CV1)
S12XS Family Reference Manual, Rev. 1.12
272 Freescale Semiconductor
10.1.3 Block Diagram
Figure 10-1. ADC12B16C Block Diagram
VSSA
AN8
ATD_12B16C
Analog
MUX
Mode and
Successive
Approximation
Register (SAR)
Results
ATD 0
ATD 1
ATD 2
ATD 3
ATD 4
ATD 5
ATD 6
ATD 7
and DAC
Sample & Hold
VDDA
VRL
VRH
Sequence Complete
+
-
Comparator
Clock
Prescaler
Bus Clock
ATD Clock
ATD 8
ATD 9
ATD 10
ATD 11
ATD 12
ATD 13
ATD 14
ATD 15
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AN9
AN10
AN11
AN12
AN13
AN14
AN15
ETRIG0
(See device specifi-
cation for availability
ETRIG1
ETRIG2
ETRIG3
and connectivity)
Timing Control
ATDDIENATDCTL1
Trigger
Mux
Internal
Clock
Interrupt
Compare Interrupt
ICLK
Analog-to-Digital Converter (ADC12B16CV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 273
10.2 Signal Description
This section lists all inputs to the ADC12B16C block.
10.2.1 Detailed Signal Descriptions
10.2.1.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger
for the ATD conversion.
10.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0
These inputs can be configured to serve as an external trigger for the ATD conversion.
Refer to device specification for availability and connection of these inputs!
10.2.1.3 VRH, VRL
VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.
10.2.1.4 VDDA, VSSA
These pins are the power supplies for the analog circuitry of the ADC12B16C block.
10.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ADC12B16C.
10.3.1 Module Memory Map
Figure 10-2 gives an overview on all ADC12B16C registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Address Name Bit 7 6 5 4 3 2 1 Bit 0
0x0000 ATDCTL0 RReserved 000
WRAP3 WRAP2 WRAP1 WRAP0
W
0x0001 ATDCTL1 RETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
W
0x0002 ATDCTL2 R0 AFFC ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE
W
= Unimplemented or Reserved
Figure 10-2. ADC12B16C Register Summary (Sheet 1 of 3)
Analog-to-Digital Converter (ADC12B16CV1)
S12XS Family Reference Manual, Rev. 1.12
274 Freescale Semiconductor
0x0003 ATDCTL3 RDJM S8C S4C S2C S1C FIFO FRZ1 FRZ0
W
0x0004 ATDCTL4 RSMP2 SMP1 SMP0 PRS[4:0]
W
0x0005 ATDCTL5 R0 SC SCAN MULT CD CC CB CA
W
0x0006 ATDSTAT0 RSCF 0ETORF FIFOR CC3 CC2 CC1 CC0
W
0x0007 Unimple-
mented R0 000 0 0 0 0
W
0x0008 ATDCMPEH RCMPE[15:8]
W
0x0009 ATDCMPEL RCMPE[7:0]
W
0x000A ATDSTAT2H R CCF[15:8]
W
0x000B ATDSTAT2L R CCF[7:0]
W
0x000C ATDDIENH RIEN[15:8]
W
0x000D ATDDIENL RIEN[7:0]
W
0x000E ATDCMPHTH RCMPHT[15:8]
W
0x000F ATDCMPHTL RCMPHT[7:0]
W
0x0010 ATDDR0 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0012 ATDDR1 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0014 ATDDR2 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0016 ATDDR3 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0018 ATDDR4 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x001A ATDDR5 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x001C ATDDR6 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x001E ATDDR7 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0020 ATDDR8 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0022 ATDDR9 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
Address Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Figure 10-2. ADC12B16C Register Summary (Sheet 2 of 3)
Analog-to-Digital Converter (ADC12B16CV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 275
0x0024 ATDDR10 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0026 ATDDR11 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x0028 ATDDR12 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x002A ATDDR13 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x002C ATDDR14 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
0x002E ATDDR15 RSee Section 10.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 10.3.2.12.2, “Right Justified Result Data (DJM=1)”
W
Address Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Figure 10-2. ADC12B16C Register Summary (Sheet 3 of 3)
Analog-to-Digital Converter (ADC12B16CV1)
S12XS Family Reference Manual, Rev. 1.12
276 Freescale Semiconductor
10.3.2 Register Descriptions
This section describes in address order all the ADC12B16C registers and their individual bits.
10.3.2.1 ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
Module Base + 0x0000
76543210
RReserved 000
WRAP3 WRAP2 WRAP1 WRAP0
W
Reset 0 0 0 01111
= Unimplemented or Reserved
Figure 10-3. ATD Control Register 0 (ATDCTL0)
Table 10-1. ATDCTL0 Field Descriptions
Field Description
3-0
WRAP[3-0] Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-
channel conversions. The coding is summarized in Table 10-2.
Table 10-2. Multi-Channel Wrap Around Coding
WRAP3 WRAP2 WRAP1 WRAP0 Multiple Channel Conversions (MULT = 1)
Wraparound to AN0 after Converting
0000 Reserved1
0001 AN1
0010 AN2
0011 AN3
0100 AN4
0101 AN5
0110 AN6
0111 AN7
1000 AN8
1001 AN9
1010 AN10
1011 AN11
1100 AN12
1101 AN13
1110 AN14
1111 AN15
Analog-to-Digital Converter (ADC12B16CV1)
S12XS Family Reference Manual, Rev. 1.12
Freescale Semiconductor 277
10.3.2.2 ATD Control Register 1 (ATDCTL1)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
1If only AN0 should be converted use MULT=0.
Module Base + 0x0001
76543210
RETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
W
Reset 0 0 1 01111
Figure 10-4. ATD Control Register 1 (ATDCTL1)
Table 10-3. ATDCTL1 Field Descriptions
Field Description
7
ETRIGSEL External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-
0 inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
not effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in Table 10-5.
6–5
SRES[1:0] A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 10-4 for
coding.
4
SMP_DIS Discharge Before Sampling Bit
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
3–0
ETRIGCH[3:0] External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs
as source for the external trigger. The coding is summarized in Table 10-5.
Table 10-4. A/D Resolution Coding
SRES1 SRES0 A/D Resolution
0 0 8-bit data
0 1 10-bit data
1 0 12-bit data
1 1 Reserved
Analog-to-Digital Converter (ADC12B16CV1)
S12XS Family Reference Manual, Rev. 1.12
278 Freescale Semiconductor
10.3.2.3 ATD Control Register 2 (ATDCTL2)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Table 10-5. External Trigger Channel Select Coding
ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is
0 0 0 0 0 AN0
0 0 0 0 1 AN1
0 0 0 1 0 AN2
0 0 0 1 1 AN3
0 0 1 0 0 AN4
0 0 1 0 1 AN5
0 0 1 1 0 AN6
0 0 1 1 1 AN7
0 1 0 0 0 AN8
0 1 0 0 1 AN9
0 1 0 1 0 AN10
0 1 0 1 1 AN11
0 1 1 0 0 AN12
0 1 1 0 1 AN13
0 1 1 1 0 AN14
0 1 1 1 1 AN15
1 0 0 0 0 ETRIG01
1Only if ETRIG3-0 input option is available (see device specification), else ETRISEL is ignored, that means
external trigger source is still on one of the AD channels selected by ETRIGCH3-0
1 0 0 0 1 ETRIG11
1 0 0 1 0 ETRIG21
1 0 0 1 1 ETRIG31
1 0 1 X X Reserved
1 1 X X X Reserved
Module Base + 0x0002
76543210
R0 AFFC ICLKSTP ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE
W
Reset 0 0 0 00000
= Unimplemented or Reserved
Figure 10-5. ATD Control Register 2 (ATDCTL2)
