Preliminary v1.5.2 54SX Family FPGAs RadTolerant and HiRel Fe a t ur es * Up to 225 User I/Os Rad To ler ant 54S X Fam i ly * Up to 1,080 Dedicated Flip-Flops * Tested Total Ionizing Dose (TID) Survivability Level E asy L ogi c In teg ra ti on * Radiation Performance to 100Krads (Si) (ICC Standby Parametric) * Non-Volatile, User Programmable * Devices Available from Tested Pedigreed Lots * Highly Predictable Performance with 100% Automatic Place and Route * Up to 160 MHz On-Chip Performance * 100% Resource Utilization with 100% Pin Locking * Offered as Class B and E-Flow (Actel Space Level Flow) * Mixed Voltage Support--3.3V Operation with 5.0V Input Tolerance for Low Power Operation * QMl Certified Devices * JTAG Boundary Scan Testing in Compliance with IEEE Standard 1149.1 H iR el 5 4 S X F a m i ly * Fastest HiRel FPGA Family Available * Up to 240 MHz On-Chip Performance * Low Cost Prototyping Vehicle for RadTolerant Devices * Offered as Commercial or Military Temperature Tested and Class B * Cost Effective QML MIL-Temp Plastic Packaging Options * Standard Hermetic Packaging Offerings * QML Certified Devices * Secure Programming Technology Prevents Reverse Engineering and Design Theft * Permanently Programmed for Operation on Power-Up * Unique In-System Diagnostic and Debug Facility with Silicon Explorer * Supported by Actel's Designer Series and DeskTOP Series Development Systems with Automatic Timing Driven Place and Route * Predictable, Reliable, and Permanent Antifuse Technology Performance High D ens it y Dev ic es * 16,000 and 32,000 Available Logic Gates SX P r o du ct Pr of i l e Device RT54SX16 A54SX16 RT54SX32 A54SX32 Capacity System Gates Logic Gates 24,000 16,000 24,000 16,000 48,000 32,000 48,000 32,000 Logic Modules 1,452 1,452 2,880 2,880 Register Cells 528 528 1,080 1,080 Combinatorial Cells 924 924 1,800 1,800 User I/Os (Maximum) 177 176 224 225 JTAG Yes Yes Yes Yes 208, 256 208, 256 208, 256 208, 256 Packages (by pin count) CQFP S ep t e m b er 2 0 0 0 (c) 2000 Actel Corporation 1 G en er al D e sc r i p t i on Actel's SX family of FPGAs features a revolutionary sea-of-modules architecture that delivers next-generation device performance and integration levels not currently achieved by any other FPGA architecture. SX devices greatly simplify design time, enable dramatic reductions in design costs and power consumption, and speed time-to-market for performance-intensive applications. Actel's RadTolerant (RT) and HiRel versions of the SX Family of FPGAs offer all of these advantages for applications such as commercial and military satellites, deep space probes, and all types of military and high reliability equipment. The RT and HiRel versions are fully pin compatible allowing designs to migrate across different applications that may or may not have radiation requirements. Also, the HiRel devices can be used as a low cost prototyping tool for RT designs. The programmable architecture of these devices offer high performance, design flexibility, and fast and inexpensive prototyping--all without the expense of test vectors, NRE charges, long lead times, and schedule and cost penalties for design modifications that are required by ASIC devices. Fas t and Fl exi ble New Ar chi t ect ur e Actel's SX architecture features two types of logic modules, the combinatorial cell (C-cell) and the register cell (R-cell), each optimized for fast and efficient mapping of synthesized logic functions. Optimal use of the silicon is made by locating the routing and interconnect resources in the metal layers above the logic modules, enabling the entire floor of the device to be spanned with an uninterrupted grid of fine-grained, synthesis-friendly logic modules (or "sea-of-modules") which reduces the distance signals have to travel between logic modules. To minimize signal propagation delay, SX devices employ both local and general routing resources. The high-speed local routing resources (DirectConnect and FastConnect) enable very fast local signal propagation that is optimal for fast counters, state machines, and datapath logic. The general system of segmented routing tracks allows any logic module in the array to be connected to any other logic or I/O module. Within this system, propagation delay is minimized by limiting the number of antifuse interconnect elements to five (typically 90 percent of connections use only three antifuses). The unique local and general routing structure featured in SX devices gives fast and predictable performance, allows 100 percent pin-locking with full logic utilization, enables concurrent PCB development, reduces design time, and allows designers to achieve performance goals with a minimum of effort. 2 Further complementing the SX's flexible routing structure is a hard-wired, constantly-loaded clock network that has been tuned to provide fast clock propagation with minimal clock skew. Additionally, the high performance of the internal logic has eliminated the need to embed latches or flip-flops in the I/O cells to achieve fast clock-to-out or fast input set-up times. SX devices have easy-to-use I/O cells that do not require HDL instantiation, facilitating design re-use and reducing design and verification time. D evi ce Des cr ip ti on The RT54SX16 and A54SX16 devices have 16,000 available gates and up to 177 I/Os. The RT54SX32 and A54SX32 have 32,000 available gates and up to 225 I/Os. All of these devices support JTAG boundary scan testability. All of these devices are available in Ceramic Quad Flat Pack (CQFP) packaging, with 208-pin and 256-pin versions. The 256-pin version offers the user the highest I/O capability, while the 208-pin version offers pin compatibility with the commercial Plastic Quad Flat Pack (PQFP-208). This compatibility allows the user to prototype using the very low cost plastic package and then switch to the ceramic package for production. For more information on plastic packages, refer to the SX family FPGAs data sheet at: http://www.actel.com/docs/datasheets/A54SXDS.pdf The A54SX16 and A54SX32 are manufactured using a 0.35 technology at the Chartered Semiconductor facility in Singapore. These devices offer the highest speed performance available in FPGAs today. The RT54SX16 and RT54SX32 are manufactured using a 0.6 technology at the Matsushita (MEC) facility in Japan. These devices offer levels of radiation survivability far in excess of typical CMOS devices. R ad i a t i o n S ur vi v ab i l i t y Total dose results are summarized in two ways. First by the maximum total dose level that is reached when the parts fail to meet a device specification but remain functional. For Actel FPGAs, the parameter that exceeds the specification first is ICC, the standby supply current. Second by the maximum total dose that is reached prior to the functional failure of the device. The RT SX devices have varying total dose radiation survivability. The ability of these devices to survive radiation effects is both device and lot dependent. The customer must evaluate and determine the applicability of these devices to their specific design and environmental requirements. 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l Actel will provide total dose radiation testing along with the test data on each pedigreed lot that is available for sale. These reports are available on our website or you can contact your local sales representative to receive a copy. A listing of available lots and devices will also be provided. These results are only provided for reference and for customer information. For a radiation performance summary, see Radiation Performance of Actel Products at http://www.actel.com/hirel. This summary will also show single event upset (SEU) and single event latch-up (SEL) testing that has been performed on Actel FPGAs. Q M L C e rti f i c at i on Actel has achieved full QML certification, demonstrating that quality management, procedures, processes, and controls are in place and comply with MIL-PRF-38535, the performance specification used by the Department of Defense for monolithic integrated circuits. QML certification is a good example of Actel's commitment to supplying the highest quality products for all types of high-reliability, military and space applications. Many suppliers of microelectronics components have implemented QML as their primary worldwide business system. Appropriate use of this system not only helps in the implementation of advanced technologies, but also allows for a quality, reliable and cost-effective logistics support throughout QML products' life cycles. D i sc l ai m e r All radiation performance information is provided for information purposes only and is not guaranteed. The total dose effects are lot-dependent, and Actel does not guarantee that future devices will continue to exhibit similar radiation characteristics. In addition, actual performance can vary widely due to a variety of factors, including but not limited to, characteristics of the orbit, radiation environment, proximity to satellite exterior, amount of inherent shielding from other sources within the satellite and actual bare die variations. For these reasons, Actel does not guarantee any level of radiation survivability, and it is solely the responsibility of the customer to determine whether the device will meet the requirements of the specific design. D ev el o pm en t T oo l S up po r t The 54SX RadTolerant and RadHard devices are fully supported by Actel's line of FPGA development tools, including the Actel DeskTOP series and Designer Advantage tools. The Actel DeskTOP Series is an integrated design environment for PCs that includes design entry, simulation, synthesis, and place and route tools. Designer Advantage is Actel's suite of FPGA development point tools for PCs and Workstations that includes the ACTgen Macro Builder, Designer with DirectTime timing driven place and route and analysis tools, and device programming software. In addition, the 54SX RadTolerant and RadHard devices contain ActionProbe circuitry that provides built-in access to every node in a design, enabling 100-percent real-time observation and analysis of a device's internal logic nodes without design iteration. The probe circuitry is accessed by Silicon Explorer, an easy to use integrated verification and logic analysis tool that can sample data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer attaches to a PC's standard COM port, turning the PC into a fully functional 18 channel logic analyzer. Silicon Explorer allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to a few seconds. 3 O r d e r i n g I nf o r m a t i o n RT54SX32 - 1 CQ 256 B Application (Temperature Range) Blank = Commercial (0 to +70C) M = Military (-55 to +125C) B = MIL-STD-883 E = E-Flow (Actel Space Level Flow) Package Lead Count Package Type CQ = Ceramic Quad Flat Pack Speed Grade Blank = Standard Speed -1 = Approximately 15% Faster than Standard Part Number A54SX16 A54SX32 RT54SX16 RT54SX32 = = = = 16,000 Gates 32,000 Gates 16,000 Gates--RadTolerant 32,000 Gates--Rad Tolerant Pr od uc t P l a n Speed Grade Application Std -1* C M B E 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) 208-Pin Ceramic Quad Flat Pack (CQFP) -- 256-Pin Ceramic Quad Flat Pack (CQFP) -- 208-Pin Ceramic Quad Flat Pack (CQFP) 256-Pin Ceramic Quad Flat Pack (CQFP) 208-Pin Ceramic Quad Flat Pack (CQFP) -- 256-Pin Ceramic Quad Flat Pack (CQFP) -- RT54SX16 Devices A54SX16 Devices RT54SX32 Devices A54SX32 Devices Contact your Actel sales representative for product availability. Applications: C = Commercial Availability: = Available M = Military P = Planned B = MIL-STD-883 -- = Not Planned E = E-flow (Actel Space Level Flow) 4 * Speed Grade: -1 = Approx. 15% Faster than Standard 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l C er a m i c De v i ce R es ou r c es Table 1 * JTAG Pin Functionality User I/Os Device Program Fuse Blown (Dedicated JTAG Mode) CQFP 208-Pin CQFP 256-Pin RT54SX16 171 176 A54SX16 172 177 RT54SX32 170 224 A54SX32 171 225 Package Definitions: CQFP = Ceramic Quad Flat Pack (Contact your Actel sales representative for product availability.) JT A G All SX devices feature hard-wired IEEE 1149.1 JTAG Boundary Scan Test circuitry and offer superior diagnostic and testing capabilities by providing JTAG and probing capabilities. These functions are controlled through the special JTAG pins in conjunction with the program fuse. The functionality of each pin is described in Table 1. Figure 1 is a block diagram of the A54SX JTAG circuitry and Figure 2 on page 6 shows the RT54SX JTAG circuitry. TDI Program Fuse Not Blown (Flexible Mode) TCK, TDI, TDO are dedicated JTAG pins TCK, TDI, TDO are flexible and may be used as I/Os No need for pull-up resistor for TMS Use a pull-up resistor of 10 k on TMS In the dedicated JTAG mode, TCK, TDI, and TDO are dedicated JTAG pins and cannot be used as regular I/Os. In flexible mode, TMS should be set HIGH through a pull-up resistor of 10 k. TMS can be pulled LOW to initiate the JTAG sequence. In addition, RT54SX devices include a TRST pin which is used to reset the JTAG state machine in "test-logic-reset" mode. The program fuse determines whether the device is in dedicated or flexible mode. The default (fuse not blown) is flexible mode. Regardless of which mode is chosen, tying the TRST pin LOW will disable all JTAG functionality. Data Registers (DRs) 0 1 output stage TDO Instruction Register (IR) clocks and/or controls TMS TAP Controller TCK Power-up Reset Figure 1 * A54SX JTAG Circuitry 5 TDI Data Registers (DRs) 0 1 Instruction Register (IR) clocks and/or controls TMS TCK TRST external hard-wired pin Figure 2 * RT54SX JTAG Circuitry 6 TAP Controller output stage TDO 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l SX F am i l y A r c hi t ec t ur e The SX family architecture was designed to satisfy next-generation performance and integration requirements for production-volume designs in a broad range of applications. interconnect elements, which are embedded between the M2 and M3 layers. The antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection. P rog ra m ma ble Int er con nect E l em ent The extremely small size of these interconnect elements gives the SX family abundant routing resources and provides excellent protection against design pirating. Reverse engineering is virtually impossible, because it is extremely difficult to distinguish between programmed and unprogrammed antifuses, and there is no configuration bitstream to intercept. Actel's SX family provides much more efficient use of silicon by locating the routing interconnect resources between the Metal 2 (M2) and Metal 3 (M3) layers (Figure 3). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on SRAM FPGAs and previous generations of antifuse FPGAs), and enables the entire floor of the device to be spanned with an uninterrupted grid of logic modules. Interconnection between these logic modules is achieved using Actel's patented metal-to-metal programmable antifuse Additionally, the interconnects (i.e., the antifuses and metal tracks) have lower capacitance and lower resistance than any other device of similar capacity, leading to the fastest signal propagation in the industry. Routing Tracks Metal 3 Amorphous Silicon/ Dielectric Antifuse Tungsten Plug Via Tungsten Plug Via Metal 2 Metal 1 Tungsten Plug Contact Silicon Substrate Figure 3 * SX Family Interconnect Elements 7 Logi c Modul e Des ign The SX family architecture has been called a "sea-of-modules" architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing (see Figure 4). Actel provides two types of logic modules, the register cell (R-cell) and the combinatorial cell (C-cell). The R-cell contains a flip-flop featuring more control signals than in previous Actel architectures, including asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines). The R-cell registers feature programmable clock polarity, selectable on a register-by-register basis (Figure 5 on page 9). This provides the designer with additional flexibility while allowing mapping of synthesized functions into the SX FPGA. The clock source for the R-cell can be chosen from the hard-wired clock or the routed clock. and its associated inverter function dramatically increases the number of combinatorial functions that can be implemented in a single module from 800 options in previous architectures to more than 4,000 in the SX architecture. An example of the improved flexibility enabled by the inversion capability is the ability to integrate a 3-input exclusive-OR function into a single C-cell. This facilitates construction of 9-bit parity-tree functions with 2 ns propagation delays. At the same time, the C-cell structure is extremely synthesis-friendly, simplifying the overall design and reducing synthesis time. C hip Ar ch it ect ur e The SX family's chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications. The C-cell implements a range of combinatorial functions up to 5-inputs (Figure 6 on page 9). Inclusion of the DB input Channelled Array Architecture Sea-of-Modules Architecture Figure 4 * Channelled Array and Sea-of-Modules Architectures 8 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l S0 Routed Data Input S1 PSETB Direct Connect Input D Q Y HCLK CLKA, CLKB CLRB CKS CKP Figure 5 * R-Cell D0 D1 Y D2 D3 Sa Sb DB A0 B0 A1 B1 Figure 6 * C-Cell Modu le Or gani zat ion Actel has arranged all C-cell and R-cell logic modules into horizontal banks called Clusters. There are two types of Clusters: Type 1 contains two C-cells and one R-cell, while Type 2 contains one C-cell and two R-cells. To increase design efficiency and device performance, Actel has further organized these modules into SuperClusters (see Figure 7 on page 10). SuperCluster 1 is a two-wide grouping of Type 1 clusters. SuperCluster 2 is a two-wide group containing one Type 1 cluster and one Type 2 cluster. SX devices feature more SuperCluster 1 modules than SuperCluster 2 modules because designers typically require more combinatorial logic than flip-flops. Ro uti ng Res our ce s Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect that enable extremely fast and predictable interconnections of modules within Clusters and SuperClusters (see Figure 8 and Figure 9 on page 11). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance. 9 R-Cell S0 C-Cell D0 Routed Data Input S1 D1 PSETB Y D2 Direct Connect Input D Q Y D3 Sa Sb HCLK CLKA, CLKB CLRB DB CKS CKP Cluster 1 A0 Cluster 2 Type 1 SuperCluster Cluster 2 B0 A1 B1 Cluster 1 Type 2 SuperCluster Figure 7 * Cluster Organization DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-cell in a given SuperCluster. DirectConnect uses a hard-wired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns. variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100% automatic place and route software to minimize signal propagation delays. FastConnect enables horizontal routing between any two logic modules within a given SuperCluster, and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering maximum pin-to-pin propagation of 0.4 ns. Actel's high-drive routing structure provides three clock networks. The first clock, called HCLK, is hard-wired from the HCLK buffer to the clock select MUX in each R-cell. This provides a fast propagation path for the clock signal. The hard-wired clock is tuned to provide clock skew as low as 0.25 ns. The remaining two clocks (CLKA, CLKB) are global clocks that can be sourced from external pins or from internal signal logic within the SX device. In addition to DirectConnect and FastConnect, the architecture makes use of two globally-oriented routing resources known as segmented routing and high-drive routing. Actel's segmented routing structure provides a 10 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l DirectConnect * No antifuses FastConnect * One antifuse Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 1 SuperClusters Figure 8 * DirectConnect and FastConnect for Type 1 SuperClusters DirectConnect * No antifuses FastConnect * One antifuse Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 2 SuperClusters Figure 9 * DirectConnect and FastConnect for Type 2 SuperClusters 11 3. 3 V / 5V O p era t i n g C o nd i t i o ns A bs ol u t e M ax i m u m Ra t i n gs 1 Symbol Parameter VCCR R ec o m m en d ed O pe r a t i ng C on d i t i o ns Limits Units DC Supply Voltage -0.3 to +6.0 V VCCA DC Supply Voltage -0.3 to +4.0 V VCCI DC Supply Voltage -0.3 to +4.0 V VI Input Voltage -0.5 to +5.5 V VO Output Voltage -0.5 to +3.6 V -30 to +5.0 mA -40 to +125 C IIO TSTG I/O Source Sink Current 2 Storage Temperature Parameter Commercial Military Units 0 to +70 -55 to +125 C 3.3V Power2 Supply Tolerance 10 10 %VCC 5V Power Supply 2 Tolerance 5 10 %VCC Temperature Range1 Notes: 1. Stresses beyond those listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. The I/O source sink numbers refer to tristated inputs and outputs Note: 1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. 2. All power supplies must be in the recommended operating range for 250s. For more information, please refer to the Power-Up Design Considerations application note at http://www.actel.com/appnotes. El e c t r i c al S p ec i f i c at i o n s Commercial Symbol Parameter VOH (IOH = -8mA) (TTL) (IOH = -20A) (CMOS) Min. Max. Min. Max. (VCCI - 0.1) VCCI (VCCI - 0.1) VCCI 2.4 VCCI (IOH = -6mA) (TTL) VOL Military V 2.4 (IOL= 20A) (CMOS) 0.10 (IOL = 12mA) (TTL) 0.50 Units VCCI V (IOL = 8mA) (TTL) 0.50 VIL Low Level Inputs VIH High Level Inputs tR, tF Input Transition Time tR, tF 50 50 ns CIO CIO I/O Capacitance 10 10 pF ICC Standby Current, ICC 4.0 25 mA ICC(D) ICC(D) IDynamic VCC Supply Current 12 0.8 2.0 0.8 2.0 V V See the "Power Dissipation" section on page 14. 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l Po w e r- U p S e qu en ci ng RT 54S X 16, A 54S X16 , RT 54S X 32, A5 4S X32 VCCA 3.3V VCCR 5.0V VCCI 3.3V Power-Up Sequence Comments 5.0V First 3.3V Second No possible damage to device. 3.3V First 5.0V Second Possible damage to device. Po w e r - D ow n Se q ue nc i n g RT54SX16, A54SX16, RT54SX32, A54SX32 VCCA 3.3V VCCR 5.0V VCCI 3.3V Power-Down Sequence Comments 5.0V First 3.3V Second Possible damage to device. 3.3V First 5.0V Second No possible damage to device. Pa c ka ge T he r m a l C ha r a ct e r i s t i c s The device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. Maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for an RT54SX16 in a CQFP 256-pin package at military temperature and still air is as follows: Max. junction temp. (C) - Max. ambient temp. (C) 150C - 125C Absolute Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------ = ------------------------------------ = 1.09W ja (C/W) 23C/W ja Pin Count jc Still Air Units Ceramic Quad Flat Pack (CQFP) 208 7.5 29 C/W Ceramic Quad Flat Pack (CQFP) 256 4.6 23 C/W Ceramic Quad Flat Pack (CQFP) 208 6.9 35 C/W Ceramic Quad Flat Pack (CQFP) 256 3.5 20 C/W Ceramic Quad Flat Pack (CQFP) 208 7.9 30 C/W Ceramic Quad Flat Pack (CQFP) 256 5.6 25 C/W Ceramic Quad Flat Pack (CQFP) 208 7.6 30 C/W Ceramic Quad Flat Pack (CQFP) 256 4.8 24 C/W Package Type RT54SX16 RT54SX32 A54SX16 A54SX32 13 Po w e r D i ss i pa t i o n P = [ICCstandby + ICCactive] * VCCA + IOL * VOL * N + IOH *(VCCA - VOH) * M where: ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. the totempole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. E qui va len t Cap acit an ce The power dissipated by a CMOS circuit can be expressed by Equation 1: Power (W) = CEQ * VCCA2 * F (1) where: VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. Accurate values for N and M are difficult to determine because they depend on the design and on the system I/O. The power can be divided into two components: static and active. S tat i c P ow er Co m ponen t The power due to standby current is typically a small component of the overall power. Standby power is shown below for military, worst case conditions (70C). ICC VCC Power 20 mA 3.6V 72 mW CEQ = Equivalent capacitance in pF VCCA = Power supply in volts (V) F = Switching frequency in MHz Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCCA. Equivalent capacitance is frequency-independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. C E Q V alu es (pF) Act i ve P ower C om po nent Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency-dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piece-wise linear summation over all components. Power =VCCA2 * [(m * CEQM * fm)modules + (n * CEQI * fn)inputs+ (p * (CEQO + CL) * fp)outputs+ 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2+ (r2 * fq2)routed_Clk2 + (2) 0.5 * (s1 * CEQCD * fs1)dedicated_CLK] RT54SX16 A54SX16 RT54SX32 A54SX32 Equivalent Capacitance (pF) Modules CEQM 7.0 3.9 7.0 3.9 Input Buffers CEQI 2.0 1.0 2.0 1.0 Output Buffers CEQO 10.0 5.0 10.0 5.0 Routed Array Clock Buffer Loads CEQCR 0.4 0.2 0.6 0.3 Dedicated Clock Buffer Loads CEQCD 0.25 0.15 0.34 0.23 routed_Clk1 r1 120 60 210 107 routed_Clk2 r2 120 60 210 107 s1 528 528 1,080 1,080 Fixed Capacitance (pF) Fixed Clock Loads Clock Loads on Dedicated Array Clock 14 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l De ter m in ing Av er age S wi tc hing Fr equ ency where: To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: m = Number of logic modules switching at fm n = Number of input buffers switching at fn p = Number of output buffers switching at fp q1 = Number of clock loads on the first routed array clock q2 = Number of clock loads on the second routed array clock Logic Modules (m) = 80% of modules Inputs Switching (n) = # inputs/4 r1 = Fixed capacitance due to first routed array clock Outputs Switching (p) = # output/4 r2 = Fixed capacitance due to second routed array clock First Routed Array Clock Loads (q1) = 40% of sequential modules s1 = Fixed number of clock loads on the dedicated array clock = (528 for A54SX16) Second Routed Array Clock Loads (q2) = 40% of sequential modules CEQM = Equivalent capacitance of logic modules in pF Load Capacitance (CL) = 35 pF CEQI = Equivalent capacitance of input buffers in pF = F/10 CEQO = Equivalent capacitance of output buffers in pF Average Logic Module Switching Rate (fm) CEQCR = Equivalent capacitance of routed array clock in pF Average Input Switching Rate (fn) = F/5 Average Output Switching Rate (fp) = CEQCD = Equivalent capacitance of dedicated array clock in pF Average First Routed Array Clock Rate (fq1) = F/2 CL = Output lead capacitance in pF F/2 fm = Average logic module switching rate in MHz Average Second Routed Array Clock = Rate (fq2) fn = Average input buffer switching rate in MHz F fp = Average output buffer switching rate in MHz Average Dedicated Array Clock Rate = (fs1) fq1 = Average first routed array clock rate in MHz fq2 = Average second routed array clock rate in MHz F/10 15 Te m p er a t u r e an d Vo l t a ge D er at i n g Fa ct or s (Normalized to Worst-Case Commercial, T J = 70 C, V CCA = 3.0V) Junction Temperature (TJ) VCCA -40 0 25 70 85 125 3.0 0.78 0.87 0.89 1.00 1.04 1.16 3.3 0.73 0.82 0.83 0.93 0.97 1.08 3.6 0.69 0.77 0.78 0.87 0.92 1.02 54 S X T i m i n g M o d el * Input Delays I/O Module tINY = 2.2 ns Internal Delays Predicted Routing Delays Combinatorial Cell Output Delays I/O Module tIRD2 = 1.2 ns tDHL = 2.8 ns tPD =0.9 ns tRD1 = 0.7 ns tRD4 = 2.2 ns tRD8 = 4.3 ns I/O Module tDHL = 2.8 ns Register Cell D Q Register Cell tRD1 = 0.7 ns D Q tRD1 = 0.7 ns tENZH = 2.8 ns tSUD = 0.8 ns tHD = 0.0 ns tRCO = 0.6 ns Routed Clock tRCO = 0.6 ns tRCKH = 2.8 ns (100% Load) FMAX = 175 MHz Hard-Wired Clock tHCKH = 1.3 ns FHMAX = 240 MHz *Values shown for A54SX16-1 at worst-case commercial conditions. H ar d-W i re d C loc k R out ed Cl ock External Set-Up = tINY + tIRD1 + tSUD - tHCKH External Set-Up = tINY + tIRD1 + tSUD - tRCKH = 2.2 + 0.7 + 0.8 - 1.7 = 2.0 ns Clock-to-Out (Pin-to-Pin) 16 = 2.2 + 0.7 + 0.8 - 2.4 = 1.3 ns Clock-to-Out (Pin-to-Pin) = tHCKH + tRCO + tRD1 + tDHL = tRCKH + tRCO + tRD1 + tDHL = 1.7 + 0.6 + 0.7 + 2.8 = 5.8 ns = 2.4 + 0.6 + 0.7 + 2.8 = 6.5 ns 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l O ut p u t B uf f e r D e l ay s E D VCC In 50% Out VOL PAD To AC test loads (shown below) TRIBUFF VCC GND 50% VOH En 1.5V 1.5V 50% VCC VCC 50% GND 1.5V Out En Out GND 10% VOL tDLH tENZL tDHL tENLZ GND 50% VOH 50% 90% 1.5V tENZH tENHZ A C T e st L oa d s Load 1 (Used to measure propagation delay) Load 2 (Used to measure rising/falling edges) VCC GND To the output under test 50 pF R to VCC for tPLZ/tPZL R to GND for tPHZ/tPZH R = 1 k To the output under test 50 pF I n pu t B uf f er D e l ay s PAD C - Ce l l D el a y s S A B Y INBUF Y VCC 3V In 0V 1.5V 1.5V VCC Out GND 50% 50% VCC Out GND 50% 50% 50% tINY S, A or B tPD GND 50% tPD VCC Out tINY 50% tPD GND 50% tPD 17 R eg i st e r C e l l Ti m i ng C ha r a ct e r i s t i c s Fli p- Flop s D PRESET CLK Q CLR (Positive edge triggered) tHD D tSUD CLK tHP tHPWH, tRPWH tRCO tHPWL, tRPWL Q tCLR tPRESET CLR tWASYN PRESET Ti m i ng C ha r a ct e r i s t i c s Lo ng T r ack s Timing characteristics for 54SX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all 54SX family members. Internal routing delays are device dependent. Design dependency means actual delays are not determined until after placement and routing of the user's design is complete. Delay values may then be determined by using the DirectTime Analyzer utility or performing simulation with post-layout delays. Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically up to 6% of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout (FO=24) routing delays in the data sheet specifications section. Cr it ic al Net s and T ypi cal Ne ts T im i ng Der at in g Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6 percent of the nets in a design may be designated as critical, while 90 percent of the nets in a design are typical. 54SX devices are manufactured in a CMOS process. Therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. 18 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l A 54 SX 1 6 T i m i n g C h ar ac t e r i st i cs (Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 C) C-Cell Propagation Delays1 `-1' Speed Parameter Description Min. tPD Internal Array Module Max. `Std' Speed Min. Max. Units 0.9 1.0 ns Predicted Routing Delays2 tDC FO=1 Routing Delay, Direct Connect 0.1 0.1 ns tFC FO=1 Routing Delay, Fast Connect 0.6 0.7 ns tRD1 FO=1 Routing Delay 0.7 0.8 ns tRD2 FO=2 Routing Delay 1.2 1.4 ns tRD3 FO=3 Routing Delay 1.7 2.0 ns tRD4 FO=4 Routing Delay 2.2 2.6 ns tRD8 FO=8 Routing Delay 4.3 5.0 ns tRD12 FO=12 Routing Delay 5.6 6.6 ns tRD18 FO=18 Routing Delay 9.4 11.0 ns tRD24 FO=24 Routing Delay 12.4 14.6 ns tRCO Sequential Clock-to-Q 0.6 0.8 ns tCLR Asynchronous Clear-to-Q 0.6 0.8 ns tSUD Flip-Flop Data Input Set-Up 0.8 0.9 ns tHD Flip-Flop Data Input Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 2.4 2.9 ns R-Cell Timing I/O Module Input Propagation Delays tINYH Input Data Pad-to-Y HIGH 2.2 2.6 ns tINYL Input Data Pad-to-Y LOW 2.2 2.6 ns 3 Predicted Input Routing Delays tIRD1 FO=1 Routing Delay 0.7 0.8 ns tIRD2 FO=2 Routing Delay 1.2 1.4 ns tIRD3 FO=3 Routing Delay 1.7 2.0 ns tIRD4 FO=4 Routing Delay 2.2 2.6 ns tIRD8 FO=8 Routing Delay 4.3 5.0 ns tIRD12 FO=12 Routing Delay 5.6 6.6 ns tIRD18 FO=18 Routing Delay 9.4 11.0 ns tIRD24 FO=24 Routing Delay 12.4 14.6 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 19 A 54 SX 1 6 T i m i n g C h ar ac t e r i st i cs (continued) (Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 C) I/O Module - TTL Output Timing1 Parameter Description tDLH Data-to-Pad LOW to HIGH tDHL `-1' Speed Min. Max. `Std' Speed Min. Max. Units 2.8 3.3 ns Data-to-Pad HIGH to LOW 2.8 3.3 ns tENZL Enable-to-Pad, Z to L 2.3 2.8 ns tENZH Enable-to-Pad, Z to H 2.8 3.3 ns tENLZ Enable-to-Pad, L to Z 4.5 5.2 ns tENHZ Enable-to-Pad, H to Z 2.2 2.6 ns dTLH Delta LOW to HIGH 0.05 0.06 ns/pF dTHL Delta HIGH to LOW 0.05 0.08 ns/pF Input LOW to HIGH (Pad to R-Cell Input) 1.7 2.0 ns Input HIGH to LOW (Pad to R-Cell Input) 1.9 2.2 ns Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH Minimum Pulse Width HIGH 2.1 2.4 ns tHPWL Minimum Pulse Width LOW 2.1 2.4 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.4 4.2 0.4 4.9 ns ns 240 205 MHz Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 2.4 2.9 ns Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 2.7 3.1 ns Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 2.9 3.3 ns Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 2.9 3.5 ns Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 2.8 3.3 ns Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 2.9 3.5 ns Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH Min. Pulse Width HIGH 3.1 3.7 ns tRPWL Min. Pulse Width LOW 3.1 3.7 ns tRCKSW Maximum Skew (Light Load) 0.6 0.8 ns tRCKSW Maximum Skew (50% Load) 0.8 0.9 ns tRCKSW Maximum Skew (100% Load) 0.8 0.9 ns Note: 1. Delays based on 35 pF loading, except for tENZL and tENZH . For tENZL and tENZH the loading is 5 pF. 20 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l R T5 4S X 16 T i m i ng C ha r a ct er i s t i c s (Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 C) C-Cell Propagation Delays1 `-1' Speed Parameter Description Min. tPD Internal Array Module Max. `Std' Speed Min. Max. Units 1.7 1.8 ns Predicted Routing Delays2 tDC FO=1 Routing Delay, Direct Connect 0.2 0.2 ns tFC FO=1 Routing Delay, Fast Connect 1.1 1.3 ns tRD1 FO=1 Routing Delay 1.3 1.5 ns tRD2 FO=2 Routing Delay 2.2 2.6 ns tRD3 FO=3 Routing Delay 3.1 3.6 ns tRD4 FO=4 Routing Delay 4.0 4.7 ns tRD8 FO=8 Routing Delay 7.8 9.0 ns tRD12 FO=12 Routing Delay 10.1 11.9 ns tRD18 FO=18 Routing Delay 17.0 19.8 ns tRD24 FO=24 Routing Delay 22.4 26.3 ns tRCO Sequential Clock-to-Q 1.5 2.0 ns tCLR Asynchronous Clear-to-Q 1.5 2.0 ns tSUD Flip-Flop Data Input Set-Up 2.0 2.2 ns tHD Flip-Flop Data Input Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 4.4 5.3 ns R-Cell Timing I/O Module Input Propagation Delays tINYH Input Data Pad-to-Y HIGH 4.0 4.7 ns tINYL Input Data Pad-to-Y LOW 4.0 4.7 ns 3 Predicted Input Routing Delays tIRD1 FO=1 Routing Delay 1.3 1.5 ns tIRD2 FO=2 Routing Delay 2.2 2.6 ns tIRD3 FO=3 Routing Delay 3.1 3.6 ns tIRD4 FO=4 Routing Delay 4.0 4.7 ns tIRD8 FO=8 Routing Delay 7.8 9.0 ns tIRD12 FO=12 Routing Delay 10.1 11.9 ns tIRD18 FO=18 Routing Delay 17.0 19.8 ns tIRD24 FO=24 Routing Delay 22.4 26.3 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 21 R T5 4S X 16 T i m i ng C ha r a ct er i s t i c s (continued) (Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 C) I/O Module - TTL Output Timing1 Parameter Description tDLH Data-to-Pad LOW to HIGH tDHL `-1' Speed Min. Max. `Std' Speed Min. Max. Units 5.1 6.0 ns Data-to-Pad HIGH to LOW 5.1 6.0 ns tENZL Enable-to-Pad, Z to L 4.2 5.1 ns tENZH Enable-to-Pad, Z to H 5.1 6.0 ns tENLZ Enable-to-Pad, L to Z 8.1 9.4 ns tENHZ Enable-to-Pad, H to Z 4.0 4.7 ns dTLH Delta LOW to HIGH 0.09 0.11 ns/pF dTHL Delta HIGH to LOW 0.09 0.15 ns/pF Input LOW to HIGH (Pad to R-Cell Input) 3.1 3.6 ns Input HIGH to LOW (Pad to R-Cell Input) 3.5 4.0 ns Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH Minimum Pulse Width HIGH 3.8 4.4 ns tHPWL Minimum Pulse Width LOW 3.8 4.4 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.8 7.6 0.8 8.9 ns ns 130 110 MHz Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 4.4 5.3 ns Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 4.9 5.6 ns Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 5.3 6.0 ns Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 5.3 6.3 ns Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 5.1 6.0 ns Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 5.3 6.3 ns Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH Min. Pulse Width HIGH 5.6 6.7 ns tRPWL Min. Pulse Width LOW 5.6 6.7 ns tRCKSW Maximum Skew (Light Load) 1.1 1.5 ns tRCKSW Maximum Skew (50% Load) 1.5 1.7 ns tRCKSW Maximum Skew (100% Load) 1.5 1.7 ns Note: 1. Delays based on 35 pF loading, except for tENZL and tENZH . For tENZL and tENZH the loading is 5 pF. 22 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l A 54 SX 3 2 T i m i n g C h ar ac t e r i st i cs (Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 C) C-Cell Propagation Delays1 `-1' Speed Parameter Description Min. tPD Internal Array Module Max. `Std' Speed Min. Max. Units 0.9 1.0 ns Predicted Routing Delays2 tDC FO=1 Routing Delay, Direct Connect 0.1 0.1 ns tFC FO=1 Routing Delay, Fast Connect 0.6 0.7 ns tRD1 FO=1 Routing Delay 0.7 0.8 ns tRD2 FO=2 Routing Delay 1.2 1.4 ns tRD3 FO=3 Routing Delay 1.7 2.0 ns tRD4 FO=4 Routing Delay 2.2 2.6 ns tRD8 FO=8 Routing Delay 4.3 5.0 ns tRD12 FO=12 Routing Delay 5.6 6.6 ns tRD18 FO=18 Routing Delay 9.4 11.0 ns tRD24 FO=24 Routing Delay 12.4 14.6 ns tRCO Sequential Clock-to-Q 0.6 0.8 ns tCLR Asynchronous Clear-to-Q 0.6 0.8 ns tSUD Flip-Flop Data Input Set-Up 0.8 0.9 ns tHD Flip-Flop Data Input Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 2.4 2.9 ns R-Cell Timing I/O Module Input Propagation Delays tINYH Input Data Pad-to-Y HIGH 2.2 2.6 ns tINYL Input Data Pad-to-Y LOW 2.2 2.6 ns 3 Predicted Input Routing Delays tIRD1 FO=1 Routing Delay 0.7 0.8 ns tIRD2 FO=2 Routing Delay 1.2 1.4 ns tIRD3 FO=3 Routing Delay 1.7 2.0 ns tIRD4 FO=4 Routing Delay 2.2 2.6 ns tIRD8 FO=8 Routing Delay 4.3 5.0 ns tIRD12 FO=12 Routing Delay 5.6 6.6 ns tIRD18 FO=18 Routing Delay 9.4 11.0 ns tIRD24 FO=24 Routing Delay 12.4 14.6 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 23 A 54 SX 3 2 T i m i n g C h ar ac t e r i st i cs (continued) (Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 C) I/O Module - TTL Output Timing1 Parameter Description tDLH Data-to-Pad LOW to HIGH tDHL `-1' Speed Min. Max. `Std' Speed Min. Max. Units 2.8 3.3 ns Data-to-Pad HIGH to LOW 2.8 3.3 ns tENZL Enable-to-Pad, Z to L 2.3 2.8 ns tENZH Enable-to-Pad, Z to H 2.8 3.3 ns tENLZ Enable-to-Pad, L to Z 4.5 5.2 ns tENHZ Enable-to-Pad, H to Z 2.2 2.6 ns dTLH Delta LOW to HIGH 0.05 0.06 ns/pF dTHL Delta HIGH to LOW 0.05 0.08 ns/pF Input LOW to HIGH (Pad to R-Cell Input) 1.7 2.0 ns Input HIGH to LOW (Pad to R-Cell Input) 1.9 2.2 ns Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH Minimum Pulse Width HIGH 2.1 2.4 ns tHPWL Minimum Pulse Width LOW 2.1 2.4 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.4 4.2 0.4 4.8 ns ns 240 205 MHz Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 2.4 2.9 ns Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 2.7 3.1 ns Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 2.9 3.3 ns Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 2.9 3.5 ns Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 2.8 3.3 ns Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 2.9 3.5 ns Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH Min. Pulse Width HIGH 3.1 3.7 ns tRPWL Min. Pulse Width LOW 3.1 3.7 ns tRCKSW Maximum Skew (Light Load) 0.6 0.8 ns tRCKSW Maximum Skew (50% Load) 0.8 0.9 ns tRCKSW Maximum Skew (100% Load) 0.8 0.9 ns Note: 1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF. 24 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l R T5 4S X 32 T i m i ng C ha r a ct er i s t i c s (Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 C) C-Cell Propagation Delays1 `-1' Speed Parameter Description Min. tPD Internal Array Module Max. `Std' Speed Min. Max. Units 1.7 1.8 ns Predicted Routing Delays2 tDC FO=1 Routing Delay, Direct Connect 0.2 0.2 ns tFC FO=1 Routing Delay, Fast Connect 1.1 1.3 ns tRD1 FO=1 Routing Delay 1.3 1.5 ns tRD2 FO=2 Routing Delay 2.2 2.6 ns tRD3 FO=3 Routing Delay 3.1 3.6 ns tRD4 FO=4 Routing Delay 4.0 4.7 ns tRD8 FO=8 Routing Delay 7.8 9.0 ns tRD12 FO=12 Routing Delay 10.1 11.9 ns tRD18 FO=18 Routing Delay 17.0 19.8 ns tRD24 FO=24 Routing Delay 22.4 26.3 ns tRCO Sequential Clock-to-Q 1.5 2.0 ns tCLR Asynchronous Clear-to-Q 1.5 2.0 ns tSUD Flip-Flop Data Input Set-Up 2.0 2.2 ns tHD Flip-Flop Data Input Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 4.4 5.3 ns R-Cell Timing I/O Module Input Propagation Delays tINYH Input Data Pad-to-Y HIGH 4.0 4.7 ns tINYL Input Data Pad-to-Y LOW 4.0 4.7 ns 3 Predicted Input Routing Delays tIRD1 FO=1 Routing Delay 1.3 1.5 ns tIRD2 FO=2 Routing Delay 2.2 2.6 ns tIRD3 FO=3 Routing Delay 3.1 3.6 ns tIRD4 FO=4 Routing Delay 4.0 4.7 ns tIRD8 FO=8 Routing Delay 7.8 9.0 ns tIRD12 FO=12 Routing Delay 10.1 11.9 ns tIRD18 FO=18 Routing Delay 17.0 19.8 ns tIRD24 FO=24 Routing Delay 22.4 26.3 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 25 R T5 4S X 32 T i m i ng C ha r a ct er i s t i c s (continued) (Worst-Case Military Conditions, V C CR = 4.75V, V CCA, V C CI = 3.0V, T J = 125 C) I/O Module - TTL Output Timing1 Parameter Description tDLH Data-to-Pad LOW to HIGH tDHL `-1' Speed Min. Max. `Std' Speed Min. Max. Units 5.1 6.0 ns Data-to-Pad HIGH to LOW 5.1 6.0 ns tENZL Enable-to-Pad, Z to L 4.2 5.1 ns tENZH Enable-to-Pad, Z to H 5.1 6.0 ns tENLZ Enable-to-Pad, L to Z 8.1 9.4 ns tENHZ Enable-to-Pad, H to Z 4.0 4.7 ns dTLH Delta LOW to HIGH 0.09 0.11 ns/pF dTHL Delta HIGH to LOW 0.09 0.15 ns/pF Input LOW to HIGH (Pad to R-Cell Input) 3.1 3.6 ns Input HIGH to LOW (Pad to R-Cell Input) 3.5 4.0 ns Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH Minimum Pulse Width HIGH 3.8 4.4 ns tHPWL Minimum Pulse Width LOW 3.8 4.4 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.8 7.6 0.8 8.9 ns ns 130 110 MHz Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 4.4 5.3 ns Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 4.9 5.6 ns Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 5.3 6.0 ns Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 5.3 6.3 ns Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 5.1 6.0 ns Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 5.3 6.3 ns Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH Min. Pulse Width HIGH 5.6 6.7 ns tRPWL Min. Pulse Width LOW 5.6 6.7 ns tRCKSW Maximum Skew (Light Load) 1.1 1.5 ns tRCKSW Maximum Skew (50% Load) 1.5 1.7 ns tRCKSW Maximum Skew (100% Load) 1.5 1.7 ns Note: 1. Delays based on 35 pF loading, except tENZL and tENZH . For tENZL and tENZH the loading is 5 pF. 26 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l Pi n D es c r i pt i on CLKA Clock A (Input) TTL clock input for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. CLKB Clock B (Input) TTL clock input for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. GND Ground LOW supply voltage. HCLK Dedicated (Hard-wired) Array Clock (Input) TTL clock input for sequential modules. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. I/O Input/Output (Input, Output) The I/O pin functions as an input, output, three-state, or bi-directional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are tri-stated by the Designer Series software. NC No Connection This pin is not connected to circuitry within the device. PRA ActionProbe A (Output) The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when verification has been completed. PRB ActionProbe B (Output) The Probe B pin is used to output data from any node within the device. This diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when verification has been completed. TCK TDI TDO Test Data Output (output) Serial output for JTAG. In flexible mode, TDO is active when the TMS pin is set LOW (Table 1 on page 5). This pin functions as an I/O when the JTAG state machine reaches the "logic reset" state. TMS Test Mode Select (Input) The TMS pin controls the use of JTAG pins (TCK, TDI, TDO). In flexible mode, when the TMS pin is set LOW, the TCK, TDI, and TDO pins are JTAG pins (Table 1 on page 5). Once the JTAG pins are in JTAG mode they will remain in JTAG mode until the internal JTAG state machine reaches the "logic reset" state. At this point the JTAG pins will be released and will function as regular I/O pins. The "logic reset" state is reached 5 TCK cycles after the TMS pin is set HIGH. In dedicated JTAG mode, TMS functions as specified in the IEEE 499.1 JTAG Specifications. JTAG operation is further described on page 5. TRST Test Reset Pin (Input) JTAG reset pin (active LOW). This pin is used to reset the JTAG state machine in "test-logic-reset" state to avoid accidental shifts into various JTAG operations due to the effects of heavy ions in a radiation environment. When this pin is tied LOW, the device is held in the "test-logic-reset" state and the JTAG functionality cannot be used. When this pin is tied HIGH, the JTAG function can operate. This pin should not be left floating. V CCI 3.3V Supply Voltage Supply voltage for I/Os. V CCA 3.3V Supply Voltage Supply voltage for Array. V CCR 5.0V Supply Voltage Supply voltage for input tolerance (required for internal biasing). Table 2 * Supply Voltages Test Clock (Input) Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active when the TMS pin is set LOW (Table 1 on page 5). This pin functions as an I/O when the JTAG state machine reaches the "logic reset" state. Test Data Input (Input) Serial input for JTAG and diagnostic probe. In flexible mode, TDI is active when the TMS pin is set LOW (Table 1 on page 5). This pin functions as an I/O when the JTAG state machine reaches the "logic reset" state. A54SX16 A54SX32 RTSX16 RTSX32 Maximum Maximum Input Output Tolerance Drive V C CA V CCI V C CR 3.3V 3.3V 5.0V 3.3V 3.3V 3.3V 3.3V 5.0V 5.0V 3.3V 27 Pa c ka ge P i n A s si g nm e n t s 208-Pin CQFP (Top View) 208 207 206 205 204 203 202 201 200 164 163 162 161 160 159 158 157 Pin #1 Index 1 156 2 155 3 154 4 153 5 152 6 151 7 150 8 149 208-Pin CQFP 44 113 45 112 46 111 47 110 48 109 49 108 50 107 51 106 52 105 53 54 55 56 57 58 59 60 61 28 97 98 99 100 101 102 103 104 54SX Family FPGAs RadTolerant and HiRel 208- P in CQF P Pin Number A54SX16 Function RT54SX16 Function A54SX32 Function 1 GND GND GND 2 TDI, I/O TDI, I/O TDI, I/O 3 I/O I/O I/O 4 I/O I/O I/O 5 I/O I/O I/O 6 I/O I/O I/O 7 I/O I/O I/O 8 I/O I/O I/O 9 I/O I/O I/O 10 I/O I/O I/O 11 TMS TMS TMS VCCI VCCI 12 VCCI 13 I/O I/O I/O 14 I/O I/O I/O 15 I/O I/O I/O 16 I/O I/O I/O 17 I/O I/O I/O 18 I/O I/O I/O 19 I/O I/O I/O 20 I/O I/O I/O 21 I/O I/O I/O 22 I/O I/O I/O 23 I/O I/O I/O 24 I/O I/O I/O VCCR VCCR 25 VCCR 26 GND GND GND 27 VCCA VCCA VCCA 28 GND GND GND 29 I/O I/O I/O 30 I/O TRST I/O 31 I/O I/O I/O 32 I/O I/O I/O 33 I/O I/O I/O 34 I/O I/O I/O 35 I/O I/O I/O 36 I/O I/O I/O 37 I/O I/O I/O 38 I/O I/O I/O 39 I/O I/O I/O VCCI VCCI 40 VCCI 41 VCCA VCCA VCCA 42 I/O I/O I/O 43 I/O I/O I/O 44 I/O I/O I/O 45 I/O I/O I/O 46 I/O I/O I/O 47 I/O I/O I/O 48 I/O I/O I/O 49 I/O I/O I/O 50 I/O I/O I/O 51 I/O I/O I/O 52 GND GND GND Notes: 1. Pin 30 in RT54SX16 and RT54SX32-CQ208 are TRST pins. 2. Pin 65 in A54SX32 and RT54SX32-CQ208 are No Connects. RT54SX32 Function Pin Number A54SX16 Function RT54SX16 Function A54SX32 Function RT54SX32 Function GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCR GND VCCA GND I/O TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCA GND VCCR I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCA GND VCCR I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCA GND VCCR I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCA GND VCCR I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O 29 208- P in CQF P (Co nti nue d) Pin Number A54SX16 Function RT54SX16 Function A54SX32 Function 105 GND GND GND 106 I/O I/O I/O 107 I/O I/O I/O 108 I/O I/O I/O 109 I/O I/O I/O 110 I/O I/O I/O 111 I/O I/O I/O 112 I/O I/O I/O 113 I/O I/O I/O VCCA VCCA 114 VCCA VCCI VCCI 115 VCCI 116 I/O I/O I/O 117 I/O I/O I/O 118 I/O I/O I/O 119 I/O I/O I/O 120 I/O I/O I/O 121 I/O I/O I/O 122 I/O I/O I/O 123 I/O I/O I/O 124 I/O I/O I/O 125 I/O I/O I/O 126 I/O I/O I/O 127 I/O I/O I/O 128 I/O I/O I/O 129 GND GND GND VCCA VCCA 130 VCCA 131 GND GND GND VCCR VCCR 132 VCCR 133 I/O I/O I/O 134 I/O I/O I/O 135 I/O I/O I/O 136 I/O I/O I/O 137 I/O I/O I/O 138 I/O I/O I/O 139 I/O I/O I/O 140 I/O I/O I/O 141 I/O I/O I/O 142 I/O I/O I/O 143 I/O I/O I/O 144 I/O I/O I/O VCCA VCCA 145 VCCA 146 GND GND GND 147 I/O I/O I/O VCCI VCCI 148 VCCI 149 I/O I/O I/O 150 I/O I/O I/O 151 I/O I/O I/O 152 I/O I/O I/O 153 I/O I/O I/O 154 I/O I/O I/O 155 I/O I/O I/O 156 I/O I/O I/O Notes: 1. Pin 30 in RT54SX16 and RT54SX32-CQ208 are TRST pins. 2. Pin 65 in A54SX32 and RT54SX32-CQ208 are No Connects. 30 RT54SX32 Function Pin Number A54SX16 Function RT54SX16 Function A54SX32 Function RT54SX32 Function GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND VCCR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCR GND VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCR GND VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCR GND VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCR GND VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l Pa c ka ge P i n A s si g nm e n t s (continued) 256- P in CQF P (T op Vie w) 256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193 Pin #1 Index 1 192 2 191 3 190 4 189 5 188 6 187 7 186 8 185 256-Pin CQFP 56 137 57 136 58 135 59 134 60 133 61 132 62 131 63 130 64 129 65 66 67 68 69 70 71 72 73 121 122 123 124 125 126 127 128 31 256-Pin CQFP Pin Number A54SX16 Function RT54SX16 Function A54SX32 Function RT54SX32 Function Pin Number A54SX16 Function RT54SX16 Function A54SX32 Function RT54SX32 Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS NC NC I/O I/O NC I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCA GND NC I/O I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O VCCA I/O NC I/O I/O NC I/O GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS NC NC I/O I/O NC I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCA GND NC I/O TRST I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O VCCA I/O NC I/O I/O NC I/O GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCA GND I/O I/O TRST I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 I/O NC I/O I/O NC I/O GND I/O NC I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCI GND VCCA I/O HCLK I/O NC I/O I/O I/O NC I/O I/O I/O NC I/O I/O NC I/O GND I/O NC I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCI GND VCCA I/O HCLK I/O NC I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCI GND VCCA I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCI GND VCCA I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O Note: 1. Pin 34 in RT54SX16 and RT54SX32-CQ256 are TRST pins. 32 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l 256-Pin CQFP (Continued) Pin Number A54SX16 Function RT54SX16 Function A54SX32 Function RT54SX32 Function Pin Number A54SX16 Function RT54SX16 Function A54SX32 Function RT54SX32 Function 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 I/O NC I/O I/O I/O GND I/O I/O I/O NC I/O I/O I/O NC I/O I/O I/O NC I/O I/O NC TDO, I/O NC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC I/O NC I/O I/O I/O GND I/O I/O I/O NC I/O I/O I/O NC I/O I/O I/O NC I/O I/O NC TDO, I/O NC GND I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC NC NC I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO, I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 GND VCCR GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O GND I/O NC NC I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O NC I/O I/O I/O NC I/O I/O GND VCCR GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O NC I/O I/O NC I/O I/O NC I/O I/O NC I/O GND I/O NC NC I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O NC I/O I/O I/O NC I/O I/O GND VCCR GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCR GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Note: 1. Pin 34 in RT54SX16 and RT54SX32-CQ256 are TRST pins. 33 256-Pin CQFP (Continued) Pin Number A54SX16 Function RT54SX16 Function A54SX32 Function RT54SX32 Function Pin Number A54SX16 Function RT54SX16 Function A54SX32 Function RT54SX32 Function 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCI GND VCCR GND PRA, I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCI GND VCCR GND PRA, I/O I/O NC I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCI GND VCCR GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCI GND VCCR GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 I/O I/O NC I/O I/O NC GND I/O I/O NC I/O I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O TCK, I/O I/O I/O NC I/O I/O NC GND I/O I/O NC I/O I/O I/O NC I/O I/O NC I/O I/O NC I/O I/O TCK, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O Note: 1. Pin 34 in RT54SX16 and RT54SX32-CQ256 are TRST pins. 34 5 4 S X F a m ily F P GA s R a d T o le r a n t a n d H iR e l Pa c ka ge M e ch an i c al D r a w i ng s 208- P in and 256 -P in CQF P (Ca vi ty Up ) Top View H D1 D2 No. 1 Ceramic Tie Bar L1 E2 E1 k F e b Side View A A1 Lid Heat Sink for CQ256 t C Lead Kovar Notes: 1. Outside lead frame holes (from dimension H) are circular. 2. Seal ring and lid are connected to Ground. 3. Lead material is Kovar with minimum 50 microinches gold plate over nickel. 4. Packages are shipped unformed with the ceramic tie bar. 5. CQ256 has a Heat Sink on the back. 35 Cer am i c Qu ad Flat Pa ck CQFP 208 CQFP 256 Dimension Min. Nom. Max. Min. Nom. Max. A 2.20 2.44 2.67 2.19 2.44 2.69 A1 2.05 2.29 2.52 2.04 2.29 2.50 b 0.18 0.20 0.22 0.18 0.20 0.22 c 0.10 0.15 0.20 0.10 0.15 0.18 D1/E1 28.96 29.21 29.46 35.64 36.00 36.36 D2/E2 25.50 BSC 31.50 BSC e 0.50 BSC 0.50 BSC F 6.86 7.75 8.64 7.67 7.75 H 70.00 BSC 70.00 BSC K 65.90 BSC 65.90 BSC L1 t 74.60 75.00 75.40 7.83 74.62 75.00 75.38 0.38 0.51 0.64 Notes: 1. All dimensions are in millimeters. 2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance. 36 54SX Family FPGAs RadTolerant and HiRel Li s t o f C ha ng e s The following table lists critical changes that were made in the current version of the document. Previous version Preliminary v1.5 Changes in current version (Preliminary v 1.5.1 (web-only)) Power up and down sequencing information was modified: damage to the device is possible when 3.3V is powered up first and when 5.0V is powered down first. Page 13 The last line of equation 2 was cut off in the previous version. It has been replaced in 14 the existing version. 37 38 54SX Family FPGAs RadTolerant and HiRel 39 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Europe Ltd. Daneshill House, Lutyens Close Basingstoke, Hampshire RG24 8AG United Kingdom Tel: +44-(0)125-630-5600 Fax: +44-(0)125-635-5420 Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81-(0)3-3445-7671 Fax: +81-90)3-3445-7668 5172141-7/10.00