Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPIC6B595 SLIS032B - JULY 1995 - REVISED JUNE 2015 TPIC6B595 Power Logic 8-Bit Shift Register 1 Features * * * 1 * * * Low rDS(on),5 (Typical) Avalanche Energy, 30 mJ Eight Power DMOS Transistor Outputs of 150-mA Continuous Current Output Clamp Voltage, 50 V Devices are Cascadable Low-Power Consumption 2 Applications * * * * The storage register transfers data to the output buffer when shift-register clear (SRCLR) is high. When SRCLR is low, the input shift register is cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices. Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sink-current capability. Each output provides a 500mA typical current limit at TC = 25C. The current limit decreases as the junction temperature increases for additional device protection. Instrumentation Clusters Tell-Tale Lamps LED Illumination and Controls Automotive Relay or Solenoids Drivers 3 Description The TPIC6B595 device is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium current or high-voltage loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The TPIC6B595 is characterized for operation over the operating case temperature range of -40C to 125C. Device Information(1) PART NUMBER TPIC6B595 PACKAGE BODY SIZE (NOM) SOIC (20) 12.80 mm x 7.50 mm PDIP (20) 24.33 mm x 6.35 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Symbol G RCK SRCLR SRCK SER IN 9 EN3 12 C2 8 R SRG8 13 C1 3 4 1D 2 5 6 DRAIN0 DRAIN1 DRAIN2 7 DRAIN3 14 DRAIN4 15 DRAIN5 16 DRAIN6 17 DRAIN7 2 18 SER OUT This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPIC6B595 SLIS032B - JULY 1995 - REVISED JUNE 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 4 4 4 5 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Parameter Measurement Information .................. 9 Detailed Description ............................................ 11 8.1 Overview ................................................................. 11 8.2 Functional Block Diagram ....................................... 11 8.3 Feature Description................................................. 12 8.4 Device Functional Modes........................................ 13 9 Application and Implementation ........................ 14 9.1 Application Information............................................ 14 9.2 Typical Application ................................................. 14 10 Power Supply Recommendations ..................... 16 11 Layout................................................................... 16 11.1 Layout Guidelines ................................................. 16 11.2 Layout Example .................................................... 17 12 Device and Documentation Support ................. 18 12.1 12.2 12.3 12.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 13 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History Changes from Revision A (May 2005) to Revision B * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 4 Changes from Original (July 1995) to Revision A * 2 Page Page Changed SRCLR timing diagram .......................................................................................................................................... 9 Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 TPIC6B595 www.ti.com SLIS032B - JULY 1995 - REVISED JUNE 2015 5 Pin Configuration and Functions DW or N Package 20-Pin SOIC or PDIP Top View NC VCC SER IN DRAIN0 DRAIN1 DRAIN2 DRAIN3 SRCLR G GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 NC GND SER OUT DRAIN7 DRAIN6 DRAIN5 DRAIN4 SRCK RCK GND NC - No internal connection Pin Functions PIN NAME NO. DRAIN0 4 DRAIN1 5 DRAIN2 6 DRAIN3 7 DRAIN4 14 DRAIN5 15 DRAIN6 16 DRAIN7 17 G GND NC I/O DESCRIPTION O Open-drain output Output enable, active-low 9 I 10, 11, 19 -- Power ground No internal connection 1, 20 -- RCK 12 I Register clock SERIN 3 I Serial data input SEROUT 18 O Serial data output SRCK 15 I Shift register clock SRCLR 8 I Shift register clear, active-low VCC 2 I Power supply Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 3 TPIC6B595 SLIS032B - JULY 1995 - REVISED JUNE 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Logic supply voltage (2) -0.3 7 V VI Logic input voltage -0.3 7 V VDS Power DMOS drain-to-source voltage (3) -0.3 50 V Continuous source-to-drain diode anode current 0 500 mA Pulsed source-to-drain diode anode current (4) 0 1 A ID Pulsed drain current, each output, all outputs ON, TC = 25C (4) 0 500 mA ID Continuous drain current, each output, all outputs ON, TC = 25C (4) 0 150 mA mA (4) IDM Peak drain current single output, TC = 25C 0 500 EAS Single-pulse avalanche energy (see Figure 11) 0 30 mJ IAS Avalanche current (5) 0 500 mA Continuous total dissipation See Thermal Information TJ Operating virtual junction temperature -40 150 C TC Operating case temperature -40 125 C Tstg Storage temperature -65 150 C (1) (2) (3) (4) (5) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to GND. Each power DMOS source is internally connected to GND. Pulse duration 100 s and duty cycle 2%. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25C, L = 1.5 H, IAS = 200 mA (see Figure 11). 6.2 ESD Ratings VALUE Human-body model (HBM), per AEC Q100-002 (1) V(ESD) (1) Electrostatic discharge Charged-device model (CDM), per AEC Q100-011 UNIT 2000 All pins 500 Corner pins (1, 10, 20, 11) 750 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VCC Logic supply voltage VIH High-level input voltage VIL Low-level input voltage 4.5 NOM MAX 5.5 0.85 VCC -500 V V 0.15 VCC Pulsed drain output current, TC = 25C, VCC = 5 V, all outputs on (1) (2) (see Figure 7) UNIT 500 V mA tsu Setup time, SER IN high before SRCKM (see Figure 9) 20 ns th Hold time, SER IN high after SRCKM , (see Figure 9) 20 ns tw Pulse duration (see Figure 9) 40 ns TC Operating case temperature -40 (1) (2) 4 125 C Pulse duration 100 s and duty cycle 2%. Technique should limit TJ - TC to 10C maximum. Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 TPIC6B595 www.ti.com SLIS032B - JULY 1995 - REVISED JUNE 2015 6.4 Thermal Information TPIC6B595 THERMAL METRIC (1) DW (SOIC) N (PDIP) 20 PINS 20 PINS UNIT RJA Junction-to-ambient thermal resistance 75.3 57 C/W RJC(top) Junction-to-case (top) thermal resistance 39.8 58.5 C/W RJB Junction-to-board thermal resistance 43.1 38 C/W JT Junction-to-top characterization parameter 15.4 25.2 C/W JB Junction-to-board characterization parameter 42.6 37.9 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX V(BR)DSX Drain-to-source breakdown voltage ID = 1 mA VSD Source-to-drain diode forward voltage IF = 100 mA VOH High-level output voltage, SER OUT IOH = -20 A, VCC = 4.5 V 4.4 4.49 IOH = -4 mA, VCC = 4.5 V 4 4.2 VOL Low-level output voltage, SER OUT IOL = 20 A, VCC = 4.5 V 0.005 0.1 IOL = 4 mA, VCC = 4.5 V 0.3 0.5 IIH High-level input current VCC = 5.5 V, VI = VCC IIL Low-level input current VCC = 5.5 V, VI = 0 50 V 0.85 1 A -1 A 20 100 All outputs ON 150 300 0.4 5 Logic supply current VCC = 5.5 V ICC(FRQ) Logic supply current at frequency fSRCK = 5 MHz, All outputs off, CL = 30 pF, See Figure 9 and Figure 2 IN Nominal current VDS(on) = 0.5 V, IN = ID, TC = 85C See (1) (2) (3) 90 VDS = 40 V, VCC = 5.5 V 0.1 5 IDSX OFF-state drain current VDS = 40 V TC = 125C VCC = 5.5 V 0.15 8 4.2 5.7 6.8 9.5 5.5 8 Static drain-source ON-state resistance ID = 100 mA, TC = 125C, VCC = 4.5 V See (1) and (2) and Figure 3 and Figure 4 ID = 350 mA, VCC = 4.5 V (1) (2) (3) V 1 ICC rDS(on) V V All outputs OFF ID = 100 mA, VCC = 4.5 V UNIT A mA mA A Technique should limit TJ - TC to 10C maximum. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V at TC = 85C. Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 5 TPIC6B595 SLIS032B - JULY 1995 - REVISED JUNE 2015 www.ti.com 6.6 Switching Characteristics VCC = 5 V, TC = 25C PARAMETER tPLH TEST CONDITIONS MIN Propagation delay time, low-to-high-level output from G TYP 150 MAX UNIT ns tr Propagation delay time, high-to-low-level output CL = 30 pF, ID = 100 mA, See Figure 5, from G Figure 8 and Figure 9 Rise time, drain output 200 ns tf Fall time, drain output 200 ns ta Reverse-recovery-current rise time 100 ns trr Reverse-recovery time tPHL (1) (2) 6 IF = 100 mA, di/dt = 10 A/s (1) See Figure 10 (2) , 90 ns 300 Technique should limit TJ - TC to 10C maximum. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 TPIC6B595 www.ti.com SLIS032B - JULY 1995 - REVISED JUNE 2015 6.7 Typical Characteristics 2.5 10 VCC = 5 V TC = - 40C to 125C 4 I CC - Supply Current - mA IAS - Peak Avalanche Current - A TC = 25C 2 1 0.4 2 1.5 1 0.5 0.2 0.1 0.1 0.2 0.4 1 2 4 0 0.1 10 1 tav - Time Duration of Avalanche - ms VCC = 5 V See Note A 16 14 TC = 125C 12 10 8 6 TC = 25C 4 TC = - 40C 2 0 0 100 500 200 300 400 ID - Drain Current - mA 600 700 Figure 3. Drain-to-Source On-State Resistance vs Drain Current ID = 100 mA See Note A 7 TC = 125C 6 5 TC = 25C 4 3 TC = - 40C 2 1 0 4 4.5 5 5.5 6 6.5 VCC - Logic Supply Voltage - V 7 Figure 4. Static Drain-to-Source On-State Resistance vs Logic Supply Voltage 0.45 tf tr 200 tPLH 150 tPHL 100 50 -50 I D - Maximum Continuous Drain Current of Each Output - A ID = 100 mA See Note A 250 Switching Time - ns 8 Technique should limit TJ - TC to 10C maximum. Technique should limit TJ - TC to 10C maximum. 300 Figure 2. Supply Current vs Frequency r DS(on) - Static Drain-to-Source On-State Resistance - r DS(on) - Drain-to-Source On-State Resistance - Figure 1. Peak Avalanche Current vs Time Duration of Avalanche 18 100 10 f - Frequency - MHz VCC = 5 V 0.4 0.35 0.3 0.25 TC = 25C 0.2 0.15 TC = 100C 0.1 TC = 125C 0.05 0 -25 0 25 50 75 100 TC - Case Temperature - C 1 125 2 3 4 5 6 7 8 N - Number of Outputs Conducting Simultaneously Technique should limit TJ - TC to 10C maximum Figure 5. Switching Time vs Case Temperature Figure 6. Maximum Continuous Drain Current of Each Output vs Number of Outputs Conducting Simultaneously Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 7 TPIC6B595 SLIS032B - JULY 1995 - REVISED JUNE 2015 www.ti.com I D - Maximum Peak Drain Current of Each Output - A Typical Characteristics (continued) 0.5 d = 10% 0.45 d = 20% 0.4 0.35 d = 50% 0.3 0.25 d = 80% 0.2 0.15 VCC = 5 V TC = 25C d = tw/tperiod = 1 ms/tperiod 0.1 0.05 0 1 2 3 4 5 6 7 8 N - Number of Outputs Conducting Simultaneously Figure 7. Maximum Peak Drain Current of Each Output vs Number of Outputs Conducting Simultaneously 8 Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 TPIC6B595 www.ti.com SLIS032B - JULY 1995 - REVISED JUNE 2015 7 Parameter Measurement Information 5V 24 V 7 2 8 13 Word Generator (see Note A) 3 12 SRCLR DUT DRAIN SER IN 4 3 2 1 0 5V 0V 4 -7, 14 -17 Output CL = 30 pF (see Note B) RCK 9 5 ID VCC G 5V G RL = 235 SRCK 6 SRCK 0V 5V SER IN 0V 5V RCK 0V 5V SRCLR 0V GND 10, 11, 19 24 V DRAIN1 0.5 V VOLTAGE WAVEFORMS TEST CIRCUIT A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 . B. CL includes probe and jig capacitance. Figure 8. Resistive-Load Test Circuit and Voltage Waveforms 5V G 5V 50% 50% 0V 24 V tPLH tPHL 2 8 13 Word Generator (see Note A) 3 12 9 V SRCLR CC SRCK ID 4 -7, 14 -17 DUT RL = 235 tr GND 5V 50% SRCK 0V tsu 10, 11, 19 TEST CIRCUIT 0.5 V tf SWITCHING TIMES CL = 30 pF (see Note B) RCK 10% 10% Output 24 V 90% 90% DRAIN SER IN G Output th 5V SER IN 50% 50% 0V tw INPUT SETUP AND HOLD WAVEFORMS A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 . B. CL includes probe and jig capacitance. Figure 9. Test Circuit, Switching Times, and Voltage Waveforms Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 9 TPIC6B595 SLIS032B - JULY 1995 - REVISED JUNE 2015 www.ti.com Parameter Measurement Information (continued) TP K DRAIN Circuit Under Test 0.1 A 2500 F 250 V di/dt = 20 A/s + 25 V L = 1 mH IF (see Note A) IF - 0 TP A 25% of IRM t2 t1 t3 Driver IRM RG VGG (see Note B) ta 50 trr TEST CIRCUIT CURRENT WAVEFORM A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. B. The VGG amplitude and RG are adjusted for di/dt = 20 A/s. A VGG double-pulse train is used to set IF = 0.1 A, where t1 = 10 s, t2 = 7 s, and t3 = 3 s. Figure 10. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode 5V 15 V tw 2 8 V SRCLR CC 10.5 Word Generator (see Note A) 3 12 9 DUT G See Note B 200 mH SER IN 4 -7, 14 -17 DRAIN RCK 5V Input ID 13 SRCK tav 0V IAS = 0.5 A ID VDS GND V(BR)DSX = 50 V MIN VDS 10, 11, 19 SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT VOLTAGE AND CURRENT WAVEFORMS A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, ZO = 50 . B. Input pulse duration, tw, is increased until peak current IAS = 0.5 mA. Energy test level is defined as EAS = IAS x V(BR)DSX x tav/2 = 30 mJ. Figure 11. Single-Pulse Avalanche Energy Test Circuit and Waveforms 10 Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 TPIC6B595 www.ti.com SLIS032B - JULY 1995 - REVISED JUNE 2015 8 Detailed Description 8.1 Overview The TPIC6B595 device is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection, so it can also drive relays, solenoids, and other medium-current or high-voltage loads. 8.2 Functional Block Diagram G RCK SRCLR 9 12 4 D SRCK 13 C1 D C2 CLR SER IN DRAIN0 8 5 3 D C1 D C2 CLR D C1 6 C1 7 C1 14 C1 15 C1 16 C1 DRAIN6 D C2 17 CLR D DRAIN5 D C2 CLR D DRAIN4 D C2 CLR D DRAIN3 D C2 CLR D DRAIN2 D C2 CLR D DRAIN1 DRAIN7 D C2 CLR 10, 11, 19 18 GND SER OUT Figure 12. Logic Diagram (Positive Logic) Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 11 TPIC6B595 SLIS032B - JULY 1995 - REVISED JUNE 2015 www.ti.com Functional Block Diagram (continued) EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 50 V Input 25 V 20 V 12 V GND GND Figure 13. Schematic of Inputs 8.3 Feature Description 8.3.1 Serial-In Interface This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register clear (SRCLR) is high. 8.3.2 Clear Register A logical low on (SRCLR) clears all registers in the device. TI suggests clearing the device during power up or initialization. 8.3.3 Output Control Holding the output enable (G) high holds all data in the output buffers low, and all drain outputs are off. Holding (G) low makes data from the storage register transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are OFF. When data is high, the DMOS transistor outputs have sink-current capability. This pin can also be used for global PWM dimming. 8.3.4 Cascaded Application The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices. Connect the device (SEROUT) pin to the next device (SERIN) for daisy Chain. This provides improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. 8.3.5 Current Limit Function Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sink current capability. Each output provides a 500-mA typical current limit at TC = 25C. The current limit decreases as the junction temperature increases for additional device protection. 12 Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 TPIC6B595 www.ti.com SLIS032B - JULY 1995 - REVISED JUNE 2015 8.4 Device Functional Modes 8.4.1 Operation With V(VCC) < 4.5 (Minimum V(VCC)) This device works normally during 4.5 V V(VCC) 5.5 V, when operation voltage is lower than 4.5 V. TI can't ensure the behavior of device, including communication interface and current capability. 8.4.2 Operating With 5.5 V < V(VCC) < 6 V This device works normally during this voltage range, but reliability issues may occur while the device works for a long time in this voltage range. Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 13 TPIC6B595 SLIS032B - JULY 1995 - REVISED JUNE 2015 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The TPIC6B595 device is a serial-in parallel-out, Power+LogicE 8-bit shift register with low-side switch DMOS outputs rating of a 150 mA per channel. The device is designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium currentor high-voltage loads. The following focuses on automotive cluster applications for the TPIC6B595 device. 9.2 Typical Application The typical application of the TPIC6B595 device is the automotive cluster driver. In this example, two TPIC6B595 power shift registers are cascaded and used to turn on LEDs in the cluster panel. In this case, the LED must be updated after all 16 bits of data have been loaded into the serial shift registers. MCU outputs the data to the serial input (SER IN) while clocking the shift register clock (SRCK). After the 16th clock, a pulse to the register clock (RCK) transfers the data to the storage registers. If output enable (G) is low, then the LEDs are turned ON corresponding to the status word with ones being ON and zeros OFF. With this simple scheme, MCU use SPI interface can turn on 16 LEDs using only two ICs as illustrated in Figure 14. Vbattery Vbattery 5V 5V R1 R2 R3 R4 R5 R6 R7 R8 0.1 uF 10 k R9 R9 R9 R9 R9 R9 R9 D9 D10 D11 D12 D13 D14 D15 D16 10 k VCC VCC TPIC6B595 TPIC6B595 DRAIN0 SRCK D1 D2 D3 D4 D5 D6 D7 DRAIN0 D8 DRAIN1 RCK MCU R9 0.1 uF DRQIN2 SRCK DRAIN1 RCK DRQIN2 SER IN DRAIN3 SER IN DRAIN3 SRCLR DRAIN4 SRCLR DRAIN4 G DRAIN5 G DRAIN5 DRAIN6 DRAIN6 DRAIN7 DRAIN7 SER OUT SER OUT GND TO SERIAL INPUT OF THE NEXT STAGE GND Figure 14. Typical Application Schematic 9.2.1 Design Requirements Use the design parameters in Table 1 for this design example. Table 1. Design Parameters 14 DESIGN PARAMETER EXAMPLE VALUE VSUPPLY 9-16 V V(D1), V(D2), V(D3), V(D4), V(D5), V(D6),V(D7), V(D8) 2V V(D9), V(D10),V(D11), V(D12), V(D13), V(D14),V(D15), V(D16) 3.3 V I(D1), I(D2), I(D3), I(D4), I(D5), I(D6),I(D7), I(D8) 20mA When Vbattery is 12 V I(D9), I(D10), I(D11), I(D12), I(D13), I(D14),I(D15), I(D16) 30mA When Vbattery is 12 V Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 TPIC6B595 www.ti.com SLIS032B - JULY 1995 - REVISED JUNE 2015 9.2.2 Detailed Design Procedure To * * * begin the design process, one must decide on a few parameters. The designer must know the following: Vsupply - LED supply is connect battery directly or fix voltage, this application connect the battery directly. V(Dx) - LED forward voltage I(Dx) - LED setting current when battery is 12 V. R1,R2,R3,R4,R5,R6,R7,R8 R1 R2 R3 R4 R5 R6 R7 R8 V supply V(Dx) 12V 2V I(Dx ) 0.02A 500 : (1) When Vsupply is 9 V, I(D1) I(D2 ) I(D3 ) I(D4 ) I(D5 ) I(D6 ) I(D7 ) I(D8 ) I(D4 ) I(D5 ) I(D6 ) I(D7 ) I(D8 ) V supply V(Dx) Rx 14mA (2) When Vsupply is 16 V, I(D1) I(D2 ) I(D3 ) V supply V(Dx) Rx 28mA (3) R9,R10,R11,R12,R13,R14,R15,R16 R9 R10 R11 R12 R13 R14 R15 R16 V supply V(Dx) 12V 3.3V I( Dx ) 0.03A 290 : (4) When Vsupply is 9 V, I(D9) I(D10 ) I(D11) I(D12 ) I(D13 ) I(D14 ) I(D15 ) I(D16 ) V supply V(Dx) Rx 19.7mA (5) When Vsupply is 16 V, I( D9 ) I( D10 ) I( D11) I(D12 ) I(D13 ) I( D14 ) I( D15 ) I( D16 ) V supply V(Dx) Rx 43.8mA (6) NOTE If customers can accept the current variation when battery voltage is changing, they can connect to the battery directly. If customers need the less variation of current, they must use the voltage regulator as supply voltage of LED, or change to constant current LED driver directly. 9.2.3 Application Curve Figure 15. CH1 is SRCK, CH2 is RCK, CH3 is SER IN, CH4 is D1 current Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 15 TPIC6B595 SLIS032B - JULY 1995 - REVISED JUNE 2015 www.ti.com 10 Power Supply Recommendations The TPIC6B595 device is designed to operate from an input voltage supply range from 4.5 V and 5.5 V. This input supply should be well regulated. TI recommends placing the ceramic bypass capacitors near the VCC pin. 11 Layout 11.1 Layout Guidelines There is no special layout requirement for the digital signal pin; the only requirement is placing the ceramic bypass capacitors near the corresponding pin. Because the TPIC6B595 device does not have a thermal shutdown protection function, to prevent thermal damage, TJ must be less than 150C. If the total sink current is high, the power dissipation might be large. The devices are currently not available in the thermal pad package, so good PCB design can optimize heat transfer, which is absolutely essential for the long-term reliability of the device. Maximize the copper coverage on the PCB to increase the thermal conductivity of the board, because the major heat-flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely important when the design does not include heat sinks attached to the PCB on the other side of the package. * Add as many thermal vias as possible directly under the package ground pad to optimize the thermal conductivity of the board. * All thermal vias should be either plated shut or plugged and capped on both sides of the board to prevent solder voids. To ensure reliability and performance, the solder coverage should be at least 85%. 16 Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 TPIC6B595 www.ti.com SLIS032B - JULY 1995 - REVISED JUNE 2015 11.2 Layout Example Power Ground both in TOP and Bottom NC NC TPIC6B595 Vcc GND VIA to Ground SER IN SER OUT DRAIN0 DRAIN7 DRAIN1 DRAIN6 DRAIN2 DRAIN5 DRAIN3 DRAIN4 SRCK SRCLR G RCK GND GND Figure 16. TPIC6B595 Layout Example Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 17 TPIC6B595 SLIS032B - JULY 1995 - REVISED JUNE 2015 www.ti.com 12 Device and Documentation Support 12.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright (c) 1995-2015, Texas Instruments Incorporated Product Folder Links: TPIC6B595 PACKAGE OPTION ADDENDUM www.ti.com 15-Sep-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) TPIC6B595DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPIC6B595DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPIC6B595DWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPIC6B595DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPIC6B595N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Op Temp (C) Device Marking (4/5) -40 to 125 TPIC6B595 TPIC6B595 -40 to 125 TPIC6B595 TPIC6B595 -40 to 125 TPIC6B595N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Sep-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPIC6B595DWR Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.3 2.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Sep-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPIC6B595DWR SOIC DW 20 2000 367.0 367.0 45.0 Pack Materials-Page 2 PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 TYP 9.97 SEATING PLANE PIN 1 ID AREA A 0.1 C 20 1 13.0 12.6 NOTE 3 18X 1.27 2X 11.43 10 11 B 7.6 7.4 NOTE 4 20X 0.51 0.31 0.25 C A B 2.65 MAX 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0 -8 0.3 0.1 1.27 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 11 10 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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