2
SRG8
9
12
8
13
3
EN3
C2
R
C1
1D
G
RCK
SRCLR
SRCK
SER IN
4
6
5
14
7
16
15
18
17
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT
2
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TPIC6B595
SLIS032B –JULY 1995–REVISED JUNE 2015
TPIC6B595 Power Logic 8-Bit Shift Register
The storage register transfers data to the output
1 Features buffer when shift-register clear (SRCLR) is high.
1• Low rDS(on),5 Ω(Typical) When SRCLR is low, the input shift register is
• Avalanche Energy, 30 mJ cleared. When output enable (G) is held high, all data
in the output buffers is held low and all drain outputs
• Eight Power DMOS Transistor Outputs of 150-mA are off. When G is held low, data from the storage
Continuous Current register is transparent to the output buffers. When
• Output Clamp Voltage, 50 V data in the output buffers is low, the DMOS-transistor
• Devices are Cascadable outputs are off. When data is high, the DMOS
transistor outputs have sink-current capability. The
• Low-Power Consumption serial output (SER OUT) allows for cascading of the
data from the shift register to additional devices.
2 Applications Outputs are low-side, open-drain DMOS transistors
• Instrumentation Clusters with output ratings of 50 V and 150-mA continuous
• Tell-Tale Lamps sink-current capability. Each output provides a 500-
• LED Illumination and Controls mA typical current limit at TC= 25°C. The current limit
decreases as the junction temperature increases for
• Automotive Relay or Solenoids Drivers additional device protection.
3 Description The TPIC6B595 is characterized for operation over
The TPIC6B595 device is a monolithic, high-voltage, the operating case temperature range of −40°C to
medium-current power 8-bit shift register designed for 125°C.
use in systems that require relatively high load power.
The device contains a built-in voltage clamp on the Device Information(1)
outputs for inductive transient protection. Power PART NUMBER PACKAGE BODY SIZE (NOM)
driver applications include relays, solenoids, and SOIC (20) 12.80 mm × 7.50 mm
other medium current or high-voltage loads. TPIC6B595 PDIP (20) 24.33 mm × 6.35 mm
This device contains an 8-bit serial-in, parallel-out (1) For all available packages, see the orderable addendum at
shift register that feeds an 8-bit D-type storage the end of the data sheet.
register. Data transfers through the shift and storage
registers on the rising edge of the shift-register clock
(SRCK) and the register clock (RCK), respectively.
Logic Symbol
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPIC6B595
SLIS032B –JULY 1995–REVISED JUNE 2015
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Table of Contents
8.2 Functional Block Diagram....................................... 11
1 Features.................................................................. 18.3 Feature Description................................................. 12
2 Applications ........................................................... 18.4 Device Functional Modes........................................ 13
3 Description............................................................. 19 Application and Implementation ........................ 14
4 Revision History..................................................... 29.1 Application Information............................................ 14
5 Pin Configuration and Functions......................... 39.2 Typical Application ................................................. 14
6 Specifications......................................................... 410 Power Supply Recommendations ..................... 16
6.1 Absolute Maximum Ratings ...................................... 411 Layout................................................................... 16
6.2 ESD Ratings ............................................................ 411.1 Layout Guidelines ................................................. 16
6.3 Recommended Operating Conditions....................... 411.2 Layout Example .................................................... 17
6.4 Thermal Information.................................................. 512 Device and Documentation Support................. 18
6.5 Electrical Characteristics........................................... 512.1 Community Resources.......................................... 18
6.6 Switching Characteristics.......................................... 612.2 Trademarks........................................................... 18
6.7 Typical Characteristics.............................................. 712.3 Electrostatic Discharge Caution............................ 18
7 Parameter Measurement Information .................. 912.4 Glossary................................................................ 18
8 Detailed Description............................................ 11 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................. 11 Information........................................................... 18
4 Revision History
Changes from Revision A (May 2005) to Revision B Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 4
Changes from Original (July 1995) to Revision A Page
• Changed SRCLR timing diagram .......................................................................................................................................... 9
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1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
VCC
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
SRCLR
G
GND
NC
GND
SER OUT
DRAIN7
DRAIN6
DRAIN5
DRAIN4
SRCK
RCK
GND
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SLIS032B –JULY 1995–REVISED JUNE 2015
5 Pin Configuration and Functions
DW or N Package
20-Pin SOIC or PDIP
Top View
NC – No internal connection
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
DRAIN0 4
DRAIN1 5
DRAIN2 6
DRAIN3 7 O Open-drain output
DRAIN4 14
DRAIN5 15
DRAIN6 16
DRAIN7 17
G 9 I Output enable, active-low
GND 10, 11, 19 — Power ground
NC 1, 20 — No internal connection
RCK 12 I Register clock
SERIN 3 I Serial data input
SEROUT 18 O Serial data output
SRCK 15 I Shift register clock
SRCLR 8 I Shift register clear, active-low
VCC 2 I Power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Logic supply voltage(2) –0.3 7 V
VILogic input voltage –0.3 7 V
VDS Power DMOS drain-to-source voltage(3) –0.3 50 V
Continuous source-to-drain diode anode current 0 500 mA
Pulsed source-to-drain diode anode current(4) 0 1 A
IDPulsed drain current, each output, all outputs ON, TC= 25°C(4) 0 500 mA
IDContinuous drain current, each output, all outputs ON, TC= 25°C(4) 0 150 mA
IDM Peak drain current single output, TC= 25°C(4) 0 500 mA
EAS Single-pulse avalanche energy (see Figure 11) 0 30 mJ
IAS Avalanche current(5) 0 500 mA
Continuous total dissipation See Thermal Information
TJOperating virtual junction temperature –40 150 °C
TCOperating case temperature –40 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
(3) Each power DMOS source is internally connected to GND.
(4) Pulse duration ≤100 μs and duty cycle ≤2%.
(5) DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 1.5 H, IAS = 200 mA (see Figure 11).
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1) ±2000
All pins ±500
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per AEC Corner pins (1, 10, 20,
Q100-011 ±750
11)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VCC Logic supply voltage 4.5 5.5 V
VIH High-level input voltage 0.85 VCC V
VIL Low-level input voltage 0.15 VCC V
Pulsed drain output current, TC= 25°C, VCC = 5 V, all outputs on(1)(2) (see –500 500 mA
Figure 7)
tsu Setup time, SER IN high before SRCKM↑(see Figure 9) 20 ns
thHold time, SER IN high after SRCKM↑, (see Figure 9) 20 ns
twPulse duration (see Figure 9) 40 ns
TCOperating case temperature –40 125 °C
(1) Pulse duration ≤100 μs and duty cycle ≤2%.
(2) Technique should limit TJ−TCto 10°C maximum.
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6.4 Thermal Information TPIC6B595
THERMAL METRIC(1) DW (SOIC) N (PDIP) UNIT
20 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance 75.3 57 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 39.8 58.5 °C/W
RθJB Junction-to-board thermal resistance 43.1 38 °C/W
ψJT Junction-to-top characterization parameter 15.4 25.2 °C/W
ψJB Junction-to-board characterization parameter 42.6 37.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Drain-to-source breakdown
V(BR)DSX ID= 1 mA 50 V
voltage
Source-to-drain diode forward
VSD IF= 100 mA 0.85 1 V
voltage IOH =−20 µA, VCC = 4.5 V 4.4 4.49
High-level output voltage, SER
VOH V
OUT IOH =−4 mA, VCC = 4.5 V 4 4.2
IOL = 20 µA, VCC = 4.5 V 0.005 0.1
Low-level output voltage, SER
VOL V
OUT IOL = 4 mA, VCC = 4.5 V 0.3 0.5
IIH High-level input current VCC = 5.5 V, VI= VCC 1 µA
IIL Low-level input current VCC = 5.5 V, VI= 0 –1 µA
All outputs OFF 20 100
ICC Logic supply current VCC = 5.5 V µA
All outputs ON 150 300
fSRCK = 5 MHz, CL= 30 pF,
Logic supply current at
ICC(FRQ) 0.4 5 mA
frequency All outputs off, See Figure 9 and Figure 2
VDS(on) = 0.5 V,
INNominal current IN= ID, See (1)(2)(3) 90 mA
TC= 85°C
VDS = 40 V, VCC = 5.5 V 0.1 5
IDSX OFF-state drain current µA
VDS = 40 V VCC = 5.5 V 0.15 8
TC= 125°C
ID= 100 mA, 4.2 5.7
VCC = 4.5 V
ID= 100 mA,
Static drain-source ON-state See (1) and(2) and Figure 3
rDS(on) TC= 125°C, 6.8 9.5 Ω
resistance and Figure 4
VCC = 4.5 V
ID= 350 mA, 5.5 8
VCC = 4.5 V
(1) Technique should limit TJ−TCto 10°C maximum.
(2) These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
(3) Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage
drop of 0.5 V at TC= 85°C.
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6.6 Switching Characteristics
VCC = 5 V, TC= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Propagation delay time, low-to-high-level output ns
tPLH 150
from G
Propagation delay time, high-to-low-level output ns
CL= 30 pF, ID= 100 mA, See Figure 5,
tPHL 90
from G Figure 8 and Figure 9
trRise time, drain output 200 ns
tfFall time, drain output 200 ns
taReverse-recovery-current rise time IF= 100 mA, di/dt = 10 A/µs(1) (2), 100 ns
See Figure 10
trr Reverse-recovery time 300
(1) Technique should limit TJ−TCto 10°C maximum.
(2) These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
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Switching Time − ns
−50
TC− Case Temperature − °C
ID= 100 mA
See Note A
200
150
100
50
250
300
tPHL
tPLH
tr
tf
−25 0 25 50 75 100 125
− Maximum Continuous Drain Current
N − Number of Outputs Conducting Simultaneously
of Each Output − A
D
I
0
1 2 3 4 5 6 7 8
VCC = 5 V
TC= 25°C
TC= 125°C
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
TC= 100°C
10
8
4
2
0
6
0 100 200 300 400
14
12
16
18
500 600 700
ID− Drain Current − mA
VCC = 5 V
See Note A
TC= 25°C
TC= − 40°C
TC= 125°C
Ω
DS(on) − Drain-to-Source On-State Resistance −
r
VCC − Logic Supply Voltage − V
4
3
1
0
4 4.5 5 5.5
5
7
8
6 6.5 7
6
2
TC= 125°C
TC= 25°C
TC= − 40°C
ID= 100 mA
See Note A
Ω
DS(on) − Static Drain-to-Source On-State Resistance −
r
I − Supply Current − mA
CC
f − Frequency − MHz
1
0.5
0
0.1 1 10
1.5
2
100
2.5
VCC = 5 V
TC= − 40°C to 125°C
2
1
10
4
0.1 0.2 10.4 2 104
0.2
0.1
0.4
I − Peak Avalanche Current − A
AS
tav − Time Duration of Avalanche − ms
TC= 25°C
TPIC6B595
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SLIS032B –JULY 1995–REVISED JUNE 2015
6.7 Typical Characteristics
Figure 1. Peak Avalanche Current vs Time Duration of Figure 2. Supply Current vs Frequency
Avalanche
Technique should limit TJ−TCto 10°C maximum.
Technique should limit TJ−TCto 10°C maximum.
Figure 4. Static Drain-to-Source On-State Resistance
Figure 3. Drain-to-Source On-State Resistance vs Logic Supply Voltage
vs Drain Current
Technique should limit TJ−TCto 10°C maximum
Figure 6. Maximum Continuous Drain Current of
Figure 5. Switching Time vs Case Temperature Each Output vs Number of Outputs Conducting
Simultaneously
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− Maximum Peak Drain Current of Each Output − A
D
N − Number of Outputs Conducting Simultaneously
I
0.15
0.05
0.4
0
1 2 3 4 5
0.3
0.2
0.35
0.5
6 7 8
0.45
0.25
0.1 VCC = 5 V
TC= 25°C
d = tw/tperiod
= 1 ms/tperiod
d = 10%
d = 20%
d = 50%
d = 80%
TPIC6B595
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Typical Characteristics (continued)
Figure 7. Maximum Peak Drain Current of
Each Output vs Number of Outputs Conducting Simultaneously
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4 −7,
14 −17
TEST CIRCUIT
SWITCHING TIMES
G
5 V
50%
24 V
0.5 V
90%
10%
tPLH
tr
50%
90%
10%
tPHL
tf
SRCK
5 V
50%
SER IN
5 V
50% 50%
tsu th
tw
INPUT SETUP AND HOLD WAVEFORMS
5 V 24 V
VCC
DRAIN
SRCLR
SER IN
RL= 235 Ω
CL= 30 pF
(see Note B)
G
Output
SRCK
RCK
DUT
GND
Output
Word
Generator
(see Note A)
10, 11, 19
8
13
3
12
9
0 V
0 V
0 V
ID
2
TEST CIRCUIT
5 V
VCC
DRAIN
GND
SRCLR
SER IN
RL= 235 Ω
CL= 30 pF
(see Note B)
VOLTAGE WAVEFORMS
G
Output
SRCK
RCK
Word
Generator
(see Note A)
76543210 5 V
SRCK
5 V
G
5 V
SER IN
RCK
SRCLR
5 V
5 V
DUT
24 V
DRAIN1
24 V
0 V
0 V
0 V
0.5 V
0 V
10, 11, 19
8
13
3
12
9
0 V
4 −7,
14 −17
ID
2
TPIC6B595
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SLIS032B –JULY 1995–REVISED JUNE 2015
7 Parameter Measurement Information
A. The word generator has the following characteristics: tr≤10 ns, tf≤10 ns, tw= 300 ns, pulsed repetition rate
(PRR) = 5 kHz, ZO= 50 Ω.
B. CLincludes probe and jig capacitance.
Figure 8. Resistive-Load Test Circuit and Voltage Waveforms
A. The word generator has the following characteristics: tr≤10 ns, tf≤10 ns, tw= 300 ns, pulsed repetition rate
(PRR) = 5 kHz, ZO= 50 Ω.
B. CLincludes probe and jig capacitance.
Figure 9. Test Circuit, Switching Times, and Voltage Waveforms
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15 V
10.5 Ω
200 mH
SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT
twtav
IAS = 0.5 A
V(BR)DSX = 50 V
VOLTAGE AND CURRENT WAVEFORMS
Input
ID
VDS
See Note B
VCC
DRAIN
SRCLR
SER IN
G
SRCK
RCK
Word
Generator
(see Note A)
DUT
GND
5 V
VDS
ID
2
8
13
3
12
9
10, 11, 19
4 −7,
14 −17
5 V
0 V
MIN
0.1 A
IF
0
IRM
25% of IRM
ta
trr
di/dt = 20 A/µs
+
−
2500 µF
250 V
L = 1 mH
IF
(see Note A)
RG
VGG
(see Note B)
Driver
TP A
50 Ω
Circuit
Under
Test
DRAIN
25 V
t1t3
t2
TP K
TEST CIRCUIT CURRENT WAVEFORM
TPIC6B595
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Parameter Measurement Information (continued)
A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and
connected to the TP A test point.
B. The VGG amplitude and RGare adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF= 0.1 A, where
t1= 10 µs, t2= 7 µs, and t3= 3 µs.
Figure 10. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode
A. The word generator has the following characteristics: tr≤10 ns, tf≤10 ns, ZO= 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 0.5 mA.
Energy test level is defined as EAS = IAS × V(BR)DSX × tav/2 = 30 mJ.
Figure 11. Single-Pulse Avalanche Energy Test Circuit and Waveforms
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G
RCK
SRCLR
SRCK
SER IN
CLR
D
C1
D
C2
CLR
D
C1
SER OUT
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
D
C2
D
C2
D
C2
D
C2
D
C2
D
C2
D
C2
4DRAIN0
5DRAIN1
10, 11, 19 GND
6DRAIN2
7DRAIN3
14 DRAIN4
15 DRAIN5
16 DRAIN6
17 DRAIN7
9
8
3
12
13
18
TPIC6B595
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SLIS032B –JULY 1995–REVISED JUNE 2015
8 Detailed Description
8.1 Overview
The TPIC6B595 device is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use
in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for
inductive transient protection, so it can also drive relays, solenoids, and other medium-current or high-voltage
loads.
8.2 Functional Block Diagram
Figure 12. Logic Diagram (Positive Logic)
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EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS
VCC
Input
GND
GND
DRAIN
50 V
20 V
25 V
12 V
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www.ti.com
Functional Block Diagram (continued)
Figure 13. Schematic of Inputs
8.3 Feature Description
8.3.1 Serial-In Interface
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data
transfers through both the shift and storage registers on the rising edge of the shift register clock (SRCK) and the
register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register
clear (SRCLR) is high.
8.3.2 Clear Register
A logical low on (SRCLR) clears all registers in the device. TI suggests clearing the device during power up or
initialization.
8.3.3 Output Control
Holding the output enable (G) high holds all data in the output buffers low, and all drain outputs are off. Holding
(G) low makes data from the storage register transparent to the output buffers. When data in the output buffers is
low, the DMOS transistor outputs are OFF. When data is high, the DMOS transistor outputs have sink-current
capability. This pin can also be used for global PWM dimming.
8.3.4 Cascaded Application
The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices.
Connect the device (SEROUT) pin to the next device (SERIN) for daisy Chain. This provides improved
performance for applications where clock signals may be skewed, devices are not located near one another, or
the system must tolerate electromagnetic interference.
8.3.5 Current Limit Function
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sink
current capability. Each output provides a 500-mA typical current limit at TC= 25°C. The current limit decreases
as the junction temperature increases for additional device protection.
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8.4 Device Functional Modes
8.4.1 Operation With V(VCC) < 4.5 (Minimum V(VCC))
This device works normally during 4.5 V ≤V(VCC)≤5.5 V, when operation voltage is lower than 4.5 V. TI can't
ensure the behavior of device, including communication interface and current capability.
8.4.2 Operating With 5.5 V < V(VCC) < 6 V
This device works normally during this voltage range, but reliability issues may occur while the device works for a
long time in this voltage range.
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VCC
GND
SER OUT
RCK
SER IN
SRCLR
DRAIN0
G
DRAIN1
DRQIN2
TPIC6B595
SRCK
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
5 V
10 k 0.1 uF
MCU
VCC
GND
SER OUT
RCK
SER IN
SRCLR
G
TPIC6B595
SRCK
5V
10 k 0.1 uF
Vbattery Vbattery
TO SERIAL INPUT OF THE NEXT
STAGE
R1 R2 R3 R4 R5 R6 R7 R8
D1 D2 D3 D4 D5 D6 D7 D9D8
R9 R9 R9 R9 R9 R9 R9 R9
D10 D11 D12 D13 D14 D15 D16
DRAIN0
DRAIN1
DRQIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPIC6B595 device is a serial-in parallel-out, Power+LogicE 8-bit shift register with low-side switch DMOS
outputs rating of a 150 mA per channel. The device is designed for use in systems that require relatively high
load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power
driver applications include relays, solenoids, and other medium currentor high-voltage loads. The following
focuses on automotive cluster applications for the TPIC6B595 device.
9.2 Typical Application
The typical application of the TPIC6B595 device is the automotive cluster driver. In this example, two TPIC6B595
power shift registers are cascaded and used to turn on LEDs in the cluster panel. In this case, the LED must be
updated after all 16 bits of data have been loaded into the serial shift registers. MCU outputs the data to the
serial input (SER IN) while clocking the shift register clock (SRCK). After the 16th clock, a pulse to the register
clock (RCK) transfers the data to the storage registers. If output enable (G) is low, then the LEDs are turned ON
corresponding to the status word with ones being ON and zeros OFF. With this simple scheme, MCU use SPI
interface can turn on 16 LEDs using only two ICs as illustrated in Figure 14.
Figure 14. Typical Application Schematic
9.2.1 Design Requirements
Use the design parameters in Table 1 for this design example.
Table 1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
VSUPPLY 9-16 V
V(D1), V(D2), V(D3), V(D4), V(D5), V(D6),V(D7), V(D8) 2 V
V(D9), V(D10),V(D11), V(D12), V(D13), V(D14),V(D15), V(D16) 3.3 V
I(D1), I(D2), I(D3), I(D4), I(D5), I(D6),I(D7), I(D8) 20mA When Vbattery is 12 V
I(D9), I(D10), I(D11), I(D12), I(D13), I(D14),I(D15), I(D16) 30mA When Vbattery is 12 V
14 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6B595
V supply V(Dx)
I(D9) I(D10) I(D11) I(D12) I(D13) I(D14) I(D15) I(D16) 43.8mA
Rx
Vsupply V(Dx)
I(D9) I(D10) I(D11) I(D12) I(D13) I(D14) I(D15) I(D16) 19.7mA
Rx
R9,R10,R11,R12,R13,R14,R15,R16 V supply V(Dx) 12V 3.3V
R9 R10 R11 R12 R13 R14 R15 R16 290
I(Dx) 0.03A
:
Vsupply V(Dx)
I(D1) I(D2) I(D3) I(D4) I(D5) I(D6) I(D7) I(D8) 28mA
Rx
Vsupply V(Dx)
I(D1) I(D2) I(D3) I(D4) I(D5) I(D6) I(D7) I(D8) 14mA
Rx
R1,R2,R3,R4,R5,R6,R7,R8 V supply V(Dx) 12V 2V
R1 R2 R3 R4 R5 R6 R7 R8 500
I(Dx) 0.02A
:
TPIC6B595
www.ti.com
SLIS032B –JULY 1995–REVISED JUNE 2015
9.2.2 Detailed Design Procedure
To begin the design process, one must decide on a few parameters. The designer must know the following:
• Vsupply - LED supply is connect battery directly or fix voltage, this application connect the battery directly.
• V(Dx) – LED forward voltage
• I(Dx) – LED setting current when battery is 12 V.
(1)
When Vsupply is 9 V,
(2)
When Vsupply is 16 V,
(3)
(4)
When Vsupply is 9 V,
(5)
When Vsupply is 16 V,
(6)
NOTE
If customers can accept the current variation when battery voltage is changing, they can
connect to the battery directly. If customers need the less variation of current, they must
use the voltage regulator as supply voltage of LED, or change to constant current LED
driver directly.
9.2.3 Application Curve
Figure 15. CH1 is SRCK, CH2 is RCK, CH3 is SER IN, CH4 is D1 current
Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: TPIC6B595
TPIC6B595
SLIS032B –JULY 1995–REVISED JUNE 2015
www.ti.com
10 Power Supply Recommendations
The TPIC6B595 device is designed to operate from an input voltage supply range from 4.5 V and 5.5 V. This
input supply should be well regulated. TI recommends placing the ceramic bypass capacitors near the VCC pin.
11 Layout
11.1 Layout Guidelines
There is no special layout requirement for the digital signal pin; the only requirement is placing the ceramic
bypass capacitors near the corresponding pin. Because the TPIC6B595 device does not have a thermal
shutdown protection function, to prevent thermal damage, TJmust be less than 150°C. If the total sink current is
high, the power dissipation might be large. The devices are currently not available in the thermal pad package,
so good PCB design can optimize heat transfer, which is absolutely essential for the long-term reliability of the
device. Maximize the copper coverage on the PCB to increase the thermal conductivity of the board, because the
major heat-flow path from the package to the ambient is through the copper on the PCB. Maximum copper is
extremely important when the design does not include heat sinks attached to the PCB on the other side of the
package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• All thermal vias should be either plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
16 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6B595
NC
SER IN
DRAIN0
DRAIN1
DRAIN2
Vcc
SRCK
GND
SER OUT
DRAIN5
DRAIN6
DRAIN7
DRAIN4
TPIC6B595 NC
SRCLR
DRAIN3
VIA to Ground
Power Ground both
in TOP and Bottom
RCK
GND
G
GND
TPIC6B595
www.ti.com
SLIS032B –JULY 1995–REVISED JUNE 2015
11.2 Layout Example
Figure 16. TPIC6B595 Layout Example
Copyright © 1995–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: TPIC6B595
TPIC6B595
SLIS032B –JULY 1995–REVISED JUNE 2015
www.ti.com
12 Device and Documentation Support
12.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18 Submit Documentation Feedback Copyright © 1995–2015, Texas Instruments Incorporated
Product Folder Links: TPIC6B595
PACKAGE OPTION ADDENDUM
www.ti.com 15-Sep-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TPIC6B595DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC6B595
TPIC6B595DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPIC6B595
TPIC6B595DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 TPIC6B595
TPIC6B595DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPIC6B595
TPIC6B595N ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 125 TPIC6B595N
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Sep-2014
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPIC6B595DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Sep-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPIC6B595DWR SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Sep-2014
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
10.63
9.97
2.65 MAX
18X 1.27
20X 0.51
0.31
2X
11.43
TYP
0.33
0.10
0 - 8
0.3
0.1
0.25
GAGE PLANE
1.27
0.40
A
NOTE 3
13.0
12.6
B7.6
7.4
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
120
0.25 C A B
11
10
PIN 1 ID
AREA
NOTE 4
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.200
www.ti.com
EXAMPLE BOARD LAYOUT
(9.3)
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
20X (2)
20X (0.6)
18X (1.27)
(R )
TYP
0.05
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
10 11
20
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(9.3)
18X (1.27)
20X (0.6)
20X (2)
4220724/A 05/2016
SOIC - 2.65 mm max heightDW0020A
SOIC
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
10 11
20
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
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