FUJITSU MICROELECTRONICS
DATA SHEET
Copyright©2001-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.10
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
8-bit Microcontroller
CMOS
F2MC-8L MB89530A Series
MB89535A/537A/537AC/538A/538AC/F538
MB89F538L/P538/PV530
■DESCRIPTION
The MB89530A series is a one-chip microcontroller f eaturing the F2MC-8L core supporting low-v oltage and high-
speed operation. Built-in peripheral functions include timers, serial interface, A/D converter , and external interrupt.
This product is an ideal general-purpose one-chip microcontroller for a wide variety of applications from household
to industrial equipment, as well as use in portable devices.
Note : F2MC is the abbreviation of FUJITSU Fle xible Microcontroller.
■FEATURES
• Wide range of package options
• QFP package (1.00 mm pitch)
• Two types of LQFP packages (0.65 mm pitch, 0.50 mm pitch)
• SH-DIP package (1.778 mm pitch)
• BCC package (0.50 mm pitch)
• Low voltage, high-speed operating capability
Minimum instruction exe cution time 0.32 µs (at base oscillator 12.5 MHz)
•F
2MC-8L CPU Core
• Instruction set optim ized for controller operation
• Multiplication/division instructions
• 16-bit calculation
• Branching instructions with bit testing
• Bit operation instructions, etc. (Continued)
DS07-12547-7E
MB89530A Series
2DS07-12547-7E
(Continued)
• Five timer systems
• 8-bit PWM timer with 2 channels (usable as either interval timer of PWM timer)
• Pulse width count timer (supports continuous measu rement or remote control receiving applications)
• 16-bit timer counter
• 21-bit time base timer
• Watch prescaler (17-bit)
•UART
Synchronous or asynchronous operation, switchable
• 2 serial interfaces (Serial I/O)
Selection of tr ansfer direction (specify MSB fir st or LSB first) for communication with a variety of devices
• 10-bit A/D conver ter (8 channels)
• External clock input for startup support
• Time base timer output for startup support (except MB89F538/F538L)
• Pulse generators (PPG) with 2-program capability
• 6-bit PPG with selection of pulse width and pulse period
• 12-bit PPG (2 channels) with selection of pulse width and pulse period
•I
2C interface circuits
• External interrupt 1 (single-clock system : 4 channels, dual-clock system : 3 channels)
4 or 3 independent inputs, release enabled from standby mode (includes edge detection function)
• External interrupt 2 (except for MB89F538/F538L : 8 channels, MB89F538/F 538L : 7 channels)
8 or 7 independent input, release enabled form standby mode (includes level edge detection function)
• Standby modes (low power consumption modes)
• Stop mode (oscillator stops, virtually no power consumed)
• Sleep mode (CPU stops, power consumption reduced to one-third)
• Sub clock mode
• Watch mode
• Watchdog timer reset
• I/O ports
• Maximum port s
Single-clock system : Except MB89F538/F538L 53 ports
MB89F538/F538L 52 ports
Dual-clock system : Except MB89F538/F538L 51 ports
: MB89F538/ F 53 8L 50 ports
• 38 general-purpose I/O ports (CMOS) (MB89F538/F538L : 37 general-purpose I/O ports)
• 2 general-purpose I/O ports (N-ch open dr ain)
• 8 general-purpose output ports (N-ch open drain)
• General-purpose input ports (CMOS) : single-clock system : 5 ports, dual-clock system : 3 ports
MB89530A Series
DS07-12547-7E 3
■PRODUCT LINEUP
(Continued)
Part number
Parameter MB89535A MB89537A/
537AC MB89538A/
538AC MB89F538/
MB89F538L MB89P538 MB89PV530
Type Mass produced (MASK ROM) Flash product One-time
programmable
product
Evaluation
product
ROM capacity
16 Kbytes ×
8-bit
(built-in
ROM)
32 Kbyte s ×
8-bit
(built-in
ROM)
48 Kbytes ×
8-bit
(built-in
ROM)
48 Kbytes ×
8-bit
(built-in Flash)
(write from
general purpose
EPROM writer)
48 Kbytes ×
8-bit
(built-in ROM)
(write from
general purpose
EPROM writer)
48 Kbytes × 8-bit
(external ROM) *2
RAM capacity 512 bytes ×
8-bit 1 Kbyte ×
8-bit 2 Kbytes × 8-bit
Operating
voltage 2.2 V to 5.5 V *1
(MB89535A/537A/538A/537AC/538AC)
MB89F53 8 :
3.5 V to 5.5 V
MB89F538L :
2.4 V to 3.6 V *1
2.7 V to 5.5 V 2.7 V to 5.5 V
CPU functions
Basic instructions : 136
Instruction bit length : 8 bits
Instruction length : 1 bit to 3 bits
Data bit length : 1, 8, 16 bits
Minimum instruction execut ion time : 0.32 µs / 12.5 MHz
Minimum interrupt processing time : 2.88 µs / 12.5 MHz
Peripheral functions
Ports
Input ports : single-clock system : 5 (4 also usable as external interrupts)
dual-cloc k system : 3 (3 also usable as externa l interrupts)
Output-only ports (N-ch open drain)
: 8 (8 also usable as A/D converter input)
I/O ports (N-ch open drain) : 2 (2 also usable as SO2/SDA or SI2/SCL)
I/O ports (CM OS ) (Ex cep t MB89F538/F 53 8L )
: 38
I/O ports (CMOS) (MB89F538/F538L)
: 37 (21 have no other fu nc tion )
Total (except MB89F538/F538L) : single-cloc k system : 53
dual-clock system : 51
Total (MB89F538/F538L) : single-clock syst em : 52
dual-clock system : 50
Time base
timer
21 bits
Interrupt periods at main clock oscillation frequency of 12.5 MHz
(approx. 0.655 ms, 2.621 ms, 20.97 ms, 335.5 ms)
Watchdog
timer Reset period of approx. 167.8 ms to 335.6 ms at main clock frequency of 12.5 MHz
Reset period of approx. 500 ms to 1000 ms at sub clock frequency of 32.768 kHz.
PWM timer
8-bit interval timer operation
(supports square wave output, operating clock period : 1, 8, 16, 64 tinst*3)
Pulse width measurement with 8-bit resolution (conversion period : 28 tinst*3 to 28 × 64 t inst*3)
2 channels (can also be used as int erval timer, can al so be used as ch.1 outpu t and ch.2 count
clock)
Watch prescaler Interval time s at 17-bit sub clock base frequency of 32.7 68 kHz
(approx. 31.25 ms, 0.25 s, 0.50 s, 1.00 s, 2.00 s, 4.00 s)
MB89530A Series
4DS07-12547-7E
(Continued)
*1 : Depends on operating frequency.
*2 : Using external ROM and MBM27C512.
*3 : tinst represents instruction execution tim e. This can be select ed as 1/4, 1/ 8, 1/16, 1/ 64 of the m ain clock cycle
or 1/2 of the sub clock cycle.
Note : MB89535A/537A/538A have no built-in I2C functions.
To use I2C functions, choose the MB89PV530/MB89P538/F538/F538L/537AC/538AC.
Part number
Parameter MB89535A MB89537A/
537AC MB89538A/
538AC MB89F538/
MB89F538L MB89P538 MB89PV530
Peripheral fu nctions
Pulse width
count timer
8-bit one-shot timer operation
(supports underflow output, operating clock period : 1, 4, 32 tinst*3, external)
8-bit reload timer operation
(supports squa re wave output, operating clock period : 1, 4, 32 tinst*3, external)
8-bit pulse width measurement operation
(continuous measurement, “H” width measurement, “L” width measurement, ↑ to ↑, ↓ to ↓, “H”
width measurement and ↑ to↑)
16-bit timer/
counter
16-bit timer operation (operating clock period : 1 tinst*3, external)
16-bit event counter operation (select rising, falling, or both edges)
16-bit × 1 channe l
Serial I/O 8 bits length
Selection of LSB first or MSB first
Transfer clock (2, 8, 32 tinst*3, external)
UART/SIO CLK synchronous/CLK asynchronous data transfer capability (8, 9-bit with parity bit, or 7,8-bit
without parity bit) .
Built-in baud rate generator provides selection of 14 baud rate settings.
UART
CLK synchronous/CLK asynchronous data transfer capability (4, 6, 7, 8-bit with parity bit, or 5,
7, 8, 9-bit without parity bit) .
Built-in baud rate generator provides selection of 14 baud rate settings.
External clock output, 2-channel 8-bit PWM timer output also available for baud rate setti ngs.
External
interrupt 1
Single-clock system : 4 channels independen t, dual-clock system : 3 channels independent.
Selection of rising, falling, or both edge detection.
Can be used for recovery from standby mode (edge detection also available in stop mode)
External
interrupt 2 Except MB89F538/F538L : 8 channels, MB89F538/F538L : 7 channels
Can be used for recovery from standby mode.
6-bit PPG,
12-bit PPG Can generate square wave signals with programmable period.
6-bit × 1 channel or 12-bit × 2 channels.
I2C bus
interface ⎯1-channel , compatible with Intel System Administrator bus version 1.0 and
Philips I2C specifications.
2-line communications (on MB89PV530/P538/F538/F538L/537AC/538AC)
A/D converter
10-bit resolution × 8 channels.
A/D conversion functi ons (conversion time : 60 tinst*3)
Supports repeated calls from external clock (except MB89F538/F538L) .
Supports repeated calls from internal clock.
Standard voltage input provided (AVR)
Standby modes
(power saving
modes) Sleep mode, stop mode, sub clock mode, watch mode.
Process CMOS
MB89530A Series
DS07-12547-7E 5
■MODEL DIFFERENCES AND SELECTION CONSIDERATIONS
: Model-package combination available
: Model-package combination not available
Conversion sockets for pin pitch conversion can be used.
Part number
Package MB89535A MB89537A/
537AC MB89538A/
538AC MB89F538 MB89F538L MB89P538 MB89PV530
DIP-64P-M01
FPT-64P-M24
FPT-64P-M06
FPT-64P-M23
LCC-64P-M19
MDP-64C-P02
MQP-64C-P01
MB89530A Series
6DS07-12547-7E
■DIFFERENCES AMONG PRODUCTS
1. Memory Capacity
When this prod uct is used in an evalu ation pro duct or ot her e v aluation configur ation, it is necessary to carefully
confirm the differences between the model being used and the product it is evaluating. Particular attention should
be given to the following (Refer to “ CPU CORE 1.Memory Space”) .
• The program ROM area starts from address 4000H on the MB89F538, MB89F538L, MB89P538 and
MB89PV530 models.
• Note upper limits on RAM , such as stack areas, et c.
2. Current Consumption
• On the MB89PV530, the additional current consumed by the EPROM is added at the connecting socket on
the back side.
• When operating at low speed, the current consumption in the one-time PROM or EPROM models is greater
than on the MASK ROM models. However, current consumption in sleep or stop modes is identical.
For details, refer to “ ELECTRICAL CHARA CTERISTICS”.
3. Mask Options
The options available for use, and the method of specifying options, differ according to the model. Before use,
check the “ MASK OPTIONS” specification section.
4. Wild Register Functions
The following table shows areas in which wild register functions can be used.
Wild Register Usag e Area s
Part number Address space
MB89PV530 4000H to FFFFH
MB89P538 4000H to FFFFH
MB89F538/F538L 4000H to FFFFH
MB89537A/537AC 8000H to FFFFH
MB89538A/538AC 4000H to FFFFH
MB89535A C000H to FFFFH
MB89530A Series
DS07-12547-7E 7
■PIN ASSIGNMENTS
(Continued)
(TOP VIEW)
(DIP-64P-M01)
(MDP-64C-P02)
*1 : Pin 10 is MOD2 pin for MB89F538/F538L and P47/INT27/ADST pins except for MB89F538/F538L.
*2 : Pin 25 and pin 26 are P63/INT13, P64 pins for single-clock system and X0A, X1A pins for dual-clock
system.
*3 : The function of pin 57 depe nds on the model. For details, refer to “■PIN DESCRIPTIONS” and
“■HANDLING DEVICES”.
*4 : Package top pin assignments (MB89PV530 only)
N.C. : Internal connection only. Not for use.
Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name
65 A15 73 A1 81 O6 89 A8
66A1274 A0 82 O7 90A13
67 A7 75 O1 83 O8 91 A14
68 A6 76 O2 84 CE 92 VCC
69 A5 77 O3 85 A10
70 A4 78 VSS 86 OE
71 A3 79 O4 87 A11
72 A2 80 O5 88 A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P36/WTO
P37/PTO1
P40/INT20/EC
P41/INT21/SCK2
P42/INT22/SO2/SDA
P43/INT23/SI2/SCL
P44/INT24/UCK2
P45/INT25/UO2
P46/INT26/UI2
P47/INT27/ADST/MOD2*1
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT10
P61/INT11
P62/INT12
P63/INT13/X0A*2
P64/X1A*2
RST
MOD0
MOD1
X0
X1
VSS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCC
P35/PWC
P34/PTO2
P33/SI1 (UI1)
P32/SO1 (UO1)
P31/SCK1 (UCK1) /LMCO
P30/PPG03/MCO
C/N.C. *3
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20/PWCK
P21/PPG01
P22/PPG02
P23
P24
P25
P26
P27
92
91
90
89
88
87
86
85
84
83
82
81
80
79
65
66
67
68
69
70
71
72
73
74
75
76
77
78
VCC
A14
A13
A8
A9
A11
OE
A10
CE
O8
O7
O6
O5
O4
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O1
O2
O3
VSS
*4
MB89530A Series
8DS07-12547-7E
(Continued)
(TOP VIEW)
(FPT-64P-M24)
(FPT-64P-M23)
*1 : Pin 2 is MOD2 pin for MB89F538/F538L and P47/INT27/ADST pins except for MB89F538/F538L.
*2 : Pin 17 and pin 18 are P63/INT13, P64 pins for single-clock system and X0A, X1A pins for dual-clock
system.
*3 : The function of pin 49 depends on the model. For details, refer to “■PIN DESCRIPTIONS” and
“■HANDLING DEVICES”.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P46/INT26/UI2
P47/INT27/ADST/MOD2*1
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT10
P61/INT11
P62/INT12
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P63/INT13/X0A*2
P64/X1A*2
RST
MOD0
MOD1
X0
X1
VSS
P27
P26
P25
P24
P23
P22/PPG02
P21/PPG01
P20/PWCK
P45/INT25/UO2
P44/INT24/UCK2
P43/INT23/SI2/SCL
P42/INT22/SO2/SDA
P41/INT21/SCK2
P40/INT20/EC
P37/PTO1
P36/WTO
VCC
P35/PWC
P34/PTO2
P33/SI1 (UI1)
P32/SO1 (UO1)
P31/SCK1 (UCK1) /LMCO
P30/PPG03/MCO
C/N.C.*3
MB89530A Series
DS07-12547-7E 9
(Continued)
(TOP VIEW)
(FPT-64P-M06)
(MQP-64C-P01)
*1 : Pin 3 is MOD2 pin for MB89F538/F538L and P47/INT27/ADST pins except for MB89F538/F538L.
*2 : Pin 18 and pin 19 are P63/INT13, P64 pins for single-clock system and X0A, X1A pins for dual-clock
system.
*3 : The function of pin 50 depe nds on the model. For details, refer to “■PIN DESCRIPTIONS” and
“■HANDLING DEVICES”.
*4 : Package top pin assignments (MB89PV530 only)
N.C. : In ternal connection only. Not for use.
Pin no. Pin name Pin no. Pin name Pin no. Pin name Pin no. Pin name
65 N.C. 73 A2 81 N.C. 89 OE
66 A15 74 A1 82 O4 90 N.C.
67A1275 A0 83 O5 91A11
68 A7 76 N.C. 84 O6 92 A9
69 A6 77 O1 85 O7 93 A8
70 A5 78 O2 86 O8 94 A13
71 A4 79 O3 87 CE 95 A14
72 A3 80 VSS 88 A10 96 VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
P30/PPG03/MCO
C/N.C.
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20/PWCK
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P45/INT25/UO2
P46/INT26/UI2
P47/INT27/ADST/MOD2*1
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT10
P61/INT11
P62/INT12
P63/INT13/X0A*2
P64/X1A*2
64
63
62
61
60
59
58
57
56
55
54
53
52
RST
MOD0
MOD1
X0
X1
VSS
P27
P26
P25
P24
P23
P22/PPG02
P21/PPG01
94
95
96
65
66
67
68
84
83
82
81
80
79
78
20
21
22
23
24
25
26
27
28
29
30
31
32
P44/INT24/UCK2
P43/INT23/SI2/SCL
P42/INT22/SO2/SDA
P41/INT21/SCK2
P40/INT20/EC
P37/PTO1
P36/WTO
VCC
P35/PWC
P34/PTO2
P33/SI1 (UI1)
P32/SO1/ (UO1)
P31/SCK1 (UCK1) /LMCO
85
86
87
88
89
90
91
92
93
77
76
75
74
73
72
71
70
69
*4*3
MB89530A Series
10 DS07-12547-7E
(Continued)
(TOP VIEW)
(LCC-64P-M19)
*1 : Pin 2 is MOD2 pin for MB89F538/F538L and P47/INT27/ADST pins except for MB89F538/F538L.
*2 : Pin 17 and 18 are P63/INT13 , P64 pins for single-clock system and X0A, X1A pins for dual-clock system.
*3 : The function of pin 49 depends on the model. For details, refer to “■PIN DESCRIPTIONS” and
“■HANDLING DEVICES”.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P46/INT26/UI2
P47/INT27/ADST/MOD2∗1
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7
AVCC
AVR
AVSS
P60/INT10
P61/INT11
P62/INT12
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P63/INT13/X0A∗2
P64/X1A∗2
RST
MOD0
MOD1
X0
X1
VSS
P27
P26
P25
P24
P23
P22/PPG02
P21/PPG01
P20/PWCK
P45/INT25/UO2
P44/INT24/UCK2
P43/INT23/SI2/SCL
P42/INT22/SO2/SDA
P41/INT21/SCK2
P40/INT20/EC
P37/PTO1
P36/WTO
VCC
P35/PWC
P34/PTO2
P33/SI1 (UI1)
P32/SO1 (UO1)
P31/SCK1 (UCK1) /LMCO
P30/PPG03/MCO
C/NC∗3
MB89530A Series
DS07-12547-7E 11
■PIN DESCRIPTIONS
(Continued)
Pin no. Pin name I/O
circuit
type*7Function
SH-DIP*1
MDIP*2QFP*3
MQFP*4LQFP*5
BCC*6
30 23 22 X0 AConnecting pins to crystal oscillator circuit or other
oscillator circuit. T he X0 pin can connect to an external
clock. In that case, X1 is left open.
31 24 23 X1
28 21 20 MOD0 BInput pins for memory access mode setting.
Connect directly to Vss.
29 22 21 MOD1
27 20 19 RST C
Reset I/O pin. This pin has pull-up resistance with
CMOS I/O or hyste resis input. At an internal reset
request, an ’L’ signal is output. An ’L’ level input
initializes the internal circuits.
56 to 49 49 to 42 48 to 41 P00 to P07 D General purpose I/O ports.
48 to 41 41 to 34 40 to 33 P10 to P17 D General purpose I/O ports.
40 33 32 P20/PWCK E General purpose I/O port .Resource I/O pin (hysteresis
input).Hysteresis input. This pin also functions as a
PWC input.
39 32 31 P21/
PPG01 DGeneral purpose I/O port.This pin also functions as the
PPG01 output .
38 31 30 P22/
PPG02 DGeneral purpose I/O port.This pin also functions as the
PPG02 output .
37 30 29 P23 D General purpose I/O port .
36 29 28 P24 D General purpose I/O port .
35 28 27 P25 D General purpose I/O port .
34 27 26 P26 D General purpose I/O port .
33 26 25 P27 D General purpose I/O port .
58 51 50 P30/
PPG03/
MCO DGeneral purpose I/O port.This pin also functions as the
PPG03 output .
59 52 51 P31/SCK1
(UCK1) /
LMCO EGeneral purpose I/O port.Resource I/O pin (hysteresis
input).This pin als o fu nct ion s as th e UART /SI O clo ck
input/output pin.
60 53 52 P32/SO1
(UO1) DGeneral purpose I/O port.This pin also functions as the
UART/SIO data output pin.
61 54 53 P33/SI1
(UI1) EGeneral purpose I/O port.Resource input/output pin
(hysteresis input).This pin also functions as the UART/
SIO serial data input p in.
62 55 54 P34/PTO2 D General purpose I/O port.This pin also functions as the
PWM timer 2 output pin.
63 56 55 P35/PWC E General purpose I/O port.Resource I/O pin (hysteresis
input).This pin als o fu nct ion s as a PWC inp ut .
MB89530A Series
12 DS07-12547-7E
(Continued)
Pin no. Pin
name
I/O
circuit
type*7Function
SH-DIP*1
MDIP*2QFP*3
MQFP*4LQFP*5
BCC*6
15857
P36/
WTO DGeneral purpose I/ O port.Resource output.
This pin also funct ion s as the PWC ou tp ut pin.
25958
P37/
PTO1 DGeneral purpose I/ O port.Resource output.
This pin also funct ion s as the PWM time r 1 ou tp ut pi n.
36059
P40/
INT20/
EC EGeneral purpose I/O port.Resource I/O pin (hysteresis
input).Thi s pin als o fu nct i on s as an ext er nal inte rr up t
input or 16-bit t imer/counter input.
46160
P41/
INT21/
SCK2 EGeneral purpose I/O port.Resource I/O pin (hysteresis
input).Thi s pin als o fu nct i on s as an ext er nal inte rr up t
input or SIO clock I/O pin.
56261
P42/
INT22/
SO2/
SDA
G
N-ch open drain output.
Resource I/O pin (hysteresis only for INT22 input) .
This pin also functions as an external interrupt input,
SIO serial data output, or I2C data line.
66362
P43/
INT23/
SI2/SCL G
N-ch open drain output.
Resource I/O pin (hysteresis only for INT23 input) .
This pin also functions as an external interrupt, SIO
serial data input, or I2C clock I/O pin.
76463
P44/
INT24/
UCK2 E
General purpose I/O port.
Resource I/O pin (hysteresis input) .
This pin also functions as an exter nal interrupt input or
UART clock I/O pin.
8164
P45/
INT25/
UO2 E
General purpose I/O port.
Resource I/O pin (hysteresis input) .
This pin also functions as an exter nal interrupt input or
UART data output pin.
921
P46/
INT26/
UI2 E
General purpose I/O port.
Resource I/O pin (hysteresis input) .
This pin also functions as an exter nal interrupt input or
UART data input pin.
10 3 2
P47/
INT27/
ADST EExcept MB89F538/F538L
General purpose I/O port.
Resource I/O pin (hysteresis input) .
This pin also functions as an external interrupt input or
A/D converter clock input pin.
MB89F538/F538L
Input pins for memory access mode setting.
Connect directly to Vss.
MOD2 B
11 to 18 4 to 11 3 to 10 P50/AN0
to P57/
AN7 HN-ch open drain output port.
This pin also functions as an A/D converter analog input
pin.
MB89530A Series
DS07-12547-7E 13
(Continued)
*1 : DIP-64P-M01
*2 : MDP-64C-P02
*3 : FPT-64P-M06
*4 : MQP-64C-P01
*5 : FPT-64P-M24/M23
*6 : LCC-64P-M19
*7 : For I/O circuit type, refer to “ ■I/O CIRCUIT TYPE” .
Pin no. Pin name I/O
circuit
type*7Function
SH-DIP*1
MDIP*2QFP*3
MQFP*4LQFP*5
BCC*6
22 to 24 15 to 17 14 to 16 P60/INT10
to
P62/INT12 IGeneral purpose input port.
Resource input pin (hysteresis input) .
This pin also functions as an external interrupt input pin.
25 18 17 P63/INT13 I Single-clock system
General purpose input port.
Resource input (hysteresis
input) .
This pin also functions as an
external interrupt.
X0A A Dual-clock system Connected pin for sub clock.
26 19 18 P64 J Single-clock system General purpose input port.
X1A A Dual-clock system Connected pin for sub clock.
64 57 56 VCC ⎯Power supply pin.
32 25 24 VSS ⎯Ground pin (GND) .
19 12 11 AVCC ⎯A/D converter power supply pin.
20 13 12 AVR ⎯A/D converter reference voltage input pin.
21 14 13 AVSS ⎯A/D converter power supply pin.
Used at the same voltage level as the Vss supply.
57 50 49 C ⎯
MB89F538
Capacitor connection pin for
stabilization power supply.
Connect an external ceramic
capacitor of approximat ely
0.1 µF.
MB89P538
If “Available” is selected for
the step-down circuit
stabilization time, VCC is fixed.
If “Unavailable” is selected for
the step-down circuit
stabilization time, VSS is fixed.
MB89PV530
MB89537A/537AC
MB89538A/538AC
MB89535A
MB89F538L
N.C. pin
MB89530A Series
14 DS07-12547-7E
External EPROM Socket Pin Function Descriptions (MB89PV530 only)
*1 : MDP-64C-P02
*2 : MQP-64C-P01
*3 : For I/O circuit type, refer to “ ■I/O CIRCUIT TYPE” .
Pin no. Pin name I/O Circuit
type*3Function
MDIP*1MQFP*2
65
66
67
68
69
70
71
72
73
74
66
67
68
69
70
71
72
73
74
75
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O Address output pins.
75
76
77
77
78
79
O1
O2
O3 I Data input pins
78 80 VSS O Power supply pin (GND) .
79
80
81
82
83
82
83
84
85
86
O4
O5
O6
O7
O8
I Data input pins.
84 87 CE OROM chip enable pin.
Outputs an “H” level signal in standby mode.
85 88 A10 O Address output pin.
86 89 OE OROM output enable pin.
Outputs “L” at all times.
87
88
89
91
92
93
A11
A9
A8 O
Address output pins.
90 94 A13 O
91 95 A14 O
92 96 VCC O EPROM power supply pin.
⎯
65
76
81
90
N.C. O Internally connected.
These pins always left open.
MB89530A Series
DS07-12547-7E 15
■I/O CIRCUIT TYPES
(Continued)
Type Circuit Remarks
A
Oscillator feedback resistance
• High speed side = approx. 1 MΩ
• Low speed side = approx. 10 MΩ
B
• Hysteresis input
• Pull-down resistance built-in to
MB89535A
MB89537A/537AC
MB89538A/538AC
C
• Pull-up resistance approx. 50 kΩ
• Hysteresis input
D
• CMOS I/O
• Software pull-up resistance can be
used. Approx. 50 kΩ
E
• CMOS I/O
• Software pull-up resistance can be
used. Approx. 50 kΩ
N-ch
N-ch
X1 (X1A)
X0 (X0A) P-ch
P-ch Clock input
Standby contr ol
R
Mode input
R
P-ch
N-ch
Reset output
Reset input
P-ch
P-ch
N-ch
RPull-up control
resistor
Digital output
Digital output
Port input
P-ch
P-ch
N-ch
RPull-up control
resistors
Port input
Resource input
Digital output
Digital output
MB89530A Series
16 DS07-12547-7E
(Continued)
Type Circuit Remarks
G
• N-ch open drain output
• Hysteresis input
• CMOS input
H
• N-ch open drain output
• Analog input (A/D converter)
I
• Hysteresis input
• CMOS input
• Software pull-up resistance can be
used. Approx. 50 kΩ
J
• CMOS input
• Software pull-up resistance can be
used. Approx. 50 kΩ
N-ch
Resource input
Port input
Digital output
N-ch
P-ch
Analog input
Digital output
P-ch
RPull-up control resistors
Port
Resource
P-ch
RPull-up control resistors
Port
MB89530A Series
DS07-12547-7E 17
■HANDLING DEVICES
1. Preventing Latch-up
Care must be taken to ensure that maximum voltage ratings are not exceeded (to prevent latch-up) . When
CMOS integrated circuit devices are subjected to applied voltages higher than Vcc at input and output pins (other
than medium- and high-withstand voltage pins), or to voltages lower than Vss, as well as when voltages in excess
of rated levels are applied between Vcc and Vss, the phenomenon known as latch-up can occur.
When a latch-up condition occurs, supply current can increase dramatically and may destroy semiconductor
elements. In using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.
Also when switching power on or off to analog systems, care must be taken that analog power supplies (AVCC,
AVR) and an a log inpu t sign a ls do no t exceed the level of the digital power supply.
2. Power Supply Voltage Fluctuations
Even within the warranted operating range of the Vcc supply voltage, sudden changes in supply voltage can
cause abnormal operation. As a measure f or stability, it is recommended that the Vcc ripple fluctuation (peak to
peak value) should be kept within 10% of the reference Vcc value on commercial power supply (50 Hz/60 Hz),
and instantaneous voltage fluctuations such as at power-on and shutdown should be kept within a transient
v ariability limit of 0.1V/ms.
3. Treatment of Unused Input Pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistance.
4. Treatment of N.C. Pins
Any pins marked ’NC’ (not connected) must be left open.
5. Treatment of Power Supply Pins on Models with Built-in A/D Converter
Ev en when A/D con v erters are not in use, pins shou ld be connected so that AVCC = VCC, and AVSS = AVR = VSS.
6. Precautions for Use of External Clock
Ev en when an external clock signal is used, an oscillator stabilization wait period is used after a power-on reset,
or escape from sub clock mode or stop mode.
7. Execution of Programs on RAM
Debugging of programs executed on RAM cannot be performed even when using the MB89PV530.
8. Wild Register Functions
Wild registers cannot be debugged with t he MB89PV530 and tools. To verify oper ations, actual in- device testing
on the MB89P538 or MB89F538/F538L is advised.
MB89530A Series
18 DS07-12547-7E
9. Details on handling the C terminal of the MB89530 series
The MB89530 series contains the following products. The regulator integrated model and the regulator-less
model have different performance characteristics.
Although these product models have the same internal resources, the operation sequence after a power-on
reset is different between the regulator integrated model and regulator-less model.
The operat ion sequence after a power-on reset of each model is shown below.
As above, the regulator integrated model starts the CPU behind the regulator-less model. This is because th e
regulator re quires a settling time for normal operation.
The MB89P538 offers a choice of regulat or-integra ted and regulator-less models selectable depending on the
C-terminal treatment. Use the right one for your mask board.
10. Note to Noise in the External Reset Pin (RST)
If the reset pulse applied to the e xternal reset pin (RST) does not meet the sp ecifications, it may cause malf unc-
tions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST).
Part No. Operation Voltage integrated model Terminal type Terminal treatments
MB89PV530
2.7 V to 5.5 V
Not included N.C. terminal Not required
MB89P538 Included
C terminal
Fixed to VCC
Not included Fixed to VSS
MB89F538 3.5 V to 5.5 V Inclu ded 0.1 µF capacitor
connected
MB89F538L 2.3 V to 3.6 V
Not included N.C. terminal Not required
MB89537A/537AC
2.2 V to 5.5 VMB89538A/538AC
MB89535A
Power supply (VCC)
CPU operation of r egulator
integrated model (MB89F538 only)
CPU operation of regulator-less
model (exclude MB89F538)
Voltage step-down circuit stabilization time
+ oscillation stabilization time
(219/FCH) + (218/FCH)
Oscillation stabiliza-
tion time (218/FCH)
CPU started on regulator-less
model (Reset vector) CPU started on regulator
integrated mod el (R eset vecto r)
FCH : Crystal oscillator frequency
MB89530A Series
DS07-12547-7E 19
■PROGRAMMING AND ERASING FLASH MEMORY ON THE MB89F538/F538L
1. Flash Memory
The flash memory is located between 4000H and FFFFH in the CPU memory map and incorporates a flash
memory interface circuit that allows read access and program access from the CPU to be performed in the same
way as MASK ROM. Progr amming and erasing flash memory is also performed via the flash memory interface
circuit by executing instructions in the CPU. This enables the flash memor y to be updated in place under the
control of the CPU, providing an efficient meth od of updating program and data.
2. Flash Memory Features
• 48 Kbytes × 8- bit configuration (16 Kbytes + 8 Kbyt es + 8 Kbytes + 16 Kbytes sectors)
• Automatic programming algorithm (Embedded algorithm : Equivalent to MBM29LV200)
• Includes an erase pause and restart function
• Data polling and toggle bit for detection of program/erase completion
• Detection of program/erase completion via CPU interrupt
• Compatible with JEDEC-standar d com m a nd s
• Sector Protection (sectors can be combined in any combination)
• No. of program/erase cycles : 10,000 (Min)
3. Procedure for Programming and Erasing Flash Memory
Programming and reading flash memory cannot be performed at the same time. Accordingly, to program or
erase flas h memo ry, the progr am mu st fir st be copied f ro m fla sh memo ry to RAM so that programming can be
performed without program access from flash memory.
4. Flash Memory Register
• Flash memory control status register (FMCS)
5. Sector Configuration
The tab le belo w sho ws the sector configur ation of fla sh memory and lists the addresses of each sector f or bo th
during CPU access a flash memory programming.
• Sector configuration of flash memory
* : Prog rammer address
The progr ammer ad dress is the address to be used instea d of the CPU addr ess when pro gr amming data f rom
a parallel flash memory progr ammer . Use the progr ammer address on prog ramming or era sing using a general-
purpose parallel programmer.
Flash Memory CPU Address Programmer Address*
16 Kbytes FFFFH to C000H1FFFFH to 1C000H
8 Kbytes BFFFH to A000H1BFFFH to 1A000H
8 Kbytes 9FFFH to 8000H19FFFH to 18000H
16 Kbytes 7FFFH to 4000H17FFFH to 14000H
RR/W R/W
RDY
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
007AH
Address
000X00-0B
Initial value
Reserved Reserved ⎯Reserved
R/W ⎯
R/W
R/W
R/W
INTE RDYINT WE
MB89530A Series
20 DS07-12547-7E
■ONE-TIME WRITING SPECIFICATIONS WITH PROM AND EPROM MICROCONTROLLERS
The MB89P538 has a PROM mode with functions equivalent to the MBM27C1001, allowing writing with a general
pur pose ROM writer using a prop rietar y adapter. Note, however, that the use of electronic signature mode is
not supported.
• Memory map for EPROM mode
The following illustration shows a memory map for EPROM mode. There are no PROM options.
4000H
FFFFH
1FFFFH
0000H0000H
RAM
ROM
I/O
0080H
4000H
0880H
FFFFH
0200H
0100HGeneral
purpose
register
Normal operating mode
Prohibited
EPROM mode (corresponding
addresses on EPROM writer)
Program
(EPROM)
Prohibited
Prohibited
MB89530A Series
DS07-12547-7E 21
• Recommended screening conditions
Before one-time writing of microcontroller programs to PROM, high temperature aging is recommended as a
screening process for chips before they are mounted.
• About writing yields
The nature of chips before one-time writing of microcontroller programs to PROM prevents the use of all-bit
writing tests. Therefore it is not possible to guarantee writing yields of 100% in some cases.
Program, verify
High temperature aging
+150 °C, 48h
Read
Mount
MB89530A Series
22 DS07-12547-7E
■EPROM WRITING TO PIGGY-BACK/EVALUATION CHIPS
This section describes methods of writing to EPROM on pi ggy-back/evaluat ion chips.
• EPROM model
MBM27C512-20TV
• Memory Space
• Writing to EPROM
1) Set up the EPROM writer for the MBM27C512.
2) Load program data to the ERPOM writer, in the area 4000H to FFFFH.
3) Use the EPROM writer to write to the area 4000H to FFFFH.
4000H
FFFFH
0000H0000H
RAM
PROM
48 KbytesEPROM
I/O
0080H
4000H
FFFFH
0880H
Normal operatin g mo de
Prohibited
(Corresponding address on
ROM writer)
Prohibited
MB89530A Series
DS07-12547-7E 23
■BLOCK DIAGRAM
4
P63/INT13/X0A*1
P64/X1A*1
P60/INT10 to P62/INT12
X0
X1
RST
P30/PPG03/MCO
P32/SO1 (UO1)
P34/PTO2
P35/PWC
P36/WTO
P37/PTO1
P33/SI1 (UI1)
P31/SCK1 (UCK1)
/LMCO
F2MC-8L
CPU
MOD0, MOD1, MOD2*2, VCC, VSS, C/N.C.
PWC
UART/SIO
8
8
P00 to P07
P10 to P17
P20/PWCK
P21/PPG01
P22/PPG02
P40/INT20/EC
P41/INT21/SCK2
P44/INT24/UCK2
P45/INT25/UO2
P46/INT26/UI2
P47/INT27/ADST*2
P50/AN0 to P57/AN7
AVCC
AVR
AVSS
P43/INT23/
SI2/SCL
P42/INT22/
SO2/SDA
P23 to P27
8
8
SIO
UART
I2C
ROM (16 Kbytes/32 Kbytes/48 Kbytes)
8-bit
PWM timer 2
8-bit
PWM timer 1
Sub clock
Main clock
Low voltage
oscillator circuit
(32.786 kHz)
Clock control
Watch prescaler
External interrupt 1
(edge)
CMOS I/O port
Oscillator circuit
Clock controller
Reset circuit
(watchdog timer)
21-bit time
base timer
6-bit PPF03
CMOS I/O port
RAM (512 Kbytes/1 Kbyte/2 Kbytes)
Wild register
Other pins
CMOS I/O port
CMOS I/O port
12-bit PPG01
12-bit PPG02
CMOS I/O port
16-bit timer/
counter 1
External interrupt 2
(level)
N-ch I/O
CMOS I/O port
N-ch output
10-bit
A/D converter
Port 6
Port 0
Port 1
Port 2
Port 4
Port 3
Port 5
Internal data bus
*1 : P63/INT13, P64 pins for single-clock system and X0A, X1A pins dual-clock system
*2 : MOD2 pin for MB89F53 8/F538L and P47/INT27/ADST pin except for MB89F538/F538L.
MB89530A Series
24 DS07-12547-7E
■CPU CORE
1. Memory Space
The MB89530A se ries has 64 Kb ytes of memory space , containing all I/O, data areas, an d progr am area s. The
I/O area is located at the lowest addresses, with the data area placed immediately above. The data area can
be partitioned into register areas, stack areas, or direct access areas depending on the application. The program
area is located at the opposite end of memor y, closest to the highest addresses, and the highest part of this
area is assigned to the tables of interrupt and reset vectors and vector call instructions. The following diagram
shows the structure of memory space in the MB89530A series.
• Memory Map
0000H
RAM
ROM
I/O
0080H
0C80H
0480H
FFFFH
0200H
0100H
0C91H
8000H
FFC0H
0000H
RAM
MB89537A/537AC
0000H
RAM
ROM
I/O
0080H
0C80H
0280H
FFFFH
0200H
0100H
0C91H
C000H
FFC0H
MB89535A
MB89PV530
MB89P538/F538/F538L
MB89538A/538AC
ROM
I/O
0080H
0C80H
0880H
FFFFH
0200H
0100H
0C91H
4000H
FFC0H
General
purpose
register
General
purpose
register
General
purpose
register
Open
Wild register
Open
Vector tables*2
Open
Wild register
Open
Vector tables*2
*1 : The external RO M area is on the MB89PV530 only.
*2 : Vector tables (reset , interrupt, vector call instructions)
External ROM*1
Open
Wild register
Open
Vector tables*2
MB89530A Series
DS07-12547-7E 25
2. Registers
The F2MC-8L ser ies has two types of registers, dedicated-use registers within the CPU, and general-purpose
registers in memory.
In addition, the PS r egister can be divided so that the upper 8 bits ar e used as a register bank pointer (RP), and
the lower 8 bits as a condition code register (CCR). (Refer to the following illustration.)
Program counter (PC) : 16-bit length, shows the location where instructions are stored.
Accumulator (A) : 16-bit length, a temporary memory register for calculation operations.
The lower byte is used for 8-bit data processing instructions.
Temporary accumulat or (T) : 16-bit length, performs calculations with the accumulator.
The lower byte is used for 8-bit data processing instructions.
Index register (IX) : 16-bit length, a register for index modification.
Extra pointer (EP) : 16-bit length, a pointer indicatin g memory addresses.
Stack pointer (SP) : 16-bit length, indicates stack areas.
Program status (PS) : 16-bit length, contains register pointer and condition code.
PC
A
T
IX
EP
SP
PS
16 bits
: Program counter
: Accumulator
: Temporary accumulator
: Index register
: Extra pointer
: Stack pointer
: Program status
FFFDH
Initial value
Not fixed
Not fixed
Not fixed
Not fixed
Not fixed
I-flag = 0, IL1, 0 = 11
Other bits not fixed
• Program status register configuration
PS
RP CCR
15 14 1312 11 10 9 876543210
RP Open Open Open H I IL1 IL0 N Z VC
MB89530A Series
26 DS07-12547-7E
The RP register shows the address of the register bank currently being used, so that the RP value and the actual
address are related by the con version rule shown in the following illustration.
The CCR register has bits that show the content of results of calculations and transferred data, and bits that
control CPU operation during interrupts.
In addition, the following general purpose registers are available.
General purpose registers: 8 bits length, used to contain data.
The general pur pose registers are 8-bit registers located in memor y. There are eight such registers per bank,
and the MB89530A ser ies have up to 32 banks for use. The bank currently in use is indicated by the register
bank pointer (RP).
H-flag : Set to “1” if calculations result in carry or borrow operations from bit 3 to bit 4, otherwise set to “0”.
This flag is used for decimal correction instructions.
I-flag : This flag is set to “1” if interrupts are enabled, and “0” if interrup ts are prohibited.
The default value at reset is “0”.
IL1, 0 : Indicates the level of the currently permitted interrupts.
Only interrupt requests having a more powerful level than the value of these bits will be processed.
IL1 IL0 Interrupt level Strength
001Strong
Weak
01
102
113
N-flag : Set to “1” if the highest bit is “1” after a calculation, otherwise cleared to “0”.
Z-flag : Set to “1” if a calculation result is “0”, otherwise cleared to “0”.
V-flag : Set to “1” if a two’s complement overflo w results during a calculation, otherwise cleared to “0”.
C-flag : Set to “1” if a calculation results in a carry or borrow operation from bit 7, otherwise cleared to “0”.
This is also the shift-out value in a shift instruction.
• General purpose register area real address conversion principle
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3R2 R1 R0 b2b1b0
A7 A6 A5 A4 A3A2 A1 A0
A15 A14 A13A12 A11 A10 A9 A8
Address
generated
RP upper Operation code
lower
MB89530A Series
DS07-12547-7E 27
•Register bank configuration
R0
R1
R2
R3
R4
R5
R6
R7
Address at this location =
0100H + 8 × (RP)
Memory area
32 banks
MB89530A Series
28 DS07-12547-7E
■I/O MAP
(Continued)
Address Register
name Register description Write/Read Initial value
00HPDR0 Port 0 data register R/W XXXXXXXXB
01HDDR0 Port 0 direction register W 0 0 0 0 0 0 0 0B
02HPDR1 Port 1 data register R/W XXXXXXXXB
03HDDR1 Port 1 direction register W 0 0 0 0 0 0 0 0B
04H to 06H (Reserved area)
07HSYCC System clock control register R/W X -1 MM1 0 0B
08HSTBC Standby control register R/W 0 0 0 1 0 - - -B
09HWDTC Watchdog control register R/W 0 - - - XXXXB
0AHTBTC Time base timer control register R/W 0 0 - - - 0 0 0B
0BHWPCR Watch prescaler control register R/W 0 0 - - 0 0 0 0B
0CHPDR2 Port 2 data register R/W XXXXXXXXB
0DHDDR2 Port 2 direction register R/W 0 0 0 0 0 0 0 0B
0EHPDR3 Port 3 data register R/W XXXXXXXXB
0FHDDR3 Port 3 direction register R/W 0 0 0 0 0 0 0 0B
10HPDR4 Port 4 data register R/W XXXX 1 1 XXB
11HDDR4 Port 4 direction register R/W 0 0 0 0 - - 0 0B
12HPDR5 Port 5 data register R/W 1 1 1 1 1 1 1 1 B
13HPDR6 Port 6 data register R XXXXXXXXB
14H to 21H (Reserved area)
22HSMC11 Serial mode control register 1 (UART) R/W 0 0 0 0 0 0 0 0B
23HSRC1 Serial rate cont ro l register (UART) R/W - - 0 1 1 0 0 0B
24HSSD1 S erial status and data register (UART) R/W 0 0 1 0 0 - 1XB
25HSIDR1/
SODR1 Serial input/output data register (UART) R/W XXXXXXXXB
26HSMC12 Serial mode control register 2 (UART) R/W - - 1 0 0 0 0 1B
27HCNTR1 PWM control register 1 R/W 0 0 0 0 0 0 0 0B
28HCNTR2 PWM control register 2 R/W 0 0 0 - 0 0 0 0B
29HCNTR3 PWM control register 3 R/W - 0 0 0 - - - -B
2AHCOMR1 PWM compare register 1 W XXXXXXXXB
2BHCOMR2 PWM compare register 2 W XXXXXXXXB
2CHPCR1 PWC pulse width control register 1 R/W 0 0 0 - - 0 0 0B
2DHPCR2 PWC pulse width control register 2 R/W 0 0 0 0 0 0 0 0B
2EHRLBR PWC reload buffer register R/W XXXXXXXXB
2FHSMC21 Serial mode control register 1 (UART/SIO) R/W 0 0 0 0 0 0 0 0B
30HSMC22 Serial mode control register 2 (UART/SIO) R/W 0 0 0 0 0 0 0 0B
31HSSD2 Serial status and data register (UART/SIO) R/W 0 0 0 0 1 - - -B
32HSIDR2/
SODR2 Serial data register (UART/SIO) R/W XXXXXXXXB
33HSRC2 Baud rate generator reload register R/W XXXXXXXXB
MB89530A Series
DS07-12547-7E 29
(Continued)
Address Register
name Register description Write/Read Initial value
34HADC1 A/D control register 1 R/W 0 0 0 0 0 0 - 0B
35HADC2 A/D control register 2 R/W - 0 0 0 0 0 0 1B
36HADDL A/D data register low R/W XXXXXXXXB
37HADDH A/D data register high R/W - - - - - - 0 0B
38HPPGC2 PPG2 control register (12-bit PPG) R/W 0 0 0 0 0 0 0 0B
39HPRL22 PPG2 reload register 2 (12-bit PPG) R/W 0X0 0 0 0 0 0B
3AHPRL21 PPG2 reload register 1 (12-bit PPG) R/W XX0 0 0 0 0 0B
3BHPRL23 PPG2 reload register 3 (12-bit PPG) R/W XX0 0 0 0 0 0B
3CHTMCR 16-bit timer control register R/W - - 0 0 0 0 0 0B
3DHTCHR 16- bit timer counter register high R/W 0 0 0 0 0 0 0 0B
3EHTCLR 16-bit timer counter register low R/W 0 0 0 0 0 0 0 0B
3FHEIC1 External interrupt 1 control register 1 R/W 0 0 0 0 0 0 0 0B
40HEIC2 External interrupt 1 control register 2 R/W 0 0 0 0 0 0 0 0B
41H to 48H (Reserved area)
49HDDCR D DC select register R/W - - - - - - - 0B
4AH, 4BH (Reserved area)
4CHPPGC1 PPG1 control register (12-bit PPG) R/W 0 0 0 0 0 0 0 0B
4DHPRL12 PPG1 reload register 2 (12-bit PPG) R/W 0X0 0 0 0 0 0B
4EHPRL11 PPG1 reload register 1 (12-bit PPG) R/W XX0 0 0 0 0 0B
4FHPRL13 PPG1 reload register 3 (12-bit PPG) R/W XX0 0 0 0 0 0B
50HIACR I2C address control register R/W - - - - - 0 0 0B
51HIBSR I2C bus status register R 0 0 0 0 0 0 0 0B
52HIBCR I2C bus control register R/W 0 0 0 0 0 0 0 0B
53HICCR I2C clock control register R/W 0 0 0 XXXXXB
54HIADR I2C address regi ster R/W - XXXXXXXB
55HIDAR I2C data register R/W XXXXXXXXB
56HEIE2 External interrupt 2 control register R/W 0 0 0 0 0 0 0 0B
57HEIF2 External interrupt 2 flag r egister R/W - - - - - - - 0B
58HRCR1 6-bit PPG control register 1 R/W 0 0 0 0 0 0 0 0B
59HRCR2 6-bit PPG control register 2 R/W 0X0 0 0 0 0 0B
5AHCKR Clock output control register R/W - - - - - - 0 0B
5BH to 6FH (Reserved area)
70HSMR Serial mode register (SIO) R/W 0 0 0 0 0 0 0 0B
71HSDR Serial data register (SIO) R/W XXXXXXXXB
72HPURR0 Po rt 0 pull-up resistance register R/W 1 1 1 1 1 1 1 1 B
73HPURR1 Po rt 1 pull-up resistance register R/W 1 1 1 1 1 1 1 1 B
74HPURR2 Po rt 2 pull-up resistance register R/W 1 1 1 1 1 1 1 1 B
75HPURR3 Po rt 3 pull-up resistance register R/W 1 1 1 1 1 1 1 1 B
76HPURR4 Po rt 4 pull-up resistance register R/W 1 1 1 1 - -1 1 B
77HWREN Wild register enable register R/W - - 0 0 0 0 0 0B
MB89530A Series
30 DS07-12547-7E
(Continued)
• Description of write/read symbols :
• Description of initial values :
Note : Do not use reserved spaces.
Address Register
name Register description Write/Read Initial value
78HWROR Wild register data test register R/W - - 0 0 0 0 0 0B
79HPURR6 Po rt 6 pull-up resistance register R/W - - - 1 1 1 1 1 B
7AHFMCS Flash memory control status resister R/W 0 0 0X0 0 - 0B
7BHILR1 Interrupt level setting register 1 W 1 1 1 1 1 1 1 1B
7CHILR2 Interrupt level setting register 2 W 1 1 1 1 1 1 1 1B
7DHILR3 Interrupt level setting register 3 W 1 1 1 1 1 1 1 1B
7EHILR4 Interrupt level setting register 4 W 1 1 1 1 1 1 1 1B
7FHITR Interrupt test register Access prohibited XXXXXX0 0B
C80HWRARH1 Upper address setting register 1 R/W XXXXXXXXB
C81HWRARL1 Lower address setting register 1 R/W XXXXXXXXB
C82HWRDR1 Data setting register 1 R/W XXXXXXXXB
C83HWRARH2 Upper address setting register 2 R/W XXXXXXXXB
C84HWRARL2 Lower address setting register 2 R/W XXXXXXXXB
C85HWRDR2 Data setting register 2 R/W XXXXXXXXB
C86HWRARH3 Upper address setting register 3 R/W XXXXXXXXB
C87HWRARL3 Lower address setting register 3 R/W XXXXXXXXB
C88HWRDR3 Data setting register 3 R/W XXXXXXXXB
C89HWRARH4 Upper address setting register 4 R/W XXXXXXXXB
C8AHWRARL4 Lower address setting register 4 R/W XXXXXXXXB
C8BHWRDR4 Data setting register 4 R/W XXXXXXXXB
C8CHWRARH5 Upper address setting register 5 R/W XXXXXXXXB
C8DHWRARL5 Lower address setting register 5 R/W XXXXXXXXB
C8EHWRDR5 Data setting register 5 R/W XXXXXXXXB
C8FHWRARH6 Upper address setting register 6 R/W XXXXXXXXB
C90HWRARL6 Lower address setting register 6 R/W XXXXXXXXB
C91HWRDR6 Data setting register 6 R/W XXXXXXXXB
R/W : read/write enabled
R : Read only
W : Write only
0 : This bit initialized to “0”.
1 : This bit initialized to “1”.
X : The initial value of this bit is not determined.
M : The initial value of this bit is a mask option.
- : This bit is not used.
MB89530A Series
DS07-12547-7E 31
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
*1 : The parameter is based on AVss = Vss = 0 V.
*2 : AVcc and Vcc are to be used at the same potential. AVR should not exceed AVcc + 0.3 V. (Continued)
Parameter Symbol Rating Unit Remarks
Min Max
Supply voltage*1
VCC,
AVCC VSS − 0.3 VSS + 6.0 V MB89535A/537A/538A*2
MB89537AC/538AC
MB89F538/F538L//P538
MB89PV530
AVR VSS − 0.3 VSS + 6.0 V
Input voltage*1VIVSS − 0.3 VCC + 0.3 V Other than P42, P43
VSS − 0.3 VSS + 6.0 V P42, P43
Output voltage*1VOVSS − 0.3 VCC + 0.3 V Other than P42, P43
VSS − 0.3 VSS + 6.0 V P42, P43
Maximum clamp current ICLAMP − 2.0 + 2.0 mA *3
Total maximum clamp
current Σ| ICLAMP | ⎯20 mA *3
“L” level maximum output
current IOL ⎯15 mA
“L” level aver age output
current IOLAV ⎯4mA
Average value
(operating current × operating duty)
“L” level maximum total
output current ΣIOL ⎯100 mA
“L” level average total output
current ΣIOLAV ⎯40 mA Average value
(operating current × operating duty)
“H” level maximum output
current IOH ⎯−15 mA
“H” level average out put
current IOHAV ⎯−4mA
Average value
(operating current × operating duty)
“H” level maximum total
output current ΣIOH ⎯−50 mA
“H” level average total
output current ΣIOHAV ⎯−20 mA Average value
(operating current × operating duty)
Current consumption PD⎯300 mW
Operating temperature TA−40 +85 °C
Storage temperature Tstg −55 +150 °C
MB89530A Series
32 DS07-12547-7E
(Continued)
*3 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40, P41, P44 to P47, P60 to P64
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is lo w, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input whe n the microc ontroller current is of f (not fixed a t 0 V) , the power supply is
provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to operate the power-on result.
• Care mu st be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.
• Sample recommended circuits :
WARNING: Sem iconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
VCC
R
• Input/Output Equivalent circuits
+B input (0 V to 16 V)
Limiting
resistance
Protective diode
MB89530A Series
DS07-12547-7E 33
2. Recommended Operating Conditions (AVss = Vss = 0 V)
* : Varies according to frequency used, and instruction cycle.
Refer to “Operating voltage vs. operating frequency (MB89P538/MB89PV530) ”, “Operating voltage vs. operating
frequency (MB89535A/ 537A/538A/537A C/538A C) ”, “Ope rating v oltage vs . operating fr equency (MB89F538) ”
and “5. A/D Converter Electrical Characteristics”.
Parameter Symbol Value Unit Remarks
Min Max
Supply voltage VCC,
AVCC
2.2* 5.5 V Range warranted for
normal operation MB89535A
MB89537A/538A
MB89537AC/
538AC
1.5 5.5 V RAM status in stop
mode
2.7* 5.5 V Range warranted for
normal operation MB89P538
MB89PV530
1.5 5.5 V RAM status in stop
mode
3.5 5.5 V Range warranted for
normal operation MB89F538
3.0 5.5 V RAM status in stop
mode
2.4 3.6 V Range warranted for
normal operation MB89F538L
1.5 3.6 V RAM status in stop
mode
AVR 3.5 AVCC V
Operating temperature TA−40 +85 °C
MB89530A Series
34 DS07-12547-7E
• Operating voltage vs. operating frequency (MB89P538/MB89PV530)
• Operating voltage vs. operating frequency (MB89535A/537A/538A/537AC/538AC)
5.5
5.0
4.0
3.5
3.0
2.0
2.2
2.7
1.0
01.0
4.0
2.0
2.0
3.0 4.0 5.0
0.8
6.0 7.0 8.0 9.0 10.0
0.4
11.0 12.0
12.5
0.32
Range of warr anted a nalo g pre c ision : VCC = AVCC = 3.5 V to 5.5 V
Operating voltage VCC (V)
Operating frequency (MHz)
(at instruction cycle = 4 / FCH)
Minimum instruction execution time (Instruction cycles) (µs)
indicates warranted operation at TA = −10 °C to +55 °C
5.5
5.0
4.0
3.5
3.0
2.0
2.2
2.7
1.0
01.0
4.0
2.0
2.0
3.0 4.0 5.0
0.8
6.0 7.0 8.0 9.0 10.0
0.4
11.0 12.0
12.5
0.32
Range of warr anted analog precision : VCC = AVCC = 3.5 V to 5.5 V
Operating voltage VCC (V)
Operating frequency (MHz)
(at instruction cycle = 4 / FCH)
Minimum instruction execution time (Instruction cycles) (µs)
MB89530A Series
DS07-12547-7E 35
• Operating voltage vs. operating frequency (MB89F538)
•Operating voltage vs. operating frequency (MB89F538L)
5.5
5.0
4.0
3.5
3.0
2.0
1.0
01.0
4.0
2.0
2.0
3.0 4.0 5.0
0.8
6.0 7.0 8.0 9.0 10.0
0.4
11.0 12.0
12.5
0.32
Range of warra nted analog precision : VCC = AVCC = 3.5 V to 5.5 V
Operating voltage VCC (V)
Operating frequency (MHz)
Minimum instruction execution time (Instruction cycles) (µs)
4.0
3.6
3.0
2.4
2.0
1.0
01.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0
12.5
4.0 2.0 0.8 0.4 0.32
Range of warranted analog precision : VCC = AVCC = 2.4 V to 3.6 V
Operating voltage VCC (V)
Operating frequency (MHz)
(at instruction cycle = 4 / FCH)
Minimum instruction execution time (Instruction cycles) (µs)
MB89530A Series
36 DS07-12547-7E
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconducto r device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data shee t. Users consider ing application outside th e listed cond itions are advised t o contact
their representatives beforehand.
MB89530A Series
DS07-12547-7E 37
3. DC Characteristics
(1) Supply Voltage at 5.0 (V) (except MB89F538L)
(AVCC = VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
(Continued)
Parameter Symbol Pin name Condi-
tion Value Unit Remarks
Min Typ Max
“H” level
input voltage
VIH
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P64,
SI1, SI2
⎯0.7 VCC ⎯VCC + 0.3 V
VIHS
RST, MOD0, MOD1,
INT20 to INT27, UCK1,
UI1, INT10 to INT13,
SCK1, EC, PWCK,
PWC, SCK2, UCK2,
UI2, ADST
⎯0.8 VCC ⎯VCC + 0.3 V
VIHSMB SCL, SDA ⎯VSS + 1.4 ⎯VSS + 5.5 V With SMB input
buffer selected*1
VIHI2C ⎯0.7 VCC ⎯VSS + 5. 5 V With I2C input
buffer selected*1
“L” level
input voltage
VIL
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P64,
SI1, SI2
⎯VSS − 0.3 ⎯0.3 VCC V
VILS
RST, MOD0, MOD1,
INT20 to INT27, UCK1,
UI1, INT10 to INT13,
SCK1, EC, PWCK,
PWC, SCK2, UCK2,
UI2, ADST
⎯VSS − 0.3 ⎯0.2 VCC V
VILSMB SCL, SDA ⎯VSS − 0.3 ⎯VSS + 0.6 V With SMB input
buffer selected*1
VILI2C ⎯VSS − 0.3 ⎯0.3 VCC VWith I2C input
buffer selected*1
Open drain
output applied
voltage
VD1 P50 to P57 ⎯VSS − 0.3 ⎯VCC + 0.3 V
VD2 P42, P43 VSS + 5.5 V
“H” level
output voltage VOH
P00 to P07, P10 to P17,
P20 to P24, P30 to P37,
P40, P41, P44 t o P47
IOH =
−2.0 mA 4.0 ⎯⎯V
P25 to P27 IOH =
−3.0 mA
“L” level
output
voltage VOL
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
RST
IOL =
4.0 mA ⎯⎯0.4 V
MB89530A Series
38 DS07-12547-7E
(AVCC = VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Input leak
current
(Hi-Z output
leak current)
ILI
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P60 to P64
0.0 V < VI <
VCC −5⎯+5µAWith no pull-up re-
sistance specified
Open drain
output leak
current ILIOD P42, P43 0.0 V < VI <
VSS + 5.5 V ⎯⎯ 5µA
Pull-up
resistance RUP
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40, P41, P44 to P46,
P47*2, P60 to P64, RST
⎯25 40 100 kΩ
With pull-up
resistance speci-
fied. The RST
signal is excluded.
Pull-down
resistance RDOWN MOD0, MOD1 ⎯25 40 100 kΩOnly for mask
ROM product.
Supply
current
ICC1
VCC
FCH = 10.0 MHz
VCC = 5.0 V
tinst = 0.4 µs
⎯15 20 mA MB89P538/
PV530
⎯610mAMB89F538
⎯813mA
MB89535A/7A/8A
MB89537AC/
538AC
ICC2 FCH = 10.0 MHz
VCC = 5.0 V
tinst = 6.4 µs
⎯58.5mA
MB89P538/
PV530
⎯1.5 3 mA MB89F538
⎯1.5 3 mA MB89535A/7A/8A
MB89537AC/
538AC
ICCS1 FCH = 10.0 MHz
VCC = 5.0 V
tinst = 0.4 µs
⎯57mA
Sleep mode
MB89P538/
PV530
⎯35mA
Sleep mode
MB89F538
⎯2.5 5 mA
Sleep mode
MB89535A/7A/8A
MB89537AC/
538AC
ICCS2 FCH = 10.0 MHz
VCC = 5.0 V
tinst = 6.4 µs
⎯1.5 3 mA Sleep mode
MB89P538/
PV530
⎯12mA
Sleep mode
MB89F538
⎯12mA
Sleep mode
MB89535A/7A/8A
MB89537AC/
538AC
MB89530A Series
DS07-12547-7E 39
(Continued) (AVCC = VCC = 5.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
*1 : The MB89PV530/P538/F538/537AC/538AC have a built-in I2C function, and a choice of inp u t buffers by
software setting.
MB89535A /5 37 A/5 3 8A have no built-i n I2C functions, and therefore this standard does not apply.
*2 : For P47 of MB89F538, pull-up resistor is not mounted as this pin is used as MOD2 pin.
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Supply
current
ICCL
VCC
FCL =
32.768 kHz
VCC = 5.0 V
TA = +25 °C
⎯37mA
Sub mode
MB89P538/
PV530
⎯400 800 µASub mode
MB89F538
⎯50 85 µA
Sub mode
MB89535A/7A/8A
MB89537AC/
538AC
ICCLS
FCL =
32.768 kHz
VCC = 5.0 V
TA = +25 °C
⎯30 50 µASub, sleep mode
MB89P538/
PV530
⎯15 30 µASub, sleep mode
MB89F538
⎯15 30 µA
Sub, sleep mode
MB89535A/7A/8A
MB89537AC/
538AC
ICCT
FCL =
32.768 kHz
VCC = 5.0 V
TA = +25 °C
⎯515µAWatch mode,
main stop
ICCH TA = +25 °C⎯310µA Sub, stop modes
IAAVCC FCH = 10.0 MHz ⎯46mA
A/D conversion
running
IAH TA = +25 °C⎯15µA A/D stopped
Input
capacitance CIN Except VCC, VSS, AVCC,
AVSS f = 1 MHz ⎯515pF
MB89530A Series
40 DS07-12547-7E
(2) Supply Voltage at 3.0 (V) (except MB89F538)
(AVCC = VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
(Continued)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
“H” level
input voltage
VIH
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P64,
SI1, SI2
⎯0.7 VCC ⎯VCC + 0.3 V
VIHS
RST, MOD0, MO D1,
INT20 to INT27, UCK1,
UI1, INT10 to INT13,
SCK1, EC, PWCK,
PWC, SCK2, UCK2,
UI2, ADST
⎯0.8 VCC ⎯VCC + 0.3 V
VIHSMB
SCL, SDA
⎯VSS + 1.4 ⎯VSS + 5.5 V With SMB
input buffer
selected*
VIHI2C ⎯0.7 VCC ⎯VSS + 5.5 V With I2C
input buffer
selected*
“L” level
input voltage
VIL
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P60 to P64,
SI1, SI2
⎯VSS − 0.3 ⎯0.3 VCC V
VILS
RST, MOD0, MOD1,
INT20 to INT27, UCK1,
UI1, INT10 to INT13,
SCK1, EC, PWCK, PWC,
SCK2, UCK2, UI2, ADST
⎯VSS − 0.3 ⎯0.2 VCC V
VILSMB
SCL, SDA
⎯VSS − 0.3 ⎯VSS + 0.6 V With SMB
input buffer
selected*
VILI2C ⎯VSS − 0.3 ⎯0.3 VCC VWith I2C
input buffer
selected*
Open drain
output
applied
voltage
VD1 P50 to P57
⎯VSS − 0.3 ⎯
VCC + 0.3 V
VD2 P42, P43 VSS + 5.5 V
“H” level
output
voltage VOH
P00 to P07, P10 to P17,
P20 to P24, P30 to P37,
P40, P41, P44 to P47 IOH = −2.0 mA 2.4 ⎯⎯V
P25 to P27 IOH = −3.0 mA
“L” level
output
voltage VOL
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
RST
IOL = 4.0 mA ⎯⎯0.4 V
MB89530A Series
DS07-12547-7E 41
(Continued) (AVCC = VCC = 3.0 V, AVss = Vss = 0 V, TA = −40 °C to +85 °C)
* : The MB89PV530/P538/F538L/537AC/538AC have a built-in I2C function, and a choice of input buffers by software
setting.
MB89535A/537A/538A have no built-in I2C functions, and therefore this standard does not apply.
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Input leak
current
(Hi-Z output
leak current)
ILI
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P60 to P64
0.0 V < VI <
VCC −5⎯+5µAWith no pull-up
resistance
specified
Open drain
output leak
current ILIOD P42, P43 0.0 V < VI < VSS
+ 5.5 V ⎯⎯ 5µA
Pull-up
resistance RUP
P00 to P07, P10 to P17,
P20 to P27, P30 to P37,
P40, P41, P44 to P47,
P60 to P64, RST
⎯25 70 100 kΩ
With pull-up
resistance specified.
The RST signal is
excluded.
Pull-down
resistance RDOWN MOD0, MOD1 ⎯25 70 100 kΩ
Supply
current
ICC1
VCC
FCH = 10.0 MHz
tinst = 0.4 µs
⎯610mA
⎯⎯45 mA Flash memory
programming/erase
MB89F538L
ICC2 FCH = 10.0 MHz
tinst = 6.4 µs⎯1.5 3 mA
ICCS1 FCH = 10.0 MHz
tinst = 0.4 µs⎯2 4 mA Sleep mode
ICCS2 FCH = 10.0 MHz
tinst = 6.4 µs⎯1 2 mA Sleep mode
ICCL
FCL =
32.768 kHz
VCC = 3.0 V
TA = +25 °C
⎯13mA
Sub modes
MB89P538/PV530
⎯35 90 µASub modes
MB89F538L
⎯20 50 µASub modes
MB89535A/7A/8A
MB89537AC/538AC
ICCLS
FCL =
32.768 kHz
VCC = 3.0 V
TA = +25 °C
⎯15 30 µASub, sleep modes
ICCT
FCL =
32.768 kHz
VCC = 3.0 V
TA = +25 °C
⎯515µAWatch mode, main
stop
ICCH TA = +25 °C⎯15µA Sub, stop modes
IAAVCC FCH = 10.0 MHz ⎯13mA
A/D conversion
running
IAH TA = +25 °C⎯15µA A/D stopped
Input
capacitance CIN Except VCC, VSS, AVCC,
AVSS f = 1 MHz ⎯515pF
MB89530A Series
42 DS07-12547-7E
4. AC Characteristics
(1) Reset Timing (VCC = 5.0 V, AV ss = Vss = 0 V, TA = −40 °C to +85 °C)
Notes: • tHCYL is the main clock oscillator period.
•If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may
cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the
external reset pin (RST).
(2) Power-on Reset (AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Note : Be sure that the power supply will come on within the selected oscillator stabilization period. Also, when
varying the supply voltage during operation, it is recommended that the supply voltage be increased gradually .
Parameter Symbol Condition Value Unit
Min Max
RST “L” pulse width tZLZH ⎯48 tHCYL ⎯ns
Parameter Symbol Condition Value Unit Remarks
Min Max
Power on time tR⎯0.5 50 ms
Power shutoff time tOFF ⎯1⎯ms Waiting time until
power-on
RST 0.2 VCC0.2 VCC
tZLZH
V
CC
t
R
2.2 V
0.2 V 0.2 V 0.2 V
t
OFF
MB89530A Series
DS07-12547-7E 43
(3) Clock Timing Standards (AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Clock frequency FCH X0, X1
⎯
1⎯12.5 MHz Main clock
FCL X0A, X1A ⎯32.768 ⎯kHz Sub clock
Clock cycle time tHCYL X0, X1 80 ⎯1000 ns Main clock
tLCYL X0A, X1A ⎯30.5 ⎯µs Sub clock
Input clock pulse width
PWH
PWL X0 20 ⎯⎯ns External clock
PWHL
PWLL X0A ⎯15.2 ⎯µs External clock
Input clock rise,
fall time tCR
tCF X0 ⎯⎯10 ns External clock
• X0, X1 timing and application conditions
• Clock application conditions
tHCYL
PWH
tCR tCF
PWL
0.2 VCC 0.2 VCC 0.2 VCC
0.8 VCC 0.8 VCC
X0
X0 X1
C1C2
FCH
FCH
X0 X1
Using a crystal oscillator
or
ceramic oscillator Using an external clock
signal
Open
MB89530A Series
44 DS07-12547-7E
(4) Instruction Cycle (AVss = Vss = 0 V, TA = −40 °C to +85 °C)
Parameter Symbol Rated value Unit Remarks
Instruction cycle
(minimum instruction
execution time) tinst
4/FCH, 8/FCH, 16/FCH, 64/FCH µsOperating at FCH = 12 .5 MHz
(4/FCH)
tinst = 0.32 µs
2/FCL µsOperating at FCL = 32.768 kHz
tinst = 61.036 µs
• X0A, X1A timing and application conditions
• Clock application conditions
tLCYL
PWHL
tCR tCF
PWLL
0.2 VCC 0.2 VCC 0.2 VCC
0.8 VCC 0.8 VCC
X0A
X0A X1A
Rd
X0A X1A
C1C2
FCL
FCL
Using a crystal oscillator
or
ceramic oscillator
Using an external clock
signal
Open
MB89530A Series
DS07-12547-7E 45
(5) Serial I/O Timing (VCC = 5.0 V, AV ss = Vss = 0 V, TA = −40 °C to +85 °C)
Note : For tinst refer to “ (4) Instruction Cycle”.
Parameter Symbol Pin name Condition Value Unit
Min Max
Serial clock cycle time tSCYC SCK, UCK Internal
clock
operation
2 tinst ⎯µs
SCK↓→SO tSLOV SCK, SO, UCK, UO −200 +200 ns
Valid SI→SCK↑tIVSH SI, SCK, UI, UCK 200 ⎯ns
SCK↑→valid SI hold time tSHIX SCK, SI, UCK, UI 200 ⎯ns
Serial clock “H” pulse width tSHSL SCK, UCK External
clock
operation
1 tinst ⎯µs
Serial clock “L” pulse width tSLSH 1 tinst ⎯µs
SCK↓→SO time tSLOV SCK, SO, UCK, UO 0 200 ns
Valid SI→SCK↑tIVSH SI, SCK, UI, UCK 200 ⎯ns
SCK↑→ valid SI hold time tSHIX SCK, SI, UCK, UI 200 ⎯ns
Internal shift clock mode
External shift clock mode
SCK
UCK
SO
UO
SI
UI
tSCYC
tIVSH
tSLOV
tSHIX
0.8 V
0.8 V
2.4 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.8 V
2.4 V
SCK
UCK
SO
UO
SI
UI
tSLSH tSHSL
tIVSH
tSLOV
tSHIX
0.2 VCC
0.8 V
2.4 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
0.2 VCC 0.8 VCC0.8 VCC
MB89530A Series
46 DS07-12547-7E
(6) Peripheral Input Timing (VCC = 5.0 V, AV ss = Vss = 0 V, TA = −40 °C to +85 °C)
Note : Fo r tinst refer to “ (4 ) Ins truction Cyc l e” .
Parameter Symbol Pin name Condition Value Unit
Min Max
Peripheral input “H” level
pulse width 1 tILIH1 INT10 to INT13,
INT20 to INT27,
EC, PWC, PWCK
⎯2 tinst ⎯µs
Peripheral input “L” level
pulse width 1 tIHIL1 ⎯2 tinst ⎯µs
Peripheral input “H” level
pulse width 2 tILIH2 ADST ⎯28 tinst ⎯µs
Peripheral input “L” level
pulse width 2 tIHIL2 ⎯28 tinst ⎯µs
EC, INT, PWC, PWCK tIHIL1 tILIH1
0.2 VCC 0.2 VCC
0.8 VCC0.8 VCC
ADSTtIHIL2 tILIH2
0.2 VCC 0.2 VCC
0.8 VCC0.8 VCC
MB89530A Series
DS07-12547-7E 47
(7) I2C Timing (VCC = 5.0 V, AV ss = Vss = 0 V, TA = −40 °C to +85 °C)
Notes : • For tinst refer to “ (4) Instruction Cycle”.
• The v alue “m” in t he abov e tab le is t he v alue from the shift cloc k frequency settin g bits (CS4, CS3) in t he
I2C clock control register “ICCR”. For details, refer to the register description in the hardware manual.
• The v alue ’n ’ in the abo v e tab l e is the value from the shif t cloc k fr equency se tting bits (CS2, CS0) in the
I2C cloc k control register “ICCR”. For details, refer to the register description in the hardware manual.
• tDOSU appears when the interrupt period is longer than the SCL “L” width.
• The rated values for SDA and SCL assume a start up time of 0 ns.
Parameter Symbol Pin
name Condition Value Unit Remarks
Min Max
Start condition outp u t tSTA SCL
SDA ⎯1 / 4 tinst ×
m × n − 20 1 / 4 tinst ×
m × n + 20 ns Master
only
Stop condition outp ut tSTO SCL
SDA ⎯1 / 4 tinst ×
(m × n + 8) − 20 1 / 4 tinst ×
(m × n + 8) + 20 ns Master
only
Start condition dete ct ion tSTA SCL
SDA ⎯1 / 4 tinst × 6 + 40 ⎯ns
Stop condition dete ctio n tSTO SCL
SDA ⎯1 / 4 tinst × 6 + 40 ⎯ns
Restart condition output tSTASU SCL
SDA ⎯1 / 4 tinst ×
(m × n + 8) − 20 1 / 4 tinst ×
(m × n + 8) + 20 ns Master
only
Restart condition detection tSTASU SCL
SDA ⎯1 / 4 tinst × 4 + 40 ⎯ns
SCL output “L” width tLOW SCL ⎯1 / 4 tinst ×
m × n − 20 1 / 4 tinst ×
m × n + 20 ns Master
only
SCL output “H” width tHIGH SCL ⎯1 / 4 tinst ×
(m × n + 8) − 20 1 / 4 tinst ×
(m × n + 8) + 20 ns Master
only
SDA output delay time tDO SDA ⎯1 / 4 tinst × 4 − 20 1 / 4 tinst × 4 + 20 ns
Setup after SDA output
interrupt interval tDOSU SDA ⎯1 / 4 tinst × 4 − 20 ⎯ns
SCL input “L” width tLOW SCL ⎯1 / 4 tinst × 6 + 40 ⎯ns
SCL input “H” width tHIGH SCL ⎯1 / 4 tinst × 2 + 40 ⎯ns
SDA input setup tSU SDA ⎯40 ⎯ns
SDA input hold tHO SDA ⎯0⎯ns
MB89530A Series
48 DS07-12547-7E
• I2C interface [Data sending (master/slave) ]
• I2C interface [Data receiving (master/slave) ]
9
ACK
tDO tSU tSU tDOSU
tDO
tHOtLOWtSTAtSTASU
SDA
SCL 1
SDA
SCL
67 89
tSU
tHIGH tLOW
tHO tDO tDO tDOSU
tSTO
ACK
MB89530A Series
DS07-12547-7E 49
5. A/D Conver ter Electrical Characteristics
(1) MB89535A/537A/537AC/538A/538AC/P538/PV530
(VCC = 3.5 V to 5.5 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C)
* : Includes sampling time.
Note : For tinst refer t o “4. AC Characteristics (4) Instruction Cycle”.
(2) MB89F538 (VCC = 3.5 V to 5.5 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C)
* : Includes sampling time.
Note : For tinst refer t o “4. AC Characteristics (4) Instruction Cycle”.
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Resolution capability
⎯
⎯
⎯⎯⎯10 bit
AVCC = VCC
Total error
AVR = AVCC
⎯⎯±3.0 LSB
Linear error ⎯⎯±2.5 LSB
Differential linear error ⎯⎯±1.9 LSB
Zero transition voltage VOT AVSS −
1.5 LSB AVSS +
0.5 LSB AVSS +
2.5 LSB V
Full scale transition
voltage VFST AVR −
3.5 LSB AVR −
1.5 LSB AVR +
1.5 LSB V
Inter-channel varia tion
⎯
⎯⎯4.0 LSB
Conversion time
⎯
⎯60 tinst ⎯µs*
Sampling time ⎯16 tinst ⎯µs
Analog input current IAIN AN0 to
AN7 ⎯⎯10 µA
Analog input voltage VAIN 0⎯AVR V
Reference voltage ⎯AVR AVSS + 3.5 ⎯AVCC V
Reference voltage
supply current IRA/D running ⎯400 ⎯µA
IRH A/D off ⎯⎯ 5µA
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Resolution capability
⎯
⎯
⎯⎯⎯10 bit
AVCC = VCC
Total error
AVR = AVCC
⎯⎯±5.0 LSB
Linear error ⎯⎯±2.5 LSB
Differential linear error ⎯⎯±1.9 LSB
Zero transition voltage VOT AVSS −
1.5 LSB AVSS +
0.5 LSB AVSS +
4.5 LSB V
Full scale transition
voltage VFST AVR −
6.5 LSB AVR −
1.5 LSB AVR +
1.5 LSB V
Inter-channel varia tion
⎯
⎯⎯4.0 LSB
Conversion time
⎯
⎯60 tinst ⎯µs*
Sampling time ⎯16 tinst ⎯µs
Analog input current IAIN AN0 to
AN7 ⎯⎯10 µA
Analog input voltage VAIN 0⎯AVR V
Reference voltage ⎯AVR AVSS + 3.5 ⎯AVCC V
Reference voltage
supply current IRA/D running ⎯400 ⎯µA
IRH A/D off ⎯⎯ 5µA
MB89530A Series
50 DS07-12547-7E
(3) MB89F538L (V CC = 2.4 V to 3.6 V, AVSS = VSS = 0 V, TA = −40 °C to +85 °C)
* : Includes sampling time
Parameter Symbol Pin name Condition Value Unit Remarks
Min Typ Max
Resolution capability
⎯
⎯
⎯⎯⎯10 bit
AVCC = VCC
Total error
AVR = AVCC
⎯⎯±3.0 LSB
Linear error ⎯⎯±2.5 LSB
Differential linear error ⎯⎯±1.9 LSB
Zero transition voltage VOT AVSS −
1.5 LSB AVSS +
0.5 LSB AVSS +
2.5 LSB V
Full scale transition
voltage VFST AVR −
3.5 LSB AVR −
1.5 LSB AVR +
1.5 LSB V
Inter-channel varia tion
⎯
⎯⎯4.0 LSB
Conversion time
⎯
⎯60 tinst ⎯µs*
Sampling time ⎯16 tinst ⎯µs
Analog input current IAIN AN0 to AN7 ⎯⎯10 µA
Analog input voltage VAIN 0⎯AVR V
Reference voltage ⎯
AVR
AVSS +
2.4 ⎯AVCC V
Reference voltage
supply current IRA/D running ⎯200 ⎯µA
IRH A/D off ⎯⎯ 5µA
MB89530A Series
DS07-12547-7E 51
(4) A/D Converter Terms and Definitions
• Resolution
The level of analog variation that can be distinguished by the A/D converter.
• Linear err or (unit : LSB)
The deviation between the value along a straight line connecting the zero transition point
(“00 0000 0000”←→“00 0000 0001”) of a device and the full- scale transition point
(“11 1111 1110”←→“11 1111 1111”) , compa red with the actual conversion values obtained.
• Differential linear error (Unit : LSB)
The deviation from the theoretical inp ut voltage required to prod uce a change of 1 LSB in output code.
• Total error (Unit : LSB)
The difference between theoretical conversion value and actual conversion value.
(Continued)
V
FST
1.5 LSB
1 LSB
0.5 LSB
V
OT
AVRAV
SS
3FF
H
3FE
H
3FD
H
004
H
003
H
002
H
001
H
V
NT
(1 LSB I N +
0.5 LSB)
AVRAV
SS
3FF
H
3FE
H
3FD
H
004
H
003
H
002
H
001
H
Theoretical input/output
characteristics
Analog input
Digital output
1 LSB = VFST − VOT
1022 (V)
Total error
Analog input
Digital output
Total error in digital output N = VNT − {1 LSB × N + 0.5 LSB}
1 LSB
Actual conversion
characteristics
Actual
conversion
characteristics
Theoretical
characteristics
MB89530A Series
52 DS07-12547-7E
(Continued)
004
H
003
H
002
H
001
H
AV
SS
AVR
3FF
H
3FE
H
3FD
H
3FC
H
AVRAV
SS
3FFH
3FEH
3FDH
004H
003H
002H
001H
AVSS AVR
VNT
(1 LSB × N + VOT)
V (N + 1) T
VNT
N + 1H
NH
N − 1H
N − 2H
AVSS AVR
Zero tran sition error
Analog input
Full-scale transition error
Digital output
Digital output
Linear error
Analog input
Differential linear error
Analog input
Digital output
Digital output
−1
Differential linear
error in digital output N V (N + 1) T − VNT
1 LSB
Actual
conversion
characteristics
Actual
conversion
characteristics
VOT (actual
measurement value)
Actual conversion
characteristics
VFST (actual
measurement
value)
Actual
conversion
characteristics
Actual conversion
characteristics
VOT (actual measurement value)
VFST
(actual
measure-
ment
value)
Theoretical
characteristics
Actual conversion
characteristics
Actual conversion
characteristics
Theoretical characteristics
Actual
conversion
characteristics
Analog input linear
error in digital output N VNT − {1 LSB × N + VOT}
1 LSB
Theoretical characteristics
= =
Analog input
MB89530A Series
DS07-12547-7E 53
(5) Precautionary Information
• Input Impedance of Analog Input Pins
The A/D converter of MB89530A has a sample & hold circuit as shown below, which uses a sample-and-hold
capacitor to obtain the voltage at the analog input pin for 8 instruction cycles f ollowing the start of A/D conversion.
F or this reason if the e xternal circuits pro viding the analog input sig nal have high output impedance , the analog
input voltage may not stabilize within the analog input sampling time. It is therefore recommended that the output
impedance of external circuits be reduced to 10 kΩ or less.
• About error
The smaller the absolute value |AVR - AVss| is, the greater the relative error becomes.
• Analog Input Equivalen t Circuit
C
RComparator
If analog input impedance is
10 kΩ or more, the use of a
capacitor of approximately
0.1 µF is recommended.
Analog input pin
Sample-and-hold circuit
Closes 8 instruction cycles
after the start of A/D conversion
Analog channel selector
MB89535A/537A/537AC/538A/538AC
C := 45 pF R := 2.2 kΩ
MB89F538
C := 30 pF R := 3.2 kΩ
MB89F538L
C := 49 pF R := 7.1 kΩ
MB89P538, MB8 9 P53 0
C := 64 pF R := 3.0 kΩ
MB89530A Series
54 DS07-12547-7E
6. Flash Memory
• Flash memory programming/erase characteristics
* : Excludes internal programming time before erase.
Parameter Conditions Value Unit Remarks
Min Typ Max
Sector erase
time
Per 1 sector,
Constant value independe nt
with sector capacitance TA = +25 °C,
VCC = 5.0 V
⎯115s*
Programming
time Per 1 byte ⎯8 3600 µs
Chip erase time ⎯5⎯s*
Program/Erase cycle ⎯10000 ⎯⎯cycle
MB89530A Series
DS07-12547-7E 55
■EXAMPLE CHARACTERISTICS (MB89538A)
(1) Power Supply Current (Extern al Clo ck)
(2) “H” Level Input Voltage/ “L” Level Input Volta ge (CMOS Input)
(3) “H” Level Input Voltage / ”L” Level Input Voltage (Hysteresis Input)
I
CC1
vs. V
CC
0
2
4
6
8
10
12
14
234567
VCC (V)
ICC1 (mA)
(TA = + 25 ˚C)
12.5 MHz
1 MHz
2 MHz
5 MHz
8 MHz
10 MHz
I
CCS1
vs. V
CC
0
1
2
3
4
5
234567
VCC (V)
ICCS1 (mA)
(TA = + 25 ˚C)
12.5 MHz
1 MHz
2 MHz
5 MHz
8 MHz
10 MHz
V
IN
vs. V
CC
0
1
2
3
4
234567
VCC (V)
VIN (V)
(TA = + 25 ˚C)
V
IN
vs. V
CC
0
1
2
3
4
234567
VCC (V)
VIN (V)
(TA = + 25 ˚C)
V
IH
V
IL
MB89530A Series
56 DS07-12547-7E
(4) Pull-up Resistor Value
(5) ”H” Level Output Voltage
(6) ”L” Level Output Voltage
RPULL vs. VCC
10
100
1000
034526
VCC (V)
Pull-up (kΩ)
(TA = + 25 ˚C)
1
VCC - VOH1 vs. IOH
0.0
1.0
1.2
1.4
1.6
0 468210
IOH
(mA)
VCC - VOH1
(V)
(T
A
= + 25 ˚C, V
CC
= 5 V)
0.4
0.2
0.6
0.8
VCC - VOH2 vs. IOH
0.0
0.5
0.6
0.7
0.8
0 468210
IOH
(mA)
VCC - VOH2
(V)
(T
A
= + 25 ˚C, V
CC
= 5 V)
0.2
0.1
0.3
0.4
0.9
VCC - VOL vs. IOL
0.0
0.5
0.6
0.7
0.8
0 468210
IOL
(mA)
VCC - VOL
(V)
(T
A
= + 25 ˚C, V
CC
= 5 V)
0.2
0.1
0.3
0.4
0.9
MB89530A Series
DS07-12547-7E 57
(7) AD Converter Characteristic Example
-2.5
0.0
1.5
2.0
2.5
0 640 768 896512 1024
(V
CC
= AVR = 5 V, F
CH
= 10 MHz)
-1.5
-2.0
-1.0
-0.5
3.0
128 256 384
-3.0
1.0
0.5
-2.5
0.0
1.5
2.0
2.5
0 640 768 896512 1024
-1.5
-2.0
-1.0
-0.5
128 256 384
1.0
0.5
-4.0
0.0
2.0
3.0
4.0
0 640 768 896512 1024
(V
CC
= AVR = 5 V, F
CH
= 10 MHz)
-2.0
-3.0
-1.0
128 256 384
1.0
Linearity Error
Error (LSB)
Conversion charact eristic
Differential linearity error
Error (LSB)
Conversion charact eristic
Total Error
Error (LSB)
Conversion characteristic
MB89530A Series
58 DS07-12547-7E
■MASK OPTIONS
* : FCH: Main clock frequency
No Part number
MB89535A
MB89537A
MB89537AC
MB89538A
MB89538AC
MB89F538-101
MB89F538-201
MB89F538L-101
MB89F538L-201
MB89P538-101
MB89P538-201 MB89PV530-101
MB89PV530-201
Method of
specification Specify at time
of mask order Setting
not possible Setting
not possible Setting
not possible
1
Main clock
Select oscillator
stabilization wait period
(FCH* = 10 MHz)
approx.214/FCH*
(approx.1.6 ms)
approx.217/FCH*
(approx.13.1 ms)
approx.218/FCH*
(approx.26.2 ms)
Selection
available 218/FCH*
(approx. 26.2 ms) 218/FCH*
(approx. 26.2 ms) 218/FCH*
(approx. 26.2 ms)
2Clock mode selection
• 2-system clock mode
• 1-system clock mode
Selection
available • 101 : 1-system clock mode
• 201 : 2-system clock mode
MB89530A Series
DS07-12547-7E 59
■ORDERING IN FORMATION
Part number Package Remarks
MB89535AP
MB89537AP
MB89537ACP
MB89538AP
MB89538ACP
MB89P538-101P
MB89P538-201P
MB89F538-101P
MB89F538-201P
MB89F538L-101P
MB89F538L-201P
DIP-64P-M01 MB89535AP, MB89537AP and MB89538AP
do not have I2C functions.
MB89535APF
MB89537APF
MB89537ACPF
MB89538APF
MB89538ACPF
MB89P538-101PF
MB89P538-201PF
MB89F538-101PF
MB89F538-201PF
MB89F538L-101PF
MB89F538L-201PF
FPT-64P-M06 MB895 35APF, MB89537APF and
MB89538APF do not have I2C functions.
MB89535APMC
MB89537APMC
MB89537ACPMC
MB89538APMC
MB89538ACPMC
MB89P538-101PMC
MB89P538-201PMC
MB89F538-101PMC
MB89F538-201PMC
MB89F538L-101PMC
MB89F538L-201PMC
FPT-64P-M23 MB89535APMC, MB89537APMC and
MB89538APM C do not ha ve I2C funct i on s.
MB89535APMC1
MB89537APMC1
MB89537ACPMC1
MB89538APMC1
MB89538ACPMC1
FPT-64P-M24 MB89535APMC1, MB89537APMC1 and
MB89538APMC1 do not have I2C functions.
MB89535APV4
MB89537APV4
MB89537ACPV4
MB89538APV4
MB89538ACPV4
MB89F538L-101PV4
MB89F538L-201PV4
LCC-64P-M19 MB89535APV4, MB89537APV4, and
MB89538APV4 do not have I2C functions.
MB89PV530-101C
MB89PV530-201C MDP-64C-P02
MB89PV530-101CF
MB89PV530-201CF MQP-64C-P01
MB89530A Series
60 DS07-12547-7E
■PACKAGE DIMENSIONS
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/ (Continued)
64-pin plastic SH-DIP Lead pitch 1.778mm(70mil)
Package width ×
package length 17 × 58 mm
Sealing method Plastic mold
Mounting height 5.65 mm MAX
64-pin plastic SH-DIP
(DIP-64P-M01)
(DIP-64P-M01)
C
2001-2008 FUJITSU MICROELECTRONICS LIMITED D64001S-c-4-6
58.00
+0.22
–0.55 +.009
–.022
2.283
17.00±0.25
(.669±.010)
3.30
+0.20
–0.30
.130
–.012
+.008
+.028
–.008
.195
–0.20
+0.70
4.95
+.016
–.008
.0543
–0.20
+0.40
1.3781.778(.0700) 0.47±0.10
(.019±.004) 1.00
+0.50
–0
.039
–.0
+.020
+.020
–.007
.028
–0.19
+0.50
0.70
19.05(.750)
(.011±.004)
0.27±0.10
0~15
INDEX-2
INDEX-1
M
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note: Pins width and pins thickness include plating thickness.
MB89530A Series
DS07-12547-7E 61
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/ (Continued)
64-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 10.0 × 10.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Weight 0.32 g
Code
(Reference) P-LFQFP64-10×10-0.50
64-pin plastic LQFP
(FPT-64P-M24)
(FPT-64P-M24)
LEAD No.
Details of "A" part
0.25(.010)
(Stand off)
(.004±.004)
0.10±0.10
(.024±.006)
0.60±0.15
(.020±.008)
0.50±0.20
1.50
+0.20
–0.10
+.008
–.004
.059
0˚~8˚
"A"
0.08(.003)
(.006±.002)
0.145±0.055
0.08(.003)
M
(.008±.002)
0.20±0.05
0.50(.020)
12.00±0.20(.472±.008)SQ
10.00±0.10(.394±.004)SQ
INDEX
49
64
3348
17
32
161
2005 FUJITSU LIMITED F64036S-c-1-1
C
(Mounting height)
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2005-2008 FUJITSU MICROELECTRONICS LIMITED F64036S-c-1-2
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.
MB89530A Series
62 DS07-12547-7E
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/ (Continued)
64-pin plastic QFP L ead pitch 1.00 mm
Package width ×
package length 14 × 20 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 3.35 mm MAX
Code
(Reference) P-QFP64-14×20-1.00
64-pin plastic QFP
(FPT-64P-M06)
(FPT-64P-M06)
C
2003-2008 FUJITSU MICROELECTRONICS LIMITED F64013S-c-5-6
0.20(.008)
M
18.70±0.40
(.736±.016)
14.00±0.20
(.551±.008)
1.00(.039)
INDEX
0.10(.004)
119
20
32
52
64
3351
20.00±0.20(.787±.008)
24.70±0.40(.972±.016)
0.42±0.08
(.017±.003)
0.17±0.06
(.007±.002)
0~8
°
1.20±0.20
(.047±.008)
3.00
+0.35
–0.20
(Mounting height)
.118
+.014
–.008
0.25
+0.15
–0.20
.010
+.006
–.008
(Stand off)
Details of "A" part
"A" 0.10(.004)
*
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.
MB89530A Series
DS07-12547-7E 63
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/ (Continued)
64-pin plastic LQFP Lead pitch 0.65 mm
Package width ×
package length 12.0 × 12.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference) P-LFQFP64-12×12-0.65
64-pin plastic LQFP
(FPT-64P-M23)
(FPT-64P-M23)
C
2003 FUJITSU LIMITED F64034S-c-1-1
0.65(.026)
0.10(.004)
116
17
32
49
64
3348
*12.00±0.10(.472±.004)SQ
14.00±0.20(.551±.008)SQ
INDEX
0.32±0.05
(.013±.002)
M
0.13(.005)
0.145±0.055
(.0057±.0022)
"A"
.059
–
.004
+.008
–
0.10
+0.20
1.50
0~8˚
0.25(.010)
(Mounting height)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2003-2008 FUJITSU MICROELECTRONICS LIMITED F64034S-c-1-2
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3)Pins width do not include tie bar cutting remainder.
MB89530A Series
64 DS07-12547-7E
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/ (Continued)
64-pin plastic BCC Lead pitch 0.50 mm
Package width ×
package length 9.00 mm × 9.00 mm
Sealing method Plastic mold
Mounting height 0.80 mm MAX
Weight 0.10g
64-pin plastic BCC
(LCC-64P-M19)
(LCC-64P-M19)
C
2002 FUJITSU LIMITED C64019S-c-1-1
1
17
4933
0.50±0.10
(.020±.004)
0.50(.020)
TYP
8.10(.319)
TYP
8.20(.323)
TYP
"C" "B"
"A"
7.00(.276)REF
7.00(.276)
REF
0.50±0.10
(.020±.004)
0.50(.020)
TYP
8.10(.319)TYP
8.20(.323)TYP
(0.80(.031)MAX)
0.075±0.025
(.003±.001)
17
3349
1
9.00±0.10(.354±.004)
(Stand off)
9.00±0.10
(.354±.004)
0.05(.002) 0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
Details of "B" part
C0.2(.008)
0.30±0.06
(.012±.002)
0.70±0.06
(.028±.002)
Details of "A" part Details of "C" part
0.55±0.06
(.022±.002)
0.55±0.06
(.022±.002)
(Mount height)
INDEX AREA
8.25(.325)REF
8.25(.325)
REF
"A"
(.024±.002)
0.60±0.06
0.30±0.06
(.012±.002)
0.14(.006)MIN.
©2002-2008 FUJITSU MICROELECTRONICS LIMITED C64019S-c-1-2 Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB89530A Series
DS07-12547-7E 65
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/ (Continued)
64-pin ceramic MDIP Lead pitch 1.778mm (70mil)
Row spacing 19.05mm (750mil)
Motherboard
materialCeramic
Mounted
packing materialPlastic
64-pin ceramic MDIP
(MDP-64C-P02)
(MDP-64C-P02)
+0.13
–0.08
+.005
–.003
INDEX AREA
0°~9°
(.750±.012)
19.05±0.30
0.46
.018
(2.240±.025)
(.010±.002)
0.25±0.05
(.050±.010)
1.27±0.25
(.135±.015)
3.43±0.38
55.12(2.170)REF
(.035±.005)
0.90±0.13
(.070±.010)
1.778±0.25
10.16(.400)MAX
33.02(1.300)REF
(.100±.010)
2.54±0.25
(.738±.012)
18.75±0.30
TYP
15.24(.600)
56.90±0.64
1994-2008 FUJITSU MICROELECTRONICS LIMITED M64002SC-1-5
C
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB89530A Series
66 DS07-12547-7E
(Continued)
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
64-pin ceramic MQFP Lead pitch 1.00 mm
Lead shape Straight
Motherboard
materialCeramic
Mounted package
materialPlastic
64-pin ceramic MQFP
(MQP-64C-P01)
(MQP-64C-P01)
C
1994-2008 FUJITSU MICROELECTRONICS LIMITED M64004SC-1-4
15.58±0.20
(.613±.008)
16.30±0.33
(.642±.013)
18.70(.736)TYP
INDEX AREA
0.30(.012)
TYP
1.27±0.13
(.050±.005)
22.30±0.33
(.878±.013)
24.70(.972)
TYP
10.16(.400)
TYP
12.02(.473)
TYP14.22(.560)
TYP
18.12±0.20
(.713±.008)
1.27±0.13
(.050±.005) 0.30(.012)TYP
7.62(.300)TYP
9.48(.373)TYP
11.68(.460)TYP
0.50(.020)TYP 0.15±0.05
(.006±.002)
10.82(.426)
MAX
0.40±0.10
(.016±.004) .047
Ð.008
+.016
Ð0.20
+0.40
1.20
0.40±0.10
(.016±.004)
1.00±0.25
(.039±.010)
18.00(.709)
TYP
1.00±0.25
(.039±.010)
12.00(.472)TYP
.047
Ð.008
+.016
Ð0.20
+0.40
1.20
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB89530A Series
DS07-12547-7E 67
■MAIN CHANGES IN THIS EDITION
Page Section Change Re su lt s
⎯⎯
Added the part number.
MB89F538L
⎯⎯
Changed the package code.
FPT-64P-M03 → FPT-64P-M24
FPT-64P-M09 → FPT-64P-M23
Deleted LCC-64P-M 1 6 .
19 ■ PROGRAMMING AND ERASING FLASH
MEMORY ON THE MB89F538/F538L Deleted the “6. ROM Programmer Adaptor and
Recommended ROM Programmers”.
20 ■ ONE-TIME WRITING SPECIFICATIONS
WITH PROM AND EPROM
MICROCONTROLLERS D ele te d th e “• ROM writer adapters”.
22 ■ EPROM WRITING TO PIGGY-BACK/
EVALUATION CHIPS Deleted the “• Writer adapter”.
49 ■ ELECTRICAL CHARACTERISTICS
5. A/D Converter Electrical Characteristics Changed the unit of Zero transition voltage and Full scale
transition voltage
mV → V
53 Changed the figure of “• Input Impedance of Analog Input
Pins”.
MB89530A Series
The vertical lines marked in the left side of the page show the changes.
59
■ ORDERING INFORMATION Added the order informations.
MB89F538L-101P, MB89F538L-201P
MB89F538L-101PF, MB89F538L-201PF
MB89F538L-101PMC, MB89F538L-201PMC
MB89F538L-101PV4, MB89F538L-201PV4
Changed the order informations.
MB89P538P-101 → MB89P538-101P
MB89P538P-201 → MB89P538-201P
MB89F538P-101 → MB89F538-101P
MB89F538P-201 → MB89F538-201P
MB89P538PF-101 → MB89P538-101PF
MB89P538PF-201 → MB89P538-201PF
MB89F538PF-101 → MB89F538-101PF
MB89F538PF-201 → MB89F538-201PF
MB89535APFM → MB89535APMC
MB89537APFM → MB89537APMC
MB89537ACPFM → MB89537ACPMC
MB89538APFM → MB89538APMC
MB89538ACPFM → MB89538ACPMC
MB89P588PFM-101 → MB89P538-101PMC
MB89P588PFM-201 → MB89P538-201PMC
MB89F538PFM-101 → MB89F538-101PMC
MB89F538PFM-201 → MB89F538-201PMC
MB89535APFV → MB89535APMC1
MB89537APFV → MB89537APMC1
MB89537ACPFV → MB89537 ACPM C 1
MB89538APFV → MB89538APMC1
MB89538ACPFV → MB89538 ACPM C 1
MB89PV530C-101 → MB89PV530-101C
MB89PV530C-201 → MB89PV530-201C
MB89PV530CF-101 → MB89PV530-101CF
MB89PV530CF-201 → MB89PV530-201CF
61 ■ PACKAGE DIMENSIONS Changed the package figure.
FPT-64P-M03 → FPT-64P-M24
63 Changed the package figure.
FPT-64P-M09 → FPT-64P-M23
Page Section Change Re su lt s
MB89530A Series
DS07-12547-7E 69
MEMO
MB89530A Series
70 DS07-12547-7E
MEMO
MB89530A Series
DS07-12547-7E 71
MEMO
MB89530A Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
F or further inf ormation please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408 -737-5999
http://www.fma.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
FUJITSU MICROELECTR ONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-36 88 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The informatio n, such as desc riptions of function and application circuit examples, in this document a re present ed solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of functio n and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual p roper ty right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and househo ld use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe p hysical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redund ancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Business & Media Promotion Dept.
