REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
ADP3412
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Dual MOSFET Driver
with Bootstrapping
FUNCTIONAL BLOCK DIAGRAM
VCC BST
DRVH
SW
DRVL
PGND
IN
DLY
OVERLAP
PROTECTION
CIRCUIT
ADP3412
FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High Side Drive
One PWM Signal Generates Both Drives
Programmable Transition Delay
Anticross-Conduction Protection Circuitry
APPLICATIONS
Multiphase Desktop CPU Supplies
Mobile Computing CPU Core Power Converters
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
VCC
BST
DRVH
SW
IN
DRVL
ADP3412
12V
CBST
PGND
1V
1V
Q1
Q2
DELAY
5V
DLY
D1
CDLY
Figure 1. General Application Circuit
GENERAL DESCRIPTION
The ADP3412 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs which are the two switches in a
nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propa-
gation delay and a 30 ns transition time. One of the drivers can
be bootstrapped and is designed to handle the high voltage
slew rate associated with “floating” high side gate drivers. The
ADP3412 includes overlapping drive protection (ODP) to pre-
vent shoot-through current in the external MOSFETs.
–2– REV. A
ADP3412–SPECIFICATIONS
1
Parameter Symbol Conditions Min Typ Max Unit
SUPPLY
Supply Voltage Range VCC 4.15 5.0 7.5 V
Quiescent Current ICC
Q
12 mA
PWM INPUT
Input Voltage High
2
2.0 V
Input Voltage Low
2
0.8 V
HIGH SIDE DRIVER
Output Resistance, Sourcing Current V
BST
– V
SW
= 4.6 V 2.5 5 Ω
Output Resistance, Sinking Current V
BST
– V
SW
= 4.6 V 2.5 5 Ω
Transition Times
3
(See Figure 2) tr
DRVH
, tf
DRVH
V
BST
– V
SW
= 4.6 V, C
LOAD
= 3 nF 20 35 ns
Propagation Delay
3, 4
(See Figure 2) tpdh
DRVH
V
BST
– V
SW
= 4.6 V 10 20 Note 5 ns
tpdl
DRVH
V
BST
– V
SW
= 4.6 V 25 ns
LOW SIDE DRIVER
Output Resistance, Sourcing Current VCC = 4.6 V 2.5 5 Ω
Output Resistance, Sinking Current VCC = 4.6 V 2.5 5 Ω
Transition Times
3
(See Figure 2) tr
DRVL
, tf
DRVL
VCC = 4.6 V, C
LOAD
= 3 nF 20 35 ns
Propagation Delay
3, 4
(See Figure 2) tpdh
DRVL
VCC = 4.6 V 30 ns
tpdl
DRVL
VCC = 4.6 V 25 ns
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA).
3
AC specifications are guaranteed by characterization but not production tested.
4
For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.
5
Maximum propagation delay = 40 ns + (1 ns/pF C
DLY
).
Specifications subject to change without notice.
(TA = 0ⴗC to 70ⴗC, VCC = 5 V, BST = 4 V to 26 V, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V
IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature Range . . . . . . 0°C to 125°C
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
θ
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.
ADP3412
–3–
REV. A
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Function
1BST Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW Pins
holds this bootstrapped voltage for the high side MOSFET as it is switched. The capacitor should be
chosen between 100 nF and 1 F.
2IN TTL-level input signal that has primary control of the drive outputs.
3DLY Low High Transition Delay. A capacitor from this pin to ground programs the propagation delay from
turn-off of the lower FET to turn-on of the upper FET. The formula for the low high transition delay
is DLY = C
DLY
× (1 ns/pF) + 20 ns. The rise time for turn-on of the upper FET is not included in the formula.
4VCC Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7SW This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating
return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-
on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the
high low transition delay is determined at this pin.
8DRVH Buck Drive. Output drive for the upper (buck) MOSFET.
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADP3412JR 0°C to 70°C 8-Lead Standard Small Outline Package (SOIC) SOIC-8
PIN CONFIGURATION
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
ADP3412
BST
IN
DLY
VCC
DRVH
SW
PGND
DRVL
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3412 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ADP3412
–4– REV. A
IN
DRVL
DRVH-SW
SW
tpdl
DRVL
tf
DRVL
tr
DRVH
tpdh
DRVH
tpdl
DRVH
tf
DRVH
tr
DRVL
V
TH
V
TH
1V
tpdh
DRVL
Figure 2. Nonoverlap Timing Diagram
(Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted)
DRVH
DRVL
IN
VCC = 5V
C
LOAD
= 3nF
V
SW
= 0V
VOLTAGE
TIME – ns
20ns/DIV
2V/DIV
TPC 1. DRVH Fall and DRVL Rise
Times
AMBIENT TEMPERATURE – ⴗC
30
25
0
08525
TIME – ns
50 75
20
15
10
5
35
RISE TIME
FALL TIME
VCC = 5V
C
LOAD
= 3nF
TPC 4. DRVL Rise and Fall Times vs.
Temperature
JUNCTION TEMPERATURE – ⴗC
30
25
0
025
TIME – ns
50 75
tpdl
DRVH
VCC = 5V
C
LOAD
= 3nF
tpdl
DRVL
20
15
10
5
100 125
TPC 7. Propagation Delay vs.
Temperature
Typical Performance Characteristics–ADP3412
–5–
REV. A
DRVL
DRVH
IN
VCC = 5V
CLOAD = 3nF
CDLY = 20pF
VOLTAGE
TIME – ns
20ns/DIV
2V/DIV
TPC 2. DRVL Fall and DRVH Rise
Times
CAPACITANCE – nF
40
061
TIME – ns
2345
VCC = 5V
T
A
= 25ⴗC
30
20
10
0
DRVH
DRVL
TPC 5. DRVH and DRVL Rise Times
vs. Load Capacitance
IN FREQUENCY – kHz
40
0
SUPPLY CURRENT – mA
35
20
15
10
5
30
25
01200200 400 600 800 1000
VCC = 5V
T
A
= 25ⴗC
C
LOAD
= 3nF
TPC 8. Supply Current vs.
Frequency
JUNCTION TEMPERATURE – ⴗC
30
25
008525
TIME – ns
50 75
20
15
10
5
RISE TIME
FALL TIME
VCC = 5V
C
LOAD
= 3nF
TPC 3. DRVH Rise and Fall Times vs.
Temperature
CAPACITANCE – nF
35
0
TIME – ns
30
25
20
15
10
5
0
123456
VCC = 5V
T
A
= 25ⴗC
DRVH
DRVL
TPC 6. DRVH and DRVL Fall Times
vs. Load Capacitance
JUNCTION TEMPERATURE – ⴗC
11.0
10.5
9.0
0 12525
SUPPLY CURRENT – mA
50 75 100
10.0
9.5
VCC = 5V
f
IN
= 250kHz
C
LOAD
= 3nF
TPC 9. Supply Current vs.
Temperature
ADP3412
–6– REV. A
THEORY OF OPERATION
The ADP3412 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high side and the low side FETs. Each driver
is capable of driving a 3 nF load with only a 20 ns transition time.
A more detailed description of the ADP3412 and its features
follows. Refer to the General Application Circuit in Figure 1.
Low Side Driver
The low side driver is designed to drive low R
DS(ON)
N-channel
MOSFETs. The maximum output resistance for the driver is
5Ω for both sourcing and sinking gate current. The low output
resistance allows the driver to have 20 ns rise and fall times into
a 3 nF load. The bias to the low side driver is internally con-
nected to the VCC supply and PGND.
The driver’s output is 180 degrees out of phase with the PWM
input.
High Side Driver
The high side driver is designed to drive a floating low R
DS(ON)
N-channel MOSFET. The maximum output resistance for the
driver is 5 Ω for both sourcing and sinking gate current. The
low output resistance allows the driver to have 20 ns rise and fall
times into a 3 nF load. The bias voltage for the high side driver
is developed by an external bootstrap supply circuit, which is
connected between the BST and SW Pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, C
BST
. When the ADP3412 is starting up, the SW Pin
is at ground, so the bootstrap capacitor will charge up to VCC
through D1. When the PWM input goes high, the high side
driver will begin to turn ON the high side MOSFET, Q1, by
pulling charge out of C
BST
. As Q1 turns ON, the SW Pin will
rise up to V
IN
, forcing the BST Pin to V
IN
+ V
C(BST)
, which is
enough gate-to-source voltage to hold Q1 ON. To complete the
cycle, Q1 is switched OFF by pulling the gate down to the volt-
age at the SW Pin. When the low side MOSFET, Q2, turns
ON, the SW Pin is pulled to ground. This allows the bootstrap
capacitor to charge up to VCC again. The high side driver’s
output is in phase with the PWM input.
Overlap Protection Circuit
The overlap protection circuit (OPC) prevents both of the
main power switches, Q1 and Q2, from being ON at the same
time. This is done to prevent shoot-through currents from flow-
ing through both power switches and the associated losses that
can occur during their ON-OFF transitions. The overlap pro-
tection circuit accomplishes this by adaptively controlling the
delay from Q1’s turn OFF to Q2’s turn ON and by externally
setting the delay from Q2’s turn OFF to Q1’s turn ON.
To prevent the overlap of the gate drives during Q1’s turn OFF
and Q2’s turn ON, the overlap circuit monitors the voltage at
the SW Pin. When the PWM input signal goes low, Q1 will begin
to turn OFF (after a propagation delay), but before Q2 can turn
ON, the overlap protection circuit waits for the voltage at the SW
Pin to fall from V
IN
to 1 V. Once the voltage on the SW Pin has
fallen to 1 V, Q2 will begin turn ON. By waiting for the voltage
on the SW Pin to reach 1 V, the overlap protection circuit ensures
that Q1 is OFF before Q2 turns on, regardless of variations in
temperature, supply voltage, gate charge, and drive current.
To prevent the overlap of the gate drives during Q2’s turn OFF
and Q1’s turn ON, the overlap circuit provides a programmable
delay that is set by a capacitor on the DLY Pin. When the PWM
input signal goes high, Q2 will begin to turn OFF (after a propa-
gation delay), but before Q1 can turn ON, the overlap protection
circuit waits for the voltage at DRVL to drop to around 10% of
VCC. Once the voltage at DRVL has reached the 10% point,
the overlap protection circuit will wait for a 20 ns typical propa-
gation delay plus an additional delay based on the external
capacitor, C
DLY
. The delay capacitor adds an additional 1 ns/pF
of delay. Once the programmable delay period has expired, Q1
will begin turn ON. The delay allows time for current to com-
mutate from the body diode of Q2 to an external Schottky diode,
which allows turnoff losses to be reduced. Although not as fool-
proof as the adaptive delay, the programmable delay adds a
safety margin to account for variations in size, gate charge, and
internal delay of the external power MOSFETs.
APPLICATION INFORMATION
Supply Capacitor Selection
For the supply input (VCC) of the ADP3412, a local bypass
capacitor is recommended to reduce the noise and to supply some
of the peak currents drawn. Use a 1 µF, low ESR capacitor.
Multilayer ceramic chip (MLCC) capacitors provide the best
combination of low ESR and small size and can be obtained from
the following vendors:
Murata GRM235Y5V106Z16 www.murata.com
Taiyo-
Yuden EMK325F106ZF www.t-yuden.com
Tokin C23Y5V1C106ZP www.tokin.com
Keep the ceramic capacitor as close as possible to the ADP3412.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (C
BST
) and
a Schottky diode, as shown in Figure 1. Selection of these com-
ponents can be done after the high side MOSFET has been
chosen.
The bootstrap capacitor must have a voltage rating that is able
to handle the maximum battery voltage plus 5 V. A minimum
50 V rating is recommended. The capacitance is determined
using the following equation:
CQ
V
BST
GATE
BST
=∆
where, Q
GATE
is the total gate charge of the high side MOSFET,
and ∆V
BST
is the voltage droop allowed on the high side MOSFET
drive. For example, the IRF7811 has a total gate charge of about
20 nC. For an allowed droop of 200 mV, the required boot-
strap capacitance is 100 nF. A good quality ceramic capacitor
should be used.
A Schottky diode is recommended for the bootstrap diode due
to its low forward drop, which maximizes the drive available for
the high side MOSFET. The bootstrap diode must have a mini-
mum 40 V rating to withstand the maximum battery voltage
plus 5 V. The average forward current can be estimated by:
IQf
F(AVG) GATE MAX
≈×
ADP3412
–7–
REV. A
where f
MAX
is the maximum switching frequency of the control-
ler. The peak surge current rating should be checked in-circuit,
since this is dependent on the source impedance of the 5 V sup-
ply and the ESR of C
BST
.
Delay Capacitor Selection
The delay capacitor, C
DLY
, is used to add an additional delay
when the low side FET drive turns off and when the high side
drive starts to turn on. The delay capacitor adds 1 ns/pF of
additional time to the 20 ns of fixed delay.
If a delay capacitor is required, look for a good quality ceramic
capacitor with an NPO or COG dielectric, or for a good quality
mica capacitor. Both types of capacitors are available in the 1 pF
to 100 pF range and have excellent temperature and leakage
characteristics.
1
2
3
4
8
7
6
5
BST
IN
DLY
VCC
DRVH
SW
PGND
DRVL
U2
ADP3412
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VID4
VID3
VID2
VID1
VCC
REF
CS–
PWM1
VID0
COMP
FB
CT
PWM2
CS+
PWRGND
GND
U1
ADP3160
U3
ADP3412
1
2
3
4
8
7
6
5
BST
IN
DLY
VCC
DRVH
SW
PGND
DRVL
C15
C14C13
C12
V
IN
12V
V
IN
RTN
270␮F ⴛ 4
OS-CON 16V
R
A
60.4k⍀
R
B
10k⍀
C
OC
1.4nF
R
Z
1.1k⍀C11 C16 C17 C18 C19 C20 C21 C22
1200␮F ⴛ 8
OS-CON 2.5V
11m⍀ ESR (EACH)
V
CC(CORE)
1.1V – 1.85V
53.4A
V
CC(CORE)
RTN
Q3
FDB7030L
D1
MBR052LTI
Q5
2N3904
L2
600nH
L1
600nH
Q1
FDB7030L
Q2
FDB8030L
C10
1␮F
D2
MBR052LTI
C7
15pF
C5
1␮F
Z1
ZMM5236BCT
R5
2.4k⍀
R8
330⍀
C23
330pF
C22
1nF
C4
4.7␮F
R6
10⍀C21
15nF
C26
4.7␮F
C8
15pF
C6
1␮F
C9
1␮F
R7
20⍀
R4
4m⍀
C2
100pF
C1
150pF
R1
1k⍀
Q4
FDB8030L
++
++++++
FROM
CPU
Figure 3. 53.4 A Intel CPU Supply Circuit
Printed Circuit Board Layout Considerations
Use the following general guidelines when designing printed
circuit boards:
1. Trace out the high current paths and use short, wide traces
to make these connections.
2. Connect the PGND Pin of the ADP3412 as close as pos-
sible to the source of the lower MOSFET.
3. The VCC bypass capacitor should be located as close as
possible to VCC and PGND Pins.
Typical Application Circuits
The circuit in Figure 3 shows how two drivers can be com-
bined with the ADP3160 to form a total power conversion
solution for V
CC(CORE)
generation in a high current GOA com-
puter. Figure 4 gives a CPU a similar application circuit for a
35 A processor.
ADP3412
–8– REV. A
1000␮F ⴛ 6
RUBYCON ZA SERIES
1
2
3
4
8
7
6
5
BST
IN
DLY
VCC
DRVH
SW
PGND
DRVL
U2
ADP3412
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
U1
ADP3160
VID4
VID3
VID2
VID1
VCC
REF
CS–
PWM1
VID0
COMP
FB
CT
PWM2
CS+
PWRGND
GND
U3
ADP3412
C15C14C13
C12
V
IN
5V
V
IN
RTN
R
A
14.7k⍀
R
B
22.1k⍀
C
OC
1nF
R
Z
10k⍀
FROM
CPU
C11 C16 C17 C18 C19 C20 C27 C28
V
CC(CORE)
1.1V – 1.85V
35A
V
CC(CORE)
RTN
Q3
FDB6035AL
D1
MBR052LTI
Q5
2N3904
L2
600nH
L1
600nH
Q1
FDB6035AL
Q2
FDB7030L
C10
1␮F
D2
MBR052LTI
C7
15pF
C5
1␮F
Z1
ZMM5236BCT
R5
2.4k⍀
R8
330⍀
C23
330pF
C22
1nF
C4
4.7␮F
R6
10⍀C21
15nF
C26
4.7␮F
C8
15pF
C6
1␮F
C9
1␮F
R7
20⍀
R4
5m⍀
C2
100pF
C1
150pF
R1
1k⍀Q4
FDB7030L
+ ++ + + + + +
1000␮F ⴛ 8
RUBYCON ZA SERIES
24m⍀ ESR (EACH)
12V V
CC
12V V
CC
RTN
C25C24
1
2
3
4
8
7
6
5
BST
IN
DLY
VCC
DRVH
SW
PGND
DRVL
Figure 4. 35 A Athlon CPU Supply Circuit
ADP3412
–9–
REV. A
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
0.25 (0.0098)
0.19 (0.0075)
1.27 (0.0500)
0.41 (0.0160)
0.50 (0.0196)
0.25 (0.0099) ⴛ 45ⴗ
8ⴗ
0ⴗ
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
85
41
5.00 (0.1968)
4.80 (0.1890)
PIN 1
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.33 (0.0130)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
OUTLINE DIMENSIONS
ADP3412
–10– REV. A
Revision History
Location Page
08/02—Data Sheet changed from REV. 0 to REV. A.
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
–11–
–12–
C01023–0–8/02 (A)
PRINTED IN U.S.A.