10-Bit, 65/80/105 MSPS
Dual A/D Converter
Preliminary Technical Data AD9216
Rev.
PrD_6
/
15
/
2004
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license
is granted by implication or otherwise under any patent or patent rights of
Analog Devices. Trademarks and registered trademarks are the property of
their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,
U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
Integrated Dual 10-Bit A-to-D Converters
Single 3 V Supply Operation (2.7 V to 3.3 V)
SNR = 58 dBc (to Nyquist, AD9216-105)
SFDR = 75 dBc (to Nyquist, AD9216-105)
Low Power: 280mW at 105MSPS
Differential Input with 500 MHz 3 dB Bandwidth
Exceptional Cross Talk Immunity > 75dB
Flexible Analog Input: 1 V p-p to 2 V p-p Range
Offset Binary or Twos Complement Data Format
Clock Duty Cycle Stabilizer
APPLICATIONS
Ultrasound Equipment
IF Sampling in Communications Receivers:
3G, Radio Point-to-Point, LMDS, MMDS
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
GENERAL DESCRIPTION
The AD9216 is a dual, 3 V, 10-bit, 65/80/105 MSPS analog-to-
digital converter. It features dual high performance sample-and
hold amplifiers and an integrated voltage reference. The
AD9216 uses a multistage differential pipelined architecture
with output error correction logic to provide 10-bit accuracy
and guarantee no missing codes over the full operating
temperature range at up to 105 MSPS data rates. The wide
bandwidth, differential SHA allows for a variety of user
selectable input ranges and offsets including single-ended
applications. It is suitable for various applications including
multiplexed systems that switch full-scale voltage levels in
successive channels and for sampling inputs at frequencies well
beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available on the
AD9216 (all speed grades) and can compensate for wide
variations in the clock duty cycle, allowing the converters to
maintain excellent performance. The digital output data is
presented in either straight binary or twos complement format.
Out-of-range signals indicate an overflow condition, which can
be used with the most significant bit to determine low or high
overflow.
Fabricated on an advanced CMOS process, the AD9216 is
available in a space saving 64-lead LFCSP (9x9) and is
specified over the industrial temperature range (–40°C to
+85°C).
ADC D9A-D0A
Output Mux/
Buffers
AGND
VIN- _A
CLK_A
AD9216
SHA 10
VIN+_A
DCS
SENSE
REFT_A
10
AVDD
ADC
VIN-_B SHA
VIN+_B 10 D10B-D0B
10
MUX_SELECT
CLK_B
AGND
DRGND
SHARED_REF
PWDN_A
DFS
Mode
Control
+
-
REFB_A
REFT_B
REFB_B
Clock
Duty Cycle
Stabilizer
PWDN_B
OTR_B
OEB_B
OEB_A
OTR_A
Output Mux/
Buffers
0.5V
VREF
DRVDD
Figure 1. Functional Block Diagram
PRODUCT HIGHLIGHTS
1. Pin compatible with AD9238, dual 12-bit
20/40/65MSPS ADC and AD9248, dual 14-bit
20/40/65MSPS ADC.
2. Speed grade options off 105 MSPS, 80 MSPS, and
65 MSPS allow flexibility between power, cost, and
performance to suit an application.
3. Low power consumption:
AD9216-105: 105 MSPS = 280 mW
AD9216-80: 80 MSPS = 238 mW
AD9216-65: 65 MSPS = 215mW
4. The patented SHA input maintains excellent
performance for input frequencies up to 100 MHz and
can be configured for single-ended or differential
operation.
5. Typical channel isolation of 75 dB @ fIN = 10 MHz.
6. The clock duty cycle stabilizer maintains performance
over a wide range of clock duty cycles.
AD9216 Preliminary Technical Data
Rev. PrD Page 2 of 20 6/15/2004
TABLE OF CONTENTS
General Description..............................................................1
Product Highlights ................................................................1
DC Specifications (Continued) .............................................4
Switching Specifications .......................................................4
AC Specifications .................................................................5
Absolute Maximum Ratings .....................................................7
ESD Caution.........................................................................7
Terminology........................................................................10
Typical Performance CharacteristiC PLOTS (TBD)..............12
Equivalent Circuits .................................................................13
Theory of Operation............................................................ 13
Analog Input ....................................................................... 13
Clock Input and Considerations .......................................... 15
Power Dissipation and Standby Mode ................................ 15
Digital Outputs.................................................................... 15
Timing ................................................................................ 16
Data Format........................................................................ 16
Voltage Reference............................................................... 17
Evaluation Board Diagrams (TBD) ........................................ 19
Outline Dimensions ................................................................ 20
REVISION HISTORY
PrA: Initial Version
PrB: included specification tables, ordering guide, package and pin configuration and Theory of operation sections.
PrC: Corrected pin configuration figure (Fig3) pin naming errors , updated supply spec, corrected timing diagram and latency.
PrD: Removed 120MSPS Grade, Updated DCS,OEB_B pin descriptions, updated input referred noise, Demux Timing Diagram needs
updating
Preliminary Technical Data AD9216
Rev. PrD Page 3 of 20 6/15/2004
AD9216–SPECIFICATIONS
DC SPECIFICATIONS
Table 1. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.)
Test AD9216BCP-65/80 AD9216BCP-105
Parameter Temp Level Min Typ Max Min Typ Max Unit
RESOLUTION Full VI 10 10 Bits
ACCURACY
No Missing Codes Guaranteed Full VI 10 10 Bits
Offset Error Full VI ±0.3 ±TBD ±0.30 ±TBD % FSR
Gain Error1 Full IV ±1.0 ±TBD ±1.0 ±TBD % FSR
Differential Nonlinearity (DNL)2 Full V ±0.5 ±0.5 LSB
25°C I ±0.5 ±TBD ±0.5 ±TBD LSB
Integral Nonlinearity (INL)2 Full V ±0.5 ±0.5 LSB
25°C I ±0.5 ±TBD ±0.5 ±TBD LSB
TEMPERATURE DRIFT
Offset Error Full V ±15 ±15 ppm/°C
Gain Error1 Full V ±30 ±30 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full VI ±5 ±35 ±5 ±35 mV
Load Regulation @ 1.0 mA Full V 0.8 0.8 mV
Output Voltage Error (0.5 V Mode) Full V ±2.5 ±2.5 mV
Load Regulation @ 0.5 mA Full V 0.1 0.1 mV
INPUT REFERRED NOISE
Input Span = 1 V 25°C V 0.8 0.8 LSB rms
Input Span = 2.0 V 25°C V 0.4 0.4 LSB rms
ANALOG INPUT
Input Span = 1.0 V Full IV 1 1 V p-p
Input Span = 2.0 V Full IV 2 2 V p-p
Input Capacitance3 Full V 2 2 pF
REFERENCE INPUT RESISTANCE Full V 7 7 k?
POWER SUPPLIES
Supply Voltages
AVDD Full IV 2.7 3.0 3.3 2.7 3.0 3.3 V
DRVDD Full IV 2.25 2.5 3.6 2.25 2.5 3.6 V
Supply Current
IAVDD2 Full V TBD/TBD TBD mA
IDRVDD2 Full V TBD/TBD TBD mA
PSRR Full V ±0.01 ±0.01 % FSR
POWER CONSUMPTION
DC Input4 Full V TBD/TBD TBD mW
Sine Wave Input2 Full VI 215/238 280 mW
Standby Power5 Full V 1/1 1 mW
MATCHING CHARACTERISTICS
Offset Error Full V ±0.1 ±0.1 % FSR
Gain Error Full V ±0.05 ±0.05 % FSR
1 Gain error and gain temperature coefficient are based on the A/D converter only (with a fixed 1.0 V external reference).
2 Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure xx for the equivalent analog input
structure.
4 Measured with dc input at maximum clock rate.
5 Standby power is measured with the CLK_A and CLK_B pins inactive (i.e., set to AVDD or AGND).
Specifications subject to change without notice.
AD9216 Preliminary Technical Data
Rev. PrD Page 4 of 20 6/15/2004
DC SPECIFICATIONS (CONTINUED)
Table 2. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.)
Test AD9216BCP-65/80 AD9216BCP-105 Unit
Parameter Temp Level Min Typ Max Min Typ Max
LOGIC INPUTS
High Level Input Voltage Full IV 2.0 2.0 V
Low Level Input Voltage Full IV 0.8 0.8 V
High Level Input Current Full IV -10 +10 -10 +10 µA
Low Level Input Current Full IV -10 +10 -10 +10 µA
Input Capacitance Full IV 2 2 pF
LOGIC OUTPUTS1
DRVDD = 2.5V
High Level Output
Voltage Full IV 2.45 2.45 V
Low Level Output Voltage Full IV 0.05 0.05 V
1 Output Voltage Levels measured with 5 pF load on each output.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Table 3. Switching Specifications
Test AD9216BCP-65/80 AD9216BCP-105
Parameter Temp Level Min Typ Max Min Typ Max Unit
SWITCHING PERFORMANCE
Max Conversion Rate Full VI 65/80 105 MSPS
Min Conversion Rate Full V 1 1 MSPS
CLK Period Full V 15.4/12.2 9.5 ns
CLK Pulsewidth High1 Full V 6.2/5 4.2 ns
CLK Pulsewidth Low1 Full V 6.2/5 4.2 ns
DATA OUTPUT PARAMETER
Output Delay2 (tPD) Full VI 2.0 4.8 6.0 2.0 4.8 6.0 ns
Pipeline Delay (Latency) Full V 6 6 Cycles
Aperture Delay (tA) Full V 1.0 1.0 ns
Aperture Uncertainty (tJ) Full V 0.5 0.5 ps rms
Wake-Up Time3 Full V 2.5 2.5 ms
OUT-OF-RANGE RECOVERY
TIME Full V 2 2
1 The AD9216 has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see TPC xx).
2 Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output.
3 Wake -up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Specifications subject to change without notice.
t
A
tPD
N–8 N–7 N–6 N–5 N–4 N–3 N–2 N-1 NN+1
ANALOG
INPUT
CLK
DATA
OUT
N–1
NN+1 N+2
N+3
N+4 N+5 N+6 N+7
N+8
Figure 2. Timing Diagram
Preliminary Technical Data AD9216
Rev. PrD Page 5 of 20 6/15/2004
AC SPECIFICATIONS
Table 4. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = –0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.)
Test AD9216BCP-65/80 AD9216BCP-105
Parameter Temp Level Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO
fINPUT = 2.4 MHz 25°C V 58 57 dBc
fINPUT = 19.6 MHz Full V 58 dBc
25°C IV TBD 58 dBc
fINPUT = 32.5 MHz Full V 57 dBc
25°C IV TBD 57 dBc
fINPUT = 69 MHz Full V dBc
25°C IV dBc
fINPUT = 100 MHz 25°C V 57 56 dBc
SIGNAL-TO-NOISE AND DISTORTION RATIO
fINPUT = 2.4 MHz 25°C V 58 57 dBc
fINPUT = 19.6 MHz Full V 58 dBc
25°C IV TBD 58 dBc
fINPUT = 32.5 MHz Full V 57 dBc
25°C IV TBD 56 dBc
fINPUT = 69 MHz Full V dBc
25°C IV dBc
fINPUT = 100 MHz 25°C V 56 55 dBc
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = 2.4 MHz 25°C V 9.4 9.3 Bits
fINPUT = 19.6 MHz Full V 9.4 Bits
25°C I TBD 9.4 Bits
fINPUT = 32.5 MHz Full V 9.3 Bits
25°C I TBD 9.1 Bits
fINPUT = 69 MHz Full V Bits
25°C I Bits
fINPUT = 100 MHz 25°C V 9.1 8.9 Bits
TOTAL HARMONIC DISTORTION
fINPUT = 2.4 MHz 25°C V -70.0 -70.0 dBc
fINPUT = 19.6 MHz Full V -69.0 dBc
25°C I -70.0 TBD dBc
fINPUT = 32.5 MHz Full V -69.0 dBc
25°C I -68.0 TBD dBc
fINPUT = 69 MHz Full V dBc
25°C I dBc
fINPUT = 100 MHz 25°C V -67.0 -66.0 dBc
WORST HARMONIC (2nd or 3rd)
fINPUT = 19.6 MHz Full V -75.0 dBc
fINPUT = 32.5 MHz Full V -74.0 dBc
fINPUT = 69 MHz Full V dBc
SPURIOUS FREE DYNAMIC RANGE
fINPUT = 2.4 MHz 25°C V 75.0 75.0 dBc
fINPUT = 19.6 MHz Full V 75.0 dBc
25°C I TBD 75.0 dBc
fINPUT = 32.5 MHz Full V 74.0 dBc
25°C I TBD 74.0 dBc
fINPUT = 69 MHz Full V dBc
25°C I dBc
AD9216 Preliminary Technical Data
Rev. PrD Page 6 of 20 6/15/2004
fINPUT = 100 MHz 25°C V dBc
CROSSTALK Full V -80.0 -80.0 dB
Specifications subject to change without notice.
Preliminary Technical Data AD9216
Rev. PrD Page 7 of 20 6/15/2004
ABSOLUTE MAXIMUM RATINGS
Table 5. AD9216 Absolute Maximum Ratings1
Parameter Rating
Pin Name With Respect To Min Max Unit
ELECTRICAL
AVDD AGND -0.3 +3.9 V
DRVDD DRGND -0.3 +3.9 V
AGND DRGND -0.3 +0.3 V
AVDD DRVDD -3.9 +3.9 V
Digital Outputs CLK, DCS, MUX_SELECT, SHARED_REF, DRGND -0.3 DRVDD + 0.3 V
OEB, DFS AGND -0.3 AVDD + 0.3 V
VINA, VINB AGND -0.3 AVDD + 0.3 V
VREF AGND -0.3 AVDD + 0.3 V
SENSE AGND -0.3 AVDD + 0.3 V
REFB, REFT AGND -0.3 AVDD + 0.3 V
PDWN AGND -0.3 AVDD + 0.3 V
ENVIRONMENTAL2
Operating Temperature -45 +85 °C
Junction Temperature +150 °C
Lead Temperature (10 sec) +300 °C
Storage Temperature -65 +150 °C
1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability
is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2 Typical thermal impedances (64-lead LQFP); ? ?JA = 54°C/W. These measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
EXPLANATION OF TEST LEVELS
I 100% production tested.
II 100% production tested at 25°C and sample tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100%
production tested at temperature extremes for military devices.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although this
product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
AD9216 Preliminary Technical Data
Rev. PrD Page 8 of 20 6/15/2004
Table 6. ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD9216BCP-65 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP)
AD9216BCPZ-80 –40°C to +85°C 64-Lead Lea d Frame Chip Scale Package (LFCSP)
AD9216BCPZ-105 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP)
AD9216BCPZRL7-65 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP)
AD9216BCPZRL7-80 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP)
AD9216BCPZRL7-
105 –40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP)
AD9216-65PCB Evaluation Board with AD9216BCPZ-65
AD9216-40PCB Evaluation Board with AD9216BCPZ-80
AD9216-105PCB Evaluation Board with AD9216BCPZ-105
AD9216
64Leadfor
LF-CSP
TOPVIEW
(Not toScale)
11
AGND
VIN-_A
AGND
AVDD
REFT_A
REFB_A
VREF
SENSE
13
4
5
6
7
12
8
9
2
3
14
10
15
1
REFB_B
REFT_B
AVDD
AGND
VIN+_B16
VIN-_B
VIN+_A
AGND
D2_A
D0_A
DNC
DNC
DNC
DNC
DRVDD
DRGND
OTR_B
D9_B(MSB)
D8_B
D7_B
D6_B
D5_B
38
36
45
44
43
42
37
41
40
47
46
35
39
34
48
D1_A
33 D4_B
27
AVDD
DCS
DFS
PDWN_B
OEB_B
DNC
DNC
DNC
DNC
29
20
21
22
23
28
24
25
18
19
30
26
31
17
D0_B
DRVDD
D1_B
D2_B32
D3_B
CLK_B
DRGND
CLK_A
D9_A(MSB)
54
52
61
60
59
58
53
57
56
63
62
51
55
50
64
49
AVDD
SHARED_REF
MUX_SELECT
PDWN_A
OEB_A
D8_A
D7_A
D6_A
DRGND
DRVDD
D5_A
D4_A
D3_A
OTR_A
Figure 3. Pin Configuration
Preliminary Technical Data AD9216
Rev. PrD Page 9 of 20 6/15/2004
Table 7. Pin Function Descriptions
Pin
Number Mnemonic Description
2 VIN+_A Analog Input Pin (+) for Channel A
3 VIN–_A Analog Input Pin (-) for Channel A
15 VIN+_B Analog Input Pin (+) for Channel B
14 VIN-_B Analog Input Pin (-) for Channel B
6 REFT_A Differential Reference (+) for Channel A
7 REFB_A Differential Reference (-) for Channel A
11 REFT_B Differential Reference (+) for Channel B
10 REFB_B Differential Reference (-) for Channel B
8 VREF Voltage Reference Input/Output
9 SENSE Reference Mode Selection
18 CLK_B Clock Input Pin for Channel B
63 CLK_A Clock Input Pin for Channel A
19 DCS Enable Duty Cycle Stabilizer (DCS) Mode ( Tie to AVDD to enable)
20 DFS Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement)
21 PDWN_B Power-Down Function Selection for Channel B (Active High)
60 PDWN_A Power-Down Function Selection for Channel A (Active High)
22 OEB_B Output Enable Bit for Channel B (Low Setting Enables Channel B Output Data Bus)
59 OEB_A Output Enable Bit for Channel A (Low Setting Enables Channel A Output Data Bus)
46–51, 54-
57 D0_A (LSB)-D9_A
(MSB) Channel A Data Output Bits
27, 30-38 D0_B (LSB) –D9_B
(MSB) Channel B Data Output Bits
39 OTR_B Out-of-Range Indicator for Channel B
58 OTR_A Out-of-Range Indicator for Channel A
62 SHARED_REF Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared
Reference Mode)
61 MUX_SELECT Data Multiplexed Mode. (See description for how to enable; high setting disables output data
Multiplexed mode)
5, 12, 17,
64 AVDD Analog Power Supply
1, 4, 13, 16 AGND Analog Ground
28, 40, 53 DRGND Digital Output Ground
29, 41, 52 DRVDD Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor.
Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF
23-26, 42-
45 DNC Do Not Connect Pins. Should be left floating.
AD9216 Preliminary Technical Data
Rev. PrD Page 10 of 20 6/15/2004
TERMINOLOGY
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Aperture Jitter
The variation in aperture delay for successive samples, which is
manifested as noise on the input to the A/D converter.
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 1 1/2
LSB beyond the last code transition. The deviation is measured
from the middle of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 10-Bits resolution indicates that all 2048
codes must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value 1/2
LSB below VIN+ = VIN-. Offset error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2
LSB above negative full scale. The last transition should occur
at an analog value 1 1/2 LSB below the nominal full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
TMIN or TMAX.
Power Supply Rejection
The specification shows the maximum change in full scale
from the value with the supply at the minimum limit to the
value with the supply at its maximum limit.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal, expressed as a
percentage or in decibels relative to the peak carrier signal
(dBc).
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
S/N+D is expressed in decibels relative to the peak carrier
signal (dBc).
Effective Number of Bits (ENOB)
Using the following formula:
effective number of bits for a
device for sine wave inputs at a given input frequency can be
calculated directly from its measured SINAD.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels relative to the peak carrier
signal (dBc).
Spurious Free Dynamic Range (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (fCLOCK/2), this is often referred to as
Nyquist sampling.
IF Sampling
Due to the effects of aliasing, an ADC is not necessarily limited
to Nyquist sampling. Higher sampled frequencies will be
aliased down into the first Nyquist zone (DC - fCLOCK/2) on the
output of the ADC. Care must be taken that the bandwidth of
the sampled signal does not overlap Nyquist zones and alias
onto itself. Nyquist sampling performance is limited by the
bandwidth of the input SHA and clock jitter (jitter adds more
noise at higher input frequencies).
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the A/D
converter to reacquire the analog input after a transient from
10% above positive full scale to 10% above negative full scale,
or from 10% below negative full scale to 10% below positive
full scale.
(
)
026761SINADENOB ..
−
=
Preliminary Technical Data AD9216
Rev. PrD Page 11 of 20 6/15/2004
Crosstalk
Coupling onto one channel being driven by a (-0.5 dBFS)
signal when the adjacent interfering channel is driven by a full-
scale signal. Measurement includes all spurs resulting from
both direct coupling and mixing components.
AD9216 Preliminary Technical Data
Rev. PrD Page 12 of 20 6/15/2004
TYPICAL PERFORMANCE CHARACTERISTIC PLOTS (TBD)
Preliminary Technical Data AD9216
Rev. PrD Page 13 of 20 6/15/2004
EQUIVALENT CIRCUITS
Figure xx. Equivalent Analog Input Circuit
Figure xx. Equivalent Digital Output Circuit
Figure xx. Equivalent Digital Input Circuit
THEORY OF OPERATION
The AD9216 consists of two high performance analog-to-
digital converters (ADCs) that are based on the AD9215
converter core. The dual ADC paths are independent, except for
a shared internal band gap reference source, VREF. Each of the
ADC’s paths consists of a proprietary front end sample-and-
hold amplifier (SHA) followed by a pipelined switched
capacitor ADC. The pipelined ADC is divided into three
sections, consisting of a 4-bit first stage followed by five 1.5-
bit stages and a final 3-bit fl ash. Each stage provides sufficient
overlap to correct for fl ash errors in the preceding stages. The
quantized outputs from each stage are combined through the
digital correction logic block into a final 10-bit result. The
pipelined architecture permits the first stage to operate on a
new input sample, while the remaining stages operate on
preceding samples. Sampling occurs on the rising edge of the
respective clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution fl ash ADC and a residual multiplier to drive the next
stage of the pipeline. The residual multiplier uses the fl ash
ADC output to control a switched capacitor digital-to-analog
converter (DAC) of the same resolution. The DAC output is
subtracted from the stage’s input signal and the residual is
amplified (multiplied) to drive the next pipeline stage. The
residual multiplier stage is also called a multiplying DAC
(MDAC). One bit of redundancy is used in each one of the
stages to facilitate digital correction of flash errors. The last
stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be
configured as ac- or dc-coupled in differential or single-ended
modes. The output-staging block aligns the data, carries out the
error correction, and passes the data to the output buffers. The
output buffers are powered from a separate supply, allowing
adjustment of the output voltage swing.
ANALOG INPUT
The analog input to the AD9216 is a differential switched
capacitor, SHA, that has been designed for optimum
performance while processing a differential input signal. The
SHA input accepts inputs over a wide common-mode range. An
input common-mode voltage of mid supply is recommended to
maintain optimal performance.
The SHA input is a differential switched capacitor circuit. In
Figure 4, the clock signal alternatively switches the SHA
between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
AD9216 Preliminary Technical Data
Rev. PrD Page 14 of 20 6/15/2004
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network will create a low-pass filter at the ADC’s
input; therefore, the precise values are dependant on the
application. In IF under sampling applications, any shunt
capacitors should be removed. In combination with the driving
source impedance, they would limit the input bandwidth. For
best dynamic performance, the source impedances driving
VIN+ and VIN- should be matched such that common-mode
settling errors are symmetrical. These errors will be reduced by
the common-mode rejection of the ADC.
Figure 4. Switched Capacitor Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common-mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as follows:
(
)
REF
VAVDD21REFT
+
=
(
)
REF
VAVDDREFB −= 21
(
)
REF
V2REFBREFT2Span
×
=
−
×
=
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the mid-supply voltage
and, by definition, the input span is twice the value of the VREF
voltage.
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
discussed in the Internal Reference Connection section.
Maximum SNR performance will be achieved with the
AD9216 set to the largest input span of
2 VP-P. The relative SNR degradation will be 3 dB when
changing from 2 VP-P mode to 1 VP-P mode.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as follows:
2VVCM REFMIN
=
(
)
2VAVDDVCM REFMAX
+
=
The minimum common-mode input level allows the AD9216 to
accommodate ground -referenced inputs. Although optimum
performance is achieved with a differential input, a single-
ended source may be driven into VIN+ or VIN-. In this
configuration, one input will accept the signal, while the
opposite input should be set to mid-scale by connecting it to an
appropriate reference. For example, a 2 VP-P signal may be
applied to VIN+ while a 1 V reference is applied to VIN-. The
AD9216 will then accept an input signal varying between 2 V
and 0 V. In the single-ended configuration, distortion
performance may degrade significantly as compared to the
differential case. However, the effect will be less noticeable at
lower input frequencies and in the lower speed grade models
(AD9216-65 and AD9216-80).
Differential Input Configurations
As previously detailed, optimum performance will be achieved
while driving the AD9216 in a differential input configuration.
For base band applications, the AD8138 differential driver
provides excellent performance and a flexible interface to the
ADC. The output common-mode voltage of the AD8138 is
easily set to AVDD/2, and the driver can be configured in a
Sallen-Key filter topology to provide band limiting of the input
signal.
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers will not be adequate to achieve
the true performance of the AD9216. This is especially true in
IF under sampling applications where frequencies in the 70
MHz to 200 MHz range are being sampled. For these
applications, differential transformer coupling is the
recommended input configuration, as shown in Figure 5.
Figure 5. Differential Transformer Coupling
The signal characteristics must be considered when selecting a
transformer. Most RF transformers will saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
AD9216
Preliminary Technical Data AD9216
Rev. PrD Page 15 of 20 6/15/2004
cost-sensitive applications. In this configuration, there will be a
degradation in SFDR and in distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance.
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be
sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9216 provides separate clock inputs for each channel.
The optimum performance is achieved with the clocks operated
at the same frequency and phase. Clocking the channels
asynchronously may degrade performance significantly. In
some applications, it is desirable to skew the clock timing of
adjacent channels. The AD9216’s separate clock inputs allow
for clock timing skew (typically ±1 ns) between the channels
without significant performance degradation.
The AD9216 contains two clock duty cycle stabilizers, one for
each converter, that retime the non-sampling edge, providing an
internal clock with a nominal 50% duty cycle. Faster Input
clock rates (where it becomes difficult to maintain 50% duty
cycles) can benefit from using DCS as a wide range of input
clock duty cycles can be accommodated. Maintaining a 50%
duty cycle clock is particularly important in high speed
applications, when proper track-and-hold times for the
converter are required to maintain high performance. The DCS
can be enabled by tying the DCS pin high.
The duty cycle stabilizer utilizes a delay locked loop to create
the non-sampling edge. As a result, any changes to the
sampling frequency will require approximately 2 µs to 3 µs to
allow the DLL to acquire and settle to the new rate.
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT ) due only to aperture jitter (tJ) can be
calculated
with the following equation:
[
]
J
tfp211020radationSNR INPUT
×
×
×
×
=
logdeg
In the equation, the rms aperture jitter, tJ , represents the root-
sum square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification.
Under-sampling applications are particularly sensitive to jitter.
For optimal performance, especially in cases where aperture
jitter may affect the dynamic range of the AD9216, it is
important to minimize input clock jitter. The clock input
circuitry should use stable references, for example using analog
power and ground planes to generate the valid high and low
digital levels for the AD9216 clock input. Power supplies for
clock drivers should be separated from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter crystal controlled oscillators make the best clock
sources. If the clock is generated from another type of source
(by gating, dividing, or other methods), it should be retimed by
the original clock at the last step.
POWER DISSIPATION AND STANDBY MODE
The power dissipated by the AD9216 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The digital drive current can be
calculated by
NfCVICLOCKLOADDRVDDDRVDD
×
×
×
=
where N is the number of bits changing and CLOAD is the
average load on the digital pins that changed.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases with clock frequency.
Either channel of the AD9216 can be placed into standby mode
independently by asserting the PWDN_A or PDWN_B pins.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
will result in a typical power consumption of 1 mW for the
ADC. Note that if DCS is enabled, it is mandatory to disable
the clock of an independently powered-down channel.
Otherwise, significant distortion will result on the active
channel. If the clock inputs remain active while in total standby
mode, typical power dissipation of TBD mW will result.
The minimum standby power is achieved when both channels
are placed into full power-down mode (PDWN_A = PDWN_B
= HI). Under this condition, the internal references are powered
down. When either or both of the channel paths are enabled
after a power-down, the wake-up time will be directly related to
the recharging of the REFT and REFB decoupling capacitors
and to the duration of the power-down. Typically, it takes
approximately 5 ms to restore full operation with fully
discharged 0.1 µF and 10 µF decoupling capacitors on REFT
and REFB.
A single channel can be powered down for moderate power
savings. The powered-down channel shuts down internal
circuits, but both the reference buffers and shared reference
remain powered. Because the buffer and voltage reference
remain powered, the wake-up time is reduced to several clock
cycles.
DIGITAL OUTPUTS
The AD9216 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the
digital supply of the interfaced logic. The output drivers are
sized to provide sufficient output current to drive a wide variety
of logic families. However, large drive currents tend to cause
current glitches on the supplies that may affect converter
performance. Applications requiring the ADC to drive large
capacitive loads or large fan-outs may require external buffers
or latches.
AD9216 Preliminary Technical Data
Rev. PrD Page 16 of 20 6/15/2004
The data format can be selected for either offset binary or twos
complement. This is discussed later in the Data Format section.
TIMING
The AD9216 provides latched data outputs with a pipeline
delay of six clock cycles. Data outputs are available one
propagation delay (tPD) after the rising edge of the clock signal.
Refer to Figure 2 for a detailed timing diagram.
The internal duty cycle stabilizer can be enabled on the
AD9216 using the DCS pin. This provides a stable 50% duty
cycle to internal circuits.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9216.
These transients can detract from the converter’s dynamic
performance. The lowest typical conversion rate of the AD9216
is 1 MSPS. At clock rates below 1 MSPS, dynamic
performance may degrade.
Figure 6. NEEDS UPDATING Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and
MUX_SELECT
DATA FORMAT
The AD9216 data output format can be configured for either
twos complement or offset binary. This is controlled by the
Data Format Select pin (DFS). Connecting DFS to AGND will
produce offset binary output data. Conversely, connecting DFS
to AVDD will format the output data as twos complement.
The output data from the dual A/D converters can be
multiplexed onto a single 10-Bits output bus. The multiplexing
is accomplished by toggling the MUX_SELECT bit, which
directs channel data to the same or opposite channel data port.
When MUX_SELECT is logic high, the Channel A data is
directed to Channel A output bus, and Channel B data is
directed to the Channel B output bus. When MUX_SELECT is
logic low, the channel data is reversed, i.e., Channel A data is
directed to the Channel B output bus and Channel B data is
directed to the Channel A output bus. By toggling the
MUX_SELECT bit, multiplexed data is available on either of
the output data ports.
If the ADCs are run with synchronized timing, this same clock
can be applied to the MUX_SELECT bit. After the
MUX_SELECT rising edge, either data port will have the data
for its respective channel; after the falling edge, the alternate
channel’s data will be placed on the bus. Typically, the other
unused bus would be disabled by setting the appropriate OEB
high to reduce power consumption and noise. Figure 6 shows
an example of multiplex mode. When multiplexing data, the
data rate is two times the sample rate. Note that both channels
must remain active in this mode and that each channel's power-
down pin must remain low.
Preliminary Technical Data AD9216
Rev. PrD Page 17 of 20 6/15/2004
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9216. The input range can be adjusted by varying the
reference voltage applied to the AD9216, using either the
internal reference with different external resistor configurations
or an externally applied reference voltage. The input span of
the ADC tracks reference voltage changes linearly.
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap
(common mode voltage).
The Shared Reference mode allows the user to connect the
references from the dual ADCs together externally for superior
gain and offset matching performance. If the ADCs are to
function independently, the reference decoupling can be treated
independently and can provide superior isolation between the
dual channels. To enable Shared Reference mode, the
SHARED_REF pin must be tied high and external differential
references must be externally shorted. (REFT_A must be
externally shorted to REFT_B and REFB_A must be shorted to
REFB_B.)
Internal Reference Connection
A comparator within the AD9216 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 8. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider (see Figure 7), setting V
REF to 1 V.
Connecting the SENSE pin to V
REF switches the reference
amplifier output to the SENSE pin,
completing the loop and providing a 0.5 V reference output. If
a resistor divider is connected as shown in Figure xx, the
switch will again be set to the SENSE pin. This will put the
reference amplifier in a non-inverting mode with the V
REF
output defined as follows:
(
)
1R2R150VREF
+
×
=
.
In all reference configurations, REFT and REFB drive the ADC
core and establish its input span. The input range of the ADC
always equals twice the voltage at the reference pin for either
an internal or an external reference.
Figure 7. Internal Reference Configuration
Table 8. Reference Configuration Summary
Resulting Differential
Selected Mode SENSE Voltage Resulting VREF (V) Span (VP-P)
External Reference AVDD N/A 2 × External Reference
Internal Fixed Reference VREF 0.5 1.0
Programmable Reference 0.2 V to VREF 0.5 × (1 + R2/R1) 2 × VREF (See Figure xx)
Internal Fixed Reference AGND to 0.2 V 1.0 2.0
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. When multiple ADCs track one another, a
single reference (internal or external) may be necessary to
reduce gain matching errors to an acceptable level. A high
precision external reference may also be selected to provide
lower gain and offset temperature drift. Figure 10 shows the
typical drift characteristics of the internal reference in both 1 V
and 0.5 V modes. When the SENSE pin is tied to AVDD, the
internal reference will be disabled, allowing the use of an
external reference. An internal reference buffer will load the
external reference with an equivalent 7 kΩ load. The internal
buffer will still generate the positive and negative full-scale
references, REFT and REFB, for the ADC core. The input span
will always be twice the value of the reference voltage;
therefore, the external reference must be limited to a maximum
of 1 V. If the internal reference of the AD9216 is used to drive
multiple converters to improve gain matching, the loading of
the reference by the other converters must be considered.
Figure X depicts how the internal reference voltage is affected
by loading.
AD9216
AD9216 Preliminary Technical Data
Rev. PrD Page 18 of 20 6/15/2004
Figure xx. Programmable Reference Configuration
Figure xx. Typical VREF Drift
Figure xx. VREF Accuracy vs. Load
AD9216
Preliminary Technical Data AD9216
Rev. PrD Page 19 of 20 6/15/2004
EVALUATION BOARD DIAGRAMS (TBD)
AD9216 Preliminary Technical Data
Rev. PrD Page 20 of 20 6/15/2004
OUTLINE DIMENSIONS
Figure 8. 64-Lead Lead Frame Chip Scale Package (LFCSP)
PR04775-0-6/04(PrD)
