2012-2016 Microchip Technology Inc. DS40001652D-page 1
PIC16F527
Processor Features:
• Interrupt Capability
• PIC1 6F5 27 Operating Spee d:
- DC – 20 MHz Crystal oscil lator
- DC – 200 ns Instruction cycle
• High-Endurance Program and Flash Data
Memory Cells:
- 1024 x 12 user execution memory
- 64 x 8 self-writable data memory
- 100,000 write program memory endurance
- 1,000,000 write Flash data memory
endurance
- Program and Fla sh dat a retention: >40 years
• General Purpose Registers (SRAM):
- 68 x 8 for PIC16F527
• Only 36 Single-Word Instructions to Learn:
- Added RETURN and RETFIE instructions
- Added MOVLB instruction
• All Instructions are Single-Cycle except for
Program Branches which are Two-Cycle
• Four-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
for Data and Instructions
Peripheral Feat ures:
• Dev ice Features:
- One Input-only pin
- 17 I/Os
- Individual direction control
- High-curren t source/s ink
• 8-Bit Real-Time Clock/Counter (TMR0) with 8-Bit
Programmable Prescaler
• In-Circ uit Serial Programming ™ (ICSP™) via T wo
External Pin C onn ec tion s
• Analog Comparator (CMP):
- Two analog compar ators
- Absolute and programmable references
• Analog-to-Digital Converter (ADC):
- 8-bit resolution
- Eight external input channels
- One internal channel to convert comparator
- 0.6V reference input
• Operational Amplifiers (op amps):
- Two operational amplifiers
- Fully-accessible visibility
eXtreme Low-Power (XLP) Features
• Sleep mode 50 nA @ 2.0V, typical
• Watchdog Timer (WDT): 500 nA @ 2.0V, typical
Microcontroller Features:
• Brown-out Reset (BOR)
• Power-on Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with a Dedicated RC
Oscillator
• Programmable Code Protection (CP)
• Power-Saving Sleep mode with Wake-up on
Change Feature
• Selectable Oscillator Options:
- INTOSC: Precision 4 or 8 MHz internal
oscillator
- EXTRC: Low-cost external RC oscillator
- LP: Power-sa vi ng, low-frequency cryst al
- XT: Standard crystal/resonator
- HS: High-speed crystal/resonator
- EC: High-speed external clock
• Variety of Packaging Options:
- 20-Lead PDIP, SOIC, SSOP, QFN, UQFN
CMOS Technology:
• Low-Power , High-S peed CMOS Flash Technology
• Fu lly -St ati c De si gn
• Wide Operati ng Volt age and Temper ature R ange:
- Industrial: 2.0V to 5.5V
- Extended: 2.0V to 5.5V
• Operating Current:
- 1 70 uA @ 2V, 4 MHz, typical
- 1 5 uA @ 2V, 32 kHz, typical
• Standby Current:
- 100 nA @ 2V, typical
20-Pin, 8-Bit Flash Microcontroller
PIC16F527
DS40001652D-page 2 2012-2016 Microchip Technology Inc.
FIGURE 1: 20-PIN DIAGRAM FOR PIC16F527
FIGURE 2: 20-PIN DIAGRAM FOR PIC16F527
TABLE 1: PIC16F527 AND PIC16F570 FAMILY TYPES
Device
Data Sheet Index
I/O Pins(1)
Flash
Data EE (B)
SRAM (B)
8-Bit ADC
Channels
Op Amp
Comparator
8-Bit Timers
BOR
Stack Levels
Interrupts
8 MHz I nt. Osc.
Interrupt-on-Change
Pins
Weak Pull-up Pins
XLP
PIC16F527 (1) 18 1 KW 64 68 8 2 2 1 Y 4 Y Y 4 4 Y
PIC16F570 (2) 25 2 KW 64 132 8 2 2 1 Y 4 Y Y 8 8 Y
Note 1: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: DS40001652 PIC16F527 Data Sheet, 20-Pin, 8-bit Flash Microcontroller.
2: DS40001684 PIC16F570 Data Sheet, 28-Pin , 8-bit Flash Microcontroller.
PDIP, SSO P, SOIC
VDD
RA5
RA4
RA3/MCLR/VPP
RC5
RC4
RC3
RC6
RC7
RB7
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RC0
RC1
RC2
RB4
RB5
RB6
PIC16F527
1
2
3
4
5
6
714
15
16
17
18
19
20
8
9
10 11
12
13
QFN, UQFN
RA3/MCLR/VPP
RC5
RC4
RC3
RC6
RA4
RA5
VDD
VSS
RA0/ICSPDAT
PIC16F527
1
2
3
4
5
6
7
14
15
16
17
18
19
20
8
9
10
11
12
13
RA1/ICSPCLK
RA2
RC0
RC1
RC2
RC7
RB7
RB6
RB5
RB4
2012-2016 Microchip Technology Inc. DS40001652D-page 3
PIC16F527
TABLE 2: 20-PIN ALLOCATION TABLE
I/O
20-Pin PDIP/SOIC/SSOP
20-Pin QFN/UQFN
Analog
Oscillator
Comparator
Reference
Timers
Op Amp
Clock Reference
ICSP™
Basic
Pull-up
Interrupt-on-Change
RA0 19 16 AN0 — C1IN+ — — — —ICSPDAT —YY
RA1 18 15 AN1 —C1IN- CVREF — — — ICSPCLK — Y Y
RA2 17 14 AN2 — C1OUT — T0CKI — — — — — —
RA3 4 1 — — — — — — — — MCLR
VPP Y Y
RA4 3 20 AN3 OSC2 — — — — CLKOUT — — Y Y
RA5 219 —OSC1 — — — — CLKIN — — — —
RB4 13 10 — — — — — OP2- — — — — —
RB5 12 9 — — — — — OP2+ — — — — —
RB6 11 8 — — — — — — — — — — —
RB7 10 7 — — — — — — — — — — —
RC0 16 13 AN4 — C2IN+ — — — — — — — —
RC1 15 12 AN5 —C2IN- — — — — — — — —
RC2 14 11 AN6 — — — — OP2 — — — — —
RC3 7 4 AN7 — — — — OP1 — — — — —
RC4 6 3 — — C2OUT — — — — — — — —
RC5 5 2 — — — — — — — — — — —
RC6 8 5 — — — — — OP1- — — — — —
RC7 9 6 — — — — — OP1+ — — — — —
VDD 118——————— ————
VSS 20 17 — — — — — — — — — — —
PIC16F527
DS40001652D-page 4 2012-2016 Microchip Technology Inc.
Table of Contents
1.0 General Description....................... ......... .. .... .... .. ......... .... .. .... .. ......... .... .. .... ......... .. .... .. ................................................................ 5
2.0 PIC16F527 Device Varieties..... .. ......... .. .... .. .... ....... .... .. .... .. .... ....... .... .. .... .... ....... .. .... ............. ..................................................... 6
3.0 Architectural Overview ................................................................................................................................................................ 7
4.0 Memory Organization................................................................................................................................................................ 12
5.0 Se l f- Writable Fl a sh Da ta Memory Contro l..................... ................................................................ ........ .. ..... ...... ...... ..... .. ...... .... 22
6.0 I /O Po rt............................................................................................................................. ....... .. ...... ...... ..... ...... ...... ...... ..... ...... .. 26
7.0 Timer0 Module and TMR0 Register .......................................................................................................................................... 31
8.0 Sp e cial Feature s of th e CPU.......................................................... ............................................. ...... ...... . ...... ...... ...... ..... ...... .... 36
9.0 Analog-to-Digital (A/D) Converter.............................................................................................................................................. 54
10.0 Comparator(s)........................................................................................................................................................................... 59
11.0 Comparator Voltage Reference Module........................ .... .. .... ....... .... .... .. .... ......... .. .... .... .. ......... ....... ...... ..... ...... .. ...... ..... ...... .... 64
12.0 Operational Amplifier (OPA) Module............................................................................................... .. ...... ..... ...... ...... ..... ...... ...... 66
13.0 Instruction Set Summary........................................................................................................................................................... 68
14.0 Development Support. ............................................................................................................. ...... .. ...... ..... ...... ...... ...... ..... ...... .. 76
15.0 Electrical Characteristics.................................................................................................... . ...... ...... ...... ..... ...... ...... ...... ..... ...... .. 80
16.0 DC and AC Characteristics Graphs and Charts...................... ............. .... .... ............. .... ............. .... ........................................... 98
17.0 Packa g i n g In fo rmation....... ................................................................. ..................................................................................... 112
The Microch i p Webs ite..... .................................................................................... ............................................................................. 130
Customer Change Notification Service ................................................................................. .................. .. ...... ..... .. ...... ...... ..... ...... .... 130
Customer Support................................. ............... ........ ................. ................. ...... ............................................................................. 130
Product Identification System............................................................................................................................................................ 131
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2012-2016 Microchip Technology Inc. DS40001652D-page 5
PIC16F527
1.0 GENERAL DE SCRIPTION
The P IC16F 527 devi ce from Micr ochip Technology is a
low-cost, high-performance, 8-bit, fully-static, Flash-
based CMOS microcontroller. It employs a RISC
architecture with only 36 single-word/single-cycle
instr ucti ons . All ins tr uctio ns ar e sing le cy cle exce pt fo r
program branches, which take two cycles. The
PIC16F527 device delivers performance an order of
magnitu de higher than its competitors in the same p rice
category. The 12-bit wide instructions are highly
symmetrical, resulting in a typical 2:1 code
compression over other 8-bit microcontrollers in its
class. The easy-to-use and easy to remember
instruction set reduces development time significantly.
The PIC16F527 product is equipped with special
features that reduce system cost and power
requirements. The Power-on Reset (POR) and Device
Reset Timer (DRT) eliminate the need for external
Reset circuitry. There are several oscillator
configurations to choose from, including INTRC
Internal Oscillator mode and the power-saving LP
(Low-Power) Oscillator mode. Power-Saving Sleep
mode, Watchdog Timer and code protection features
improve system cost, power and reliability.
The P IC16F527 de vice is availab le in the cost-ef fectiv e
Flash programmable version, which is suitable for
production in any volume. The customer can take full
advantage of Microchip’s price leadership in Flash
programmable microcontrollers, while benefiting from
the Flash programmable flexibility.
The PIC1 6F5 27 prod uc t is s upp orte d by a ful l-fea ture d
macro assembler, a software simulator, an in-circuit
emulator, a ‘C’ compiler, a low-cost development
programmer and a full-featured programmer. All the
tools are supported on IBM® PC and compatible
machines.
1.1 Applications
The PIC16 F527 device fi ts in app lication s ranging from
personal care appliances and security systems to low-
power remote transmitters/receivers. The Flash
technology makes customizing application programs
(transmitter codes, appliance settings, receiver
frequencies, etc.) extremely fast and convenient. The
small footprint packages, for through hole or surface
mounting, make these microcontrollers perfect for
applications with space limitations. Low cost, low
power, hig h performan ce, ease of use and I/O flexibi lity
make the PIC16F527 device very versatile, even in
areas where no microcontroller use has been
considered before (e.g., timer functions, logic and
PLDs in l arge r s ystem s and coprocess or a ppl ic ati ons).
TABLE 1-1: FEATURES AND MEMORY OF PIC16F527
PIC16F527
Clock Maximum Frequency of Operation (M Hz) 20
Memory Flas h Program Memory 1024
SRAM Data Memory (bytes) 68
Flash Data Memory (bytes) 64
Peripherals Timer Module(s) TMR0
Wake- up f ro m Sle ep o n Pi n C ha nge Yes
Features I/O Pins 17
Input Pins 1
Internal Pull-ups Yes
In-Circuit Serial ProgrammingTM Yes
Number of Instructions 36
Packages 20-pin PDIP, SOIC, SSOP, QFN, UQFN
Interrupts Yes
PIC16F527
DS40001652D-page 6 2012-2016 Microchip Technology Inc.
2.0 PIC16F527 DEVICE VARIETIES
A variety of packaging options are available.
Depending on application and production
requirem ents, the p roper device o ption can be s elected
using the information in this section. When placing
orders, please use the PIC16F527 Product
Identification System at the back of this data sheet to
specify the correct part number.
2.1 Quick Turn Programming (QTP)
Devices
Microchip offers a QTP programming service for
factory production orders. This service is made
available for users who choose not to program
medium-to-high quantity units and whose code
patterns have stabilized. The devices are identical to
the Flash devices but with all Flash locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please
cont act your loc al Microchip Technology sales off ice for
more details.
2.2 Serialized Quick Turn
ProgrammingSM (SQTPSM) Devices
Microchip offers a unique programming service, where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry code,
password or ID number.
2012-2016 Microchip Technology Inc. DS40001652D-page 7
PIC16F527
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16F527 device can
be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16F527 device uses a Harvard
archite ct ure in which pr ogra m and data a re acce ssed
on separate buses. This improves bandwidth over
traditional von Neumann architectures where program
and data are fetched on the same bus. Separating
progra m and data memo ry furt her all ows instru ctions
to be sized differently than the 8-bit wide data word.
Instruction opcodes are 12 bits wide, making it
possible to have all singl e-word inst ructions. A 12-bit
wide program memory access bus fetches a 12-bit
instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions execute in a single
cycle (200 ns @ 20 MHz, 1 s @ 4 MHz) except for
program branches.
Table 3-1 below lists memory supported by the
PIC16F5 27 dev ic e.
TABLE 3-1: PIC16F527 MEM ORY
The PIC16F527 device can directly or indirectly
address its register files and data memory. All Special
Function Registers (SFR), including the PC, are
mapped in the data memory. The PIC16F527 device
has a highly orthogonal (symmetrical) instruction set
that makes it possible to carry out any operation, on
any register, using any Addressing mode. This sym-
metrical nature and lack of “special optimal situations”
make p rogramming with the PIC16F527 d evice sim ple,
yet efficient. In addition, the learning curve is reduced
significantly.
The PIC16F527 device contains an 8-bit ALU and
working register. The ALU is a general purpose arith-
metic unit. It performs arithmetic and Boolean functions
between data in the working register and any register
file.
The ALU is eight bits wide and capable of addit ion, sub-
traction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two’s comple-
ment in nature. In two-operand instructions, one
operand is ty pi ca lly the W (w ork ing ) re gis ter. T he oth er
operand is either a file register or an immediate
const ant. I n sing le ope rand in st ruction s, the ope ran d is
either the W register or a file register.
The W registe r is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC) and
Zero (Z) bit s in the ST ATUS register . The C and DC bit s
operate as a borrow and digit borrow out bit,
respect ively, in subtractio n. See th e SUBWF and ADDWF
instructions for examples.
A simplified block diagram is shown in Figure 3-2, with
the corresponding device pins described in Table 3-2.
Device
Program
Memory Data Memory
Flash
(words) SRAM
(bytes) Flash
(bytes)
PIC16F527 1024 68 64
PIC16F527
DS40001652D-page 8 2012-2016 Microchip Technology Inc.
FIGURE 3-1: PIC16F527 BLOCK DIAGRAM
Flash
Program
Memory
11 Data Bus 8
12
Program
Bus
Instruction reg
Program Counter
RAM
File
Registers
Direct Addr 0-4
RAM Addr 9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
De vice Reset
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR VDD, VSS
Timer0
PORTA
8
8
RA4
RA3
RA2
RA1/ICSPCLK
RA0/ICSPDAT
0-7
3
RA5
STACK1
STACK2
68
Internal RC
Clock
1K x 12
bytes
Timer
PORTC
RC4
RC3
RC2
RC1
RC0
RC5
Comparator 2
C1IN+
C1IN-
C1OUT
C2IN+
C2IN-
C2OUT
AN5
AN6
AN7
VDD
8-bit ADC
CVREF
CVREF
CVREF
Self-write
64x8
VREF
Comparator 1
STACK3
STACK4
Brown-out
Reset
PORTB
RB7
RB6
RB5
RB4
RC7
RC6
T0CKI
OPAMP1 & OPAMP2
OP2-
OP2
OP1+
OP1-
OP1
OP2+
AN0
AN1
AN2
AN3
AN4
Direct Addr
BSR 5-7
3
2012-2016 Microchip Technology Inc. DS40001652D-page 9
PIC16F527
TABLE 3-2: PIC16F527 PINOUT DESCRIPTION
Name Function Input Type Output Type Description
RA0/AN0/C1IN+/ICSPDAT RA0 TTL CMOS Bidirectional I/O pin. It can be software
programmed for internal weak pull-up and
wake-up from Sleep on pin change.
ICSPDAT ST CMOS ICSP™ mode Sc hmit t Trigger.
C1IN+ AN — Comparator 1 input.
AN0 AN — ADC channel input.
RA1/AN1/C1IN-/CVREF/
ICSPCLK RA1 TTL CMOS Bidirectional I/O pin. It can be software
programmed for internal weak pull-up and
wake-up from Sleep on pin change.
ICSPCLK ST — ICSP™ mode Sc hmit t Trigger.
C1IN- AN — Comparator 1 input.
CVREF — AN Programmable Voltage Reference output.
AN1 AN — ADC channel input.
RA2/AN2/C1OUT/T0CK I RA2 TTL CMOS Bidirectional I/O port.
C1OUT — CMOS Comparator 1 output.
AN2 AN — ADC channel input.
T0CKI ST — Timer0 Schmitt T rigger input pin.
RA3/MCLR/VPP RA3 TTL — Standard TTL input with weak pull-up.
MCLR ST — Master Clear (Reset). When configured as
MCLR, this pin is an active-low Reset to the
device. V oltage on MCLR/VPP must not exceed
VDD during normal device operation or the
device will enter Programming mode. Weak
pull-up is always on if configured as MCLR.
VPP HV — Te st mode high-vo ltage pin.
RA4/AN3/OSC2/CLK OUT RA4 TTL CMOS Bidirectional I/O pin. It can be software
programmed for internal weak pull-up and
wake-up from Sleep on pin change.
OSC2 — XT AL Oscillator crystal output. Connections to crystal
or resonator in Crystal Oscillator mode (XT, HS
and LP modes only, PORTB in other modes).
CLKOUT — CMOS EXTRC/INTRC CLKOUT pin (FOSC/4).
AN3 AN — ADC channel input.
RA5/OSC1/CLKIN RA5 TTL CMOS Bidirectional I/O port.
OSC1 XTAL — XTAL oscillator input pin.
CLKIN ST — EXTRC Schmitt Trigger input.
RB4/OP2- RB4 TTL CMOS Bidirectional I/O port.
OP2- AN — Op amp 2 inverting input.
RB5/OP2+ RB5 TTL CMOS Bidirectional I/O port.
OP2+ AN — Op amp 2 non-inverting input.
RB6 RB6 TTL CMOS Bidirectional I/O port.
RB7 RB7 TTL CMOS Bidirectional I/O port.
RC0/AN4/C2IN+ RC0 ST CMO S Bidirectional I/O port.
AN4 AN — ADC channel input.
C2IN+ AN — Comparator 2 input.
RC1/AN5/C2IN- RC1 ST CMO S Bidirectional I/O port.
AN5 AN — ADC channel input.
C2IN- AN — Comparator 2 input.
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not Used, TTL = TTL input, ST = Schmitt Tr igger input,
HV = High Voltage, AN = Analog Voltage
PIC16F527
DS40001652D-page 10 2012-2016 Microchip Technology Inc.
RC2/AN6/OP2 RC2 ST CMO S Bidirectional I/O port.
AN6 AN — ADC channel input.
OP2 — AN Op amp 2 output.
RC3/AN7/OP1 RC3 ST CMO S Bidirectional I/O port.
AN7 AN — ADC channel input.
OP1 — AN Op amp 1 output.
RC4/C2OUT RC4 ST CMO S Bidirectional I/O port.
C2OUT — CMOS Comparator 2 output.
RC5 RC5 ST CMO S Bidirectional I/O port.
RC6/OP1- RC6 ST CMO S Bidirectional I/O port.
OP1- AN — Op amp 1 inverting input.
RC7/OP1+ RC7 ST CMO S Bidirectional I/O port.
OP1+ AN — Op amp 1 non-inverting input.
VDD VDD — P Positive supply for logic and I/O pins.
VSS VSS — P Ground reference for logic and I/O pins.
TABLE 3-2: PIC16F527 PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not Used, TTL = TTL input, ST = Schmitt Tr igger input,
HV = High Voltage, AN = Analog Voltage
2012-2016 Microchip Technology Inc. DS40001652D-page 11
PIC16F527
3.1 Clocking Scheme/Instruction
Cycle
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC
is incremented every Q1 and the instruction is fetched
from program memory and latched into the instruction
register in Q4. It is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2 and Example 3-1.
3.2 Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute take another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO or an interrupt),
then tw o cycles are req uired to com plete the ins truction
(see Example 3-1).
A fetch cycle begins with the PC incrementing in Q1.
In the ex ecution cycle , the fetched instruction i s latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q 3 and Q4 c ycles. Dat a mem ory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC PC PC + 1 PC + 2
Fetch INST (PC)
Execute INST (PC – 1) Fetch INST (PC + 1)
Execute INST (PC) Fetch INST (PC + 2)
Execute INST (PC + 1)
Internal
Phase
Clock
All instru ctions are single cycle, except for any pro gram branches. These take two cycles, since the fetch instructio n
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
1. MOVLW 03H Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTB, BIT1 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
PIC16F527
DS40001652D-page 12 2012-2016 Microchip Technology Inc.
4.0 MEMORY ORGANIZATION
The PIC16F527 memories are organized into program
memory and data memory (SRAM).The self-writable
portion of the program memory called self-writable
Flash data mem ory is lo cated at a ddresses 400h-43F h.
All program mode commands that work on the normal
Flash memory, work on the Flash data memory. This
includes bulk erase, row/column/cycling toggles, Load
and Re ad data comm ands (Refer to Se ction 5.0 “S elf-
Writable Flash Data Memory Control” for more
details). For devices with more than 512 bytes of
program memory, a paging scheme is used. Program
memory pages are accessed using one STATUS
register bit. For the PIC16F527, with data memory
register files of more than 32 registers, a banking
scheme is used. Data memory banks are accessed
using the File Select Register (FSR).
4.1 Program Memory Orga nizati on for
PIC16F527
The PIC16F527 device has an 11-bit Program Counter
(PC) c apab le o f a d dres si ng a 2K x 12 pro gra m me mo ry
space. Program memory is partitioned into user memory ,
data memo ry an d configuration m em ory s paces.
The user memory space is the on-chip user program
memory . As shown in Figure 4-1, it extends fro m 0x000
to 0x3FF and partitions into pages, including an
Interrupt v ector at address 0x004 an d a Reset vector at
address 0x3FF.
The data memory space is the self-writable Flash data
memory block and is located at addresses PC = 400h-
43Fh. All program mode commands that work on the
normal Flas h me mory, work on th e Fl as h da ta me mo ry
block. This includes bulk erase, Load and Read data
commands.
The configuration memory space extends from 0x440
to 0x7FF. Locations from 0x448 through 0x49F are
reserved. The user ID locations extend from 0x440
through 0 x443. T he Back up OSC CAL locations exten d
from 0x444 through 0x447. The Configuration Word is
physically located at 0x7FF.
Refer to “PIC16F527 Memory Programming
Specification” (DS41640) for more details.
FIGURE 4-1: MEMORY MAP
005h
1FFh
Reset V ector
On-chip User
Program
Memory (Page 0)
200h
3FFh
3FEh
User ID Locations
Reserved
Configuration Word
400h
443h
444h
7FEh
7FFh
43Fh
440h
Unimplemented
On-chip User
Program
Memory (Page 1)
Data Memory
Self-writable
448h
49Fh
Backup OSCCAL
Locations 447h
4A0h
Configuration Memory
Space Space User Me mory
Space
Flash Data Memory
Interrupt Vector
000h
004h
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PIC16F527
4.2 Data Memory (SRAM and SFRs)
Data memory is composed of registers or bytes of
SRAM. Therefore, data memory for a device is
specified by its register file. The register file is divided
into two functional groups: Special Function Registers
(SFR) and General Purpose Registers (GPR).
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling
desired operations of the PIC16F527. Se e Section 4.3
“STATUS Register” for details.
4.2.1 GENERAL PURPOSE REGISTER
FILE
The General Purpose Regis ter file is accessed directly
or indirectly. See Section 4.8 “Direct and Indirect
Addressing”.
4.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used b y the CPU and periph eral functions to control the
operation of the device (see Section 4.3 “STATUS
Register”).
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
FIGURE 4-2: PIC16F527 REGISTER FILE MAP
File Address
00h
01h
02h
03h
04h
05h
06h
07h
1Fh
INDF(1)
TMR0
PCL
STATUS
FSR
OSCCAL
PORTA
10h
Bank 0 Bank 1 Bank 2 Bank 3
3Fh
30h
20h
5Fh
50h
40h
7Fh
70h
60h
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
PORTB
08h
Note 1: Not a physical register. See Sect ion 4.8 “Direct and Indirect Addressing”.
BSR<1:0> 00 01 10 11
2Fh 4Fh 6Fh
PORTC
INTCON0
09h
0Ah
0Bh ADRES
ADCON0
0Ch
0Fh
INDF(1)
EECON
PCL
STATUS
FSR
EEDATA
EEADR
CM2CON0
INTCON0
ANSEL
VRCON
INDF(1)
TMR0
PCL
STATUS
FSR
OSCCAL
PORTA
PORTB
ADRES
ADCON0
INDF(1)
IW
PCL
STATUS
FSR
INTCON1
ISTATUS
ANSEL
OPACON
PORTC IBSR
INTCON0 INTCON0
CM1CON0 IFSR
Addresses map back to
addresses in Bank 0.
6Ch4Ch2Ch
PIC16F527
DS40001652D-page 14 2012-2016 Microchip Technology Inc.
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR/BOR Value on all
other R esets
Bank 0
N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx
N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111
N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111
N/A BSR(2) — — — — — — BSR1 BSR0 ---- -000 ---- -0uu
00h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu
01h TMR0 Timer0 module Register xxxx xxxx uuuu uuuu
02h PCL(1) Low-order eight bits of PC 1111 1111 1111 1111
03h STATUS(2) Reserved Reserved PA0 TO PD ZDCC-001 1xxx -00q qqqq
04h FSR(2) — Indirect data memory address pointer 0xxx xxxx 0uuu uuuu
05h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 —1111 111- uuuu uuu-
06h PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
07h PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ----
08h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
09h ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 1111 1100 1111 1100
0Ah ADRES ADC Conversion Result xxxx xxxx uuuu uuuu
0Bh INTCON0 ADIF CWIF T0IF RAIF — — — GIE 0000 ---0 0000 ---0
Bank 1
N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx
N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111
N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111
N/A BSR(2) — — — — — — BSR1 BSR0 ---- -000 ---- -0uu
20h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu
21h EECON — — — FREE WRERR WREN WR RD ---0 0000 ---0 0000
22h PCL(1) Low-order eight bits of PC 1111 1111 1111 1111
23h STATUS(2) Reserved Reserved PA0 TO PD ZDCC-001 1xxx -00q qqqq
24h FSR(2) — Indirect data memory address pointer 0xxx xxxx 0uuu uuuu
25h EEDATA Self Read/Write Data xxxx xxxx uuuu uuuu
26h EEADR —— Self Read/Write Address --xx xxxx --uu uuuu
27h CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 1111 1111 quuu uuuu
28h CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 1111 1111 quuu uuuu
29h VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 001- 0000 uuu- uuuu
2Ah ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
2Bh INTCON0 ADIF CWIF T0IF RAIF — — — GIE 0000 ---0 0000 ---0
Legend: x = unknown, u = unchanged, – = unimplemented, read as '0' (if applicable), q = value depends on condition.
Shaded cells = unimplemented or unused
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an explanation of how to access
these bits.
2: Registers are implemented as two physical registers. When executing from within an ISR, a secondary register is used at the same logi ca l
location. Both registers are persistent. See Section 8.11 “Interrupts”.
3: These registers show the contents of the registers in the other context: ISR or main line code. See Sectio n 8.11 “Interr upts”.
2012-2016 Microchip Technology Inc. DS40001652D-page 15
PIC16F527
Bank 2
N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx
N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111
N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111
N/A BSR(2) — — — — — — BSR1 BSR0 ---- -000 ---- -0uu
40h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu
41h TMR0 Timer0 module Register xxxx xxxx uuuu uuuu
42h PCL(1) Low-order eight bits of PC 1111 1111 1111 1111
43h STATUS(2) Reserved Reserved PA0 TO PD ZDCC-001 1xxx -00q qqqq
44h FSR(2) — Indirect data memory address pointer 0xxx xxxx 0uuu uuuu
45h OSCCAL CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 —1111 111- uuuu uuu-
46h PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
47h PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ----
48h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
49h ADCON0 ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 1111 1100 1111 1100
4Ah ADRES ADC Conversion Result xxxx xxxx uuuu uuuu
4Bh INTCON0 ADIF CWIF T0IF RAIF — — — GIE 0000 ---0 0000 ---0
Bank 3
N/A W(2) Working Register (W) xxxx xxxx xxxx xxxx
N/A TRIS I/O Control Registers (TRISA, TRISB, TRISC) 1111 1111 1111 1111
N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler 1111 1111 1111 1111
N/A BSR(2) — — — — — — BSR1 BSR0 ---- -000 ---- -0uu
60h INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu
61h IW(3) Interrupt Working Register. (Addressed also as W register when within ISR) xxxx xxxx xxxx xxxx
62h PCL(1) Low-order eight bits of PC 1111 1111 1111 1111
63h STATUS(2) Reserved Reserved PA0 TO PD ZDCC-001 1xxx -00q qqqq
64h FSR(2) — Indirect data memory address pointer 0xxx xxxx 0uuu uuuu
65h INTCON1 ADIE CWIE T0IE RAIE — — — WUR 0000 ---0 0000 ---0
66h ISTATUS(3) Reserved Reserved PA0 TO PD ZDCC-xxx xxxx -00q qqqq
67h IFSR(3) — Indirect data memory address pointer 0xxx xxxx 0uuu uuuu
68h IBSR(3) — — — — — — BSR1 BSR0 ---- -0xx ---- -0uu
69h OPACON — — — — — — OPA2ON OPA1ON ---- --00 ---- --00
6Bh INTCON0 ADIF CWIF T0IF RAIF — — — GIE 0000 ---0 0000 ---0
TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR/BOR Value on all
other R esets
Legend: x = unknown, u = unchanged, – = unimplemented, read as '0' (if applicable), q = value depends on condition.
Shaded cells = unimplemented or unused
Note 1: The upper byte of the Program Counter is not directly accessible. See Secti on 4.6 “ Pro gr am Co unt er” f or an exp l an at i on of ho w t o a cc es s
these bits.
2: Registers are implemented as two physical registers. When executing from within an ISR, a secondary register is used at the same logi ca l
location. Both registers are persistent. See Section 8.11 “Interrupts”.
3: These registers show the contents of the registers in the other contex t: ISR or main line code. See Section 8.11 “Interr upts”.
PIC16F527
DS40001652D-page 16 2012-2016 Microchip Technology Inc.
4.3 STATUS Register
This register contains the arithmetic status of the ALU,
the Reset status and the page preselect bit.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabl ed. These bit s are set or clea red according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For exam ple, CLRF STATUS, will clear the upper thre e
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
Therefore, it is recommended that only BCF, BSF and
MOVWF instructions be used to alter the STATUS
register . These instructions do not affect the Z, DC or C
bits from the STATUS register. For other instructions
which do affect Status bits, see Section 13.0
“Instruction Set Summary”.
REGISTER 4-1: STATUS: STATUS REGISTER
R-0 R-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
Reserved Reserved PA0 TO PD ZDCC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Reserved: Read as ‘0’
bit 5 PA0: Program Page Preselect bit
1 = Page 1 (200h-3FFh)
0 = Page 0 (000h-1FFh)
bit 4 TO: Time-Out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After po wer -up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)
ADDWF:
1 = A carry from the 4th low-order bit of the result occurred
0 = A carry from the 4th low-order bit of the result did not occur
SUBWF:
1 = A borrow from the 4th low-order bit of the result did not occur
0 = A borrow from the 4th low-order bit of the result occurred
bit 0 C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF: SUBWF: RRF or RLF:
1 = A carry occurred 1 = A borrow did not occur; Load bit with LSb or MSb, respectively
0 = A carry di d not occur 0 = A borrow occurred
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PIC16F527
4.4 OPTION Register
The OPTION register is a 8-bit wide, write-only register ,
which contains various control bits to configure the Tim-
er0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A Reset sets the OPTION <7:0> bits.
Note: If TRIS bit is set to ‘0’, the wake-up on
change and pul l-up fu nction s a re dis abled
for that pin (i.e., note that TRIS overrides
Option control of RAPU and RAWU).
REGISTER 4-2: OPTION: OPTION REGISTER
W-1 W-1 W-1 W-1 W-1 W-1 W-1 W-1
RAWU(2) RAPUT0CS(1) T0SE PSA PS2 PS1 PS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 RAWU: Enable PORTA Interrupt Flag on Pin Change bit(2)
1 = Disabled
0 = Enabled
bit 6 RAPU: Enable PORTA Weak Pull-Ups bit
1 = Disabled
0 = Enabled
bit 5 T0CS: Timer0 Clock Source Select bit(1)
1 = Transition on T0C KI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignme nt bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Ti mer0
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Note 1: If the T0CS bit is set to ‘1’, it will override the TRIS function on the T0CKI pin.
2: The RAWU bit of the OPTION register must be cleared to enable the RAIF function in the INTCON0
register.
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value Timer0 Rate WDT Rate
PIC16F527
DS40001652D-page 18 2012-2016 Microchip Technology Inc.
4.5 OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used
to calibrate the 8 MHz internal oscillator macro. It
contains seven bits of calibration that uses a two’s
complement sc heme for controlling the o scilla tor speed.
See Register 4-3 for det ails .
REGISTER 4-3: OSCCAL: OSCILLATOR CALIBRATION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0
CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-1 CAL<6:0>: Oscillator Calibration bits
0111111 = Maximum frequency
•
•
•
0000001
0000000 = Center frequency
1111111
•
•
•
1000000 = Minimum frequency
bit 0 Unimplemented: Read as ‘0’
2012-2016 Microchip Technology Inc. DS40001652D-page 19
PIC16F527
4.6 Program Counter
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
For a GOTO instruction, bits <8:0> of the PC are
provided by the GOTO instruction word. The Program
Counter (PCL) is mapped to PC<7:0>. Bit 5 of the
STATUS register provides page information to bit 9 of
the PC (see Figure 4-3).
For a CALL instruction, or any instruction where the
PCL is the destination, bits <7:0> of the PC again are
provided by the instruction word. However, PC<8>
does not come fro m the in stru ct ion word, but is always
cleared (see Figure 4-3).
Instr uctions where the PCL is th e destinatio n, or modif y
PCL instructions, include MOVWF PCL, ADDWF PCL
and B SF PCL,5.
FIGURE 4-3: LOADING OF PC
BRANCH INSTRUCTIONS
4.6.1 EFFECTS OF RESET
The PC is set upon a Reset, which means that the PC
addresses the last location in the last page (i.e., the
oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 00h and
begin executing user code.
The STATUS register page preselect bits are cleared
upon a Reset, which means that pag e 0 is pre-selected.
Therefore, upon a Reset, a GOTO instruction will
automat ically cause t he program to jump to page 0 unti l
the value of the page bits is altered.
4.7 Stack
The PIC16F527 device has a 4-deep, 12-bit wide
hardware PUSH/POP stack.
A CALL instruction or an interrupt will PUSH the current
PC value, incremented by one, i nto S tack Level 1. If there
was a previous value in the Stack 1 location, it will be
pushed into the Stack 2 location. This process will be
continued throughout the remaining stack locations pop-
ulated with values. If more than four sequential CALLs
are executed, only the most recent four return addresses
are st ored.
A RETLW, RETURN or RETFIE instruction will POP
the contents of Stack Level 1 into the PC. If there was
a previo us value in the S tac k 2 location , it will be copied
into the Stack Level 1 location. This process will be con-
tinued throughout the remaining stack locations popu-
lated with values. If more than four sequential RETLWs
are executed, the stack will be filled with the address
previously stored in Stack Level 4. Note that the
W register w ill be lo aded with the li tera l v al ue specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the pro-
gram memory.
Note: Because bit 8 of the PC is cleared in the
CALL instruction or any modify PCL
instruction, all subroutine calls or com-
puted jumps are limited to the first 256
locations of any program memory page
(512 words long).
PA0
Status
PC 87 0
PCL
910
Inst ruction Word
70
GOTO Ins truction
CALL or Modify PCL Instruction
PA0
Status
PC 87 0
PCL
910
Inst ruction Word
70
Reset to ‘0’
Note 1: There are no Statu s b it s to in dic ate Stac k
Overflows or S tack Underflow conditions.
2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETFIE and RETLW
instructions.
PIC16F527
DS40001652D-page 20 2012-2016 Microchip Technology Inc.
4.8 Direct and Indirect Addressing
4.8.1 DIRECT DATA ADDRESSING: BSR
REGISTER
Traditional data memory addressing is performed in
the D irect Addr ess ing mode . In D irec t Add res sing , the
Bank Select Register bits BSR<1:0>, in the new BSR
register, are used to select the data memory ban k. The
address location within that bank comes directly from
the opcode being executed.
BSR<1:0> are the bank select bits and are used to
select the bank to be addressed (00 = Bank 0, 01 =
Bank 1, 10 = Bank 2, 11 = Bank 3).
A new instruction supports the addition of the BSR
register, called the MOVLB instruction. See
Section 13.0 “Instruction Set Summary” for more
information.
4.8.2 INDIRECT DATA ADDRESSING:
INDF AND FSR REGISTERS
The INDF Register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR Register (FSR
is a pointer). This is indirect addressing.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF Register indirectly results in a
no-operation (although Status bits may be affected).
The FSR is an 8-bit wide register. It is used in
conjunction with the INDF Register to indirectly
address the data memory area.
The FSR<6:0> bits are used to select data memory
addresses 00h to 1Fh.
FSR<7> is unimplemented and read as ‘0’.
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-1.
EXAMPLE 4-1: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
MOVLW 0x10 ;initialize pointer
MOVWF FSR ;to RAM
NEXT CLRF INDF ;c lea r I NDF
;register
INCF FSR,F ;inc pointer
BTFSC FSR,4 ;all done?
GOTO NEXT ;NO, clear next
CONTINUE : ;YES, continue
:
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PIC16F527
FIGURE 4-4: DIRECT/INDI RECT ADDRE SSING
Note 1:For register map detail see Figure 4-2.
Location Select
Location Select
Bank Select
Indirect Addressing
Direct Addressing
Data
Memory(1) 0Bh
0Ch
0
4
5
6
(FSR)
1000 01 11
00h
0Fh 2Fh 4Fh 6Fh
(opcode)
04
0
1
(BSR)
321
321
10h
Bank 0 Bank 1 Bank 2 Bank 3
1Fh 3Fh 5Fh 7Fh
Addresses map back to
addresses in Bank 0.
PIC16F527
DS40001652D-page 22 2012-2016 Microchip Technology Inc.
5.0 SELF-WRIT ABLE FLASH DATA
MEMORY CONTROL
Flash Data memory consists of 64 bytes of self-
writable memory and supports a self-write capability
that can write a single byte of memory at one time.
Data to be written to the self-writable data memory is
first written into a write latch before writing the data to
Flash memory.
Although each Flash data memory location is 12 bits
wide, access is limited to the lower eight bits. The
upper four bits will automatically default to ‘1’ in any
self-write procedure. The lower eight bits are fully
readable and writable during normal operation and
throughout the full VDD range.
The self-writable Flash data memory is not directly
mapped in the register file space. Instead, it is
indirectly addressed through the Special Function
Registers, EECON, EEDATA and EEADR.
5.1 Reading Flash Data Memory
To read a Flash data memory location the user must:
• Write the EEADR register
• Set the RD bit of the EECON register
The value written to the EEADR register determines
whic h Flas h data me mory loc ation is rea d. Set ting the
RD bit of the EECON register initiates the read. Data
from the Flash data memory read is available in the
EEDATA register immediately. The EEDATA register
will hold this value until another read is initiated or it is
modified by a write operation. Program execution is
suspended while the read cycle is in progress.
Executio n will continue with the instruction fo llowing the
one that sets the WR bit. See Example 5-1 for sample
code.
EXAMPLE 5-1: READING FROM FLASH
DATA MEMORY
5.1.1 ERASING FLASH DATA MEMORY
A row must be manually erased before writing new
data. The following sequence must be performed for a
single row erase.
1. Load EEADR with an address in the row to be
erased.
2. Set the FREE bit to enable the erase.
3. Set the WREN bit to enable write access to the
array.
4. Disable interrupts.
5. Set the WR bit to initiate the erase cycle.
If the WREN bit is not set in the instruction cycle after
the FREE bit is set, the FREE bit will be cleared in
hardware.
If the WR bit is not set in the instruction cycle after the
WREN bit is set, the WREN bit will be cleared in
hardware.
Sample code that follows this procedure is included in
Example 5-2.
Program ex ec uti on i s s uspended whi le the eras e c ycle
is in progress. Execution will continue with the
instruction following the one that sets the WR bit.
EXAMPLE 5-2: ERASING A FLASH DATA
MEMORY ROW
Note: Only a BSF command will work to enable
the Flash da ta memo ry rea d doc um en ted in
Example 5-1. No other sequence of
commands will work, no exceptions.
MOVLB 0x01 ; Switch to Bank 1
MOVF DATA_EE_ADDR,W;
MOVWF EEADR ; Data Memory
; Address to read
BSF EECON, RD ; EE Read
MOVF EEDATA, W ; W = EEDATA
Note 1: To prevent accidental corruption of the
Flas h data memor y, an unloc k se quence
is required to initiate a write or erase
cycle. Thi s se que nc e requi res that the bit
set instructions used to configure the
EECON register happen exactly as
shown in Example 5-2 and Example 5-3,
depending on the operation requested.
2: In order to preve nt any d isruption s of sel f-
writes or row erases performed on the
self-writable Flash data memory,
interrupts should be disabled prior to
executing those routines.
MOVLB 0x01 ; Switch to Bank 1
MOVLW EE_ADR_ERASE ; LOAD ADDRESS OF ROW TO
; ERASE
MOVWF EEADR ;
BSF EECON,FREE ; SELECT ERASE
BSF EECON,WREN ; ENABLE WRITES
BSF EECON,WR ; INITITATE ERASE
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5.1.2 WRITING TO FLASH DATA
MEMORY
Once a cell is erased, new data can be written.
Program execution is suspended during the write cycle.
The self-write operation writes one byte of data at one
time. The data must first be loaded into a write latch.
Once the write latch is loaded, the data will be written
to Flash data memory.
The self-write sequence is shown below.
1. Load EEADR with the address.
2. Load EEDATA with the data to be written.
3. Set the WREN bit to enable write access to the
array.
4. Disable interrupts.
5. Set the WR bit to load the data into the write
latch.
Once the WR bit is set and the processor recognizes
that the write latch is loaded, it will immediately
perform the Flash data memory write of that byte.
The specific sequence of setting the WREN bit and
setting the WR b it must be execute d to pr operly initia te
loading of the write latches and the write to Flash data
memory.
If the WR bit is not set in the instruction cycle after the
WREN bit is set, the WREN bit will be cleared in
hardware.
Sample code that follows this procedure is included in
Example 5-3.
EXAMPLE 5-3: WRITING TO FLASH DATA
MEMORY
5.2 Write/Verify
Depending on the application, good programming
practice may dictate that data written to the Flash data
memory be verified. Example 5-4 is an example of a
write/verify.
EXAMPLE 5-4: WRITE/ VERI FY OF FLASH
DATA MEMORY
Note 1: The FREE bit may be set by any
command normally used by the core.
However, the WREN and WR bits can
only be set using a series of BSF com-
mands, as documented in Example 5-1.
No other sequence of commands will
work, no exce ptions.
2: Bits <5:3> o f the EEA DR regi ster i ndica te
which ro w is to be erased .
Note 1: Only a se ries of BSF comman ds will wor k
to enable the memory write sequence
documented in Example 5-3. No other
sequence of commands will work, no
exceptions.
2: For reads, erases and writes to the Flash
data memory, there is no need to insert a
NOP into the user code as is done on mid-
range devices. The instruction
immediately following the “BSF
EECON,WR/RD” will be fetched and
executed properly.
MOVLW EE_ADR_WRITE ;LOAD ADDRESS
MOVWF EEADR ;INTO EEADR
;REGISTER
MOVLW EE_DAT A_ WR ITE ;LOAD D AT A
MOVWF EEDATA ;INTO EEDATA
;REGISTER
BSF EECON, WREN ;ENABLE WRITES
BCF INTCON, GIE ;DISA BL E INTERRUP TS
BSF EECON,WR ;LOAD WRITE LATCH
;AND PERFORM DAT A
;MEMORY WRITE
MOVF EEDATA, W ;EEDATA has not changed
;from previous write
BSF EECON, RD ;Read the value written
XORWF EEDATA, W ;
BTFSS STATUS, Z ;Is data the same
GOTO WRITE_ERR ;No, handle error
;Yes, continue
PIC16F527
DS40001652D-page 24 2012-2016 Microchip Technology Inc.
5.3 Register Definitions — Memory Control
REGISTER 5-1: EEDATA: FLASH DATA REGISTER
REGISTER 5-2: EEADR: FLASH ADDRESS REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
EEDATA7 EEDATA6 EEDATA5 EEDATA4 EEDATA3 EEDATA2 EEDATA1 EEDATA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 EEDATA<7:0>: Eight bits of data to be read from/written to data Flash
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
—— EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’.
bit 5-0 EEADR<5:0>: Six bits of data to be read from/written to data Flash
2012-2016 Microchip Technology Inc. DS40001652D-page 25
PIC16F527
REGISTER 5-3: EECON: FLASH CONTROL REGISTER
5.4 Code Protection
Code protection does not prevent the CPU from
performing read or write operations on the Flash data
memory. Refer to the code protection chapter for more
information.
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
S = Bit can only be set
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-5 Unimplemented: Read as ‘0’.
bit 4 FREE: Flash Data Memory Row Erase Enable bit
1 = Program memory row b eing pointe d to by EEADR wil l be erased o n the next w rite cycle. N o write
will be performed. This bit is cleared at the completion of the erase operation.
0 = Perform write only
bit 3 WRERR: Write Error Flag bit
1 = A write operation terminated prematurely (by device Reset)
0 = Write operation completed successfully
bit 2 WREN: Write Enable bit
1 = Allows write cycle to Flash data memory
0 = Inhibits write cycle to Flash data memory
bit 1 WR: Write Control bit
1 = Initiate a erase or write cycle
0 = Write/Erase cycle is complete
bit 0 RD: Read Control bit
1 = Initiate a read of Flash data memory
0 = Do not read Flash data memory
PIC16F527
DS40001652D-page 26 2012-2016 Microchip Technology Inc.
6.0 I/O PORT
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at high-
impedance) since the I/O control registers are all set.
6.1 PORTA
PORTA is a 6-bit I/O register. Only the low-order six
bits are used (RA<5:0>). Bits 7 and 6 are
unimpl ement ed and rea d as ‘0’ s. Pl ease note th at RA3
is an input-only pin. The Configuration Word can set
several I/Os to alternate functions. When acting as
alternate functions, the pins will read as ‘0’ during a
port read. Pins RA0, RA1, RA3 and RA4 can be
configured with weak pull-ups and also for wake-up on
change. The wake-up on change and weak pull-up
functions are not pin selectable. If RA3/MCLR is
configured as MCLR, weak pull-up is always on and
wake-up on change for this pin is not enabled.
6.2 PORTB
PORTB is a 4-bit I/O register. Only the high-order four
bits are used (RB<7:4>). Bits 0 through 3 are
unimplemented and read as ‘0’s.
6.3 PORTC
PORTC is an 8-bi t I/O registe r.
6.4 TRIS Register
The Output Driver Control register is loaded with the
contents of the W register by executing the TRIS
instruction. A ‘1’ from a TRIS register bit puts the
corresponding output driver in a High-Impedance
mode. A ‘0’ puts the contents of the output data latch
on the selected pins, enabling the output buffer. The
excepti ons are RA3, w hich is inp ut-only and the T0CK I
pin, which may be controlled by the OPTION register
(see Register 4-2).
TRIS registers are “write-only”. Active bits in these
registers are set (output drivers disabled) upon Reset.
2012-2016 Microchip Technology Inc. DS40001652D-page 27
PIC16F527
6.5 I/O Interfacin g
The equivalent circuit for an I/O port pin is shown in
Figure 6-1. All port pins, except the MCLR pin whi ch is
input-on ly, m ay be us ed for both in put and ou tput op er-
ations. For input operations, these ports are non-latch-
ing. Any input must be present until read by an input
instruction (e.g., MOVF PORTB, W). The outputs are
latched and remain unchanged until the output latch is
rewritten. To use a port pin as output, the correspond-
ing direction control bit in TRIS must be cleared (= 0).
For use as an input, the corresponding TRIS bit must
be set. Any I/O pin (ex cept MCLR) can be programmed
individually as input or output.
FIGURE 6-1: BLOCK DIAGRAM OF I/O
PIN (Example shown of
RA2 with Weak Pull-up
and Wake-up on change)
Data
Bus
QD
Q
CK
QD
Q
CK
WR
Port
TRIS ‘f’
Data
TRIS
RD Port
W
Reg
Latch
Latch
Reset
Note 1: I/O pins have protection diodes to VDD and
VSS.
2: Pin enabled as analog for ADC or comparator .
D
CK
Q
Pin Change
RxPU
ADC pin Ebl
COMP pin Ebl
ADC
COMP
I/O Pin(1)
(2)
(2)
PIC16F527
DS40001652D-page 28 2012-2016 Microchip Technology Inc.
6.6 Register Definitions — PORT Control
TABLE 6-2: PORTA PINS ORDER OF PRECEDENCE
TABLE 6-3: WEAK PULL-UP ENABLED PINS
REGISTER 6-1: PORTB: PORTB REGISTER
TABLE 6-4: PORTB PINS ORDER OF
PRECEDENCE
TABLE 6-1: PORTA: PORTA REGISTER
U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— — RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RA<5:0>: PORTA I/O Pin bits
1 = Port pin is >VIH min.
0 = Port pin is <VIL max.
Priority RA5 RA4 RA3 RA2 RA1 RA0
1 OSC1 OSC2 RA3/MCLR AN2 CVREF AN0
2CLKINCLKOUT
— C1OUT AN1 C1IN+
3 TRISA5 AN3 — T0CKI C1IN- TRISA0
4— TRISA4 — TRISA2 TRISA1 —
Device RA0 Weak Pull-up RA1 Weak Pull-up RA3 Weak Pull-up(1) RA4 Weak Pull-up
PIC16F527 Yes Yes Yes Yes
Note1: When MCLRE = 1, the weak pul l-up on MCLR is always enabled.
R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0
RB7 RB6 RB5 RB4 — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-4 RB<7:4>: PORTB I/O Pin bits
1 = Port pin is >VIH min.
0 = Port pin is <VIL max.
bit 3-0 Unimplemented: Read as ‘0’
Priority RB7 RB6 RB5 RB4
1TRISB7 TRISB6 OP2+ OP2-
2—— TRISB5 TRISB4
2012-2016 Microchip Technology Inc. DS40001652D-page 29
PIC16F527
REGISTER 6-2: PORTC: PORTC REGISTER
TABLE 6-5: PORTC PINS ORDER OF PRECEDENCE
REGISTER 6-3: ANSEL REGISTER
TABLE 6-6: REGISTERS ASSOCIATED WITH THE I/O PORTS
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 RC<7:0>: PORTC I/O Pin bits
1 = Port pin is >VIH min.
0 = Port pin is <VIL max.
Priority RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
1 OP1+ OP1- TRISC5 C2OUT OP1 OP2 C2IN- C2IN+
2TRISC7 TRISC6 —TRISC4 AN7 AN6 AN5 AN4
3— — — — TRISC3 TRISC2 TRISC1 TRISC0
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ANS<7:0>: ADC Analog Input Pin Select(1), (2)
0 = Analog function on selected ANx pin is disabled
1 = ANx configured as an analog input
Note 1: When the ANSx bits are set, the channels selected will automatically be forced into Analog mode,
regardless of the pin function previously defined, and the digital output drivers and input buffers will also
be disabled. Exceptions exist when there is more than one analog function active on the ANx pin. It is the
user’s responsibility to ensure that the ADC loading on the other analog functions does not affect their
application.
2: The ANS<7:0> bits are active regardless of the condition of ADON.
Addr e s s Nam e Bit 7 Bit 6 Bit 5 B it 4 Bit 3 B it 2 Bit 1 Bit 0 Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
N/A TRIS(1) I/O Control Registers (TRISA, TRISB, TRISC)(1) 1111 1111 1111 1111
06h PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu
07h PORTB RB7 RB6 RB5 RB4 ————xxxx ---- uuuu ----
27h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, — = unimplemented, read as ‘0’ , Shaded cells = unimplemented, read as ‘0’
Note 1: TRISA 3 is read-only ‘1’, and cannot be set as output.
PIC16F527
DS40001652D-page 30 2012-2016 Microchip Technology Inc.
6.7 I/O Programming Considerations
6.7.1 BIDIREC TION AL I/O PORTS
Some instructions operate internally as read followed
by write operations. The BCF and BSF instructions, for
exampl e, read the entire port into the CPU, execute the
bit operation and rewrite the result. Caution must be
used when these instructions are applied to a port
where one or more pin s are us ed as in put/ outp uts. For
exampl e, a BSF operati on on bit 5 of PORTB wil l cause
all eig ht bits of POR TB to be read into the CPU, bi t 5 to
be set and the POR TB val ue to be w ritten to the outp ut
latches. If another bit of PORTB is used as a bidirec-
tional I/O pin (say bit 0) and it is defined as an input at
this tim e, the input signa l present on the pin it self would
be read into the CPU and rewritten to the data latch of
this particular pin, overwriting the previous content. As
long as the pin stays in the Input mode, no problem
occur s. H oweve r, i f bit 0 i s swi tch ed in to O utp ut mo de
later on, the content of the data latch may now be
unknown.
Example 6-1 shows the effect of two sequential
Read-Modify-Write instructions (e.g., BCF, BSF, etc.)
on an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired OR”, “wired
AND”). The res ulting hig h output curre nts may dam age
the chip.
EXAMPLE 6-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT(e.g. PIC16F527)
6.7.2 SUCCESSIVE OPERATIONS ON
I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginni ng of t he inst ructio n cyc le (Figure 6-2).
Therefore, care m ust b e exercised if a wri te foll ow ed by a
read operation is carried out on the same I/O port. The
sequence of instructions should allow the pin voltage to
stabilize (load dependent) before the next instruction
causes that file to be read into the CPU. Otherwise, the
previous state of tha t pin m ay be read in to th e CPU ra ther
than the new st a te. When in doub t, it is bette r to sepa rate
these instructions with a NOP or another instruction not
accessing thi s I/O port.
FIGURE 6-2: SUCCESSIVE I/O OPERATION
;Initial PORTB Settings
;PORTB<5:3> Inputs
;PORTB<2:0> Outputs
;
; PORTB latch PORTB pins
; --------------------
BCF PORTB, 5 ;--01 -ppp--11 pppp
BCF PORTB, 4 ;--10 -ppp--11 pppp
MOVLW 007h ;
TRIS PORTB ;--10 -ppp--11 pppp
;
Note 1: The user may have expec ted the pin values to
be ‘--00 pppp’. The 2nd BCF caused RB5 to
be latched as the pin value (High).
PC PC + 1 PC + 2 PC + 3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetched
RB<5:0>
MOVWF PORTB NOP
Port pin
sampled here
NOPMOVF PORTB, W
Instruction
Executed MOVWF PORTB
(Write to PORTB) NOPMOVF PORTB,W
This example shows a write to PORTB
followed by a read from PORTB.
Data s e tu p ti me = (0.2 5 TCY – TPD)
where: TCY = instruction cycle.
TPD = propagation delay
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
(Read PORTB)
Port pi n
written here
2012-2016 Microchip Technology Inc. DS40001652D-page 31
PIC16F527
7.0 TIMER0 MODULE AND TMR0
REGISTER
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select:
- Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit of the
OPTION register. In Timer mode, the Timer0 module
will increment every instruction cycle (without pres-
caler). If TMR0 register is written, the increment is
inhibited for the following two cycles (see Figure 7-2
and Figure 7-3). The user can work aroun d this by writ-
ing an adjusted value to the TMR0 register.
There ar e two typ es of Counte r mode. The first Co unter
mode uses the T0CKI pin to increment Timer0. It is
selected by setting the T0CS bit of the OPTION regis-
ter, setting the C1T0CS bit of the CM1CON0 register
and setting the C1OUTEN bit of the CM1CON0 regis-
ter. In this mode, Timer0 will increment either on every
rising or falling edge of pin T0CKI. The T0SE bit of the
OPTION regi ster determines th e source edge. Clearing
the T0SE bit selects the rising edge. Rest rictions on the
external clock input are discussed in detail in
Section 7.1 “Using T ime r 0 with an External Clo ck” .
The second Counter mode uses the output of the
comparator to increment T imer0. It can be entered in by
setting the T0CS bit of the OPTION register, and
clearing the C1T0CS bit of the CM1CON0 register
(C1OUTEN [CM1CON0<6>] does not affect this mode
of operation). This enables an internal connection
between the comparator and the Timer0.
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit, PSA of the OPTION register. Clearing the
PSA bit will assign the prescaler to Timer0. The pres-
caler is not rea dab le or writable. Whe n the prescaler i s
assign ed to t he Timer0 mod ule, p resca le val ues o f 1: 2,
1:4,..., 1:256 are selectable. Section 7.2 “Prescaler”
details the operation of the prescaler.
A summary of registers associated with the Timer0
module is found in Table 7-1.
FIGURE 7-1: TIMER0 BLOCK DIAGRAM
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register (see Register 4-2).
2: The prescaler is shared with the Watchdog Timer.
3: The C1T0CS bit is in the CM1CON0 register.
T0CKI T0SE(1)
0
1
1
0
pin T0CS(1)
FOSC/4
Programmable
Prescaler(2)
Sync with
Internal
Clocks TMR0 Reg
PSOUT
(2 cycle delay)
PSOUT
Data Bus
8
PSA(1)
PS2(1), PS1(1), PS0(1)
3
Sync
0
1
Comparator
Output
C1T0CS(3)
PIC16F527
DS40001652D-page 32 2012-2016 Microchip Technology Inc.
FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
TMR0 Timer0 module Register —
CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 62
CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 63
OPTION RAWU RAPU T0CS T0SE PSA PS2 PS1 PS0 17
TRIS(1) I/O Control Registers (TRISA, TRISB, TRISC) —
Legend: Shaded cells are not us ed by Timer0. – = unimplemen ted, x = unknown, u = unchanged.
Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1.
PC – 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
Timer0
PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6
T0 T0 + 1 T0 + 2 NT0 NT0 + 1 NT0 + 2
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 + 1 Read TMR0
reads NT0 + 2
Instruction
Executed
PC + 5
PC
(Program
Counter)
PC – 1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Instruction
Fetch
Timer0
PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 6
T0 T0 + 1 NT0 NT0 + 1
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 Read TMR0
reads NT0 + 1 Read TMR0
reads NT0 + 2
Instruction
Executed
PC + 5
PC
(Program
Counter)
2012-2016 Microchip Technology Inc. DS40001652D-page 33
PIC16F527
7.1 Using Timer0 with an External
Clock
When an external cl ock input i s used for T ime r0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.1.1 EXTERN AL CLOCK
SYNCHRONIZATION
When no pr escal er is used, t he ex ternal clo ck inp ut is
the same as the pre sc al er outp ut. Th e sy nch ron iz atio n
of T0CKI with the internal phase clocks is accom-
plishe d by sampling the prescale r output on the Q2 and
Q4 cy cles of the in ternal phase clocks (se e Figure 7-4).
Therefore, it is necessary for T0CKI to be high for at
least 2 TOSC (and a small RC delay of 2 Tt0H) and low
for at least 2 TOSC (and a small RC delay of 2 Tt0H).
Refer to the electrical specification of the desired
device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
pres caler, so t hat the prescale r output is symme trical.
For the external clock to meet the sampling require-
ment, the ripple counter must be taken into account.
Therefore, i t is nec essa ry for T0CKI to h ave a perio d of
at least 4 TOSC (and a small RC delay of 4 Tt0H) d ivided
by the presc aler value . The only requi rement on T0CK I
high and low time is that they do not violate the
minimum pulse width requirement of Tt0H. Refer to
param ete rs 40, 41 and 42 in the electric al s pec if ica t io n
of the desired device.
7.1.2 TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 7-4 shows the
delay from the external clock edge to the timer
incrementing.
FIGURE 7-4: TIMER0 TIMING WITH EXTERNAL CLOCK
Increment Timer0 (Q4)
External Clock Input or Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Timer0 T0 T0 + 1 T0 + 2
Small pulse
misses sampling
External Clock/ Pres caler
Output After Sampling (3)
Prescaler Output (2)
(1)
Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error
in measuring the interval between two edges on Timer0 input = ±4 TOSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
PIC16F527
DS40001652D-page 34 2012-2016 Microchip Technology Inc.
7.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (see Section 8.7 “Watch-
dog Timer (WDT)”). For simplicity, this counter is
being referred to as “prescaler” throughout this data
sheet.
The PSA and PS<2:0> bits of the OPTION register
determine prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0,
MOVWF TMR0, etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT. The prescaler is neither
readable nor writable. On a Reset, the prescaler
contains all ‘0’s.
7.2.1 SWITCHING PRESCALE R
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution). To avoid an unintended device
Reset, the following instruction sequence (see
Example 7-1) must be executed when changing the
prescaler assignment from Timer0 to the WDT.
EXAMPLE 7-1: CHANGING PRESCALER
(TIMER0 WDT)
To change the prescaler from the WDT to the Timer0
module , use the se quence sh own in Example 7-2. This
sequenc e mus t be us ed ev en if th e WDT is disab led. A
CLRWDT instruction should be executed before
switching the prescaler.
EXAMPLE 7-2: CHANGING PRESCALER
(WDT TIMER0)
Note: The prescaler may be used by either the
Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the WDT and vice versa.
CLRWDT ;Clear WDT
CLRF TMR0 ;Clear TMR0 & Prescaler
MOVLW b'00xx1111'
CLRWDT ;PS<2:0> are 000 or 001
MOVLW b'00xx1xxx' ;Set Postscaler to
OPTION ;desired WDT rate
CLRWDT ;Clear WDT and
;prescaler
MOVLW b'xxxx0xxx' ;Select TMR0, new
;prescale value and
;clock source
OPTION
2012-2016 Microchip Technology Inc. DS40001652D-page 35
PIC16F527
FIGURE 7-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY (= FOSC/4)
Sync
2
Cycles TMR0 Reg
8-bit Prescaler
8-to-1 MUX
M
MUX
Watchdog
Timer
PSA(1)
01
0
1
WDT
Time-out
PS<2:0>(1)
8
PSA(1)
WDT Enable bit
0
10
1
Data Bus
8
PSA(1)
T0CS(1)
M
U
XM
U
X
U
X
T0SE(1)
Note 1: T0CS, T0SE , PSA, PS<2:0> are bits in the OPTION register (see Register 4-2).
T0CKI
Pin
0
1
C1TOCS
Comparator
Output
PIC16F527
DS40001652D-page 36 2012-2016 Microchip Technology Inc.
8.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other
process ors are speci al circui t s that d eal with t he need s
of real-time applications. The PIC16F527
microcontrollers have a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power-
saving operating modes and offer code protection.
These features are:
• Oscillator Selection
•Reset:
- Power-on Reset (POR)
- Brown-out Reset (BOR)
- Device Reset Timer (DRT)
- Wake-up from Sleep on Pin Change
• Interrupts
• Automatic Context Saving
• Watchdog Timer (WDT)
• Sleep
• Code Protection
• ID Loc ati ons
• In-Circuit Serial Programming™
•Clock Out
The device has a Watchdog Timer, which can be shut
off only through Configuration bit WDTE. The
Watchdog Timer runs off of its own RC oscillator for
added reliability.
There is also a Device Reset Timer (DRT), intend ed to
keep the chip in Reset until the crystal oscillator is
stable. The DRT can be enabled with the DRTEN
Configuration bit. For the HS, XT or LP oscillator
opti ons, t he 18 ms ( nomin al) del ay is alw ays pr ovid ed
by the Device Reset Timer and the DRTEN bit is
ignored. When using the EC clock, INTRC or EXTRC
oscillato r op tio ns, there is a standard delay of 1 0 us on
power-up, which can be extended to 18 ms with the
use of the DRT timer. With the DRT timer on-chip,
most applications require no additional external Reset
circuitry.
The Sleep mo de is des igned to offe r a very low current
Power-Dow n mode. The us er ca n wa ke -up fro m Slee p
through a change on input pin or through a Watchdog
Timer time-out. Several oscillator options are also
made available to allow the part to fit the application,
including an internal 4/8 MHz oscillator. The EXTRC
oscillator option saves system cost while the LP crystal
option saves power. A set of Configuration bits are
used to select various options.
8.1 Configuration Bits
The PIC16F527 Configuration Words consist of 12 bits,
although some bits may be unimplemented and read as
‘1’. Configuration bits can be programmed to select
various devi ce config ura tions ( s ee Register 8-1).
Note: For QTP and SQTP code applications, if
the device is configured such that the
Internal Oscillator is selected and the
MCLRE fuse is cleared, it is possible for
code to execute when memory is verified
in ICSP™ mode. If customer code writes
to Flash data memory, the potential exists
for corruption of addresses 400h to 43Fh
during code verification. In this configura-
tion, Flash dat a memory s hould be erased
in code prior to being written in code.
2012-2016 Microchip Technology Inc. DS40001652D-page 37
PIC16F527
8.2 Register Definitions — Configuration Word
REGISTER 8-1: CONFIG: CONFIGURATION WORD REGISTER
U-1 U-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
—— DRTEN BOREN CPSW IOSCFS MCLRE CP WDTE FOSC2 FOSC1 FOSC0
bit 11 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase
bit 11-10 Unimplemented: Read as ‘1’
bit 9 DRTEN: Device Reset Timer Enable bit
1 =DRT Enabled (18ms)
0 =DRT Disabled
bit 8 BOREN: Brown-out Reset Enable bit
1 = BOR Enabled
0 = BOR Disabled
bit 7 CPSW: Code Protection bit – Self-Writable Memory
1 = Code prote ction off
0 = Code prote ction on
bit 6 IOSCFS: Internal Oscillator Frequency Select bit
1 = 8 MHz INTOSC speed
0 = 4 MHz INTOSC speed
bit 5 MCLRE: Master Clear Enable bit
1 =RA3/MCLR
pin functions as MCLR
0 =RA3/MCLR pin functions as RA3, MCLR tied internally to VDD
bit 4 CP: Code Protection bit – User Program Memory
1 = Code prote ct ion off
0 = Code prote ction on
bit 3 WDTE: Watchdog Timer Enable bit
1 = WDT enabl ed
0 = WDT disa ble d
bit 2-0 FOSC<2:0>: Oscillator Selection bits
000 = LP oscillator and automatic 18 ms DRT (DRTEN fuse ignored)
001 = XT oscillator and automatic 18 ms DRT (DRTEN fuse ignored)
010 = HS oscillator and automatic 18 ms DRT (DRTEN fuse ignored)
011 = EC oscillator with RA4 function on RA4/OSC2/CLKOUT and 10 us start-up time(2,3)
100 = INTRC with RA4 function on RA4/OSC2/CLKOUT and 10 us start-up time(2,3)
101 = INTRC with CLKOUT function on RA4/OSC2/CLKOUT and 10 us start-up time(2,3)
110 = EXTRC with RA4 function on RA4/OSC2/CLKOUT and 10 us start-up time(2,3)
111 = EXTRC with CLKOUT function on RA4/OSC2/CLKOUT and 10 us start-up time(2,3)
Note 1: Refer to the “PIC1 6F527 Me mory Prog ramming Spe cific ation” (DS41640) to d ete rmine ho w to a cc ess the
Configu ration Word.
2: DRT length and start-up time are functions of the Clock mode selection. It is the responsibility of the
application designer to ensure the use of either will result in acceptable operation. Refer to Section 15.0
“Electrical Characte ristics” for VDD rise time a nd stability requirements f or th is mode of operatio n.
3: The optional DRTEN fuse can be used to extend the start-up time to 18 ms.
PIC16F527
DS40001652D-page 38 2012-2016 Microchip Technology Inc.
8.3 Oscillator Configurations
8.3.1 OSCILLATOR TYPES
The PIC16F527 device can be operated in up to six
different oscillator modes. The user can program up to
three Con figurat ion bit s (FOSC< 2:0> ). To select one of
these modes:
• LP: Low-Power Crystal
• XT: Crystal/Resonator
• HS: High-Speed Cryst al /R es ona tor
• INT RC: Intern al 4/8 MHz Oscillato r
• EXTRC: External Resistor/Cap ac ito r
• EC: External High-Speed Clock Input
8.3.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In HS, XT or LP modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (see Figure 8-1). The
PIC16F527 oscillator designs require the use of a
parallel cut crystal. Use of a series cut crystal may give
a frequency out of the crystal manufacturers
specifications. When in HS, XT or LP modes, the
device can have an external clock source drive the
OSC1/CLKIN pin (see Figure 8-2). In this mode, the
output drive levels on the OSC2 pin are very weak. If
the part is used in this fashion, then this pin should be
left open and unload ed. Also when using this mode, the
external clock should observe the frequency limits for
the Clock mode chosen (HS, XT or LP).
FIGURE 8-1: CRYSTAL OPERATION
(OR CERAMIC
RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
FIGURE 8-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT, LP
OR EC OSC
CONFIGURATION)
Note 1: This device has been designed to
perform to the parameters of its data
sheet. It has been tested to an electrical
specification designed to determine its
conformance with these parameters.
Due to process differences in the
manufacture of this device, this device
may have different performance
characteristics than its earlier version.
These di ffe rences ma y cause thi s device
to perform differently in your application
than the earlier version of this device.
2: The user should verify that the device
oscillator starts and performs as
expected. Adjusting the loading capaci-
tor values and/or the Oscillator mode
may be required.
T ABLE 8-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Osc
Type Resonator
Freq. Cap. Range
C1 Cap. Range
C2
XT 4.0 MHz 30 pF 30 pF
HS 16 MHz 10-47 pF 10-47 pF
Note 1: These values are for design guidance
only. Sinc e eac h reso nat or has it s own
characteristics, the user should consult
the resonator manufacturer for
appropriate values of external
components.
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for A T
strip cut crystals.
3: RF approx. value = 10 M.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3) Sleep
To internal
logic
RS(2)
PIC® Device
Clock From
ext. system PIC® Device
OSC2/CLKOUT
OSC1/CLKIN
OSC2/CLKOUT(1)
EC, HS, XT, LP
Note 1: Available in EC mode only.
2012-2016 Microchip Technology Inc. DS40001652D-page 39
PIC16F527
)
8.3.3 EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 8-3 shows impl ementati on of a paralle l resonant
oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a
paral lel oscillator requires. The 4.7 k resistor provides
the negative feedback for stability. The 10 k
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
FIGURE 8-3: EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
Figure 8-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180-
degree phase shift in a series resonant oscillator
circuit. The 330 resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 8-4: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
8.3.4 EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC device
option offers add iti ona l cos t sav in gs . The RC osc il lat or
frequenc y is a fun ction of the supply voltage, t he re sis -
tor (REXT) and capacitor (C EXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit-to-unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C
components used.
Figure 8-5 shows how the R/C combination is
connected to the PIC16F527 device. For REXT values
below 3.0 k, the oscillator operation may become
unst able, or stop completel y . For very high REXT value s
(e.g., 1 M), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
REXT between 5.0 k and 100 k.
TABLE 8-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR(2
Osc
Type Resonator
Freq. Cap. Range
C1 Cap. Range
C2
LP 32 kHz(1) 15 pF 15 pF
XT 200 kHz
1 MHz
4 MHz
47-68 pF
15 pF
15 pF
47-68 pF
15 pF
15 pF
HS 20 MHz 15-47 pF 15-47 pF
Note 1: For VDD > 4.5V, C1 = C2 30 pF is
recommended.
2: These values are for design guidance
only. Rs may be r equired to avoid over-
driv ing crys tal s with lo w drive leve l spe cifi-
cation. Since each crystal has its own
characteristics, the user should consult
the crystal manufacturer for appropriate
values of external components.
20 pF
+5V
20 pF
10k 4.7k
10k
74AS04
XTAL
10k
74AS04
CLKIN
To Other
Devices
PIC® Device
330
74AS04 74AS04
PIC® Device
CLKIN
To Other
Devices
XTAL
330
74AS04
0.1 mF
PIC16F527
DS40001652D-page 40 2012-2016 Microchip Technology Inc.
Although the oscillator will operate with no external
capacitor (CEXT = 0pF), we recommend using values
above 20 pF for noise and stability reasons. With no
external capacitance or with values below 20 pF, the
oscillation frequency can vary dramatically due to
chang es in ex ternal c apacitance s, such a s PCB tr ace
capac itance or package lead frame capacitance.
Sect io n 15.0 “Ele ct rica l C har acte ri stic s” shows RC
frequency variation from part-to-part due to normal
process variation. The variation is larger for larger val-
ues of R (since leaka ge current variation will affect RC
frequenc y more for la rge R) and for sm aller val ues of C
(since variation of input capacitance will affect RC
frequency more).
Also, see the Electrical Specifications section for
variation of oscillator frequency due to VDD for given
REXT/CEXT values, as well as frequency variation due
to operating temperature for given R, C and VDD
values.
FIGURE 8-5: EXTERN AL RC
OSCILLATOR MODE
8.3.5 INTERNAL 4/8 MHz RC
OSCILLATOR
The internal RC oscillator provides a fixed 4/8 MHz
(nominal) system clock at VDD = 5V and 25°C, (see
Section 15.0 “Electrical Characteristics” for
informat ion on variatio n overvoltag e and temperatu re).
In addit ion , a ca librati on in structi on is progra mmed into
the last address of memory, which contains the
calibration value for the internal RC oscillator. This
location is always non-code protected, regardless of
the code-protect settings. This value is programmed as
a MOVLW XX instruction where XX is the calibration
value, and is placed at the Reset vector. This will load
the W register with the calibration value upon Reset
and the PC will then roll over to the users program at
address 0x 000 . The us er the n ha s the option of writing
the value to the OSCCAL Register or ignoring it.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscil la tor frequ enc y.
For the PIC16F 527 device, o nly bi ts < 7:1> of O SCCAL
are used for calibration. See Register 4-3 for more
information.
VDD
REXT
CEXT
VSS
OSC1 Internal
clock
N
FOSC/4 OSC2/CLKOUT
PIC® Device
Note: Erasi ng the devi ce will al so era se the pre-
programmed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
Note: The bit 0 of the OSCCAL register is
unimplemented and should be written as
‘0’ when modifying OSCCAL for
compatibility with future devices.
2012-2016 Microchip Technology Inc. DS40001652D-page 41
PIC16F527
8.4 Reset
The device differentiates between various kinds of
Reset:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
•MCLR
Reset during normal operation
•MCLR Reset during Sleep
• WDT Time-out Reset during normal operation
• WDT Time-out Reset during Sleep
• Wake-up from Sleep on pin change
Some registers are not reset in any way, they are
unknown on POR/BOR and unchanged in any other
Reset. Most other registers are reset to “Reset state”
on Power-on Reset (POR)/Brown-out Reset (BOR),
MCLR, WDT or Wake-up on pin change Reset during
normal operation. They are not affected by a WDT
Reset during Sleep o r MCLR Reset durin g Sleep, since
these Resets are viewed as resumption o f normal oper-
ation. The exceptions to this are the TO and PD bits.
They a re set or cl ear ed dif fer entl y in di f feren t Reset sit-
uations. Thes e bits are us ed in software to determine
the natur e of Reset. See Table 4-1 for a full descriptio n
of Reset states of all registers.
TABLE 8-3: RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
Power-on Reset (POR) or Brown-out Reset (BOR) 0001 1xxx
MCLR Reset during normal operation 000u uuuu
MCLR Reset durin g Sleep 0001 0uuu
WDT Reset during Sleep 0000 0uuu
WDT Reset normal operation 0000 uuuu
Wake-up from Sleep on pin change 1001 0uuu
Wake-up from Sleep on comparator change 0101 0uuu
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’.
PIC16F527
DS40001652D-page 42 2012-2016 Microchip Technology Inc.
8.4.1 MCLR ENABLE
This Configuration bit, when set to a ‘1’, enables the
exte rnal MCLR Reset function. When cleared to ‘0’, the
MCLR function is tied to the internal VDD and the pin i s
assigned to be an inp ut-only pin function. See Figure 8-6.
FIGURE 8-6: MCLR SELECT
8.5 Power-on Reset (POR)
The PIC16F527 device in corporates an on-chip Power-
on Reset (POR) circuitry, which provides an internal
chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper oper-
ation. To take advantage of the internal POR, program
the MCLR/VPP pin as MCLR and tie through a resistor
to VDD, or program the pin as an input pin. An internal
weak pu ll-u p res is tor is impl emented using a trans is tor
(refer to Table 15-8 for the pull-up resistor ranges). This
will eliminate external RC components usually needed
to create a Power-on Reset. A maximum rise time for
VDD is specified. See Section 15.0 “Electrical Char-
acteristics” for details.
When the device starts normal operation (exit the
Reset condition), device operating parameters (volt-
age, fre quency, t em pera ture ,...) m ust be m et to ensure
operation. If these conditions are not met, the device
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 8-7.
The Power-on Reset circuit and the Device Reset
Timer (see Section 8.6 “Devic e Reset Tim er (DR T) ” )
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, it will reset the Reset latch and thus
end the on-chip Reset signal.
A power-up example where MCLR is held low i s shown
in Figure 8-8. VDD is allowed to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset TDRT msec after MCLR goe s high.
In Figure 8-9, the on-chip Power-on Reset feature is
being use d (MCLR a nd V DD are tied together or the pin
is programmed to be an input pin). The VDD is stable
before the s tart-up timer ti mes out and there is no prob-
lem in getting a proper Reset. However, Figure 8-10
depict s a pro ble m situ ation whe re VDD rises too slowly.
The time be tw ee n when the DRT senses tha t MCLR is
high and when MCLR and VDD actually reach their full
value, is too long. In this situation, when the start-up
timer times out, VDD has not reached the VDD (min)
value a nd the chip may not f unc tio n c orre ct ly. For such
situations, we recommend that external RC circuits be
used to a chieve l onger POR de lay time s (see Figure 8-
9).
For additional information, refer to Application Notes
AN522, Power-Up Considerations (DS00522) and
AN607, Power-up Trouble Shooting (DS00607).
MCLR/VPP
MCLRE Internal MCLR
RAPU
Note: When the device starts normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the de vice mu st be he l d in Re se t un til th e
operating conditions are met.
2012-2016 Microchip Technology Inc. DS40001652D-page 43
PIC16F527
FIGURE 8-7: SI MPLI FIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
FIGURE 8-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
FIGURE 8-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
SQ
RQ
VDD
MCLR/VPP
Power-up
Detect POR (Power-on Reset)
WDT Re set CHIP Reset
Wake-up on pin Change Reset
Device Reset
(10 us
WDT Time-out
Pin Change
Sleep
MCLR Reset
or 18 ms)
Comparator Change
Wake-up on
Comparator Change
BOR
BOREN
Timer
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT
VDD
MCLR
Inter n al POR
DRT Time-out
Internal Reset
TDRT
PIC16F527
DS40001652D-page 44 2012-2016 Microchip Technology Inc.
FIGURE 8-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
VDD
MCLR
Internal POR
DRT Time-out
Internal Reset
TDRT
V1
Note: When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 VDD min.
2012-2016 Microchip Technology Inc. DS40001652D-page 45
PIC16F527
8.6 Device Reset Timer (DRT)
On the PIC16F527 device, the DRT runs any time the
device is po wered up. DR T ru ns from Reset and va ries
based on oscillator selection and Reset type (see
Table 8-4).
The DRT operates on an internal RC oscillator. The
process or is kept in Reset as long as the DR T is active.
The DR T del ay allo w s VDD to rise above VDD min. and
for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic resona-
tors require a certain time after power-up to establish a
stable oscillation. The on-chip DRT keeps the device in
a Reset condition after MCLR has reached a logic high
(VIH MCLR) level. Programming MCLR/VPP as MCLR
and using an external RC network connected to the
MCLR input is not required in most cases. This allows
savings in cost-sensitive and/or space restricted applica-
tions, as well as allow ing the use of that pin as a general
purpose input.
The Device Reset Time delays will vary from chip-to-
chip due to VDD, temperature and process variation.
See AC parameters for details.
The D RT w ill also be tri ggered upon a Watchdog T im er
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin or comparator change. See
Section 8.10.2 “Wake-up from Sleep”, Notes 1, 2
and 3.
8.7 Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the OSC1/CLKIN pin and the
internal 4/8 MHz oscillator. This means that the WDT
will run even if the main processor clock has been
stopped, for example, by execution of a SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset, generates a device Reset.
The T O bit of the STATUS register w ill b e cleared upon
a Watchdog Timer Reset.
The WDT can be permanently disabled by
programming the configuration WDTE as a ‘0’ (see
Section 8.1 “Configuration Bits”). Refer to the
PIC16F527 Programming Specifications to determine
how to access the Confi guration Word.
TABLE 8-4: TYPICAL DRT PERIODS
8.7.1 WDT PERIOD
The WDT has a nomin al time-out p eriod of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These
periods vary with temperature, VDD and part-to-part
process va riations ( see DC spec s).
Under worst-case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out o ccurs.
8.7.2 WDT PROGRAMMING
CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
post scaler , if as signed to the WDT, and preven ts it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
Oscillator
Configuration POR Reset Subsequent
Resets
HS, XT, LP 18 ms 18 ms
EC 10 us 10 s
INTOSC, EXTRC 10 us 10 s
PIC16F527
DS40001652D-page 46 2012-2016 Microchip Technology Inc.
FIGURE 8-11: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 8-5: REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
8.8 Time-out Sequence (TO) and
Power-down (PD) Reset Status
The TO and PD bits in the STATUS register can be
tested to determine if a Reset condition has been
caused by a power-up co nditio n, a M CLR or W atc hdog
Timer (WDT) Reset.
TABLE 8-6: TO/PD ST ATUS AF TER RESET
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on
page
OPTION RAWU RAPU T0SC T0SE PSA PS2 PS1 PS0 17
Legend: Shaded boxes = Not used by Watchdog Timer.
(Figure 7-1)
Postscaler
Note 1: PSA, PS<2:0> are bits in the OPTION register.
WDT Time- out
Watchdog
Time
From Timer0 Clock Source
WDT Enable
Configuration
Bit
PSA
Postscaler
8-to-1 MUX PS<2:0>(1)
(Figure 7-4)
To Timer0
0
1M
U
X
1
0
PSA(1)
MUX
TO PD Reset Caused By
00WDT w ake-up from Sl eep
0uWDT time-out (not from Sleep )
10MCLR wake-up from Sleep
11Power-up or Brown-out Reset
uuMCLR not during Slee p
Legend: u = unchanged
Note 1: The TO and PD bits maintain their status
(u) until a Reset occur s . A low puls e on
the MCLR input does not change the TO
and PD Status bits.
2012-2016 Microchip Technology Inc. DS40001652D-page 47
PIC16F527
8.9 Brown-out Reset (BOR)
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and
then recov ers . The de vic e sh oul d be res et in the eve nt
of a brown-out. The Brown-out Reset feature is
enabled by the BOREN Configuration bit.
If VDD falls below VBOR for greater than parameter
(TBOR) (see Figure 8-12), the brown-out situation will
reset the device. This will occur regardless of VDD slew
rate. A Reset is not insured to occur if VDD falls below
VBOR for less than parame ter (TBOR).
Please see Section 15.0 “Electrical Characteristics”
for the VBOR specification and other parameters shown
in Figure 8-12.
On any Reset (Power-on, Brown-out Reset, Watchdog
T imer , et c.), the ch ip will remai n in Reset unt il VDD rises
above VBOR (see Figure 8-12). If enabled, the Device
Reset T imer will no w be inv oked, and will keep t he chip
in Reset an additional 18 ms.
If VDD drops below VBOR while the De vice Reset Timer
is running, the chip will go back into a Brown-out Reset
and the Device Reset Timer will be re-initialized. Once
VDD rises above VBOR, the Device Reset Timer will
execute a 18 ms Reset.
FIGURE 8-12: BROWN-OUT RESET TIMING AND CHARACTERISTICS
FIGURE 8-13: BROWN-OUT SITUATIONS
Note: The Device Reset T imer is enabled by the
DRTEN bit in the Configuration Word
register.
VBOR
VDD
(Device in Brown-out Reset) (Device not in Brown-out Reset)
TDRT
TBOR
Reset
(due to BOR)
VBOR + VHYST
18 ms
VBOR
VDD
Internal
Reset
VBOR
VDD
Internal
Reset 18 ms
< 18 ms
18 ms
VBOR
VDD
Internal
Reset
(DRTEN = 1)
(DRTEN = 1)
(DR TEN = 1)
PIC16F527
DS40001652D-page 48 2012-2016 Microchip Technology Inc.
8.10 Power-down Mode (Sleep)
A device may be powered down (Sleep) and later
powered up (wake-up from Sleep).
8.10.1 SLEEP
The Power-Down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keep s running, th e TO bit of the ST A TUS register is set,
the PD bit of the STATUS register is cleared and the
oscill ator dr ive r is turned off . The I/O po rts main t ain th e
status they had before the SLEEP instruction was exe-
cuted (driving high, driving low or high-impedance).
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
MCLR/VPP pin must be at a logic high level if MCLR is
enabl ed.
8.10.2 WAKE-UP FROM SLEE P
The device can wake-up from Sleep through one of
the following events:
1. A n external Reset input on RB 3/MCLR/VPP pin,
when configured as MCLR.
2. A Watchdog Timer Time-out Reset (if WDT was
enabled).
3. From an interrupt source, see Section 8.11
“Interrupts” for more information.
On waking from Sleep, the processor will continue to
execute the instruction immediately following the
SLEEP instruction. If the WUR bit is also set, upon
waking from Sleep, the device will reset. If the GIE bit
is also set, upon waking from Sleep, the processor will
branch to the interrupt vector. Please see
Section 8.11 “Interrupts” for more information.
The TO and PD bits can be used to determine the
cause of the device Reset. The TO bit is cleared if a
WDT time-out occurred and subsequently caused a
wake-up. The PD bit, which is set on power-up, is
cleared when SLEEP is invoked.
.
The WDT is cleared when the device wakes from
Sleep, regardless of the wake-up source.
Note: A Reset generated by a WDT time-out
does not drive the MCLR pin low.
Note: Caution: Right before entering Sleep,
read the input pins. When in Sleep, wake-
up occurs when the values at the pins
change from the state they were in at the
last reading. If a wake-up on change
occurs and the pins are not read before
re-entering Sleep, a wake-up will occur
immediately even if no pins change while
in Sleep mode.
Note: Caution: Right before entering Sleep,
read the comparator Configuration
register(s) CM1CON0 and CM2CON0.
When in Sleep, wake-up occurs when the
comparator output bit C1OUT and C2OUT
chang e f rom the state th ey we re in at th e
last reading. If a wake-up on comparator
change occurs and the pins are not read
before re-entering Sleep, a wake-up will
occur i mmediate ly, even if no p ins chan ge
while in Sleep mode.
2012-2016 Microchip Technology Inc. DS40001652D-page 49
PIC16F527
8.11 Interrupts
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
These following interrupt sources are available on the
PIC16F5 27 dev ic e:
• Timer0 Overflow
• ADC Completion
• Comparator Output Change
• Interru pt-o n-c han ge pin
Refer to the corresponding chapters for details.
8.11.1 OPERATION
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
The enable bits for specific interrupts can be found in
the INTCON1 register. An interrupt is recorded for a
specific interrupt via flag bits found in the INTCON0
register.
The ADC Conversion flag and the Timer0 Overflow
flags wil l b e s et re gard les s of th e s t at us o f th e G IE an d
individual interrupt enable bits.
The Comparator and Interrupt-on-change flags must
be enabled for use. One or both of the comparator
outputs can be enabled to affect the interrupt flag by
clearing the C1WU bit in the CM1CON0 register and
the C2WU bit in the CM2CON0 register. The Interrupt-
on-change flag is enabled by clearing the RAWU bit in
the OPTION register.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Cur rent Program Counter (PC) is p ushed onto th e
stack
• Several registers are automatically switched to a
secondary set of regi sters to store cr itical data.
(See Section 8.12 “Automatic Context Switch-
ing”)
• PC is loaded with the interrupt vector 0004h
The firmwa re within the Interru pt Service Rou tine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interr upt s. Bec ause the GIE b it is clea red, a ny in terrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
8.12 Automatic Context Switching
While the device is executing from the ISR, a
secondary set of W, STATUS, FSR and BSR registers
are used by the CPU. These registers are still
addressed at the same location, but hold persistent,
independent values for use inside the ISR. This allows
the contents of the primary set of registers to be
unaf fect ed by inter rupts in t he main l in e execut ion. Th e
contents of the secondary set of context registers are
visible in the SFR map as the IW, ISTATUS, IFSR and
IBSR registers. When executing code from within the
ISR, these registers will read back the main line
context, and vice versa.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, switching back to the
original set of critical registers and setting the GIE bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
8.13 Interrupts during Sleep
Any of the interrupt sources can be used to wake from
Sleep. To wake from Sleep, the peripheral must be
operating without the system clock. The interrupt
source must have the appropriate Interrupt Enable
bit(s) set prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
proce ssor will bran ch to the inter rupt vector . O therwise,
the p r oc es sor wil l co nt i nue ex e cu ti n g in st r uc tio n s a fte r
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the Section 8.10
“Power-down Mod e (Sleep)” for more details.
Note 1: Individual interrupt flag bits may be set,
regardless of the state of any other
enable bits.
2: All inte rrupts wi ll be ignore d while the G IE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
3: All interrupts should be disabled prior to
executi ng writes or row e rases in the self-
writable Flash data memory.
4: The user must manage the contents of
the context registers if they are using
interrupts that will vector to the Interrupt
Service Ro utine (ISR). The context regi s-
ters (IW, ISTATUS, IFSR and IBSR)
power up in unknown states following
POR and BOR events.
PIC16F527
DS40001652D-page 50 2012-2016 Microchip Technology Inc.
TABLE 8-7: INTERRUPT PRIORITIES
Vector or
In Sleep GIE WUR
Wake-up and Vector
W ake-up Reset
Wake-up Inline
Watchdog
Wake-up Inline
Watchdog
W ake-up Reset
1X
X
X
X
1
1
1
11
1
0
00
0
2012-2016 Microchip Technology Inc. DS40001652D-page 51
PIC16F527
8.14 Regi ster Definitions — Interrupt Control
REGISTER 8-2: INTCON0 REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
ADIF CWIF T0IF RAIF — — — GIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared by software)
0 = A/D conversion has not completed or has not been started
bit 6 CWIF: Comparator 1 or 2 Interrupt Flag bit
1 = Comparator interrupt-on-change has occurred(1)
0 = No change in Comparator 1 or 2 output
bit 5 T0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared by software)
0 = TMR0 register did not overflow
bit 4 RAIF: Port A Interrupt-on-change Flag bit
1 = Wake-up or interrupt has occurred (cleared in software)(2)
0 = Wake-up or interrupt has not occurred
bit 3-1 Unimplemented: Read as ‘0’
bit 0 GIE: Global Interrupt Enable bit
1 = Interrupt sets PC to address 0x004 (Vector to ISR)
0 = Interrupt causes wake-up and inline code execution
Note1: This bit only functions when the C1WU or C2WU bits are cleared (see Register 10-1 and Register 10-2).
2: The RAWU bit of the OPTION register must be cleared to enable this function (see Register 4-2).
PIC16F527
DS40001652D-page 52 2012-2016 Microchip Technology Inc.
REGISTER 8-3: INTCON1 REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0
ADIE CWIE T0IE RAIE — — — WUR
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 ADIE: A/D Co nverter (ADC) Interr upt Enab le bit
1 = Enables the ADC interrupt
0 = Disables the AD C interrup t
bit 6 CWIE: Comparator 1 and 2 Interrupt Enable bit
1 = Enables the Comparator 1 and 2 Interrupt
0 = Disables the Comparator 1 and 2 Interrupt
bit 5 T0IE: Ti mer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 RAIE: Port A on Pin Change Interrupt Enable bit
1 = Interrupt-on-change pin enabled
0 = Interrupt-on-change pin disabled
bit 3-1 Unimplemented: Read as ‘0’
bit 0 WUR: Wake-up Reset Enable bit
1 = Interrupt source causes device Reset on wake-up
0 = Interrupt source wakes up device from Sleep (Vector to ISR or inline execution)
2012-2016 Microchip Technology Inc. DS40001652D-page 53
PIC16F527
8.15 Program Verification/Code
Protection
If the co de protection bit has not been prog rammed, the
on-chip program memory can be read out for
verification purposes.
The first 64 locations and the last location (OSCCAL)
can be read, regardless of the code protection bit
setting.
8.16 ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other code
identification numbers. These locations are not
accessible during normal execution, but are readable
and writable during Program/Verify.
Use only the lower four bits of the ID locations and
always program the upper eight bits as ‘0’s.
8.17 In-Circuit Serial Programming™
The PIC16F527 microcontroller can be serially
progra mmed w hile in t he en d app licati on c ircuit. This is
simply don e with two lines fo r clock and da ta, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware, or a custom
firmware, to be programmed.
The devices are placed into a Program/Verify mode by
holding the ICSPCLK and ICSPDAT pins low while
raising the MCLR (VPP) pin from VIL to VIHH (see
programming specification). ICSPCLK becomes the
programming clock and ICSPDAT becomes the
programming data. Both ICSPCLK and ICSPDAT are
Schmitt Trigger inputs in this mode.
After Reset, a 6-bit command is then supplied to the
device. D ependi ng on the c omman d, 14 bits of program
data are then supplied to or from the device, depending
if the command was a load or a read. For complete
details of serial programming, please refer to the
PIC16F527 Programming Specifications.
A typical In-Circuit Serial Programming connection is
shown in Figure 8-14.
FIGURE 8-14: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
To Normal
Connections
VDD
VSS
MCLR/VPP
ICSPCLK
ICSPDAT
+5V
0V
VPP
CLK
Data
VDD
PIC® Device
PIC16F527
DS40001652D-page 54 2012-2016 Microchip Technology Inc.
9.0 ANALOG-TO-DIGITAL (A/D)
CONVERTER
The A/D Converter allows conversion of an analog
signal into an 8-bit digital signal.
9.1 Clock Divisors
The ADC has four clock source settings ADCS<1:0>.
There are three divisor values 16, 8 and 4. The fourth
setting is INTOSC with a di vi so r of four. These s ett ing s
will allow a proper conversion when using an external
oscill ato r at s pe eds from 20 MHz to 350 kHz. Using a n
external oscillator at a frequency below 350 kHz
requires the ADC oscillator setting to be INTOSC/4
(ADCS<1:0> = 11) for val id ADC result s.
The ADC requires 13 TAD periods to complete a
conversion. The divisor value s do not affect the number
of TAD periods required to perform a conversion. The
divisor values determine the length of the TAD period.
When the ADCS<1:0> bits are changed while an ADC
conversion is in pro cess, the new ADC clo ck source will
not be se lected until the next conversion is started. This
clock source selection will be lost when the device
enters Sleep.
9.1.1 VOLTAGE REFERENCE
There is n o external voltage refere nce for the ADC. The
ADC reference voltage will always be VDD.
9.1.2 ANALOG MODE SELECTION
The ANS<7:0> bits are used to configure pins for
analog input. Upon any Reset, ANS<7:0> defaults to
FF. This configures the affected pins as analog inputs.
Pins configured as analog inputs are not available for
digital output. Users should not change the ANS bits
while a conversion is in process. ANS bits are active
regardless of the condition of ADON.
9.1.3 ADC CHANNEL SELECTION
The CHS bits are used to select the analog channel to
be sampled by the ADC. The CHS<3:0> bits can be
change d at any time w itho ut adversely effec ting a co n-
version. To acquire an external analog signal, the
CHS<3:0> selection must match one of the pin(s)
selected by the ANS<7:0> bits. When the ADC is on
(ADON = 1) a nd a channel i s selected that is also b eing
used by the comparator, then both the comparator and
the ADC will see the analog voltage on the pin.
When the CHS<3:0> bits are changed during an ADC
conversion, the new channel will not be selected until
the current conversion is completed. This allows the
current conversion to complete with valid results. All
channel selection information will be lost when the
device enters Sleep.
9.1.4 T HE GO /D ONE BIT
The GO/DONE bit is us ed to d e te r mi n e th e s tat u s o f a
convers ion, to start a co nversion and to manu ally halt a
conversion in process. Setting the GO/DONE bit starts
a conversion. When the conversion is complete, the
ADC module clears the GO/DONE bit and sets the
ADIF bit in the INTCON0 register.
A conversion can be terminated by manually clearing
the GO/DONE bit while a conversion is in process.
Manual termination of a conversion may result in a
partially converted result in ADRES.
The GO/DONE bit is cleared when the device enters
Sleep, sto pping th e current conve rsion. Th e ADC doe s
not have a dedicated oscillator, it runs off of the
instruction clock. Therefore, no conversion can occur in
Sleep.
The GO/DONE bit cannot be set when ADON is clear.
9.1.5 A/D ACQUISITION REQUIREMENTS
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 9-1. The source
impedance (RS) and the internal sampling swit ch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 9-1.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 9-1 may be used. This equation
assumes that 1/2 LSb error is used (256 steps for the
ADC). The 1/2 LSb erro r is the maximum er ror allow ed
for the ADC to meet its specified resolution.
Note: The ADC clock is derived from the
instruction clock. The ADCS divisors are
then applied to create the ADC clock
Note: It is the user’s respon sibility to ensur e that
the use of the ADC and op amp
simultaneously on the same pin does not
adversely affect the signal being
monitored or adversely effect device
operation.
2012-2016 Microchip Technology Inc. DS40001652D-page 55
PIC16F527
EQUATION 9-1: ACQUISITION TIME EXAMPLE
FIGURE 9-1: ANALOG INPUT MODULE
Note 1: The ch arge hol ding capa citor ( CHOLD) is
not discharged after each conversion.
2: The max imum re commend ed impe dance
for analog sources is 10 k. This is
required to meet the pin leakage
specification.
Assumptions:
Temperature = 50°C and exte r n al im pe da n ce of 10 k
5.0V V DD
Tacq = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
=T
AMP + TC + TCOFF
=2
s + TC + [(Temperature - 25°C)(0.05
s/°C)]
Solving for Tc:
Tc = CHOLD (RIC + RSS + RS) ln(1/512)
= -25pF (l k
+ 7 k
+ 10 k
) ln(0.00196)
=2.81
s
Therefore:
Tacq = 2
s + 2.81
s + [(50°C-25°C)(0.0 5
s/°C)]
=6.06
s
CPIN
VA
Rs ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I LEAKAGE
RIC 1k
Sampling
Switch
SS Rss
CHOLD = 25 pF
VSS/VREF-
6V
Sampling Switch
5V
4V
3V
2V
567891011
(k)
VDD
± 500 nA
RSS
Legend: CPIN = Input Capacitance
VT= Threshold Vo ltage
ILEAKAGE = Leakage current at the pin due
to various junctions
RIC = Interconnect Resistance
SS = Sampling Switch
CHOLD = Sample/Hold Capacitance
PIC16F527
DS40001652D-page 56 2012-2016 Microchip Technology Inc.
9.1.6 ANALOG CONVERSION RESULT
REGISTER
The ADRES register contains the results of the last
conversion. These results are present during the
sampling period of the next analog conversi on process.
After the sampling period is over, ADRES is cleared
(= 0). A ‘leading one’ is then right shifted into the
ADRES to serve as an internal conversion complete
bit. As each bit weight, starting with the MSB, is
converted, the leading one is shifted right and the
convert ed bit is stuf fed into ADRES. Aft er a total of nin e
right shifts of the ‘leading one’ have taken place, the
conversion is complete; the ‘leading one’ has been
shifted out and the GO/DONE bit is cleared.
If the GO/DONE bit is cleared in software during a
conversion, the conversion stops and the ADIF bit will
not be set to a ‘1’. The data in ADRES is the partial
conversion result. This data is valid for the bit weights
that have been converted. The position of the ‘leading
one’ determines the number of bits that have been
converted. The bits that were not converted before the
GO/DONE was cleared are unrecoverable.
REGISTER 9-1: ADCON0: A/D CONTROL REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
ADCS1 ADCS0 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, rea d as ‘0’
-n = Value at PO R ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unk no w n
bit 7-6 ADCS<1:0>: ADC Conversion Clock Select bits
00 =F
OSC/16
01 =F
OSC/8
10 =F
OSC/4
11 = INTOSC/4
bit 5-2 CHS<3:0>: AD C C hannel Select bi ts(1)
0000 = Chann el 0 (A N 0)
0001 = Chann el 1 (A N 1)
0010 = Chann el 2 (A N 2)
0011 = Chann el 3 (A N 3)
0100 = Chann el 4 (A N 4)
0101 = Chann el 5 (A N 5)
0110 = Chann el 6 (A N 6)
0111 = Chann el 7 (A N 7)
1xxx = Reserv ed
1111 = 0.6V Fixed Input Reference (VFIR)
bit 1 GO/DONE: ADC Conversion St atus bit(2)
1 = A D C c onversion i n progress. Setting this b i t starts an ADC conversion cycle. Th i s b it i s automat ical l y
cleared by hardw ar e w he n th e AD C is done conv er tin g.
0 = ADC c onv er si on co mp let ed /n ot in pr ogr es s. Man ua ll y clearing th is bit w hil e a co nve rs io n is i n pr oc e ss
termi nat es th e cur r ent convers io n.
bit 0 ADON: ADC Enable bit
1 = ADC module is operating
0 = A D C m odule is shu t-o ff and co nsumes no po w er
Note 1: CHS<3:0> bits default to 1 after any Reset.
2: If the ADON bit is clear, the GO/DONE bit cannot be set.
2012-2016 Microchip Technology Inc. DS40001652D-page 57
PIC16F527
EXAMPLE 9-1: PERFORMING AN
ANALOG-TO-DIGITAL
CONVERSION
EXAMPLE 9-2: CHANNEL SELECTION
CHANGE DURING
CONVERSION
REGISTER 9-2: ADRES: A/D CONVERSION RESULTS REGISTER
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ADRES<7:0>: ADC Result Register bits
;Sample code operates out of BANK0
MOVLW 0xF1 ;configure A/D
MOVWF ADCON0
BSF ADCON0, 1 ;start conversion
loop0 BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop0
MOVF ADRES, W ;read result
MOVWF result0 ;save result
BSF ADCON0, 2 ;setup for read of
;channel 1
BSF ADCON0, 1 ;start conversion
loop1 BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop1
MOVF ADRES, W ;read result
MOVWF result1 ;save result
BSF ADCON0, 3 ;setup for read of
BCF ADCON0, 2 ;channel 2
BSF ADCON0, 1 ;start conversion
loop2 BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop2
MOVF ADRES, W ;read result
MOVWF result2 ;save result
MOVLW 0xF1 ;configure A/D
MOVWF ADCON0
BSF ADCON0, 1 ;start conversion
BSF ADCON0, 2 ;setup for read of
;channel 1
loop0 BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop0
MOVF ADRES, W ;read result
MOVWF result0 ;save result
BSF ADCON0, 1 ;start conversion
BSF ADCON0, 3 ;setup for read of
BCF ADCON0, 2 ;channel 2
loop1 BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop1
MOVF ADRES, W ;read result
MOVWF result1 ;save result
BSF ADCON0, 1 ;start conversion
loop2 BTFSC ADCON0, 1;wait for ‘DONE’
GOTO loop2
MOVF ADRES, W ;read result
MOVWF result2 ;save result
CLRF ADCON0 ;optional: returns
;pins to Digital mode and turns off
;the ADC module
PIC16F527
DS40001652D-page 58 2012-2016 Microchip Technology Inc.
9.1.7 SLEEP
This ADC does not have a dedicated ADC clock, and
therefore, no conversion in Sleep is possible. If a
conversion is underway and a Sleep command is
executed, the GO/DONE and ADON bits will be
cleared. This will stop any conversion in process and
power-down the ADC module to conserve power. Due
to the nature of the conversion process, the ADRES
may contain a partial conversion. At least one bit must
have bee n conve rted prior to Slee p to have pa rtial co n-
version data in ADRES. The ADCS and CHS bits are
reset to their default condition; ANS<7:0> = 1s and
CHS<3:0> = 1s.
For accurate conversions, T AD must meet the following:
•500ns < T
AD < 50 s
•TAD = 1/(FOSC/divisor)
Shaded areas indicate TAD out of range for accurate
conversions. If analog input is desired at these
frequencies, use INTOSC/8 for the ADC clock source.
TABLE 9-1: TAD FOR ADCS SETTINGS WITH VARIOUS OSCILLATORS
TABLE 9-2: EFFECTS OF SLEEP ON ADCON0
Source ADCS
<1:0> Divisor 20
MHz 16
MHz 8 MHz 4 MHz 1 MHz 500
kHz 350
kHz 200
kHz 100
kHz 32 kHz
INTOSC 11 4——.5s1s — — — — — —
FOSC 10 4.2 s.25 s.5s1s4s8s11s20s40s125 s
FOSC 01 8.4 s.5s1s2s8s16s23s40s80 s250 s
FOSC 00 16 .8 s1s2s4s16s32s46s80 s160 s500 s
ANS<7:0> ADCS1 ADCS0 CHS<3:0> GO/DONE ADON
Entering Sleep Unchanged 11 1 0 0
Wake or Reset 111100
2012-2016 Microchip Technology Inc. DS40001652D-page 59
PIC16F527
10.0 COMPARATOR(S)
This device contains two comparators and a
comparator voltage reference.
FIGURE 10-1: COMPAR ATORS BLOCK DIAGRAM
+
-
C1IN+
C1IN-
C1ON C1POL
C1T0CS
C1
OUT
C1OUTEN
C1OUT (R
egister)
T0CKI Pin
T0CKI
QD
SREAD
CM1CON0
C2WU
C1PREF
C1NREF
+
-
C2IN+
C2IN-
C2ON C2POL
C2PREF1
C2NREF
CV
REF
C2PREF2
C2
OUT
C2OUTEN
C2OUT (R
egister)
QD
S
CW
IF
READ
CM2CON0
C1WU
1
0
1
0
1
0
1
0
1
0
1
0
Fixed Input
Reference (V
FIR
)
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DS40001652D-page 60 2012-2016 Microchip Technology Inc.
10.1 Comparator Operation
A singl e com pa rato r is shown i n Figure 10-2 along w ith
the relationship between the analog input levels and
the digit al ou tput. When the an alog input a t VIN+ is less
than the analog input VIN-, the outp ut of the comp arator
is a digital low level. The shaded area of the output of
the comparator in Figure 10-2 represent the
uncert ainty due to inp ut offset s and respons e time. See
Table 15-2 for Common Mode Voltage.
FIGURE 10-2: SINGLE COMPARATOR
10.2 Comparator Reference
An internal reference si gnal may be used depending on
the com parato r operatin g mode. The analo g signal that
is presen t at VIN- is compared to the signal at VIN+, and
the digital output of the comparator is adjusted
accordingly (see Figure 10-2). Please see
Section 11.0 “Comparator Voltage Reference
Module” for internal reference specifications.
10.3 Comparator Response Time
Response time is the minimum time after selecting a
new reference voltage or input source before the
comparator output is to have a valid level. If the
comparator inputs are changed, a delay must be used
to allow the comparator to settle to i ts new state. Please
see Table 15-7 for comparator response time
specifications.
10.4 Comparator Output
The comparator output is read through the CxOUT bit
in the CM1CON0 or CM2CON0 register. This bit is
read-only. The comparator output may also be used
externally, see Section 10.1 “Comparator Opera-
tion”.
10.5 Comparator Wake-up Flag
The Comparator Wake-up Flag bit, CWIF, in the
INTCON0 register, is set whenever all of the following
conditions are met:
•C1WU
= 0 (CM1CON0<0>) or
C2WU = 0 (CM2CON0<0>)
• CM1CON0 or CM2CON0 has been read to latch
the last kn own state of the C1OU T and C2OUT bit
(MOVF CM1CON0, W)
• The output of a comparator has changed state
The wake-up flag may be cleared in software or by
anot her device Reset.
10.6 Comparator Operation During
Sleep
When the comparator is enabled it is active. To
minimi ze power co nsumption wh ile in Sleep mod e, turn
off the comparator before entering Sleep.
10.7 Ef fects of Reset
A Power-on Reset (POR) forces the CMxCON0
register to its Reset state. This forces the Comparator
input pins to analog Reset mode. Device current is
minimized when analog inputs are present at Reset
time.
10.8 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 10-3. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. Th e analog input, th erefore, must be betw een
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum source impedance of 10 k is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
–
+
VIN+
VIN-Result
Result
VIN-
VIN+
Note: Analog levels on any pin that is defined as
a digital input may cause the input buffer
to consume more current than is speci-
fied.
2012-2016 Microchip Technology Inc. DS40001652D-page 61
PIC16F527
FIGURE 10-3: ANALOG INPUT MODE
VA
RS < 10 K
AIN CPIN
5pF
VDD
VT = 0.6V
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
Legend: CPIN = Input Capacitance
VT= Threshold Voltage
ILEAKAGE = Leakage Current at the Pin
RIC = Inter conne ct Resi stance
RS= Source Impedance
VA = Analog Voltage
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DS40001652D-page 62 2012-2016 Microchip Technology Inc.
10.9 Regi ster Definitions — Comparator Control
REGISTER 10-1: CM1CON0: COMPARATOR C1 CONTROL REGISTER
R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C1OUT: Comparator Output bit
1 = VIN+ > VIN-
0 = VIN+ < VIN-
bit 6 C1OUTEN: Comparator Output Enable bit(1)
1 = Output of comparator is NOT placed on the C1OUT pin
0 = Output of comparator is placed in the C1OUT pin
bit 5 C1POL: Comparator Output Polarity bit
1 = Output of comparator is not inverted
0 = Output of comparator is inverted
bit 4 C1T0CS: Comparator TMR0 Clock Source bit
1 = TMR0 clock source selected by T0CS contro l bit
0 = Comparator output used as TMR0 clock source
bit 3 C1ON: Compara tor Enab le bit
1 = Comparator is on
0 = Comparator is off
bit 2 C1NREF: Comparator Nega tive Reference Select bit(2)
1 = C1IN- pin
0 = 0.6V Fixed Input Reference (VFIR)
bit 1 C1PREF: Comparator Positive Reference Select bit(2)
1 = C1IN+ pin
0 = C1IN- pin
bit 0 C1WU: Comparator Wake-up On Change Enable bit(3)
1 = Wake-up On Comparator Change is disabled
0 = Wake-up On Comparator Change is enabled
Note 1: Overrides TRIS control of the port.
2: When this bit selects an I/O pin and the comparator is turned on, this feature will override the TRIS and
ANSEL se ttin gs to m ake the res pec ti ve p in an a nalog input. Th e v alu e in the AN SEL re gis ter, howe ver, is
not overw rit ten. When the comparato r is tu rned of f, th e res pec tiv e pi n will revert back to the origi na l TR IS
and ANSEL settings.
3: The C1WU bit must be cleared to enable the CWIF function. See the INTCON0 register (see Register 8-
2) for more information.
2012-2016 Microchip Technology Inc. DS40001652D-page 63
PIC16F527
REGISTER 10-2: CM2CON0: COMPARATOR C2 CONTROL REGISTER
TABLE 10-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
R-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 C2OUT: Comparator Output bit
1 = VIN+ > VIN-
0 = VIN+ < VIN-
bit 6 C2OUTEN: Comparator Output Enable bit(1)
1 = Output of comparator is NOT placed on the C2OUT pin
0 = Output of comparator is placed in the C2OUT pin
bit 5 C2POL: Comparator Output Polarity bit
1 = Output of comparator not inverted
0 = Output of comparator inverted
bit 4 C2PREF2: Comparator Positive Reference Select bit
1 = C1IN+ pin
0 = C2IN- pin
bit 3 C2ON: Compara tor Enab le bit
1 = Comparator is on
0 = Comparator is off
bit 2 C2NREF: Comparator Nega tive Reference Select bit(2)
1 = C2IN- pin
0 = CVREF
bit 1 C2PREF1: Comparator Positive Reference Select bit(2)
1 = C2IN+ pin
0 = C2PREF2 controls analog input selection
bit 0 C2WU: Comparator Wake-up on Change Enable bit(3)
1 = Wake-up on Comparator change is disabled
0 = Wake-up on Comparator change is enabled.
Note 1: Overrides TRIS control of the port.
2: When this bit selects an I/O pin and the comparator is turned on, this feature will override the TRIS and
ANSEL se ttin gs to m ake the res pec ti ve p in an a nalog input. Th e v alu e in the AN SEL re gis ter, however, is
not overwritten. When the comparator is turned off, the respective pin will revert back to the original TRIS
and ANSEL settings.
3: The C2WU bit must be cleared to enable the CWIF function. See the INTCON0 register (see Register 8-
2) for more information.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
STATUS — — PA0 TO PD ZDCC16
CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 62
CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 63
TRIS I/O Control Register (TRISA, TRISB, TRISC) —
Legend: x = Unknown, u = Unchanged, – = Unimplemented, read as ‘0’, q = D epends on condition.
PIC16F527
DS40001652D-page 64 2012-2016 Microchip Technology Inc.
11.0 COMPARATOR VOLTAGE
REFERENC E MODULE
The Comparator Voltage Reference module also
allows the selection of an internally generated voltage
reference for one of the C2 comparator inputs. The
VRCON register (see Register 11-1) controls the
voltage reference module shown in Figure 11-1.
11.1 Configuring The Voltage
Reference
The voltage reference can output 32 voltage levels; 16
in a high range and 16 in a low range.
Equation 11-1 determines the output voltages:
EQUATION 11-1:
11.2 Voltage Reference Accuracy
The full range of VSS to VDD cannot be realized due to
construction of the module. The transistors on the top
and bottom of the resistor ladder network (see
Figure 11-1) keep CVREF from approaching VSS or
VDD. The exception is when the module is disabled by
clearing the VREN bit of the VRCON register. When
disabled, the reference voltage is VSS when VR<3:0>
is ‘0000’ and the VR R bit of the V RC ON register i s set.
This allows the comparator to detect a zero crossing
and not consume the CVREF module current.
The voltage reference is VDD derived and, therefore,
the CV REF output changes with fluctuations in VDD. The
tested absolute accuracy of the comparator voltage
reference can be found in Section 15.0 “Electrical
Characteristics”.
VRR = 1 (low range):
VRR = 0 (high range):
CVREF = (VDD/4) + (VR<3:0> x VDD/32)
CVREF = (VR<3:0>/24) x VDD
REGISTER 11-1: VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0 R/W-0 R/W-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0
VREN VROE VRR —VR3VR2VR1VR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 VREN: CVREF Enable bit
1 = CVREF is powered on
0 = CVREF is powered down, no current is drawn
bit 6 VROE: CVREF Out put E nable bit(1)
1 = CVREF output is enabled
0 = CVREF output is disabled
bit 5 VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 4 Unimplemented: Read as ‘0’
bit 3-0 VR<3:0> CVREF Value Selection bits
When VRR = 1: CVREF= (VR<3:0>/24)*VDD
When VRR = 0: CVREF= VDD/4+(VR<3:0>/32)*VDD
Note 1: When this bit is set, the TRIS for the CVREF pin is overridden and the analog voltage is placed on the
CVREF pi n.
2012-2016 Microchip Technology Inc. DS40001652D-page 65
PIC16F527
FIGURE 11-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
TABLE 11-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 64
CM1CON0 C1OUT C1OUTEN C1POL C1T0CS C1ON C1NREF C1PREF C1WU 62
CM2CON0 C2OUT C2OUTEN C2POL C2PREF2 C2ON C2NREF C2PREF1 C2WU 63
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’, q = value depends on condition.
VDD 8R R R
VREN
16-1 Analog
MUX
CVREF to
Comparator 2
Input
VR<3:0>
VREN
VR<3:0> = 0000
VRR
VRR
8R
RR
16 Stages
CVREF
VROE
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DS40001652D-page 66 2012-2016 Microchip Technology Inc.
12.0 OPERATIONAL AMPLIFIER
(OPA) MODUL E
The OPA module has the following features:
• Two independent Operational Amplifiers
• External connections to all ports
• 3 MHz Gain Bandwidth Product (GBWP)
12.1 OPACON Register
The OPA module i s ena bled by s etting the O PAxON bit
of the OPACON Register.
FIGURE 12-1: OPA MODULE BLOCK DIAGRAM
Note: When OPA1 or OPA2 is enab led, th e OP1
pin or OP2 pin, respectively, is driven by
the op amp output, not by the port driver.
Refer to Table 15-5 for the electr ical sp ec-
ifications for the op amp output drive
capability.
OPA1
OPACON<OPA1ON>
OP1+
OP1-
OP1
OPA2
OPACON<OPA2ON>
OP2+
OP2-
OP2
2012-2016 Microchip Technology Inc. DS40001652D-page 67
PIC16F527
REGISTER 12-1: OPACON: OP AMP CONTROL REGISTER
12.2 Effects of a Reset
A device Reset forces all registers to their Reset state.
This disables both op amps.
12.3 OPA Module Performance
Common AC and DC performance specifications for
the OPA module:
• Common Mode Voltage Range
• Leakage Current
• Input Offset Voltage
• Open Loop Gain
• Gain Bandwidth Product (GBWP)
Common mo de volta ge range is the specified voltage
range for the OP+ and OP- inputs, for which the OPA
module will perform to within its specifications. The
OPA mod ule is desi gn ed to opera te with inp ut volt age s
between 0 and VDD-1.5V. Behavior for common mode
voltages greater than VDD-1.5V, or below 0V, are
bey ond the normal oper ating range.
Leakage current is a measure of the small source or
sink currents on the OP+ and OP- inputs. To minimize
the ef fect of leakage curr ents, the ef fective impedances
connected to the OP+ and OP- inputs should be kept
as small as possible and equal.
Input offset voltage is a me asur e of th e vol tag e dif f er-
ence between the OP+ and OP- inputs in a closed loop
circuit with the OPA in its linear region. The offset volt-
age wil l appear as a DC of fset in the out put equal to the
input offset volt age, mu ltipli ed by the gai n of the circui t.
The inpu t of fset vo ltage is also affec ted by th e commo n
mode voltage.
Open loop ga in is the ratio of th e output volt age to th e
differential input voltage, (OP+) - (OP-). The gain is
greatest at DC and falls off with frequency.
Gain Bandwidth Product or GBWP is the frequency
at which the open loop gain falls off to 0 dB.
12.4 Ef fects of Sleep
When enabled, the op amps continue to operate and
consum e cu rrent wh ile the processo r is in Sl eep m ode.
TABLE 12-1: REGISTERS ASSOCIATED WITH THE OPA MODULE
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — OPA2ON OPA1ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-2 Unimplemented: Read as ‘0’
bit 1 OPA2ON: Op Amp Enable bit
1 = Op amp 2 is enabled
0 = Op amp 2 is disabled
bit 0 OPA1ON: Op Amp Enable bit
1 = Op amp 1 is enabled
0 = Op amp 1 is disabled
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on
page
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 29
OPACON — — — — — —OPA2ONOPA1ON 67
TRIS I/O Control Registers (TRISA, TRISB, TRISC) —
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for the OPA
module.
PIC16F527
DS40001652D-page 68 2012-2016 Microchip Technology Inc.
13.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categorie s.
•Byte-oriented operations
•Bit-oriented operations
•Literal and control operations
Each PIC16 instruction is a 12-bit word divided into an
opcode, which specifies the instruction type, and one
or more operands which further specify the operation
of the instruction. The formats for each of the
categories is presented in Figure 13-1, while the
various opcode fields are summarized in Table 13-1.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designa tor w h ic h s el ects the numbe r of the bi t affected
by the ope rati on, while ‘f’ repre sents the num ber of th e
file in which the bit is located.
For literal and control operations, ‘k’ represents an
8 or 9-bit constant or literal value.
TABLE 13-1: OPCOD E FIELD
DESCRIPTIONS
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a co nditio nal test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 s.
Figure 13-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal
number:
0xhhh
where ‘h’ signifies a hexadecimal digit.
FIGURE 13-1: GENERAL FORMAT FOR
INSTRUCTIONS
Field Description
f Register file address (0x 00 to 0x7F)
W Working register (accumulator)
b Bit address within an 8-bit file register
k Literal field, constant dat a or label
x Don’t care location (= 0 or 1)
The assembler wil l generate code with x = 0. It is
the recommende d form of use f or compatibilit y with
all Microchip software tools.
d Destination select;
d = 0 (store resu lt in W)
d = 1 (store result in file register ‘f’)
Default is d = 1
label Label name
TOS Top-of-Stack
PC Program Counter
WDT Watchdog Timer counter
TO Time-out bit
PD Po w e r- dow n bi t
dest Destination, either the W register or the specified
register file loc ation
[ ] Options
( ) Contents
ÆAssigned to
< > Register bit field
ŒIn the set of
italics User defined term (font is courier)
Byte-oriented file r e gister operations
11 6 5 4 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register ope rations
11 8 7 5 4 0
OP C O D E b (BIT #) f (FIL E #)
b = 3-bit bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
11 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
Literal and control operations – GOTO instruction
11 9 8 0
OPCODE k (literal)
k = 9-bit immediate value
2012-2016 Microchip Technology Inc. DS40001652D-page 69
PIC16F527
TABLE 13-2: INSTRUCTION SET SUMMARY
Mnemonic,
Operands Description Cycles 1 2-Bit Opcode Status
Affected Notes
MSb LSb
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
—
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
—
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Incr eme nt f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001
11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C, DC, Z
Z
Z
Z
Z
Z
None
Z
None
Z
Z
None
None
C
C
C, DC, Z
None
Z
1, 2, 4
2, 4
4
2, 4
2, 4
2, 4
2, 4
2, 4
2, 4
1, 4
2, 4
2, 4
1, 2, 4
2, 4
2, 4
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1(2)
1(2)
0100
0101
0110
0111
bbbf
bbbf
bbbf
bbbf
ffff
ffff
ffff
ffff
None
None
None
None
2, 4
2, 4
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLB
MOVLW
OPTION
RETFIE
RETLW
RETURN
SLEEP
TRIS
XORLW
k
k
—
k
k
k
k
—
—
k
—
—
f
k
AND literal with W
Call Subro uti ne
Clear Watchdog Timer
Unconditional branch
Inclusive OR literal with W
Move Literal to BSR Register
Move literal to W
Load OPTION register
Return from Interrupt
Return, place literal in W
Return, maintain W
Go into Standby mode
Load TRIS register
Exclusive OR literal to W
1
2
1
2
1
1
1
1
2
2
2
1
1
1
1110
1001
0000
101k
1101
0000
1100
0000
0000
1000
0000
0000
0000
1111
kkkk
kkkk
0000
kkkk
kkkk
0001
kkkk
0000
0001
kkkk
0001
0000
0000
kkkk
kkkk
kkkk
0100
kkkk
kkkk
0kkk
kkkk
0010
1111
kkkk
1110
0011
0fff
kkkk
Z
None
TO, PD
None
Z
None
None
None
None
None
None
TO, PD
None
Z
1
3
Note 1: The 9th bit o f t he pro gra m c oun ter wil l be fo rce d to a ‘0’ by any ins truc tio n tha t wri tes to th e PC exc ept for
GOTO. See Section 4.6 “Program Counter”.
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that
value pr ese nt on the pins t hemse lves. For e xamp le, if the dat a la tch is ‘1’ for a pin c onfigu red a s input and
is driven low by an external device, the data will be written back with a ‘0’.
3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state
latches of PORTA. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
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ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 f 31
d 01
Operation: (W) + (f) (dest)
Status Affected: C, DC, Z
Description: Add the contents of the W register
and register ‘f’. If ‘d’ is’0’, the result
is stored in the W register. If ‘d’ is
‘1’, the resu lt is sto r ed bac k in
register ‘f’.
ANDLW AND literal with W
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operation: (W).AND. (k) (W)
Status Affected: Z
Description: The contents of the W register are
AND’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 f 31
d [0,1]
Operation: (W) .AND. (f) (dest)
Status Affected: Z
Description: The contents of the W register are
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W register .
If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 f 31
0 b 7
Operation: 0 (f<b>)
Status Af fe cte d: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 f 31
0 b 7
Operation: 1 (f<b>)
Status Af fe cte d: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 f 31
0 b 7
Operation: skip if (f<b>) = 0
Status Af fe cte d: None
Descr iption : If bit ‘b ’ in reg ister ‘ f’ is ‘0’, then the
next instruction is skipped.
If bit ‘b’ is ‘0’, the n the nex t ins truc -
tion fetched during the current
instruction execution is discarded,
and a NOP is executed instead,
making this a 2-cycle instruction.
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BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 f 31
0 b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Desc ription : If bit ‘b ’ in reg ister ‘f’ is ‘ 1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed inste ad,
making this a 2-cycle instruction.
CALL Subroutine Call
Syntax: [ label ] CALL k
Operands: 0 k 255
Operation: (PC) + 1 Top-of-Stack;
k PC<7:0>;
(STATUS<6:5>) PC<10:9>;
0 PC<8>
Status Affected: None
Description: Subroutine call. First, return
address (PC + 1) is PUSHed onto
the stack. The 8-bit immedi ate
address is loaded into PC
bits <7:0>. The upper bi ts
PC<10:9> are loaded from
STATUS<6: 5>, PC<8> is cleare d.
CALL is a 2-cycle instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 f 31
Operation: 00h (f);
1 Z
Status Affected: Z
Description: The contents of register ‘f’ are
cleared and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W);
1 Z
Status Af fe cte d: Z
Description: The W register is cleared. Zero bit
(Z) is set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT;
0 WDT prescaler (if assigned);
1 TO;
1 PD
Status Af fe cte d: TO, PD
Description: The CLRWDT instruction resets the
WDT. It also re sets the pr escaler , if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 31
d [0,1]
Operation: (f) (dest)
Status Af fe cte d: Z
Description: The cont ents of regi ster ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register . If
‘d’ is ‘1’, th e result is stored back in
register ‘f’.
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DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 f 31
d [0,1]
Operation: (f) – 1 (dest)
Status Affected: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in regist er ‘f’.
DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 31
d [0,1]
Operation: (f) – 1 d; skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are
decr emente d. If ‘d’ is ‘0’, the res ult
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOP is executed
instead making it a 2-cycle instruc-
tion.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 511
Operation: k PC<8:0>;
STATUS<6:5> PC<10:9>
Status Affected: None
Description: GOTO is an unconditional bran ch .
The 9-bit immediate value is
loaded into PC bits <8:0>. The
upper bits of PC are loaded from
STATUS<6:5>. GOTO is a 2-cycle
instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 31
d [0,1]
Operati on: (f) + 1 (dest)
Status Af fe cte d: Z
Description: The cont ents of regi ster ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 31
d [0,1]
Operati on: (f) + 1 (dest), skip if result = 0
Status Af fe cte d: None
Description: The cont ents of regi ster ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘0’, then the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead making it a
2-cycle instruction.
IORLW Inclusive OR literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. (k) (W)
Status Af fe cte d: Z
Descripti on: The con ten ts of the W register are
OR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
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IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 31
d [0,1]
Operation: (W).OR. (f) (des t)
Status Affected: Z
Description: I nclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W re gister. If ‘d’ is ‘1’,
the result is placed back in registe r
‘f’.
MOVF Mov e f
Syntax: [ label ] MOVF f,d
Operands: 0 f 31
d [0,1]
Operation: (f) (dest)
Status Affected: Z
Description: The contents of register ‘f’ are
moved to destina tion ‘d’. If ‘d ’ is ‘0’,
destination is the W register. If ‘d’
is ‘1’, the destination is file
register ‘f’. ‘d’ = 1 is useful as a
test of a file register, since status
flag Z is affected.
MOVLB Move Literal to BSR
Syntax: [ label ] MOVLB k
Operands: 0 k 7
Operation: k (BSR)
Status Affected: None
Description: The 3-bit literal ‘k’ is loaded into
the BSR register.
MOVLW Move Literal to W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affected: None
Description: The 8-bit literal ‘k’ is loaded into
the W register. The “don’t cares”
will asse mbled as ‘0’s.
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 f 31
Operation: (W) (f)
Status Af fe cte d: None
Description: Move data from the W register to
register ‘f’.
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operati on: No operation
Status Af fe cte d: None
Descr ipti on : No operation.
OPTION Load OPTION Register
Syntax: [ label ] OPTION
Operands: None
Operation: (W) OPTION
Status Af fe cte d: None
Description: The content of the W register is
loaded into the OPTION register.
RETFIE Return From Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS PC
1 GIE
Status Af fe cte d: None
Description: The program counter is loaded
from the top of the stack (the
return addres s).
GIE bit of INTCON0 is set.
This is a 2-cycle instruction.
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RETLW Return with Literal in W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k (W);
TOS PC
Status Affected: None
Description: The W register is loaded with the
8-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address). This
is a 2-cycle ins truc tion.
RETURN Return
Syntax: [ label ] RETURN
Operands: None
Operation: TOS PC
Status Affected: None
Description: The program counter is loaded
from the top of the sta ck (the
return address). This is a 2-cycle
instruction.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 31
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag . If ‘d’ is ‘0’, the res ult
is placed in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
Cregister ‘f’
RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 31
d [0,1]
Operation: See description below
Status Af fe cte d: C
Description: The cont ents of regi ster ‘f’ are
rotated one bit to the right through
the Carry flag . If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
SLEEP Enter SLEEP Mode
Syntax: [label ]SLEEP
Operands: None
Operation: 00h WDT;
0 WDT prescaler
1 TO
0 PD
Status Af fe cte d: TO, PD
Description: T ime-out S tatus bit (TO) is s et. The
Power-dow n Status bit (PD) is
cleared.
The WDT and its prescaler are
cleared.
The proce sso r is pu t in to Sleep
mode wit h the osci llato r st op ped .
See S ecti on 8 .1 0 “Power -d own
Mode (Sleep)” on Sleep for more
details.
SUBWF Subtract W from f
Syntax: [label ] SUBWF f,d
Operands: 0 f 31
d [0,1]
Operati on: (f) – (W) dest)
Status Af fe cte d: C, DC, Z
Descr iption : Su btract (2’ s co mplemen t method )
the W reg ister fr om regist er ‘f’. If ‘d’
is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Cregister ‘f’
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SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 31
d [0,1]
Operation: (f<3:0>) (dest<7:4>);
(f<7:4>) (dest<3:0>)
Status Affected: None
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in W
register. If ‘d’ is ‘1’, the resu lt is
placed in register ‘f’.
TRIS Load TRIS Register
Syntax: [ label ] TRIS f
Operand s: f = 6
Operation: (W) TRIS register f
Status Affected: None
Description: TRIS register ‘f’ (f = 6, 7 or 8) is
loaded wi th the co nten t s of the W
register
XORLW Exclusive OR literal with W
Syntax: [ label ]XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
Description: The contents of the W register are
XOR’ed with the 8-bit literal ‘k’.
The result is placed in the W
register.
XORWF Exclusive O R W with f
Syntax: [ label ] XORWF f,d
Operands: 0 f 31
d [0,1]
Operation: (W) .XOR. (f) dest)
Status Af fe cte d: Z
Description: Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
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14.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a ful l range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
-MPASM
TM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Devic e Progra mmers
- MPLAB PM3 Device Programmer
• Low-Cost Demons tration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
14.1 MPLAB X Integrated Developme nt
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With com plete projec t managem ent, visual cal l graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multipl e project s with simu ltane ous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hin ts as you type
• Aut omati c c od e f orm atti ng bas ed on us er-d efi ned
rules
• Liv e parsing
User-Friendly, Custom iz abl e Interfa ce :
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project -Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultan eo us debuggin g sess io ns
File History and Bug Tracking:
• Loc al file hi story feature
• Built-in support for Bugzilla issue tracker
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14.2 MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Co mpilers inc lude an asse mbler , li nker and
utilities. The assembler generates relocatable object
files that can then be arc hiv ed or linked w i th ot her relo-
catable object files and archives to create an execut-
able file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assem-
bler inclu de:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Ri ch dire cti ve set
• Flexible macro language
• MPLAB X IDE compatibility
14.3 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files fo r the MPLINK Ob ject Linker , Int el® standa rd HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly co de
• Conditional assembly for multipurpose
sour ce fil es
• Directives that allow complete control over the
assembly process
14.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLI B Obje ct Libra rian man ages th e creati on and
modification of library files of precompiled code. When
a rout in e from a l ibra ry is cal led fro m a so urc e file, onl y
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, re placement, de letion and ex traction
14.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archi ved or link ed with other rel ocat ab le objec t
files and archives to create an executable file. Notable
features of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
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14.6 MPLAB X SIM Sof tware Simul ator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most periph erals and i nternal regi sters.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
developm ent too l.
14.7 MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgrad able through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cable s.
14.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 int erface and is connected to t he target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
14.9 PICkit 3 In-Circuit De bugger/
Programmer
The MPLAB PICkit 3 allows debugging and program-
ming of P IC and dsPIC Flash microcontrollers at a most
af fordable pr ice point us ing the powerfu l graphica l user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the tar-
get via a Microchip debug (RJ-11) connector (compati-
ble with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
14.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Devic e Programmer ca n read, verif y and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 h as high-spe ed co mmunicat ions an d
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
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14.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
use d in teac hing environments, for prot otyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a l ine of evaluation k its and demonstr a-
tion software for analog fil ter desi gn, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience t he specified d evice. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluati on kits.
14.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from co mpanies, such as Gimpel
and Trace S ystems
• Protocol Analyz er s from companie s, su ch as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
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15.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Ambient temperature under bias..........................................................................................................-40°C to +125°C
Storage temperature ............................................................................................................................-65°C to +150°C
Volta ge on VDD with respect to VSS ...............................................................................................................0 to +6.5V
Volta ge on MCLR with respect to VSS..........................................................................................................0 to +13.5V
Voltage on all other pins with respect to VSS................................................................................-0.3V to (VDD + 0.3V)
Total power dissipation(1) ..................................................................................................................................700 mW
Max. current out of VSS pin ....................... ..... ...... ..............................................................................................200 mA
Max. current into VDD pin...................................................................................................................................150 mA
Input clamp current, IIK (VI < 0 or VI > VDD)20 mA
Output clamp cur rent, IOK (VO < 0 or VO > VDD)20 mA
Max. output current sunk by any I/O pin...............................................................................................................25 mA
Max. output current sourced by any I/O pin.........................................................................................................25 mA
Max. output current sourced by I/O port ..............................................................................................................75 mA
Max. output current sunk by I/O port ...................................................................................................................75 mA
Note 1: Power dis sipation is calc ulated as follows : PDIS = VDD x {IDD – IOH} + {(VDD – V OH) x IOH} + (VOL x IOL)
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2012-2016 Microchip Technology Inc. DS40001652D-page 81
PIC16F527
FIGURE 15-1: PIC16F527 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
FIGURE 15-2: MAXIMUM OSCILLATOR FREQUENCY TABLE
6.0
2.5
4.0
3.0
0
3.5
4.5
5.0
5.5
410
Frequency (MHz)
VDD
20
(Volts)
25
2.0
8
0200 kHz 4 MHz 20 MHz
Frequency
HS
INTOSC
XT
LP
Oscillator Mode
EC
XTRC
8 MHz
PIC16F527
DS40001652D-page 82 2012-2016 Microchip Technology Inc.
15.1 DC Characteristics: PIC16F527 (Industrial)
DC Characteristics Standard Oper at ing Conditions (unless other wise specified)
Opera tin g Temperature -40C TA +85C (industrial)
Param.
No. Sym. Characteristic Min. Typ.(1) Max. Units Conditions
D001 VDD Supply Voltage 2.0 5.5 V See Figure 15-1
D002 VDR RA M Data Retention Voltage(2) — 1.5* — V Device in Sleep mode
D003 VPOR VDD Start Voltage to ensure
Power-on Reset —VSS —VSee Section 8.5 “Power-on
Re se t (POR)” for detai ls
D004 SVDD VDD Rise Rate to en sure
Power-on Reset 0.05* — — V/ms See Section 8.5 “Power-on
Re se t (POR)” for detai ls
D005 IDDP Supply Cur re nt D ur ing Pr og/ Er as e — 1.0* — mA VDD = 5.0V
D010 IDD Supply Current(3,4,6) —
—175
490 300
750 A
AFOSC = 4 MHz , VDD = 2.0V
FOSC = 4 MHz , VDD = 5.0V
—
—350
850 500
1300 A
AFOSC = 8 MHz , VDD = 2.0V
FOSC = 8 MHz , VDD = 5.0V
— 1800 2500 AFOSC = 20 MHz, VDD = 5. 0V
—
—13
30 22
55 A
AFOSC = 32 k H z, VDD = 2.0V
FOSC = 32 k H z, VDD = 5.0V
D020 IPD Power- down Cu rrent(5) —
—0.05
0.35 1.2
3.0 A
AVDD = 2.0V
VDD = 5.0V
D021 IBOR BOR Current(5) —
—3.5
4.0 7.0
9.0 A
AVDD = 3.0V
VDD = 5.0V
D022 IWDT WDT Current(5) —
—0.5
8.0 3.0
18.0 A
AVDD = 2.0V
VDD = 5.0V
D023 ICMP Comparator Current(5) —
—15
60 26
85 A
AVDD = 2.0V (pe r co m parator)
VDD = 5.0V (pe r co m parator)
D024 ICVREF CVREF Current(5) —
—30
75 70
125 A
AVDD = 2.0V (high range)
VDD = 5.0V (high range)
D025 IVFIR Interna l 0.6V Fixed Voltage
Reference Current(5) —
—
100
175
130
220
A
A
VDD = 2.0V (ref er ence and 1
comparator enabled)
VDD = 5.0V (ref er ence and 1
comparator enabled)
D026 IAD2A/D Current —
—0.5
0.8 2.0
3.2 A
A2.0V, No conversion in pr ogress
5.0V, No conversion in pr ogress
D027 IOPA Op Amp Current(5) —
—330
360 415
465 A
AVDD = 2.0V
VDD = 5.0V
* These parameters are characterized but not tested.
Note 1: D ata in t he Typi cal (“Typ”) colum n is based on characte rization re sults at 25°C. Thi s da ta is for design gui dance
only and is not test ed.
2: This is the limit to which VDD can be lowered in Sl eep mode w itho ut lo si ng RA M data.
3: The supply current is mainly a function of the operating voltage and frequency . Other factors such as bus loading,
oscilla to r type , b us rate, inte rn al cod e execution pattern and tem per at ur e al so have an impact on t he current
consumption.
4: The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD;
WDT en abled/disab led as specifie d.
5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If
a module current is lis te d, th e cur r ent is fo r that specific m odule enabl ed and the devi ce in Sleep.
6: Does no t incl ude curren t th r ough REXT. The current through the resistor can be estimated by the formula:
I = VDD/2REXT (mA) with REXT in k.
2012-2016 Microchip Technology Inc. DS40001652D-page 83
PIC16F527
15.2 DC Characteristics: PIC16F527 (Extended)
DC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +125C (extended)
Param.
No. Sym. Characteristic Min. Typ.(1) Max. Units Conditions
D001 VDD Supply Voltage 2.0 5.5 V See Figure 15-1
D002 VDR RAM Data Retention Voltage(2) — 1.5* — V Device in Sleep mode
D003 VPOR VDD Start Voltag e to ensure
Power-on Reset —VSS — V See Section 8.5 “Po w er-on Reset
(POR)” for details.
D004 SVDD VDD Rise Rate to ensure
Power-on Reset 0.05* — — V/ms See Section 8.5 “Po w er-on Reset
(POR)” for details.
D005 IDDP Supply Current During Prog/Erase — 1.0* — mA V DD = 5.0V
D010 IDD Supply Current(3,4,6) —
—175
490 300
750 A
AFOSC = 4 MHz, VDD = 2.0V
FOSC = 4 MHz, VDD = 5.0V
—
—350
850 500
1300 A
AFOSC = 8 MHz, VDD = 2.0V
FOSC = 8 MHz, VDD = 5.0V
— 1800 2500 AF
OSC = 20 MH z, VDD = 5.0V
—
—13
30 29
115 A
AFOSC = 32 kHz , VDD = 2.0V
FOSC = 32 kHz , VDD = 5.0V
D020 IPD Power-down Current(5) —
—0.1
0.35 9.0
15.0 A
AVDD = 2.0V
VDD = 5.0V
D021 IBOR BOR Current(5) —
—3.5
4.0 10
12 A
AVDD = 3.0V
VDD = 5.0V
D022 IWDT WDT Current(5) —
—1.0
8.0 18
22 A
AVDD = 2.0V
VDD = 5.0V
D023 ICMP Comparator Current(5) —
—15
60 30
92 A
AVDD = 2.0V (per comparator)
VDD = 5.0V (per comparator)
D024 ICVREF CVREF Current(5) —
—30
75 75
135 A
AVDD = 2.0V (high range)
VDD = 5.0V (high range)
D025 IVFIR I n ternal 0.6V Fixed Voltage
Reference Current(5) —
—
100
175
135
235
A
A
VDD = 2.0V (reference and 1
comparator enabled)
VDD = 5.0V (reference and 1
comparator enabled)
D026 IAD2A/D Current —
—0.5
0.8 10.0
16.0 A
A2.0V, No conversion in progress
5.0V, No conversion in progress
D027 IOPA Op Amp Current(5) —
—330
360 450
505 A
AVDD = 2.0V
VDD = 5.0V
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and
is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading,
oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current consumption.
4: The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CK I = VDD, MCL R = VDD; WDT
enabled/disabled as specified.
5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep mode. If a
module current is listed, the current is for t hat specific module enabled and the device in Sleep.
6: Does not include current through REXT. The current through the resistor can be estimated by the formula:
I = VDD/2REXT (mA) with REXT in k.
PIC16F527
DS40001652D-page 84 2012-2016 Microchip Technology Inc.
TABLE 15-1: DC CHARACTERISTICS: PIC16F527 (INDUSTRIAL, EXTENDED)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specif ied)
Operating temperature -4 0°C TA +85°C (industrial)
-40°C TA +125°C (extended)
Param.
No. Sym. Characteristic Min. Typ.† Max. Units Conditions
VIL Input Low Voltage
I/O ports
D030 with TTL buff er Vss — 0.8V V For all 4.5 VDD 5.5V
D030A Vss — 0.15VDD V Otherwise
D031 with Schmitt Trigger buffer Vss — 0.15VDD V
D032 MCLR, T0CKI Vss — 0.15VDD V
D033 OSC1 (EXTRC mode), (EC mode) Vss — 0.15VDD V(Note 1)
D033 OSC1 (HS mode) Vss — 0.3VDD V
D033 OSC1 (XT and LP modes) Vss — 0.3 V
VIH Input High Voltage
I/O ports —
D040 with TTL buff er 2.0 — VDD V4.5 VDD 5.5V
D040A 0.25VDD
+ 0.8VDD —VDD V Otherwise
D041 with Schmitt Trigger buffer 0.85VDD —VDD V For entire VDD range
D042 MCLR, T0CKI 0.85VDD —VDD V
D042A OS C1 (EXTRC mode), (EC mode) 0.85VDD —VDD V(Note 1)
D042A OSC1 (HS mode) 0.7VDD —VDD V
D043 OSC1 (XT and LP modes) 1.6 — VDD V
D070 IPUR PORTA and MCLR weak pull-up
current(4) 50 250 400 AVDD = 5V, VPIN = VSS
IIL Input Leakage Current(2,3)
D060 I/O ports — — ±1 AVss VPIN VDD, Pin at high-imped-
ance
D061 MCLR —±0.7±5AVss VPIN VDD
D063 OSC1 — — ±5 AVss VPIN VDD, XT, HS and LP osc
configuration
VOL Output Low Voltage
D080 I/O ports/CLKOUT — — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40C to
+85C
D080A — — 0.6 V IOL = 7.0 mA, VDD = 4.5V, -4 0 C to
+125C
D083 OSC2 — — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -4 0 C to
+85C
D083A — — 0.6 V IOL = 1.2 mA, VDD = 4.5V, -4 0 C to
+125C
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F527 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: This spec applies to all weak pull-up devices, including the weak pull-up found on MCLR.
2012-2016 Microchip Technology Inc. DS40001652D-page 85
PIC16F527
VOH Output High Voltage
D090 I/O ports/CLKOUT VDD –
0.7 ——VIOH = -3.0 mA, VDD = 4.5V, -40C to
+85C
D090A VDD –
0.7 ——VIOH = -2.5 mA, VDD = 4.5V, -40C to
+125C
D092 OSC2 VDD –
0.7 ——VIOH = -1.3 mA, VDD = 4.5V, -40C to
+85C
D092A VDD –
0.7 ——VIOH = -1.0 mA, VDD = 4.5V, -40C to
+125C
TABLE 15-1: DC CHARACTERISTICS: PIC16F527 (INDUSTRIAL, EXTENDED) (CONTINUED)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specif ied)
Operating temperature -4 0°C TA +85°C (industrial)
-40°C TA +125°C (extended)
Param.
No. Sym. Characteristic Min. Typ.† Max. Units Conditions
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F527 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: This spec applies to all weak pull-up devices, including the weak pull-up found on MCLR.
PIC16F527
DS40001652D-page 86 2012-2016 Microchip Technology Inc.
Capacitive Loading Specs on Output Pins
D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when
external clock is used to drive OSC1.
D101 CIO All I/O pins and OSC2 — — 50 pF
Flash Data Memory
D120 EDByte endurance 100K 1M — E/W -40C TA +85C
D120A EDByte endurance 10K 100K — E/W +85C TA +125C
D121 VDRW VDD for read/write VMIN —5.5V
TABLE 15-1: DC CHARACTERISTICS: PIC16F527 (INDUSTRIAL, EXTENDED) (CONTINUED)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specif ied)
Operating temperature -4 0°C TA +85°C (industrial)
-40°C TA +125°C (extended)
Param.
No. Sym. Characteristic Min. Typ.† Max. Units Conditions
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F527 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: This spec applies to all weak pull-up devices, including the weak pull-up found on MCLR.
2012-2016 Microchip Technology Inc. DS40001652D-page 87
PIC16F527
TABLE 15-2: COMPARATOR SPECIFICATIONS
Comparator Specifications Standard Operating Conditi ons (unle ss otherw is e stated)
Operating temperature -40°C to 125°C
Characteristics Sym. Min. Typ. Max. Units Comments
Input offset voltage VOS — ± 5.0 ±10.0 mV
Input common mode voltage* VCM 0—VDD – 1.5 V
CMRR* CMRR 55 — — db
Response Time(1)* TRT —150 — ns
Comparator Mode Change to
Output Valid* TMC2COV —— 10 s
* These parameters are characterized but not tested.
Note1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from
VSS to VDD – 1.5V.
TABLE 15-3: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS
Sym. Characteristics Min. Typ. Max. Units Comments
CVRES Resolution —
—VDD/24*
VDD/32 —
—LSb
LSb Low Range (VRR = 1)
High Range (VRR = 0)
Absolute Accuracy(2) —
——
—±1/2*
±1/2* LSb
LSb Low Range (VRR = 1)
High Range (VRR = 0)
Unit Resistor Value (R) —
—2K* —
Settling Time(1) ——10*s
* These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
2: Do not use reference externally when VDD < 2.7V. Under this condition, reference should only be used
with comparator Voltage Common mode observed.
TABLE 15-4: FIXED INPUT REFERENCE SPECIFICATION
Input Reference Specifications Standard Operating Conditions (unless otherw is e stated)
Operating temperature -40°C to 125°C
Characteristics Sym. Min. Typ. Max. Units Comments
Absolute Accuracy VFIR 0.5 0.60 0.7 V
PIC16F527
DS40001652D-page 88 2012-2016 Microchip Technology Inc.
TABLE 15-5: A/D CONVERTER CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature: 25°C
Param.
No. Sym. Characteristic Min. Typ.† Max. Units Conditions
A01 NRResolution — — 8 bit
A03 EINL Integral Error — — 1.5 LSb VDD = 5.0V
A04 EDNL Differential Error — — EDNL 1.7 LSb No missing codes
VDD = 5.0V
A05 EFS Full Scale Range 2. 0* — 5.5* V
A06 EOFF Offset Error — — 1.5 LSb VDD = 5.0V
A07 EGN Gain Error -0.7 — 2.2 LSb VDD = 5.0V
A10 — Monotonicity — guaranteed(1) ——VSS VAIN VDD
A25* VAIN Anal og Inp ut
Voltage VSS —VDD V
A30* ZAIN Recommended
Impedance of
Analog Voltage
Source
—— 10K
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
2012-2016 Microchip Technology Inc. DS40001652D-page 89
PIC16F527
15.3 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
FIGURE 15-3: LOAD CONDITIONS
FIGURE 15-4: EXTERNAL CLOCK TIMING
1. TppS2ppS
2. TppS
TF Frequency T Time
Lowercase subscripts (pp) and their meanings:
pp2to mcMCLR
ck CLKOUT osc Oscillator
cy Cycle time os OSC1
drt Device Reset Timer t0 T0CKI
io I/O port wdt Watchdog Timer
Uppercase letters and t heir meanings:
S
FFall PPeriod
HHigh RRise
I Invalid (high-impedance) V Valid
L Low Z High-impedance
CL
VSS
Pin
Legend:
CL = 50 pF for all pins except OSC2
15 pF for OSC2 in XT, HS or LP
modes when external clock
is used to drive OSC1
OSC1
Q4 Q1 Q2 Q3 Q4 Q1
133
44
2
PIC16F527
DS40001652D-page 90 2012-2016 Microchip Technology Inc.
TABLE 15-6: EXTERNAL CLOCK TIMING REQUIREMENTS
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial),
-40C TA +125C (extend ed )
Operating volt ag e VDD range is described in Section 15.1 “DC
Characteristics: PIC 16F527 (Ind ustrial)”.
Param.
No. Sym. Characteristic Min. Typ.(1) Max. Units Conditions
1A FOSC External CL KIN Freque nc y(2) DC — 4 MHz XT Oscillator
DC — 20 MHz HS/EC Oscillator
DC — 200 kHz LP Os ci ll ator
Oscillator Frequency(2) DC — 4 MHz EXTRC Oscillator
0.1 — 4 MHz XT Oscillator
4 — 20 MHz HS/EC Oscillator
DC — 200 kHz LP Os ci ll ator
1T
OSC External CLKIN Period(2) 250 — — ns XT Oscillator
50 — — ns HS/EC Oscillator
5——s LP Oscillator
Oscillator Period(2) 250 — — ns EXTRC Oscillator
250 — 10,000 ns XT Oscillator
50 — 250 ns HS/EC Oscillator
5——s LP Oscillator
2 TCY Instruction Cycle Time 200 4/FOSC DC ns
3 TosL,
TosH Clock in (OSC1) Low or High
Time 50* — — ns XT Oscillator
2* — — s LP Oscillator
10* — — ns HS/EC Oscillator
4TosR,
TosF Clock in (OSC1) Rise or Fall
Time — — 25* ns XT Oscillator
— — 50* ns LP Oscill ator
— — 15* ns HS/EC Oscillator
* These parameters are characterized but not tested.
Note1: Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
2012-2016 Microchip Technology Inc. DS40001652D-page 91
PIC16F527
TABLE 15-7: CALIBRATED INTERNAL RC FREQUENCIES
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial),
-40C TA +125C (extended)
Operating voltage VDD range is de scribed in Section 15.1 “DC
Characteristics: PIC16F527 (Industrial)”.
Param.
No. Sym. Characteristic Freq.
Tolerance Min. Typ.† Max. Units Conditions
F10 FOSC Internal Calibrated
INT OS C Freq uen cy (1) 1% 7.92 8.00 8.08 MHz 3.5V, 25C
2% 7.84 8.00 8.16 MHz 2.5V VDD 5.5V
0C TA +85C
5% 7.60 8.00 8.40 MHz 2.0V VDD 5.5V
-40C TA +85C (Ind.)
-40C TA +12 5C (Ext.)
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5V, 25C u nless otherwise stated. These para m eters are for design
guidance only and are not tested.
Note1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.
PIC16F527
DS40001652D-page 92 2012-2016 Microchip Technology Inc.
FIGURE 15-5: I/O TIMING
OSC1
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
17
20, 21
18
Old Value New Value
19
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 15-8: TIMING REQUIREMENTS
AC
Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial)
-40C TA +125C (extended)
Operating voltage VDD range is described in Section 15.1 “DC Characteristics: PIC16F527
(Industrial)”.
Param.
No. Sym. Characteristic Min. Typ.(1) Max. Units
17 TOSH2IOVOSC1 (Q1 cycle) to Port Out Valid(2,3) — — 100* ns
18 TOSH2IOIOSC1 (Q2 cycle) to Port Input Invalid (I/O in hold
time)(2) 50* — — ns
19 TIOV2OSH Port Input Valid to OSC1 (I/O in setup time) 20* — — ns
20 TIOR Port Output Rise Time(3) —1050**ns
21 TIOF Port Output Fall Time(3) —1050**ns
* These parameters are characterized but not tested.
** These parameters are design targets and are not tested.
Note1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: Measurements are taken in EXTRC mode.
3: See Figure 15-3 for loading conditions.
2012-2016 Microchip Technology Inc. DS40001652D-page 93
PIC16F527
FIGURE 15-6: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
FIGURE 15-7: BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
MCLR
Internal
POR
DRT
Time-out(2)
Internal
Reset
Watchdog
Timer
Reset
32
31
34
I/O pin(1)
32 32
34
30
Note 1: I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.
2: Runs in MCLR or WDT Reset only in XT, LP and HS modes.
VBOR
VDD
(Device in Brown-out Reset) (Device not in Brown-out Reset)
TBOR
Reset
(due to BOR)
VBOR + VHYST
TDRT
PIC16F527
DS40001652D-page 94 2012-2016 Microchip Technology Inc.
TABLE 15-9: BOR, POR, WATCHDOG TIMER AND DEVICE RESET TIMER
AC Characteristics
St andard Operating Conditions (unless otherwise specified)
Opera tin g Temperature -4 0 C TA +85C (industrial)
-40C TA +125C (exten ded)
Opera tin g vol tag e VDD range is described in Section 15.1 “DC
Characteristics: PIC16F527 (Industrial)”.
Param.
No. Sym. Characteristic Min. Typ.(1) Max. Units Conditions
30 TMCLMCLR Pulse Width (low ) 2000* — — ns V DD = 5.0V
31 TWDT Watchdog Timer Time-out Per i od
(no prescal er) 9*
9* 18*
18 30*
40* ms
ms VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
32 TDRT Devi ce Reset Timer Pe ri od 9*
9* 18*
18 30*
40* ms
ms VDD = 5.0V (Industrial)
VDD = 5.0V (Extended)
34 TIOZ I/O High-impedance from MCLR
low — — 2000* ns
35 VBOR Brow n- out R eset Voltage 1 .9 5 — 2.25 V ( N ote 2)
36* VHYST Brow n- out Reset Hyster esis — 50 — mV
37* TBOR Brown-out R es et Minim um
Detect ion Period 100 — — sVDD VBOR
* These parameters are characterized but not tested.
Note 1: D ata in t he Typi ca l (“Typ”) column is a t 5V, 25°C unl ess otherwi se stated. These parameters are for design
guidance only and are not tested.
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as clo se t o the device as
possible. 0.1 F and 0.01 F values in parallel are rec om m ended.
TABLE 15-10: DRT (DEVICE RESET TIMER PERIOD)
Oscillator Configuration POR Reset Subsequent Resets
IntRC, ExtRC, and EC 10 s (typical) + 18 ms (DRTEN = 1)10s (typical) + 18 ms (DRTEN = 1)
XT, HS and LP 18 ms (typical) 18 ms (typical)
TABLE 15-11: PULL-UP RESISTOR RANGES
VDD (Volts) Temperature (C) Min. Typ. Max. Units
RB0-RB7
2.0 -40 73K 105K 186K
25 73K 113K 187K
85 82K 123K 190K
125 86K 132k 190K
5.5 -40 15K 21K 33K
25 15K 22K 34K
85 19K 26k 35K
125 23K 29K 35K
MCLR
2.0 -40 63K 81K 96K
25 77K 93K 116K
85 82K 96k 116K
125 86K 100K 119K
5.5 -40 16K 20k 22K
25 16K 21K 23K
85 24K 25k 28K
125 26K 27K 29K
2012-2016 Microchip Technology Inc. DS40001652D-page 95
PIC16F527
FIGURE 15-8: TIMER0 CLOCK TIMINGS
T0CKI
40 41
42
TABLE 15-12: TIMER0 CLOCK REQUIREMENTS
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial)
-40C TA +125C (extended)
Oper at ing voltage VDD range is described in Sectio n 15.1 “DC Charact er is tics:
PIC16F5 27 ( In dus tr ial)” .
Param.
No. Sym. Characteristic Min. Typ.(1) Max. Units Conditions
40 Tt0H T0CKI High Pulse
Width No Prescaler 0.5 TCY + 20* — — ns
With Prescaler 10* — — ns
41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20* — — ns
With Prescaler 10* — — ns
42 Tt0P T 0CK I Period 20 or TCY + 40* N — — ns Whichever is greater.
N = P r e s cale Valu e
(1, 2, 4,..., 256)
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
PIC16F527
DS40001652D-page 96 2012-2016 Microchip Technology Inc.
15.4 Operational Amplifiers
TABLE 15-13: OPERATIONAL AMPLIFIER (OPA) MODULE DC SPECIFICATIONS
OPA DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
VDD = 5.0V
Operating temperature: 25°C
Param.
No. Sym. Characteristics Min. Typ. Max. Units Comments
OPA01 VOS Input Offset Voltage —513 mV
OPA02*
OPA03* IB
IOS
Input current and impedance
Input bi as current
Input offset bias current —
—2*
1* —
—nA
pA
OPA04*
OPA05* VCM
CMR
Common Mode
Common mode input range
Common mode rejection VSS
55 —
65 VDD – 1.4
—V
dB
OPA06A* AOL Open Loop Gain
DC Open loop g ai n — 70 — dB Stan dar d load
OPA07*
OPA08*
VOUT
ISC
Output
Out put voltage swing
Output short circuit current
VSS + 50
—
—
25
VDD – 50
28
mV
mA
To VDD/2 (10 k
connected to VDD,
10 k + 20 pF to Vss)
OPA10* PSR Power Supply
Power supply rejection — 70 — dB
* These parameters are characterized but not tested.
TABLE 15-14: AC CHARACTERISTICS: OPERATIONAL AMPLIFIER (OPA)
AC CHARACTERISTICS Standard Operating Conditions (unless otherwis e stated)
Operating Temperature: 25°C
VDD = 5.0V
Param.
No. Parameters Symbol Min. Typ. Max. Units Conditions
OPA12* Gain Bandwidth Product GBWP — 3 — MHz VDD = 5V
OPA1 3* Turn on Time TON ——10 µsVDD = 5V
OPA14* Phase Margin M— 55 — degrees VDD = 5V
OPA15* Slew Rate SR 2 — — V/µs VDD = 5V
* These parameters are characterized but not tested.
Note1: Data in “T yp ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2012-2016 Microchip Technology Inc. DS40001652D-page 97
PIC16F527
TABLE 15-16: THERMAL CONSIDERATIONS
TABLE 15-15: FLASH DATA MEMORY WRITE/ERASE TIME
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85 C (industria l)
-40C TA +125C (extended)
Operating Voltage VDD range is described in
Section 15.1 “DC Characteristics: PIC16F527 (Industrial)”.
Param.
No. Sym. Characteristic Min. Typ.(1) Max. Units Conditions
43 TDW Flash Data Memory
Write Cycle Time 23.55ms
44 TDE Flash Data Memory
Erase Cycle Time 23.55ms
Note 1: Dat a in the Typi cal ( “Typ”) col umn is at 5V, 25°C unless otherw ise st ated. These pa ramete rs are for de sign
guidance only and are not tested.
Standard Operating Conditions (unless otherwise stated)
VDD = 5.0V
Operating temperature: 25°C
Param.
No. Sym. Characteristic Typ. Units Conditions
TH01 JA Thermal Resistance Junction to Ambient 62.2 C/W 20-pin PDIP package
77.7 C/W 20-pin SOIC package
87.3 C/W 20-pin SSOP package
43 C/W 20-pin QFN 4x4mm package
32.8 C/W 20-pin UQFN 4x4mm package
41 C/W 20-pin UQFN 3x3mm package
TH02 JC Thermal Resistance Junction to Case 27.5 C/W 20-pin PDIP package
23.1 C/W 20-pin SOIC package
31.1 C/W 20-pin SSOP package
5.3 C/W 20-pin QFN 4x4mm package
27.4 C/W 20-pin UQFN 4x4mm package
49 C/W 20-pin UQFN 3x3mm package
TH03 TJMAX Maximum Junction Temperature 15 0 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/OI/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature. TJ = Junction Temperature.
PIC16F527
DS40001652D-page 98 2012-2016 Microchip Technology Inc.
16.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
“Typical” represent s the mean of the distribution at 25C. “MAXIMU M”, “Max.”, “MINIMUM” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each
temperature range.
Note: The gra phs and tabl es pr ovide d followi ng this note are a statistical su mmary based o n a limit ed numb er of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
2012-2016 Microchip Technology Inc. DS40001652D-page 99
PIC16F527
FIGURE 16-1: I DD, LP OSCILLATOR, FOSC = 32 kHz
Typical
Max.
0
5
10
15
20
25
30
35
40
45
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Typical: Mean (25°C)
Max: Mean + 3ı (85°C)
PIC16F527
DS40001652D-page 100 2012-2016 Microchip Tec hnology Inc.
FIGURE 16-2: I DD TYPICAL, XT AND EXTRC OSCILLATOR
FIGURE 16-3: I DD MAXIMUM, XT AND EXTRC OSCILLATOR
4 MHz EXTRC
4 MHz XT
1 MHz XT
0
100
200
300
400
500
600
700
800
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Typical: Mean (25°C)
4 MHz EXTRC
4 MHz XT
1 MHz XT
0
100
200
300
400
500
600
700
800
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: Mean + 3ı (-40°C to 125°C)
2012-2016 Microchip Technology Inc. DS40001652D-page 101
PIC16F527
FIGURE 16-4: I DD TYPICAL, EXTERNAL CLOCK MODE
FIGURE 16-5: I DD MAXIMUM, EXTERNAL CLOCK MODE
4 MHz
1 MHz
0
100
200
300
400
500
600
700
800
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Typical: Mean (25°C)
4 MHz
1 MHz
0
100
200
300
400
500
600
700
800
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: Mean + 3ı (-40°C to 125°C)
PIC16F527
DS40001652D-page 102 2012-2016 Microchip Tec hnology Inc.
FIGURE 16-6: I DD TYPICAL, INTOSC
FIGURE 16-7: I DD MAXIMUM, INTOSC
8 MHz
4 MHz
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (mA)
VDD (V)
Typical: Mean (25°C)
8 MHz
4 MHz
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (mA)
VDD (V)
Max: Mean + 3ı (-40°C to 125°C)
2012-2016 Microchip Technology Inc. DS40001652D-page 103
PIC16F527
FIGURE 16-8: I DD TYPICAL, HS OSCILLATOR
FIGURE 16-9: I DD MAXIMUM, HS OSCILLATOR
20 MHz
8 MHz
4 MHz
0.0
0.5
1.0
1.5
2.0
2.5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (mA)
VDD (V)
Typical: Mean (25°C)
20 MHz
8 MHz
4 MHz
0.0
0.5
1.0
1.5
2.0
2.5
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (mA)
VDD (V)
Max: Mean + 3ı (-40°C to 125°C)
PIC16F527
DS40001652D-page 104 2012-2016 Microchip Tec hnology Inc.
FIGURE 16-10 : IPD BASE, LOW-POWER SLEEP MODE
FIGURE 16-11: IPD, WATCHDOG TIMER (WDT)
400
Max.
200
250
300
350
400
P
D(nA)
Typical: Mean (25°C)
Max: Mean + 3ı(85°C)
Typical
0
50
100
150
200
250
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IPD (nA)
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
M
18.0
Typical
Max.
8.0
10.0
12.0
14.0
16.0
18.0
IPD (µA)
Typical: Mean (25°C)
Max: Mean + 3ı (-40°C to 85°C)
0.0
2.0
4.0
6.0
8.0
10
.
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IPD (µ
A
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
2012-2016 Microchip Technology Inc. DS40001652D-page 105
PIC16F527
FIGURE 16-12 : IPD, FIXED VOLTAGE REFERENCE (FVR)
FIGURE 16-13 : IPD, BROWN-OUT RESET (BOR)
Max.
210
Typical: Mean (25
°
C)
Typical
Max.
110
130
150
170
190
210
IPD (µA)
Typical: Mean (25°C)
Max: Mean + 3ı (-40°C to 85°C)
50
70
90
110
130
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IPD (
µ
50
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
6
TilM (25
°
C)
Typical
Max.
3
4
5
6
IPD (µA)
Typical: Mean (25°C)
Max: Mean + 3ı (-40°C to 85°C)
0
1
2
3
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IPD (µA
)
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
PIC16F527
DS40001652D-page 106 2012-2016 Microchip Tec hnology Inc.
FIGURE 16-14 : IPD, SINGLE COMPARATOR
FIGURE 16-15 : IPD, CVREF
M
80
Typical: Mean (25
°
C)
Typical
Max.
30
40
50
60
70
80
IPD (µA)
Typical: Mean (25°C)
Max: Mean + 3ı (-40°C to 85°C)
0
10
20
30
40
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IPD (
µ
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
Max.
90
100
Typical
Max.
40
50
60
70
80
90
100
IPD (µA)
Typical: Mean (25°C)
Max: Mean + 3ı (-40°C to 85°C)
0
10
20
30
40
50
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
IPD (µ
A
0
10
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
2012-2016 Microchip Technology Inc. DS40001652D-page 107
PIC16F527
FIGURE 16-16 : IPD, SINGLE OPERATIONAL AMPLIFIER (OPA) – UNITY GAIN MODE
500
Typical: Mean (25
°
C)
Max.
350
400
450
500
IPD (µA)
Typical: Mean (25°C)
Max: Mean + 3ı (-40°C to 85°C)
Typical
200
250
300
350
1.
5
2.
0
2.
5
3
.
0
3
.
5
4.
0
4.
5
5
.
0
5
.
5
6
.
0
IPD (µ
A
200
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
PIC16F527
DS40001652D-page 108 2012-2016 Microchip Tec hnology Inc.
FIGURE 16-17 : VOH vs. IOH OVER TEMPERATURE, VDD = 5.0V
FIGURE 16-18 : VOL vs. IOL OVER TEMPERATURE, VDD = 5.0 V
Max.
Typical
Min.
3
3.5
4
4.5
5
5.5
-5.5 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0
VOH (V)
IOH (mA)
Max: Mean + 3ı(-40°C)
Typical: Mean (25°C)
Min: Mean - 3ı(125°C)
Min.
Typical
Max.
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
4.5 5.5 6.5 7.5 8.5 9.5 10.5
VOL (V)
IOL (mA)
Max: Mean + 3ı(125°C)
Typical: Mean (25°C)
Min: Mean - 3ı(-40°C)
2012-2016 Microchip Technology Inc. DS40001652D-page 109
PIC16F527
FIGURE 16-19 : VOH vs. IOH OVER TEMPERATURE, VDD = 3.0 V
FIGURE 16-20 : VOL vs. IOL OVER TEMPERATURE, VDD = 3.0V
Max.
Typical
Min.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0
VOH (V)
IOH (mA)
Max: Mean + 3ı(-40°C)
Typical: Mean (25°C)
Min: Mean - 3ı(125°C)
Min.
Typical
Max.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
4.5 5.5 6.5 7.5 8.5 9.5 10.5
VOL (V)
IOL (mA)
Max: Mean + 3ı(125°C)
Typical: Mean (25°C)
Min: Mean - 3ı(-40°C)
PIC16F527
DS40001652D-page 110 2012-2016 Microchip Tec hnology Inc.
FIGURE 16-21: TTL INPUT THRESHOLD VIN vs. VDD
FIGURE 16-22: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD
Max.
Typical
Min.
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
VIN (V)
VDD (V)
Max: Mean + 3ı (-40°C)
Typical: Mean (25°C)
Min: Mean - 3ı(125°C)
VIL Max. (-40°C)
VIL Min. (125°C)
VIH Min. (-40°C)
VIH Max. (125°C)
0.5
1
1.5
2
2.5
3
3.5
4
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
V
IN
(V)
V
DD
(V)
Max: Mean + 3ı
(at Temp.)
Min: Mean - 3ı
(at Temp.)
2012-2016 Microchip Technology Inc. DS40001652D-page 111
PIC16F527
FIGURE 16-23: BROWN-OUT RESET VOLTAGE
FIGURE 16-24: WDT TIME-OUT PERIOD
Max.
Min.
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
-60 -40 -20 0 20 40 60 80 100 120 140
Voltage (V)
Temperature (°C)
Max: Mean Typical + 3ı
Min: Mean Typical - 3ı
Min.
Typical
Max. (85°C)
Max. (125°C)
0
5
10
15
20
25
30
35
40
45
50
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Time (ms)
V
DD
(V)
Max: Mean + 3ı (at Temp.)
Typical: Mean (25°C)
Min: Mean - 3ı (-40
°
C)
PIC16F527
DS40001652D-page 112 2012-2016 Microchip Tec hnology Inc.
17.0 PACKAGING INFORMATION
17.1 Package Marking Information
*Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
Legend: XX...X Customer-specifi c info rma tio n
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the even t the full Microc hip p art number c annot be marked on one lin e, it wi ll
be carried over to the next line, thus limiting the number of available
characters for customer-specific infor mation.
3
e
3
e
20-Lead PDIP (300 mil) Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F527
1307123
-E/P
3
e
20-Lead SOIC (7.50 mm) Example
-E/SO
3
e
1307123
PIC16F527
2012-2016 Microchip Technology Inc. DS40001652D-page 113
PIC16F527
Package Marking Information (Continued)
20-Lead QFN (4x4x0.9 mm) Example
PIN 1 PIN 1
PIC16
E/ML
307123
20-Lead SSOP (5.30 mm) Example
PIC16F527
1307123
-E/SS
3
e
F527
3
e
*Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the ful l Micro chip p art num ber can not be ma rked on o ne line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
20-Lead UQFN (4x4x0.5mm)
PIC16F527
DS40001652D-page 114 2012-2016 Microchip Tec hnology Inc.
Package Marking Information (Continued)
TABLE 17-1: 20-LEAD 3x3x0.5 UQFN (JP)
TOP MARKING
YYWW
20-Lead UQFN (3x3x0.5 mm)
NNN
Example
XXX 1307
123
DAF
Part Number Marking
PIC16F527T-E/JP DAF
PIC16F527T-I/JP DAE
2012-2016 Microchip Technology Inc. DS40001652D-page 115
PIC16F527
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PIC16F527
DS40001652D-page 116 2012-2016 Microchip Tec hnology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2016 Microchip Technology Inc. DS40001652D-page 117
PIC16F527
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC16F527
DS40001652D-page 118 2012-2016 Microchip Tec hnology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2016 Microchip Technology Inc. DS40001652D-page 119
PIC16F527
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DS40001652D-page 120 2012-2016 Microchip Tec hnology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2016 Microchip Technology Inc. DS40001652D-page 121
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EXPOSED
PAD
E
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1
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2012-2016 Microchip Technology Inc. DS40001652D-page 123
PIC16F527
B
A
0.20 C
0.20 C
0.10 C A B
(DATUM B)
(DATUM A)
C
SEATING
PLANE
1
2
N
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
NOTE 1
1
2
N
0.10 C A B
0.10 C A B
0.10 C
0.08 C
A1
Microchip Technology Drawing C04-255A Sheet 1 of 2
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]
D
E
A
(A3)
20X b
e
2X
D2
E2
NOTE 1
L
K
20X
PIC16F527
DS40001652D-page 124 2012-2016 Microchip Tec hnology Inc.
Microchip Technology Drawing C04-255A Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Number of Terminals
Overall Height
Terminal Width
Overall Width
Overall Length
Terminal Length
Exposed Pad Width
Exposed Pad Length
Terminal Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
D
E2
D2
A3
e
L
E
N
0.50 BSC
0.127 REF
2.60
2.60
0.30
0.20
0.45
0.00
0.25
4.00 BSC
0.40
2.70
2.70
0.50
0.02
4.00 BSC
MILLIMETERS
MIN NOM
20
2.80
2.80
0.50
0.30
0.55
0.05
MAX
K-0.20 -
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
Terminal-to-Exposed-Pad
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]
2012-2016 Microchip Technology Inc. DS40001652D-page 125
PIC16F527
RECOMMENDED LAND PATTERN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
C2
Optional Center Pad Width
Contact Pad Spacing
Optional Center Pad Length
Contact Pitch
Y2
X2
2.80
2.80
MILLIMETERS
0.50 BSC
MIN
E
MAX
4.00
Contact Pad Length (X20)
Contact Pad Width (X20)
Y1
X1
0.80
0.30
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing C04-2255A
NOM
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN]
SILK SCREEN
1
2
20
C1
C2
E
X1
Y1
G1
Y2
X2
C1Contact Pad Spacing 4.00
Contact Pad to Center Pad (X20) G1 0.20
PIC16F527
DS40001652D-page 126 2012-2016 Microchip Tec hnology Inc.
B
A
0.10 C
0.10 C
0.07 C A B
(DATUM B)
(DATUM A)
C
SEATING
PLANE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
NOTE 1
1
2
N
0.10 C A B
0.10 C A B
0.05 C
0.08 C
Microchip Technology Drawing C04-256A Sheet 1 of 2
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JP) - 3x3x0.50 mm Body [UQFN]
2X
20X
D
E
A
(A3)
A1
D2
E2
e
20X b
L
K
NOTE 1
1
2
N
2012-2016 Microchip Technology Inc. DS40001652D-page 127
PIC16F527
Microchip Technology Drawing C04-256A Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Number of Terminals
Overall Height
Terminal Width
Overall Width
Overall Length
Terminal Length
Exposed Pad Width
Exposed Pad Length
Terminal Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
D
E2
D2
A3
e
L
E
N
0.40
0.127 REF
1.65
1.65
0.30
0.15
0.45
0.00
0.20
3.00 BSC
0.40
1.75
1.75
0.50
0.02
3.00 BSC
MILLIMETERS
MIN NOM
20
1.85
1.85
0.50
0.25
0.55
0.05
MAX
K-0.20 -
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
Terminal-to-Exposed-Pad
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JP) - 3x3x0.50 mm Body [UQFN]
PIC16F527
DS40001652D-page 128 2012-2016 Microchip Tec hnology Inc.
RECOMMENDED LAND PATTERN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
C2
Optional Center Pad Width
Contact Pad Spacing
Optional Center Pad Length
Contact Pitch
Y2
X2
1.85
1.85
MILLIMETERS
0.40 BSC
MIN
E
MAX
3.00
Contact Pad Length (X20)
Contact Pad Width (X20)
Y1
X1
0.75
0.20
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing C04-2256A
NOM
20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JP) - 3x3x0.5 mm Body [UQFN]
SILK SCREEN
1
2
20
C1Contact Pad Spacing 3.00
Contact Pad to Center Pad (X20) G1 0.20
E
C1
C2 Y2
X2
2X 0.35
X1
Y1
G1
2012-2016 Microchip Technology Inc. DS40001652D-page 129
PIC16F527
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A (09/2012)
Initial release of this document.
Revision B (12/2013)
Updated Table 1 and Table 1-1; Updated Figure 3-1;
Update d Register 4-1 ; Updated sec tion 5, Self-W ritabl e
Flash Data Memory Control; Updated Note 1 in Regis-
ter 6-4; Updated section 8, Special Features of the
CPU; Updated section 9, Analog-to-Digital (A/D) Con-
verter; Updated section 10, Comparators; Updated
section 12.1, OPACON Register; Updated section 15,
Electric al Characteristi cs ; Up dat ed se ct ion 16, DC and
AC Characteristics Graphs and Charts; Other minor
corrections.
Revision C (5/2014)
Updated with new 20-lead UQFN 3x3x0.5mm package.
Updated Product Identification System page and
added new specifications for new packages.
Added Table 15-16: Thermal Considerations.
Revision D (01/2016)
Added ‘eXtreme Low-Power (XLP) Features’ section
and updated ‘PIC16F527 and PIC16F570 Family
Types’ table; Other minor corrections.
PIC16F527
DS40001652D-page 130 2012-2016 Microchip Tec hnology Inc.
THE MICROCHIP WEBSITE
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser , the website contains the followin g information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online dis cu ss io n gr oups, Microchip consu lt ant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of sem inars and events, lis tings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of inte rest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sal es Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the website
at: http://microchip.com/support
2012-2016 Microchip Technology Inc. DS40001652D-page 131
PIC16F527
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device: PIC16F527
Tape and Reel
Option: Blank = S tandard packaging (tube or tray)
T = Tape and Reel(1)
Temperature
Range: I= -40C to +85C (Industrial)
E= -40C to +125C (Extended)
Package: GZ = Micro Lead Frame (4x4x0.5) (UQFN)
JP = Micro Lead Frame (3x3x0.5) (UQFN)
ML = Micro Lead Frame (4x4x0.9) (QFN)
P = Plastic DIP (PDIP)
SO = Small Outline (7.50 mm) (SOIC)
SS = Shrink Small Outline (5.30 mm) (SSOP)
Pattern: QTP, SQTP, Code or Special Requirements
(blank oth erwis e )
Examples:
a) PIC16F527-E/P 301 = Extend ed Temp ., PDIP
package, QTP pattern #301
b) PIC16F527-I/SO = Industrial Temp., SOIC
package
c) PIC16F527T-E/SS = Extended Temp., SSOP
package, Tape and Reel
d) PIC16F527T-I/ML = Industrial Temp., QFN
Package, Tape and Reel
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel opt ion.
[X](1)
Tape and Reel
Option
-
DS40001652D-page 132 2012-2016 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be s upe rs eded by u pdates. It is y ou r responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MO ST, MOST logo, MPLAB,
OptoL yzer , PIC, PICSTAR T, PIC32 logo, RightTouch, S pyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDE M, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, I nter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, motorBench, MPA SM , MPF, MPLAB
Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHAR C, USB Check, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
Silicon St orage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012-2016, Microchip Tec hnology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0191-9
Note the following details of the code protectio n feature on Microchi p devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• T here are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakab le.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the c ode pr otection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hop ping
devices, Serial EEPROMs, microperipher als, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2012-2016 Microchip Technology Inc. DS40001652D-page 133
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
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Web Address:
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Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
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Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-67 33
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7 000
Fax: 86-10-8528-2104
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Tel: 86-28-8665-5511
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Tel: 86-23-8980-9 588
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Fax: 86-25-8473-2470
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Tel: 86-532-8502-7355
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China - Shanghai
Tel: 86-21-5407-5 533
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China - Shenyang
Tel: 86-24-2334-2 829
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Tel: 86-755-8864-2200
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Tel: 86-27-5980-5 300
Fax: 86-27-5980-5118
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Tel: 86-29-8833-7 252
Fax: 86-29-8833-7256
ASIA/PACIFIC
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
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Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
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Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohs iung
Tel: 886-7-213-7828
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Karlsruhe
Tel: 49-721-625370
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Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Italy - Milan
Tel: 39-0331-742611
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Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
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Tel: 46-8-5090-4654
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Tel: 44-118-921-5800
Fax: 44-118-921- 5820
Worldwide Sales and Service
07/14/15
