VNQ810P-E Quad channel high-side driver Features Type RDS(on) IOUT VCC VNQ810P-E 160m(1) 3.5A(1) 36V 1. Per each channel. ECOPACK(R): lead free and RoHS compliant Automotive Grade: compliance with AEC guidelines Very low standby current CMOS compatible input On-state open-load detection Off-state open-load detection Thermal shutdown protection and diagnosis Undervoltage shutdown Overvoltage clamp Output stuck to VCC detection Load current limitation Reverse battery protection Electrostatic discharge protection Table 1. SO-28 (double island) Description The VNQ810P-E is a quad HSD formed by assembling two VND810P-E chips in the same SO-28 package. The VNQ810P-E is a monolithic device made by using STMicroelectronics VIPowerTM M0-3 technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects open-load condition both in on and off-state. Output shorted to VCC is detected in the off-state. Device automatically turns off in case of ground pin disconnection. Device summary Package SO-28 (double island) September 2013 Order codes Tube Tape and reel VNQ810P-E VNQ810PTR-E Doc ID 17387 Rev 2 1/28 www.st.com 1 Contents VNQ810P-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 4 6 2/28 3.1.1 Solution 1: a resistor in the ground line (RGND only) . . . . . . . . . . . . . . 17 3.1.2 Solution 2: a diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 18 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . . 20 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 5 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 17 SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 SO-28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 17387 Rev 2 VNQ810P-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 7. Table 8. Table 9. Table 6. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC - output diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Status pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC = 13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical transient requirements on VCC pin (part 1/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical transient requirements on VCC pin (part 2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical transient requirements on VCC pin (part 3/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 17387 Rev 2 3/28 List of figures VNQ810P-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. 4/28 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching time Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Open-load on-state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Open-load off-state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SO-28 (double island) maximum turn-off current versus load inductance . . . . . . . . . . . . . 20 SO-28 double island PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 22 SO-28 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 22 Thermal fitting model of a quad channel HSD in SO-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SO-28 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO-28 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO-28 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 17387 Rev 2 VNQ810P-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram VCC1,2 Vcc OVERVOLTAGE CLAMP UNDERVOLTAGE GND1,2 CLAMP 1 OUTPUT1 INPUT1 DRIVER 1 CLAMP 2 STATUS1 CURRENT LIMITER 1 LOGIC DRIVER 2 OUTPUT2 OVERTEMP. 1 OPENLOAD ON 1 CURRENT LIMITER 2 INPUT2 OPENLOAD OFF 1 OPENLOAD ON 2 STATUS2 OPENLOAD OFF 2 OVERTEMP. 2 VCC3,4 Vcc CLAMP OVERVOLTAGE UNDERVOLTAGE GND3,4 CLAMP 3 INPUT3 OUTPUT3 DRIVER 3 CLAMP 4 STATUS3 OVERTEMP. 3 LOGIC CURRENT LIMITER 3 DRIVER 4 OUTPUT4 OPENLOAD ON 3 CURRENT LIMITER 4 INPUT4 OPENLOAD OFF 3 OPENLOAD ON 4 STATUS4 OPENLOAD OFF 4 OVERTEMP. 4 Doc ID 17387 Rev 2 5/28 Block diagram and pin description Figure 2. VNQ810P-E Configuration diagram (top view) VCC1,2 1 OUTPUT1 INPUT1 OUTPUT1 STATUS1 OUTPUT1 STATUS2 OUTPUT2 INPUT2 OUTPUT2 VCC1,2 OUTPUT2 VCC3,4 OUTPUT3 GND 3,4 OUTPUT3 INPUT3 OUTPUT3 STATUS3 OUTPUT4 STATUS4 OUTPUT4 INPUT4 OUTPUT4 14 15 VCC3,4 Suggested connections for unused and not connected pins Connection / pin Status N.C. Output Input Floating X X X X To ground 6/28 VCC1,2 GND 1,2 VCC3,4 Table 2. 28 X Doc ID 17387 Rev 2 Through 10 K resistor VNQ810P-E Electrical specifications 2 Electrical specifications 2.1 Absolute maximum ratings Stressing the device above the rating listed in the Table 5 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE program and other relevant quality document. Table 3. Absolute maximum ratings Symbol Value Unit 41 V VCC DC supply voltage -VCC Reverse DC supply voltage -0.3 V -IGND DC reverse ground pin current -200 m IOUT DC output current Internally limited A -IOUT Reverse DC output current -6 A DC input current +/-10 mA ISTAT DC Status current +/-10 mA VESD Electrostatic discharge (human body model: R = 1.5 K; C = 100 pF) - INPUT - STATUS - OUTPUT - VCC 4000 4000 5000 5000 V V V V EMAX Maximum switching energy (L = 2.5 mH; RL = 0 ; Vbat = 13.5 V; Tjstart = 150 C; IL = 9 A) 23 mJ 6.25 W Internally limited C - 55 to 150 C IIN Ptot Tj Tstg 2.2 Parameter Power dissipation (per island) at Tlead = 25C Junction operating temperature Storage temperature Thermal data Table 4. Symbol Rthj-lead Rthj-amb Rthj-amb Thermal data (per island) Parameter Value Unit 20 C/W Thermal resistance junction-lead Thermal resistance junction-ambient (one chip ON) 60(1) 44(2) C/W Thermal resistance junction-ambient (two chips ON) 46(1) 31(2) C/W 1. When mounted on a standard single-sided FR-4 board with 0.5 cm2 of Cu (at least 35 m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. 2. When mounted on a standard single-sided FR-4 board with 6 cm2 of Cu (at least 35 m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. Doc ID 17387 Rev 2 7/28 Electrical specifications 2.3 VNQ810P-E Electrical characteristics Values specified in this section are for 8 V < VCC < 36 V; -40 C < Tj < 150 C, unless otherwise stated. Figure 3. Current and voltage conventions IS3,4 IS1,2 VCC3,4 VCC3,4 VCC1,2 VF1 (1) VCC1,2 IIN1 ISTAT1 VIN1 IIN2 VSTAT1 ISTAT2 VIN2 IIN3 VSTAT2 ISTAT3 VIN3 VSTAT3 IIN4 VIN4 ISTAT4 VSTAT4 INPUT1 IOUT1 STATUS1 OUTPUT1 VOUT1 IOUT2 INPUT2 OUTPUT2 STATUS2 VOUT2 IOUT3 INPUT3 OUTPUT3 STATUS3 IOUT4 INPUT4 OUTPUT4 STATUS4 GND3,4 VOUT3 VOUT4 GND1,2 IGND3,4 IGND1,2 1. VFn = VCCn - VOUTn during reverse battery condition. Table 5. Power output Symbol Parameter VCC(1) Operating supply voltage 5.5 13 36 V Undervoltage shutdown 3 4 5.5 V Overvoltage shutdown 36 VUSD (1) VOV(1) RON IS Test conditions V IOUT = 1 A; Tj = 25 C IOUT = 1 A; VCC > 8 V On-state resistance Supply current 160 320 m m Off-state; VCC = 13 V; VIN = VOUT = 0 V 12 40 A Off-state; VCC = 13 V; VIN = VOUT = 0 V; Tj = 25 C 12 25 A On-state; VCC = 13 V; VIN = 5 V; IOUT = 0 A 5 7 mA 0 50 A -75 0 A IL(off1) Off-state output current VIN = VOUT = 0 V IL(off2) Off-state output current VIN = 0V; VOUT = 3.5 V IL(off3) Off-state output current VIN = VOUT = 0V; VCC = 13 V; Tj = 125 C 5 A IL(off4) Off-state output current VIN = VOUT = 0V; VCC = 13 V; Tj = 25 C 3 A 1. Per island. 8/28 Min. Typ. Max. Unit Doc ID 17387 Rev 2 VNQ810P-E Electrical specifications Protections(1) Table 6. Symbol Min. Typ. Max. Unit Shutdown temperature 150 175 200 C TR Reset temperature 135 Thyst Thermal hysteresis 7 tSDL Status delay in overload conditions Ilim Current limitation TTSD Vdemag Parameter Test conditions C 15 C Tj > TTSD VCC = 13 V 3.5 5 5.5 V < VCC < 36 V Turn-off output clamp voltage IOUT = 1A; L = 6mH VCC-41 20 s 7.5 A 7.5 A VCC-48 VCC-55 V 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Table 7. Symbol VF Table 8. Symbol VCC - output diode Parameter Test conditions Forward on voltage Min. Typ. Max. Unit - - 0.6 V Min. Typ. Max. Unit -IOUT = 0.5 A; Tj = 150 C Status pin Parameter Test conditions VSTAT Status low output voltage ISTAT = 1.6mA 0.5 V ILSTAT Status leakage current Normal operation; VSTAT = 5 V 10 A CSTAT Status pin Input capacitance Normal operation; VSTAT = 5 V 100 pF 8 V VSCL Status clamp voltage Table 9. Symbol ISTAT = 1 mA 6 ISTAT = - 1 mA 6.8 -0.7 V Switching (VCC = 13V) Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time RL = 13 from VIN rising edge to VOUT = 1.3 V - 30 - s td(off) Turn-off delay time RL = 13 from VIN falling edge to VOUT = 11.7 V - 30 - s dVOUT/dt(on) Turn-on voltage slope RL = 13 from VOUT = 1.3 V to VOUT = 10.4 V - See Figure 10 - V/s dVOUT/dt(off) Turn-off voltage slope RL = 13 from VOUT = 11.7 V to VOUT = 1.3 V - See Figure 12 - V/s Doc ID 17387 Rev 2 9/28 Electrical specifications Table 10. VNQ810P-E Open-load detection Symbol Parameter IOL Open-load on-state detection threshold VIN = 5 V Open-load on-state detection delay IOUT = 0 A VOL Open-load off-state voltage detection threshold VIN = 0 V tDOL(off) Open-load detection delay at turn-off tDOL(on) Table 11. Test conditions Min. 20 1.5 40 2.5 Unit 80 mA 200 s 3.5 V 1000 s Logic inputs Symbol Parameter Test conditions VIL Input low level IIL Low level input current VIH Input high level IIH High level input current VI(hyst) Input hysteresis voltage VICL Input clamp voltage Figure 4. Status timings VIN = 1.25 V Min. Typ. Max. Unit 1.25 V 1 A 3.25 V VIN = 3.25 V 10 0.5 IIN = 1 mA 6 IIN = -1 mA VINn VSTATn 6.8 8 V V OVER TEMP STATUS TIMING Tj > TTSD VINn VSTATn tSDL tDOL(off) tDOL(on) Doc ID 17387 Rev 2 A V - 0.7 OPEN LOAD STATUS TIMING (with external pull-up) IOUT < IOL VOUT > VOL 10/28 Typ. Max. tSDL VNQ810P-E Electrical specifications Figure 5. Switching time Waveforms Table 12. Truth table Conditions Input Output Sense Normal operation L H L H H H Current limitation L H H L X X H (Tj < TTSD) H (Tj > TTSD) L Overtemperature L H L L H L Undervoltage L H L L X X Overvoltage L H L L H H Output voltage > VOL L H H H L H Output current < IOL L H L H H L Doc ID 17387 Rev 2 11/28 Electrical specifications Table 13. VNQ810P-E Electrical transient requirements on VCC pin (part 1/3) ISO T/R Test levels 7637/1 Test pulse I II III IV Delays and impedance 1 - 25V - 50V - 75V - 100V 2ms, 10 2 + 25V + 50V + 75V + 100V 0.2ms, 10 3a - 25V - 50V - 100V - 150V 0.1s, 50 3b + 25V + 50V + 75V + 100V 0.1s, 50 4 - 4V - 5V - 6V - 7V 100ms, 0.01 5 + 26.5V + 46.5V + 66.5V + 86.5V 400ms, 2 Table 14. Electrical transient requirements on VCC pin (part 2/3) ISO T/R Test levels results 7637/1 Test pulse I II III IV 1 C C C C 2 C C C C 3a C C C C 3b C C C C 4 C C C C 5 C E E E Table 15. Electrical transient requirements on VCC pin (part 3/3) Class 12/28 Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. Doc ID 17387 Rev 2 VNQ810P-E Electrical specifications Figure 6. Waveforms Normal operation INPUTn OUTPUT VOLTAGEn STATUSn Undervoltage VUSDhyst VCC VUSD INPUTn OUTPUT VOLTAGEn STATUSn undefined Overvoltage VCC<VOV VCC > VOV VCC INPUTn OUTPUT VOLTAGEn STATUSn Open-load with external pull-up INPUTn VOUT > VOL OUTPUT VOLTAGEn VOL STATUSn Open-load without external pull-up INPUTn OUTPUT VOLTAGEn STATUSn Tj TTSD TR Overtemperature INPUTn OUTPUT VOLTAGEn STATUSn Doc ID 17387 Rev 2 13/28 Electrical specifications VNQ810P-E 2.4 Electrical characteristics curves Figure 7. Off-state output current Figure 8. High level input current Iih (uA) IL(off1) (uA) 1.6 5 1.44 4.5 Off state Vcc=36V Vin=Vout=0V 1.28 1.12 Vin=3.25V 4 3.5 0.96 3 0.8 2.5 0.64 2 0.48 1.5 0.32 1 0.16 0.5 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 Figure 9. 50 75 100 125 150 175 Tc (C) Tc (C) Input clamp voltage Figure 10. Status leakage current Ilstat (uA) Vicl (V) 0.05 8 7.8 Iin=1mA 7.6 0.04 Vstat=5V 7.4 0.03 7.2 7 0.02 6.8 6.6 0.01 6.4 6.2 0 6 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 Tc (C) Figure 11. Status low output voltage 75 100 125 150 175 Tc (C) Figure 12. Status clamp voltage Vstat (V) Vscl (V) 0.8 8 7.8 0.7 Istat=1.6mA Istat=1mA 7.6 0.6 7.4 0.5 7.2 0.4 7 6.8 0.3 6.6 0.2 6.4 0.1 6.2 0 6 -50 -25 0 25 50 75 100 125 150 175 -50 Tc (C) 14/28 -25 0 25 50 75 Tc (C) Doc ID 17387 Rev 2 100 125 150 175 VNQ810P-E Electrical specifications Figure 13. Overvoltage shutdown Figure 14. ILIM vs Tcase Vov (V) Ilim (A) 50 10 48 9 46 8 44 Vcc=13V 7 42 6 40 5 38 4 36 3 34 2 32 1 30 -50 -25 0 25 50 75 100 125 150 175 0 -50 Tc (C) -25 0 25 50 75 100 125 150 175 150 175 Tc (C) Figure 15. Turn-on voltage slope Figure 16. Turn-off voltage slope dVout/dt(off) (V/ms) dVout/dt(on) (V/ms) 500 1000 450 900 Vcc=13V Rl=13Ohm 800 Rl=13Ohm 400 700 350 600 300 500 250 400 200 300 150 200 100 100 50 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) 50 75 100 125 Tc (C) Figure 17. On-state resistance vs Tcase Ron (mOhm) Figure 18. On-state resistance vs VCC Ron (mOhm) 400 300 350 275 Iout=0.5A Vcc=8V; 13V & 36V 300 Iout=0.5A 250 Tc= 150C 225 250 200 200 175 150 150 Tc= 25C 125 100 100 Tc= - 40C 50 75 0 50 -50 -25 0 25 50 75 100 125 150 175 Tc (C) 5 10 15 20 25 30 35 40 Vcc (V) Doc ID 17387 Rev 2 15/28 Electrical specifications VNQ810P-E Figure 19. Input high level Figure 20. Input low level Vil (V) Vih (V) 2.6 3.6 2.4 3.4 2.2 3.2 2 3 1.8 2.8 1.6 2.6 1.4 2.4 1.2 2.2 1 2 -50 -50 -25 0 25 50 75 100 125 150 -25 0 25 175 50 75 100 125 150 175 Tc (C) Tc (C) Figure 21. Open-load on-state detection threshold Figure 22. Open-load off-state voltage detection threshold Vol (V) Iol (mA) 5 60 4.5 55 Vin=0V 4 Vcc=13V Vin=5V 50 3.5 45 3 40 2.5 35 2 30 1.5 25 1 20 0.5 15 0 -50 10 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Figure 23. Input hysteresis voltage Vhyst (V) 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 125 150 175 Tc (C) 16/28 Doc ID 17387 Rev 2 -25 0 25 50 75 Tc (C) 100 125 150 175 VNQ810P-E 3 Application information Application information Figure 24. Application schematic +5V +5V +5V VCC1,2 VCC3,4 Rprot STATUS1 Rprot INPUT1 Dld Rprot STATUS2 Rprot INPUT2 Rprot STATUS3 C Rprot OUTPUT1 OUTPUT2 OUTPUT3 INPUT3 Rprot STATUS4 OUTPUT4 Rprot INPUT4 GND1,2 GND3,4 RGND VGND +5V +5V DGND Note: Channels 3 and 4 have the same internal circuit as channel 1 and 2. 3.1 GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery. 3.1.1 Solution 1: a resistor in the ground line (RGND only) It can be used with any type of load. The following show how to dimension the RGND resistor: Equation 1 RGND 600mV / 2 (IS(on)max) Doc ID 17387 Rev 2 17/28 Application information VNQ810P-E Equation 2 RGND ( - VCC) / ( - IGND) where - IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in RGND (when VCC < 0 during reverse battery situations) is: PD = ( - VCC)2/ RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with Equation 1 where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that, if the microprocessor ground is not shared by the device ground, then the RGND produces a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift varies depending on how many devices are ON in the case of several high side drivers sharing the same RGND . If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below. 3.1.2 Solution 2: a diode (DGND) in the ground line A resistor (RGND = 1k) should be inserted in parallel to DGND if the device is driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network produces a shift ( 600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift not varies if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. 3.2 Load dump protection Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the VCC maximum DC rating. The same applies if the device is subject to transients on the VCC line that are greater than those shown in the ISO T/R 7637/1 table. 3.3 MCU I/O protection If a ground protection network is used and negative transients are present on the VCC line, the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/O pins from latching up. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os: - VCCpeak / Ilatchup Rprot (VOHC - VIH - VGND) / IIHmax 18/28 Doc ID 17387 Rev 2 VNQ810P-E Application information Example For the following conditions: VCCpeak = - 100 V Ilatchup 20 mA VOHC 4.5 V 5 k Rprot 65 k. Recommended values are: Rprot = 10 k 3.4 Open-load detection in off-state Off-state open-load detection requires an external pull-up resistor (RPU) connected between output pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1. No false open-load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT = (VPU / (RL + RPU))RL < VOlmin. 2. No misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition RPU < (VPU - VOLmax) / IL(off2). Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in standby. The values of VOLmin, VOLmax and IL(off2) are available in Section 2.3: Electrical characteristics. Figure 25. Open-load detection in off-state V batt. VPU VCC RPU INPUT DRIVER + LOGIC IL(off2) OUT + STATUS R VOL RL GROUND Doc ID 17387 Rev 2 19/28 Application information 3.5 VNQ810P-E Maximum demagnetization energy (VCC = 13.5V) Figure 26. SO-28 (double island) maximum turn-off current versus load inductance ILMAX (A) 10 A B C 1 0.01 0.1 1 L(mH) 10 100 A = single pulse at TJstart = 150 C B= repetitive pulse at TJstart = 100 C C= repetitive pulse at TJstart = 125 C VIN, IL Demagnetization Demagnetization Demagnetization t Note: Values are generated with RL = 0. In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. 20/28 Doc ID 17387 Rev 2 VNQ810P-E Package and PCB thermal data 4 Package and PCB thermal data 4.1 SO-28 thermal data Figure 27. SO-28 double island PC board Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 35 m, Copper areas: 0.5 cm2, 3 cm2, 6 cm2). Table 16. Thermal calculation according to the PCB heatsink area Chip 1 Chip 2 Tjchip1 Tjchip2 Note ON OFF RthA x Pdchip1 + Tamb RthC x Pdchip1 + Tamb OFF ON RthC x Pdchip2 + Tamb RthA x Pdchip2 + Tamb ON ON RthB x (Pdchip1 + Pdchip2) + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1 = Pdchip2 ON ON (RthA x Pdchip1) + RthC x Pdchip2 (RthA x Pdchip2) + RthC x Pdchip1 Pdchip1 Pdchip2 + Tamb + Tamb RthA = thermal resistance junction to ambient with one chip ON RthB = thermal resistance junction to ambient with both chips ON and Pdchip1 = Pdchip2 RthC = mutual thermal resistance Doc ID 17387 Rev 2 21/28 Package and PCB thermal data VNQ810P-E Figure 28. Rthj-amb vs PCB copper area in open box free air condition RTHj_am b (C/W) 70 60 50 RthA 40 RthB 30 20 RthC 10 0 1 2 3 4 5 PCB Cu heatsink area (cm ^2)/island 6 7 Figure 29. SO-28 thermal impedance junction ambient single pulse Zth(C/W) 100 0,5 cm ^2/is land 3 cm ^2/is land 6 cm ^2/is land 10 1 One channel ON Two channels ON on same chip 0.1 0.01 0.0001 0.001 0.01 0.1 1 time(s) Equation 3: pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where 22/28 = tp T Doc ID 17387 Rev 2 10 100 1000 VNQ810P-E Package and PCB thermal data Figure 30. Thermal fitting model of a quad channel HSD in SO-28 Tj_1 P d1 Tj_2 C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 C 10 C 11 C12 C 13 R 13 C14 R 14 P d2 R 17 Tj_3 R 18 C7 C8 C9 R7 R8 R9 P d3 Tj_4 P d4 C 15 R 15 R 10 R 11 R 12 C 16 R 16 T _am b Table 17. Thermal parameters Area / island (cm2) 0.5 R1 = R7 = R13 = R15 (C/W) 0.35 R2 = R8 = R14 = R16 (C/W) 1.8 R3 = R9 (C/W) 4.5 R4 = R10 (C/W) 11 R5 = R11 (C/W) 15 R6 = R12 (C/W) 30 C1 = C7 = C13 = C15 (W.s/C) 0.0001 C2 = C8 = C14 = C16 (W.s/C) 7E-04 C3 = C9 (W.s/C) 6E-03 C4 = C10 (W.s/C) 0.2 C5 = C11 (W.s/C) 1.5 C6 = C12 (W.s/C) 5 R17 = R18 (C/W) 150 Doc ID 17387 Rev 2 6 13 8 23/28 Package and packing information VNQ810P-E 5 Package and packing information 5.1 ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 5.2 SO-28 package information Figure 31. SO-28 package dimensions 24/28 Doc ID 17387 Rev 2 VNQ810P-E Package and packing information Table 18. SO-28 mechanical data Millimeters Symbol Min. Typ. A Max. 2.65 a1 0.10 0.30 b 0.35 0.49 b1 0.23 0.32 C 0.50 c1 45 (typ.) D 17.7 18.1 E 10.00 10.65 e 1.27 e3 16.51 F 7.40 7.60 L 0.40 1.27 S 8 (max.) Doc ID 17387 Rev 2 25/28 Package and packing information 5.3 VNQ810P-E SO-28 packing information Figure 32. SO-28 tube shipment (no suffix) C Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) B 28 700 532 3.5 13.8 0.6 All dimensions are in mm. A Figure 33. SO-28 tape and reel shipment (suffix "TR") Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 16.4 60 22.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) All dimensions are in mm. 16 4 12 1.5 1.5 7.5 6.5 2 End Start Top cover tape No components Components 500mm min Empty components pockets saled with cover tape. User direction of feed 26/28 Doc ID 17387 Rev 2 No components 500mm min VNQ810P-E 6 Revision history Revision history Table 19. Document revision history Date Revision Changes 27-Apr-2010 1 Initial release. 19-Sep-2013 2 Updated Disclaimer Doc ID 17387 Rev 2 27/28 VNQ810P-E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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