October 2009 Version 1.0
FME/MS/DAC80/FL1/5630
DKXC5VADAPT-1
Page 2 of 4 Production © 2004-2009 Fujitsu Microelectronics Europe GmbH
Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU
MICROELECTRONICS sales representatives before ordering.
The information and circuit diagrams in this document are
presented “as is”, no license is granted by implication or otherwise.
System Overview
The most popular device for interfacing to
high-speed data converters is an FPGA.
FPGAs provide a relatively low-cost platform
for high-speed logic, data processing, digital
data interfaces and clock management. The
DKXC5VADAPT-1 adaptor demonstrates how
simple it is to implement a high-performance
interface between an FPGA and the Fujitsu
DK8606x DAC DKs.
The adaptor is designed to interface directly to
the HiTech Global V5-PCIE2 FPGA prototype
board to combine the power of the Xilinx
Virtex-5 with the high-speed Fujitsu DAC.
System Setup
The DKXC5VADAPT-1 provides a physical
link between the data headers on the
DK86064/65-2 and the HiTech Global V5-
PCIE2. The underside of the adaptor features
6 Samtec sockets that plug directly into the
headers on the two boards.
Adaptor underside view
The board connects 28 LVDS data pairs, the
DAC loop clock pairs and two divided clock
signals between the two boards. All clock
signals are routed to dedicated global clock
inputs on the FPGA.
The complete system forms a compact
solution ideal for testing and developing an
FPGA-DAC interface.
Complete system
DAC Interface
All data and clock lines between the DAC and
FPGA are matched LVDS pairs. The adaptor
can be used with both the DK86064-2 and
DK86065-2.
Maintaining valid clock-to-data timing can
prove to be a difficult task when using high-
speed data converters. The MB86064/65
DACs avoid potential problems through the
provision of a Loop Clock system.
The Loop Clock is generated in sync with the
DAC data at the FPGA output. This clock is
passed through a user programmable delay in
the DAC and then routed back to the FPGA’s
PLL feedback input. Altering the delays in the
divided clock or Loop Clock signals allows the
user to advance or retard data timings in order
to find the optimum data eye. Once calibrated,
the system automatically compensates for the
effects of device-to-device variations, voltage
and temperature (PVT).
DAC Clock
PLL
CLKIN
DAC
Fujitsu DAC
Retard
data
Advance
data
FPGA
OSERDES
OSERDES
OSERDES
14 14 14
CLKOUT
CLKFBIN
CLK#_OUT
LPCLK_OUT
LPCLK_IN
A1-A14
DATA
GCLK
GCLK
GCLK
DAC Clock
PLL
CLKIN
DAC
Fujitsu DAC
Retard
data
Advance
data
FPGA
OSERDES
OSERDES
OSERDES
14 14 14
CLKOUT
CLKFBIN
CLK#_OUT
LPCLK_OUT
LPCLK_IN
A1-A14
DATA
GCLK
GCLK
GCLK
Loop Clock block diagram