Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com (email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
- © Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
1. Product profile
1.1 General description
Dual intermediate level N-channel enhancement mode Field-Effect Transistor (FET) in a
plastic package using TrenchMOS technology. This product is designed and qualified for
use in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Suitable for high frequency
applications due to fast switching
characteristics
Suitable for logic level gate drive
sources
Suitable for low gate drive sources
1.3 Applications
DC-to-DC converters
Logic level translators
Motor and relay drivers
1.4 Quick reference data
[1] Surface mounted on FR4 board, t 10 sec.
[2] Surface mounted on FR4, t 10 sec.
PHN210T
Dual N-channel TrenchMOS intermediate level FET
Rev. 02 — 15 December 2010 Product data sheet
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source
voltage Tj25 °C; Tj150 °C;
Repetitive peak drain-source
voltage
--30V
IDdrain current Tsp = 25 °C; Single device [1] --3.4A
Ptot total power
dissipation Tsp =2C [2] --2W
Static characteristics
RDSon drain-source
on-state
resistance
VGS =4.5V; I
D=1A;
Tj=2C -120200m
VGS =10V; I
D=2.2A;
Tj=2C -80100m
Dynamic characteristics
QGD gate-drain charge VGS =10V; I
D=2.3A;
VDS =15V; T
j=2C -0.7-nC
PHN210T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 15 December 2010 2 of 13
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET
2. Pinning information
3. Ordering information
Table 2. Pinning info rmation
Pin Symbol Description Simplified outline Graphi c sy mbol
1S1source1
SOT96-1 (SO8)
2 G1 gate1
3S2source2
4 G2 gate2
5 D drain2
6 D drain2
7 D drain1
8 D drain1
4
5
1
8
D1
mbk725
G1S1
D1 D2
G2S2
D2
Tabl e 3. Orderi ng information
Type number Package
Name Description Version
PHN210T SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PHN210T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 15 December 2010 3 of 13
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET
4. Limiting values
[1] Surface mounted on FR4 board, t 10 sec.
[2] Surface mounted on FR4, t 10 sec.
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage Continuous - 30 V
Tj25 °C; Tj150 °C; Repetitive peak
drain-source voltage -30V
VDGR drain-gate voltage RGS =20k-30V
VGS gate-source voltage -20 20 V
IDdrain current Tsp = 70 °C; Dual device [1] -1.9A
Tsp = 70 °C; Single device [1] -2.8A
Tsp = 25 °C; Dual device [1] -2.4A
Tsp = 25 °C; Single device [1] -3.4A
IDM peak drain current T sp = 25 °C; pulsed - 14 A
Ptot total power dissipation Tsp =2C [2] -2W
Tstg storage temperature -65 150 °C
Tjjunction temperature -65 150 °C
Source-drain diode
ISsource current Tsp =2C - 2.2 A
ISM peak source current Tsp = 25 °C; pulsed - 14 A
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source
avalanche energy VGS =10V; T
j(init) =2C; I
D=3.4A;
VDD 15 V; unclamped; RGS =50;
tp=0.2ms
-13mJ
IAS non-repetitive avalanche
current Vsup 15 V; VGS =10V; T
j(init) =2C;
RGS =50; unclamped -3.4A
PHN210T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 15 December 2010 4 of 13
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET
Fig 1. Normalized total power dissipation as a
function of ambient temperature Fig 2. Normalized continuous drain current as a
function of ambient temperature
Ta = 25 °C; IDM is single pulse unclamped inductive load
Fig 3. Safe operating area; continuous and peak drain
currents as a function of drain-sou rce voltage Fig 4. Single-shot avalanche rating ; avalanche
current as a function of avalanche period
40
80
120
P
der
(%)
0
T
amb
(°C)
0 16012040 80
003aaf065
40
80
120
l
D
(%)
0
T
amb
(°C)
0 16012040 80
003aaf066
003aaf067
VDS (V)
101102
101
101
1
10
102
IDM
(A)
102
RDS(on) = VDS / ID
100 ms
10 s
10 ms
1 ms
100 μs
tp = 10 μs
003aaf080
t
p
(s)
10
6
10
2
10
3
10
5
10
4
1
10
I
AS
(A)
10
1
T
j
prior to avalanche = 125 °C
25 °C
ID
VDS t
p
PHN210T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 15 December 2010 5 of 13
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET
5. Thermal characteristics
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-a) thermal resistance
from junction to
ambient
Surface mounted; FR4 board - 150 - K/W
Surface mounted; FR4 board;
t 10 sec - - 62.5 K/W
Fig 5. Transient thermal impedance from junction to ambient as a function of pulse duration
003aaf068
10
1
1
10
10
2
Z
th(j-a)
(K/W)
10
2
t
p
(s)
10
6
10
1
11010
2
10
5
10
3
10
4
t
p
t
p
T
P
t
T
δ =
single pulse
0.02
0.05 0.1
0.2
δ = 0.5
PHN210T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 15 December 2010 6 of 13
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET
6. Characteristics
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage ID=1A; V
GS =0V; T
j=25°C 30--V
ID=1A; V
GS =0V; T
j= -55 °C 27 - - V
VGS(th) gate-source threshold
voltage ID=1mA; V
DS =V
GS; Tj=-55°C --3.2V
ID=1mA; V
DS =V
GS; Tj= 150 °C 0.4 - - V
ID=1mA; V
DS =V
GS; Tj=25°C 122.8V
IDSS drain leakage current VDS =24V; V
GS =0V; T
j= 25 °C - 10 100 nA
VDS =24V; V
GS =0V; T
j= 150 °C - 0.6 10 µA
IGSS gate leakage current VGS =20V; V
DS =0V; T
j= 25 °C - 10 100 nA
VGS =-20V; V
DS =0V; T
j= 25 °C - 10 100 nA
RDSon drain-source on-state
resistance VGS =4.5V; I
D=1A; T
j= 25 °C - 120 200 m
VGS =10V; I
D=2.2A; T
j= 150 °C - - 170 m
VGS =10V; I
D=2.2A; T
j= 25 °C - 80 100 m
IDSon on-state drain current VDS =1V; V
GS =10V 3.5--A
VDS =5V; V
GS =4.5V 2--A
Dynamic character istics
QG(tot) total gate charge ID=2.3A; V
DS =15V; V
GS =10V;
Tj=2C -6-nC
QGS gate-source charge - 0.7 - nC
QGD gate-drain charge - 0.7 - nC
Ciss input capacitance VDS =20V; V
GS = 0 V; f = 1 MHz;
Tj=2C - 250 - pF
Coss output capacitance - 88 - pF
Crss reverse transfer
capacitance -54-pF
td(on) turn-on delay time VDS =20V; R
L=18; VGS =10V;
RG(ext) =6; Tj=2C -6-ns
trrise time - 8 - ns
td(off) turn-o ff delay time - 21 - ns
tffall time - 15 - ns
gfs transfer conductance VDS =20V; I
D= 2.2 A; Tj=2C 2 4.5 - S
LDinternal drain
inductance measured from drain lead to centre of
die; Tj=2C -2.5-nH
LSinternal source
inductance measured from source lead to source
bond pad; Tj=2C -5-nH
Source-drain diode
VSD source-drain voltage IS= 1.25 A; VGS =0V; T
j= 25 °C - 0.82 1.2 V
trr reverse recovery time IS= 1.25 A; dIS/dt = -100 A/µs;
VGS =0V; V
DS =25V; T
j=2C -69-ns
Qrrecovered charge - 55 - nC
PHN210T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 15 December 2010 7 of 13
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET
Tj = 25 °C Tj = 25 °C
Fig 6. Outp ut characteristics: dra in current as a
function of drain-source voltage; typical values Fig 7. Drain-source on-state resistance as a function
of drain current; typical values
VDS > ID x RDSon VDS > ID x RDSon
Fig 8. Transfer characteristics: drain current as a
function of gate-source voltage; typical values Fig 9. Forward transconductance as a function of
drain current; typical values
ID = 1 mA; VDS = VGS
Fig 10. Normalized drain-source on-state resistance
factor as a function of junction temperature Fig 11. Gate-source threshold voltage as a function of
junction temperature
4
6
2
8
10
lD
(A)
0
VDS (V)
021.60.8 1.20.4
003aaf069
VGS (V) = 20 10
4.2
4
3.8
3.6
3.4
3.2
5
0.2
0.3
0.1
0.4
0.5
RDS(on)
(Ω)
0
ID (A)
0108462
003aaf070
20
4.243.83.63.43.2
VGS (V) = 5
10
4
6
2
8
10
I
D
(A)
0
003aaf071
V
GS
(V)
0642
T
j
= 25 °C
T
j
= 150 °C
2
4
6
gfs
(S)
0
lD (A)
0108462
003aaf073
Tj = 25 °C
Tj = 150 °C
0
1.5
1
0.5
2
a
Tj (°C)
50 150100050
003aaf074
0
3
2
1
4
VGS(th)
(V)
003aaf075
Tj (°C)
70 1709010
maximum
minimum
typical
PHN210T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 15 December 2010 8 of 13
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET
Tj = 25 °C; VDS = VGS VGS = 0 V ; f = 1 MHz
Fig 12. Sub-threshold drain current as a function of
gate-source voltage Fig 13. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
ID = 2.3 A; Tj = 25 °C; VDD = 15 V VGS = 0 V
Fig 14. Gate-source vo ltage as a function of gate
charge; typical values Fig 15. Source (diode forward) current as a function of
source-drain (diode forward) voltage; typical
values
003aaf076
V
GS (V)
05312
10
4
10
5
10
2
10
3
1
I
D
(A)
10
6
maximumminimum typical
003aaf077
VDS (V)
101102
101
102
103
10
C
(pF)
Ciss
Coss
Crss
0
12
8
4
16
VGS
(V)
QG (nC)
0108462
003aaf078
4
6
2
8
10
l
F
(A)
0
V
SDS
(V)
0 1.61.20.4 0.8
003aaf079
T
j
= 150 °CT
j
= 25 °C
PHN210T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 15 December 2010 9 of 13
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET
7. Package outline
Fig 16. Package outline SOT96-1 (SO8)
UNIT A
max. A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 5.0
4.8 4.0
3.8 1.27 6.2
5.8 1.05 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.10.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
1.0
0.4
SOT96-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
4
5
pin 1 index
1
8
y
076E03 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.20
0.19 0.16
0.15 0.05 0.244
0.228 0.028
0.024 0.028
0.012
0.010.010.041 0.004
0.039
0.016
0 2.5 5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
99-12-27
03-02-18
PHN210T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 15 December 2010 10 of 13
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET
8. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PHN210T v.2 20101215 Product data sheet - PHN210T v.1
Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
PHN210T v.1 1999 0301 Product specification - -
PHN210T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 15 December 2010 11 of 13
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET
9. Legal information
9.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The p r oduct status of device(s) described in t his documen t may have changed since this documen t was publish ed and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specifica t io nThe information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
9.3 Disclaimers
Limited warranty and liability — Information in this document is be lieved to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Quick reference dataThe Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
PHN210T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 02 — 15 December 2010 12 of 13
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document ma y be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) d escribed herein may
be subject to export control regulat i ons. Export might require a prior
authorization fro m national authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in au tomotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
9.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors PHN210T
Dual N-channel TrenchMOS intermediate level FET
© NXP B.V. 2010. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 December 2010
Document identifier: PHN210T
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11. Contents
1 Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 General description . . . . . . . . . . . . . . . . . . . . . .1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
5 Thermal characteristics . . . . . . . . . . . . . . . . . . .5
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .11
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11
9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
10 Contact information. . . . . . . . . . . . . . . . . . . . . .12