NC7SZ00M5X_NL - Fairchild Semiconductor

September 2009

NC7SZ00 • Rev. 1.0.3

NC7SZ00 — TinyLogic

®

UHS Two-Input NAND Gate

NC7SZ00

TinyLogic® UHS Two-Input NAND Gate

Features

 Ultra-High Speed: tPD 2.4ns (Typical) into 50pF at

5V VCC

 High Output Drive: ±24mA at 3V VCC

 Broad VCC Operating Range: 1.65V to 5.5V

 Matches Performance of LCX Operated at 3.3V VCC

 Power Down High-Impedance Inputs/Outputs

 Over-Voltage Tolerance inputs facilitate 5V to 3V

Translation

 Proprietary Noise/EMI Reduction Circuitry

 Ultra-Small MicroPak™ Packages

 Space-Saving SOT23 and SC70 Packages

Description

The NC7SZ00 is a single two-input NAND gate from

Fairchild’s Ultra-High Speed (UHS) series of

TinyLogic®. The device is fabricated with advanced

CMOS technology to achieve ultra-high speed with high

output drive while maintaining low static power

dissipation over a broad VCC operating range. The

device is specified to operate over the 1.65V to 5.5V

VCC operating range. The inputs and output are high

impedance when VCC is 0V. Inputs tolerate voltages up

to 6V, independent of VCC operating voltage.

Related Resources

 MS-503 — Family Characteristics TinyLogic®

HS/HST and UHS Series

Ordering Information

Part Number Top Mark Eco Status Package Packing Method

NC7SZ00M5X 7Z00 RoHS 5-Lead SOT23, JEDEC MO-178 1.6mm 3000 Units on

Tape & Reel

NC7SZ00P5X Z00 RoHS 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3000 Units on

Tape & Reel

NC7SZ00L6X YY RoHS 6-Lead MicroPak™, 1.00mm Wide 5000 Units on

Tape & Reel

NC7SZ00FHX YY Green

6-Lead, MicroPak2, 1x1mm Body, .35mm

Pitch 5000 Units on

Tape & Reel

For Fairchild’s defini t i on of Eco St atus, pleas e visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

NC7SZ00 • Rev. 1.0.3 2

NC7SZ00 — TinyLogic

®

UHS Two-Input NAND Gate

Connection Diagrams

IEEE/IEC

Figure 1. Logic Symbol

Pin Configurations

Figure 2. SC70 and SOT23 (Top View) Figure 3. MicroPak (Top Through View)

Pin Definitions

Pin # SC70 / SOT23 Pin # MicroPak Name Description

1 1 A Input

2 2 B Input

3 3 GND Ground

4 4 Y Output

5 6 VCC Supply Voltage

5 NC No Connect

Function Table

Inputs Output

A B Y

L L H

L H H

H L H

H H L

H = HIGH Logic Level

L = LOW Logic Level

NC7SZ00 • Rev. 1.0.3 3

NC7SZ00 — TinyLogic

®

UHS Two-Input NAND Gate

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage -0.5 6.0 V

VIN DC Input Voltage -0.5 6.0 V

VOUT DC Output Voltage -0.5 6.0 V

VIN < -0.5V -50

IIK DC Input Diode Current VIN > 6.0V +20 mA

VOUT < -0.5V -50

IOK DC Output Diode Current VOUT > 6V, VCC=GND +20

mA

IOUT DC Output Current ±50 mA

ICC or IGND DC VCC or Ground Current ±50 mA

TSTG Storage Temperature Range -65 +150 °C

TJ Junction Temperature Under Bias +150 °C

TL Junction Lead Temperature (Soldering, 10 Seconds) +260 °C

SOT-23 200

SC70-5 150

MicroPak-6 130

PD Power Dissipation at +85°C

MicroPak2-6 120

mW

Human Body Model, JEDEC:JESD22-A114 4000

ESD Charge Device Model, JEDEC:JESD22-C101 2000 V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Conditions Min. Max. Unit

Supply Voltage Operating 1.65 5.50

VCC Supply Voltage Data Retention 1.5 5.5 V

VIN Input Voltage 0 5.5 V

VOUT Output Voltage 0 VCC V

TA Operating Temperature -40 +85 °C

VCC at 1.8V, 2.5V ±0.2V 0 20

VCC at 3.3V ± 0.3V 0 10

tr, tf Input Rise and Fall Times VCC at 5.0V ± 0.5V 0 5 ns/V

SOT-23 300

SC70-5 425

MicroPak-6 500

θJA Thermal Resistance

MicroPak2-6 560

°C/W

Note:

1. Unused inputs must be held HIGH or LOW. They may not float.

NC7SZ00 • Rev. 1.0.3 4

NC7SZ00 — TinyLogic

®

UHS Two-Input NAND Gate

DC Electrical Characteristics

TA=25°C TA=-40 to +85°C

Symbol Parameter VCC Conditions

Min. Typ. Max. Min. Max. Units

1.65 to 1.95 0.75VCC 0.75VCC

VIH HIGH Level Input Voltage 2.30 to 5.50 0.70VCC 0.70VCC V

1.65 to 1.95 0.25VCC 0.25VCC

VIL LOW Level Input Voltage 2.30 to 5.50 0.30VCC 0.30VCC V

1.65 1.55 1.65 1.55

1.80 1.70 1.80 1.70

2.30 2.20 2.30 2.20

3.00 2.90 3.00 2.90

4.50

VIN=VIL

IOH=-100µA

4.40 4.50 4.40

1.65 IOH=-4mA 1.29 1.52 1.29

1.80 IOH=-8mA 1.90 2.15 1.90

2.30 IOH=-16mA 2.40 2.80 2.40

3.00 IOH=-24mA 2.30 2.68 2.30

VOH HIGH Level Output

Voltage

4.50 IOH=-32mA 3.80 4.20 3.80

V

1.65 0.00 0.10 0.08

2.30 0.00 0.10 0.10

3.00 0.00 0.10 0.10

4.50

VIN=VIH

IOL=100µA

0.00 0.10 0.10

1.65 IOL=4mA 0.80 0.24 0.24

2.30 IOL=8mA 0.10 0.30 0.30

3.00 IOL=16mA 0.15 0.40 0.40

3.00 IOL=24mA 0.22 0.55 0.55

VOL LOW Level Output

Voltage

4.50 IOL=32mA 0.22 0.55 0.55

V

IIN Input Leakage Current 0 to 5.5 VIN=5.5V , GND ±1 ±10 µA

IOFF Power Off 0 VIN or VOUT=5.5V 1 10 µA

ICC Quiescent Supply Current 1.65 to 5.50 VIN=5.5V, GND 2 20 µA

NC7SZ00 • Rev. 1.0.3 5

NC7SZ00 — TinyLogic

®

UHS Two-Input NAND Gate

AC Electrical Characteristics

TA=25°C TA=-40 to +85°C

Symbol Parameter VCC Conditions Min. Typ. Max. Min. Max.

Units Figure

1.65 2.0 5.4 11.4 2.0 12.0

1.80 2.0 4.5 9.5 2.0 10.0

2.50 ± 0.20 0.8 3.0 6.5 0.8 7.0

3.30 ± 0.30 0.5 2.4 4.5 0.5 4.7

5.00 ± 0.50

CL=15pF,

RL=1MΩ

0.5 2.0 3.9 0.5 4.1

3.30 ± 0.30 1.5 2.9 5.0 1.5 5.2

tPHL, tPLH Propagation Delay

5.00 ± 0.50 CL=50pF,

RL=500Ω 0.8 2.4 4.3 0.8 4.5

ns Figure 4

Figure 5

CIN Input Capacitance 0.00 4 pF

3.30 24

CPD Power Dissipati on

Capacitance(2) 5.00 30 pF Figure 6

Note:

2. CPD is defined as the value of the internal equivalent capacitance derived from dynamic operating current

consumption (ICCD) at no output lading and operating at 50% duty cycle. CPD is related to ICCD dynamic operating

current by the expression: ICCD=(CPD)(VCC)(fIN)+(ICCstatic).

Figure 4. AC Test Circuit Figure 5. AC Waveforms

Note:

3. Input=AC Waveform; tr=tf=1.8ns; PRR=10MHz; Duty Cycle =50%.

Figure 6. ICCD Test Circuit

NC7SZ00 • Rev. 1.0.3 6

NC7SZ00 — TinyLogic

®

UHS Two-Input NAND Gate

Physical Dimensions

5

1

4

32

LAND PATTE RN RECOMMENDATION

B

AL

C

0.10 C

0.20 CAB

0.60 REF

0.55

0.35 SEATING PLANE

0.25

GAGE PLANE

8°

0°

NOTES: UNLESS OTHEWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MO-178, ISSUE B, VARIATION AA,

B) ALL DIMENSIONS ARE IN MILLIM ETERS.

1.45 MAX

1.30

0.90

0.15

0.05

1.90

0.95 0.50

0.30

3.00

2.60

1.70

1.50

3.00

2.80

SYMM

C0.950.95

2.60

0.70

1.00

SEE DETAIL A

0.22

0.08

C) MA05Brev5

TOP VIEW

(0.30)

Figure 7. 5-Lead SOT23, JEDEC MO-178 1.6mm

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/packaging/SOT23-5L_tr.pdf.

Package Designator Tape Section Cavity Number Cavity Status Cover Type Status

Leader (Start End) 125 (Typical) Empty Sealed

Carrier 3000 Filled Sealed

M5X Trailer (Hub End) 75 (Typical) Empty Sealed

NC7SZ00 • Rev. 1.0.3 7

NC7SZ00 — TinyLogic

®

UHS Two-Input NAND Gate

Physical Dimensions

Figure 8. 5-Lead, SC70, EIAJ SC-88a, 1.25mm Wide

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf.

Package Designator Tape Section Cavity Number Cavity Status Cover Type Status

Leader (Start End) 125 (Typical) Empty Sealed

Carrier 3000 Filled Sealed

P5X Trailer (Hub End) 75 (Typical) Empty Sealed

NC7SZ00 • Rev. 1.0.3 8

NC7SZ00 — TinyLogic

®

UHS Two-Input NAND Gate

Physical Dimensions

2. DIMENSIONS ARE IN MILLIMETERS

1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD

MAC06AREVC

Notes:

3. DRAWING CONFORMS TO ASME Y14.5M-1994

TOP VIEW

RECOMMENED

LAND PATTERN

BOTTOM VIEW

1.45

1.00

A

B0.05 C

0.05 C

2X

0.55MAX

0.05 C

(0.49)

(1)

(0.75)

(0.52)

(0.30)

6X

1X

6X

PIN 1

DETAIL A

0.075 X 45

CHAMFER

0.25

0.15

0.35

0.25

0.40

0.30

0.5

(0.05)

1.0

5X

DETAIL A

PIN 1 TERMINAL

0.40

0.30

0.45

0.35

0.10

0.00

0.10 CBA

0.05 C

C0.05 C

0.05

0.00

5X

6X (0.13)

4X

6X

Figure 9. 6-Lead, MicroPak™, 1.0mm Wide

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor represent ative to v er ify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.

Package Designator Tape Section Cavity Number Cavity Status Cover Type Status

Leader (Start End) 125 (Typical) Empty Sealed

Carrier 5000 Filled Sealed

L6X Trailer (Hub End) 75 (Typical) Empty Sealed

NC7SZ00 • Rev. 1.0.3 9

NC7SZ00 — TinyLogic

®

UHS Two-Input NAND Gate

Physical Dimensions

5X

DETAIL A

Figure 10. 6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor represent ative to v er ify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.

Package Designator Tape Section Cavity Number Cavity Status Cover Type Status

Leader (Start End) 125 (Typical) Empty Sealed

Carrier 5000 Filled Sealed

FHX Trailer (Hub End) 75 (Typical) Empty Sealed

NC7SZ00 • Rev. 1.0.3 10

NC7SZ00 — TinyLogic

®

UHS Two-Input NAND Gate