ee FAIRCHILD eee SEMICONDUCTOR? tr NC7W2Z17 TinyLogic UHS Dual Buffer with Schmitt Trigger Inputs General Description The NG7WZ17 is a dual buffer with Schmitt trigger inputs from Fairchilds Ultra High Speed Series of TinyLogic in the SC70 6-lead package. The device is fabricated with advanced GMOS technology to achieve ultra high speed with high output drive while maintaining low static power dissipation over a very broad Ver operating range. The device is specified to operate over the 1.8V to 5.5V Vag range. The inputs and outputs are high impedance when Voc is OV. Inputs tolerate voltages up to 7V independent of Vee operating voltage. Schmitt trigger inputs typically achieve 1V hysteresis between the positive going and neg- ative going input threshold voltage at 5V Voc. March 1999 Revised April 1999 Features @ Space saving SC70 6-lead package @ Ultra High Speed: tpp 3.6 ns Typ into 50 pF at 5V Vac @ High Output Drive: +24 mA at 3V Veg @ Broad Vec Operating Range; 1.8V to 5.5V @ Matches the performance of LCX when operated at 3.3V Veco @ Power down high impedance inputs/outputs @ Overvoltage tolerant inputs facilitate 5V to 3V translation @ Patented noise/EMI reduction circuitry implemented Ordering Code: Order Package Package a , Number Number Top Mark Package Description Supplied As NC7WZ17P6 MAAQO6A Z17 6-Lead $C70, EIAJ SC88, 1.25mm Wide 250 Units on Tape and Reel NC7WZ17P6X MAAQ6GA Z17 6-Lead SC70, ElAJ SC88, 1.25mm Wide 3k Units on Tape and Reel Logic Symbol Connection Diagrams IEEEAEC Ay [> Te *, aao +, 6ND Yee ota . Hp (Top View) . sae Pin One Orientation Diagram Pin Descriptions Pin Names Description H H H Ay, As Data Inputs (Ton View! ABA Yi, Yo Output Function Table I Cw Y=A Input Output Fin One A Y AAA represents Package Top Mark - see ordering code L L Note: Orientation of Top Mark determines Pin One location Read the Top H H Package Mark left to right Pin One is the lower left pin (gee diagram) H = HIGH Logic Level L = LOW Logic Level TinyLogic is a trademark of Fairchild Semiconductor Corporation 1999 Fairchild Semiconductor Corporation DS500217. prt www faischildsemi.com sindu] 4eBBiL WIWYIS YA JeyNg [ENG SHN wIIBOTAULL ZLZAAZONNC7W2Z17 Absolute Maximum Ratingswte 1) Supply Voltage (Vac) 0.5V to +7V BC Input Voltage (Vy) 0.5V to +7V DC Output Voltage (Vo 17) 0.5V to +7V BC Input Diode Current (|x) @Viy<-0.5V 50 mA DBC Gutput Diode Current (lai) @ Vou <-0.5V 50 mA DC Output Current (lou7) +50 mA BCG Vee/GND Current (lee/leno) +100 mA Storage Temperature (Ts) 85C ta +150C Junction Temperature under Bias (T|) 150C Junction Lead Temperature (T,) (Soldering, 10 seconds) 260C Power Dissipation (Pp) @ +85C 180 mW Dc Electrical Characteristics Recommended Operating Conditions Supply Voltage Operating (Ver) 1.8V to 5.5V Supply Voltage Data Retention (Vcc) 1.5V to 5.5V Input Voltage (Vy) OV to 5.5V Output Voltage (V5.7) OV to Veg Operating Temperature (Ta) 40C to +85C Thermal Resistance (6a) 350C AW Note 1: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired The datasheet specifica- tions should be met without exception to ensure that the system design is rallable over its power supply temperature and output/input loading vari- ables Fairchild does not recommend cperation cutside datasheet specifi- cations Vec Ta =+25C Ta =40C to 485C Symbol Parameter Units Conditions () Min Typ Max Min Max Vp Positive Threshold 1.8 07 1.07 15 07 1.5 Voltage 23 1.0 1.38 18 1.0 1.8 3.0 1.3 1.74 22 1.3 22 Vv 4.5 1.9 243 31 1.9 34 5.5 22 2.88 3.6 22 36 Vn Negative Threshold 1.8 0.25 0.56 09 0.25 09 Voltage 23 0.40 O75 1.15 0.40 1.15 3.0 O68 0.98 1.5 0.6 1.5 Vv 45 1.0 1.42 20 1.0 2.0 5.5 1.2 1.68 23 1.2 23 Vu Hysteresis Voltage 18 0.15 O51 10 0.15 1.0 23 0.25 0.62 14 0.25 11 3.0 o4 O76 12 04 1.2 Vv 4.5 O6 1.01 1.5 0.6 1.5 5.5 O7 1.20 17 O7 1.7 Vou HIGH Level Output 1.8 17 18 17 loy = -100 pA Voliage 23 22 23 22 3.0 29 3.0 29 4.5 44 45 44 23 19 B14 19 Vo [Min= Mik Pa 30 24 275 24 lo =-16 MA 3.0 23 262 23 lo =-24 MA 4.5 38 4.43 38 loy =-32 MA Voi LOW Level Output 1.8 0.0 01 o1 lo. = 160 PA Voltage 23 0.0 o1 o1 3.0 0.0 0.1 o.1 45 0.0 01 o1 23 0.10 03 03 Vo Yin= Vin Io. = 8mMA 30 0.16 04 o4 lo, = 16 mA 30 O24 0.55 0.55 lo. = 24 mA 4.5 0.25 0.55 0.55 Io, = 32 MA lin Input Leakage Current 0 10 5.5 +H +10 HA |iy=5.5V, GND loFr Power Off Leakage Current 0.0 1 10 WA [Vix Of Vou = 5.5 log Quiescent Supply Current | 1.810 5.5 10 10 HA [Vy = 5.54, GND www fairchildsemi.comAC Electrical Characteristics Veco Ta =+28C Ta =40C to 485C Symbol Parameter Units Conditions | Fig. No. (Vv) Min Typ Max Min Max tpLy Propagation Delay 18 2.0 69 11.9 2.0 13.1 C_ = 15 pF, Figure 1 tp P5402 15 48 82 15 90 RL =1Mo Figure 3 331403 1.0 37 5.6 1.0 62 ns 5.0+05 08 3.0 AT 08 5.2 tpLH Propagation Delay 3.3403 1.5 43 6.6 1.5 73 ns C, = 50 pF, Figure 1 teu 50+05 1.0 3.6 56 1.0 62 R, = 5000 Figure 3 Cin Input Capacitance a 25 pF Cpp Power Dissipation 33 16 pF (Note 2} Figure 2 Capacitance 5.0 12 Note 2: Capp is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (logo) at no output loading and operating at 50% duty cycle (See Figure 2) Cpp is related to legp dynamic operating current by the expression leco = (Cepkcenfint + (cestatic) AC Loading and Waveforms ar INPUT T* C_ includes load and stray capacitance Input PRR = 1 0 MHz, tw= 00 ns FIGURE 1. AC Test Circuit INPLT er Input = AC Waveform, t,=tp=1 8 ns, PRR = variable, Duty Cycle = 50% FIGURE 2. Icep Test Circuit GUTPUT INPUT OW PUT FIGURE 3. jt) = Sns AC Wavetorms Yoo GND ul www-faicchildsemi.com ZLZMZONNC7W2Z17 Tape and Reel Specification TAPE FORMAT Package Tape Number Cavity Cover Tape Designator Section Cavities Status Status Leader (Start End) 125 (typ) Empty Sealed P6 Carrier 250 Filled Sealed Trailer (Hub End} 75 (typ) Empty Sealed Leader (Start End} 125 (typ) Empty Sealed P6X Carrier 3000 Filled Sealed Trailer (Hub End) 75 (typ) Empty Sealed TAPE DIMENSIONS inches (millimeters) p82 oa-40 002 THR, S37 MAR ISR Y t (a bn r vo : z cal lected bee [1 520 05] | _ BP OT ak G7 TP | E 4 ddu.gb] | | vpn _ lle Ho a |b fit os : if ' Cp hp a 2 uw 7] ~ +P L.w wooA 7 | 4 4 : 6 | Pind? ed a SFCOTION R-B O RECTION OF FEEC e AT? +_+| 2 TANGENT POINTS 1 eayity wade SMM SECTION A-A B2NC RADIUS NOT TO SCALE Package Tape Size DIM A DIM B DIM F DIM K, DIM P1 DIM W 0.093 0.096 0.138 + 0.004 | 0.053 + 0.004 0.157 0.3154 0.004 8070-6 8mm (2.35) (2.45) (3.5+0.10) | (1.35+40.10) (4) (840.1) www fairchildsemi.comREEL DIMENSIONS inches (millimeters) TA&PE SLOT o b ro LI | DETAIL X DETAIL X | LL. We SCALE: 3X | . Wo Tape A B c D N W1 W2 W3 Size 8 7.0 0.059 | 0.512 | 0.795 | 2.165 |0.331+0.059/-0.000 0.567 W1 +0.078/-0.039 mm (177.8) | 1.50) | (13.00) | (20.20) | (55.00) | (@.40+ 1.50/-0.00) (14.40) (W1 + 2.00/-1.00) www-faicchildsemi.com ZLZMZONNC7W2Z17 TinyLogic UHS Dual Buffer with Schmitt Trigger Inputs Physical Dimensions inches (millimeters) unless otherwise noted oan aif oa CPE NPL P OMOLO PLAS. 6-Lead SC70, EIAJ SC88, 1.25mm Wide Package Number MAAQ6A LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. Accritical component in any component of a life support which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea- body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the lite support to perform when properly used in accordance with device or system, or to atfect its safety or effectiveness. instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the www.tairchildsemi.com user. Fairchidd does notassume any responsibility for use of any circuitry descnbed, no cicurt patert licenses are impled and Fairchild reserves the nght at any time without notice to change said circurtry and specications