1
ACPL-3130/J313 ACNW3130
Very High CMR 2.5 Amp Output Current
IGBT Gate Driver Optocoupler
Data Sheet
Features
• High speed response.
• Very high CMR.
• Bootstrappable supply current.
• Safety Approval (pending):
UL Recognized
- 3750 Vrms for 1 min. for ACPL-3130/J313.
- 5000 Vrms for 1 min. For ACNW3130
CSA Approval
IEC/EN/DIN EN 60747-5-2 Approved
- VIORM = 630 Vpeak for ACPL-3130 (Option 060)
- VIORM = 891 Vpeak for ACPL-J313
- VIORM = 1414 Vpeak for ACNW3130
Specications
• 2.5 A maximum peak output current.
• 2.0 A minimum peak output current.
• 40 kV/µs minimum Common Mode Rejection (CMR) at
VCM = 1500 V
• 0.5 V maximum low level output voltage (VOL) eliminates
need for negative gate drive
• ICC = 5 mA maximum supply current
• Under Voltage Lock-Out protection (UVLO) with
hysteresis
• Wide operating VCC range: 15 to 30 Volts
• 500 ns maximum switching speeds
• Industrial temperature range: -40°C to 100°C
Applications
• IGBT/MOSFET gate drive
• AC/Brushless DC motor drives
• Industrial inverters
• Switching Power Supplies (SPS)
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Description
The ACPL-3130 contains a GaAsP LED while the ACPL-
J313 and the ANCW3130 contain an AlGaAs LED. The LED
is optically coupled to an integrated circuit with a power
output stage. These optocouplers are ideally suited for
driving power IGBTs and MOSFETs used in motor control
inverter applications. The high operating voltage range
of the output stage provides the drive voltages required
by gate controlled devices. The voltage and current
supplied by these optocouplers make them ideally suited
for directly driving IGBTs with ratings up to 1200 V/100 A.
For IGBTs with higher ratings, the ACPL-3130 series can be
used to drive a discrete power stage which drives the IGBT
gate. The ANCW3130 has the highest insulation voltage of
VIORM = 1414 Vpeak in the IEC/EN/DIN EN 60747-5-2. The
ACPL-J313 has an insulation voltage of VIORM = 891 Vpeak
and the VIORM = 630 Vpeak is also available with the ACPL-
3130 (Option 060).
Functional Diagram
Note: A 0.1 µF bypass capacitor must be connected between pins VCC and VEE.
ACPL-3130 and ACPL-J313
ACNW3130
1
3
SHIELD
2
4
8
6
7
5
N/C
CATHODE
ANODE
N/C
V
CC
V
O
V
O
V
EE
1
3
SHIELD
2
4
8
6
7
5
N/C
CATHODE
ANODE
N/C
V
CC
N/C
V
O
V
EE
2
Package Outline Drawings
ACPL-3130 Outline Drawing (Standard DIP Package)
Ordering Information
Specify part number followed by option number (if desired).
Example:
Truth Table
LED
VCC – VEE
“POSITIVE GOING”
(i.e., TURN-ON)
VCC – VEE
“NEGATIVE GOING”
(i.e., TURN-OFF) VO
OFF 0 - 30 V 0 - 30 V LOW
ON 0 - 11 V 0 - 9.5 V LOW
ON 11 - 13.5 V 9.5 - 12 V TRANSITION
ON 13.5 - 30 V 12 - 30 V HIGH
ACPL-3130-XXXE
060 = IEC/EN/DIN EN 60747-5-2, VIORM = 630VPEAK (ACPL-3130 only)
300 = Gull Wing Surface Mount Option
500 = Tape and Reel Packaging Option
XXXE = Lead Free Option.
Option 500 contains 1000 units (ACPL-3130/J313), 750 units (ACNW3130) per reel.
Other options contain 50 units (ACPL-3130/J313), 42 units (ACNW3130) per tube
Option data sheets available. Contact Avago Technologies sales representative, authorized distributor, or visit our WEB
site at http://www.avagotech.com/optocouplers.
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
5 TYP. 0.254 + 0.076
- 0.051
(0.010 + 0.003)
- 0.002)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A XXXXZ
YYWW
DATE CODE
DIMENSIONS IN MILLIMETERS AND (INCHES).
5678
4321
OPTION CODE*
TYPE NUMBER
* MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
3.56 ± 0.13
(0.140 ± 0.005)
3
ACPL-3130 Gull Wing Surface Mount Option 300 Outline Drawing
ACPL-J313 Outline Drawing
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
5 TYP. 0.254 + 0.076
- 0.051
(0.010 + 0.003)
- 0.002)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
9.80 ± 0.25
(0.386 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
A XXXX
YYWW
DATE CODE
DIMENSIONS IN MILLIMETERS AND (INCHES).
5678
4321
TYPE NUMBER
OPTION NUMBERS 300 AND 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
3.56 ± 0.13
(0.140 ± 0.005)
0.635 ± 0.25
(0.025 ± 0.010) 12 ˚ NOM.
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.65 ± 0.25
(0.380 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
1.016 (0.040)
1.27 (0.050)
10.9 (0.430)
2.0 (0.080)
LAND PATTERN RECOMMENDATION
1.080 ± 0.320
(0.043 ± 0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
0.254 + 0.076
- 0.051
(0.010 + 0.003)
- 0.002)
4
ACPL-J313 Gull Wing Surface Mount Option 300 Outline Drawing
ACNW3130 Outline Drawing (8-Pin Wide Body Package)
5
6
7
8
4
3
2
1
11.15 ± 0.15
(0.442 ± 0.006)
1.78 ± 0.15
(0.070 ± 0.006)
5.10
(0.201) MAX.
1.55
(0.061)
MAX.
2.54 (0.100)
TYP. DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
7 TYP.
0.254 + 0.076
- 0.0051
(0.010 + 0.003)
- 0.002)
11.00
(0.433)
9.00 ± 0.15
(0.354 ± 0.006)
MAX.
10.16 (0.400)
TYP.
A
ACNWXXXX
YYWW
DATE CODE
TYPE NUMBER
0.51 (0.021) MIN.
0.40 (0.016)
0.56 (0.022)
3.10 (0.122)
3.90 (0.154)
0.635 ± 0.25
(0.025 ± 0.010) 12 ˚ NOM.
9.65 ± 0.25
(0.380 ± 0.010)
0.635 ± 0.130
(0.025 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.80 ± 0.25
(0.386 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
1.016 (0.040)
1.27 (0.050)
10.9 (0.430)
2.0 (0.080)
LAND PATTERN RECOMMENDATION
1.080 ± 0.320
(0.043 ± 0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
0.254 + 0.076
- 0.051
(0.010 + 0.003)
- 0.002)
5
Recommended Solder Reow Temperature Prole
Note: Use of non chlorine-activated uxes is highly recommended.
ACNW3130 Gull Wing Surface Mount Option 300 Outline Drawing
0
TIME (SECONDS)
TEMPERATURE ( °C)
200
100
50 150100 200 250
300
0
30
SEC.
50 SEC.
30
SEC.
160 °C
140 °C
150 °C
PEAK
TEMP.
245 °C
PEAK
TEMP.
240 °C
PEAK
TEMP.
230 °C
SOLDERING
TIME
200 °C
PREHEATING TIME
150 °C, 90 + 30 SEC.
2.5 °C ± 0.5 °C/SEC.
3 °C + 1 °C/–0.5 °C
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
PREHEATING RATE 3 °C + 1 C/–0.5 °C/SEC.
REFLOW HEATING RATE 2.5 °C ± 0.5 C/SEC.
6
Regulatory Information
The ACPL-3130/J313 and ACNW3130 are pending approval by the following organizations:
IEC/EN/DIN EN 60747-5-2 (ACPL-3130 Option 060 only, ACPL-J313 and ACNW3130)
Approval under:
IEC 60747-5-2 :1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01
UL
Approval under UL 1577, component recognition program, File E55361.
CSA
Approval under CSA Component Acceptance Notice #5, File CA 88324.
Recommended Pb-Free IR Prole
Note: Use of non chlorine-activated uxes is highly recommended.
217 °C
RAMP-DOWN
6 °C/SEC. MAX.
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
260 +0/-5 °C
t 25 C to PEAK
60 to 150 SEC.
15 SEC.
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
tp
ts
PREHEAT
60 to 180 SEC.
tL
TL
Tsmax
Tsmin
25
Tp
TIME
TEMPERATURE
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
7
Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*
Description Symbol ACPL-3130 Option 060 ACPL-J313 ACNW3130 Unit
Installation classication per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms I – IV I – IV I – IV
for rated mains voltage ≤ 300 Vrms I – IV I – IV I – IV
for rated mains voltage ≤ 450 Vrms I – III I – III I – IV
for rated mains voltage ≤ 600 Vrms I – III I – IV
for rated mains voltage ≤ 1000 Vrms I – III
Climatic Classication 55/100/21 55/100/21 55/100/21
Pollution Degree (DIN VDE 0110/1.89) 2 2 2
Maximum Working Insulation Voltage VIORM 630 891 1414 Vpeak
Input to Output Test Voltage, Method b* VIORM x 1.875=VPR,
100% Production Test with tm=1 sec, Partial discharge < 5 pC
VPR 1181 1670 2652 Vpeak
Input to Output Test Voltage, Method a* VIORM x 1.5=VPR,
Type and Sample Test, tm=60 sec, Partial discharge < 5 pC
VPR 945 1336 2121 Vpeak
Highest Allowable Overvoltage
(Transient Overvoltage tini = 10 sec)
VIOTM 6000 6000 8000 Vpeak
Safety-limiting values – maximum values allowed in the event of a failure, also see Figure 41 and 42.
Case Temperature TS175 175 150 °C
Input Current IS, INPUT 230 400 400 mA
Output Power PS, OUTPUT 600 600 700 mW
Insulation Resistance at TS, VIO = 500 V RS>109>109>109W
* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/DIN
EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test proles.
Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by
means of protective circuits. Surface mount classication is Class A in accordance with CECC 00802.
Table 2. Insulation and Safety Related Specications
Parameter Symbol ACPL-3130 ACPL-J313 ACNW3130 Units Conditions
Minimum External Air Gap
(Clearance)
L(101) 7.1 7.4 9.6 mm Measured from input terminals to output terminals,
shortest distance through air.
Minimum External Tracking
(Creepage)
L(102) 7.4 8.0 10.0 mm Measured from input terminals to output terminals,
shortest distance path along body.
Minimum Internal Plastic
Gap (Internal Clearance)
0.08 0.5 1.0 mm Through insulation distance conductor to conductor,
usually the straight line distance thickness between
the emitter and detector.
Tracking Resistance (Com-
parative Tracking Index)
CTI > 175 > 175 > 200 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa IIIa IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting
point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum
creepage and clearance requirements must be met as specied for individual equipment standards. For creepage, the shortest distance path along
the surface of a printed circuit board between the solder llets of the input and output leads must be considered. There are recommended techniques
such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances
will also change depending on factors such as pollution degree and insulation level.
8
Table 3. Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Note
Storage Temperature TS-55 125 °C
Operating Temperature TA-40 100 °C
Average Input Current IF(AVG) 25 mA 1
Peak Transient Input Current
(<1 µs pulse width, 300pps)
IF(TRAN) 1.0 A
Reverse Input Voltage ACPL-3130 VR5 V
ACPL-J313 3 V
ACNW3130 3 V
“High” Peak Output Current IOH(PEAK) 2.5 A 2
“Low” Peak Output Current IOL(PEAK) 2.5 A 2
Supply Voltage VCC – VEE 0 35 V
Input Current (Rise/Fall Time) tr(IN) /tf(IN) 500 ns
Output Voltage VO(PEAK) 0 VCC V
Output Power Dissipation PO250 mW 3
Total Power Dissipation PT295 mW 4
Lead Solder Temperature ACPL-3130 260°C for 10 sec., 1.6 mm below seating plane
ACPL-J313
ACNW3130 260°C for 10 sec., up to seating plane
Solder Reow Temperature Prole See Package Outline Drawings section
Table 4. Recommended Operating Conditions
Parameter Symbol Min. Max. Units Note
Power Supply VCC - VEE 15 30 V
Input Current (ON) ACPL-3130 IF(ON) 7 16 mA
ACPL-J313
ACNW3130 10 10 mA
Input Voltage (OFF) VF(OFF) - 3.0 0.8 V
Operating Temperature TA- 40 100 °C
9
Table 5. Electrical Specications (DC)
Over recommended operating conditions (TA = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V, VCC = 15 to 30 V,
VEE = Ground) unless otherwise specied. All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
Parameter Symbol Device Min. Typ. Max. Units Test Conditions Fig. Note
High Level Output Current IOH 0.5 1.5 A VO = VCC – 4 2, 3, 21 5
2.0 A VO = VCC – 15 2
Low Level Output Current IOL 0.5 2.0 A VO = VEE + 2.5 5, 6, 22 5
2.0 A VO = VEE + 15 2
High Level Output Voltage VOH VCC-4 VCC-3 V IO = -100 mA 1, 3, 23 6, 7
Low Level Output Voltage VOL 0.1 0.5 V IO = 100 mA 4, 6, 24
High Level Supply Current ICCH 2.5 5.0 mA Output open,
IF = 7 to 16 mA
7, 8
Low Level Supply Current ICCL 2.5 5.0 mA Output open,
VF = -3.0 to +0.8 V
Threshold Input Current
Low to High
IFLH ACPL-3130 2.3 5.0 mA IO = 0 mA, VO > 5 V 9, 17, 25
ACPL-J313 1.0 5.0 mA IO = 0 mA, VO > 5 V 10, 18, 25
ACNW3130 2.3 8.0 mA IO = 0 mA, VO > 5 V 11, 17, 25
Threshold Input Voltage
High to Low
VFHL 0.8 V IO = 0 mA, VO > 5 V
Input Forward Voltage VFACPL-3130 1.2 1.5 1.8 V IF = 10 mA 19
ACPL-J313 1.2 1.6 1.95 V IF = 10 mA 20
ACNW3130 1.2 1.6 1.95 V IF = 10 mA 20
Temperature Coecient of
Input Forward Voltage
DVF/DTAACPL-3130 -1.6 mV/°C IF = 10 mA
ACPL-J313 -1.3 mV/°C IF = 10 mA
ACNW3130 -1.3 mV/°C IF = 10 mA
Input Reverse Breakdown Voltage BVRACPL-3130 5 V IR = 10 µA
ACPL-J313 3 V IR = 100 µA
ACNW3130 3 V IR = 100 µA
Input Capacitance CIN ACPL-3130 60 pF f = 1 MHz, VF = 0 V
ACPL-J313 70 pF f = 1 MHz, VF = 0 V
ACNW3130 70 pF f = 1 MHz, VF = 0 V
UVLO Threshold VUVLO+ 11.0 12.3 13.5 V IF = 10 mA, VO > 5 V 26, 38
VUVLO– 9.5 10.7 12.0 V IF = 10 mA, VO > 5 V 26, 38
UVLO Hysteresis UVLOHYS 1.6 V IF = 10 mA, VO > 5 V 26, 38
10
Table 6. Switching Specications (AC)
Over recommended operating conditions (TA = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.0 to 0.8 V, VCC = 15 to 30 V,
VEE = Ground) unless otherwise specied. All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Propagation Delay Time to High Output Level tPLH 0.10 0.30 0.50 µs Rg = 10 W,
Cg = 10 nF,
f = 10 kHz,
Duty Cycle = 50%
12,13,
14, 15,
16, 27
16
Propagation Delay Time to Low Output Level tPHL 0.10 0.30 0.50 µs
Pulse Width Distortion PWD 0.3 µs 17
Propagation Delay Dierence Between Any Two Parts
or Channels
PDD
(tPHL – tPLH) -0.35 0.35 µs 39, 40 12
Rise Time tR0.1 µs 27
Fall Time tF0.1 µs
UVLO Turn On Delay tUVLO ON 0.8 µs IF = 10 mA, VO > 5 V 26
UVLO Turn O Delay tUVLO OFF 0.6 µs IF = 10 mA, VO > 5 V 26
Output High Level Common Mode Transient Immunity |CMH| 40 50 kV/µs TA = 25°C,
IF = 10 to 16 mA,
VCM = 1500 V
VCC = 30 V
27 13, 14
Output Low Level Common Mode Transient Immunity |CML| 40 50 kV/µs TA = 25°C, VF = 0 V,
VCM = 1500 V
VCC = 30 V
27 13, 15
Table 7. Package Characteristics
Over recommended temperature (TA = -40 to 100°C) unless otherwise specied. All typicals at TA = 25°C.
Parameter Symbol Device Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary Withstand
Voltage**
VISO ACPL-3130 3750 Vrms RH < 50%,
t = 1 min.,
TA = 25°C
8, 11
ACPL-J313 3750 Vrms 9, 11
ACNW3130 5000 Vrms 10, 11
Resistance Input-Output) RI-O ACPL-3130 1012 WVI-O = 500 V 11
ACPL-J313 1012 WVI-O = 500 V
ACNW3130 1012 1013 WVI-O = 500 V,
TA = 25°C
1011 WVI-O = 500 V,
TA = 100°C
Capacitance Input-Output) CI-O ACPL-3130 0.6 pF Freq=1 MHz
ACPL-J313 0.8 pF Freq=1 MHz
ACNW3130 0.5 0.6 pF Freq=1 MHz
LED-to-Case Thermal Resistance qLC 467 °C/W Thermocouple
located at center
underside of package
32
LED-to-Detector Thermal Resistance qLD 442 °C/W 32
Detector-to-Case Thermal Resistance qDC 126 °C/W 32
** The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For
the continuous voltage rating refer to your equipment level safety specication or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance
Voltage.”
11
Figure 1. VOH vs. Temperature.
Notes:
1. Derate linearly above 70° C free-air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak
minimum = 2.0 A. See Applications section for additional details on limiting IOH peak.
3. Derate linearly above 70° C free-air temperature at a rate of 4.8 mW/°C.
4. Derate linearly above 70° C free-air temperature at a rate of 5.4 mW/°C. The maximum LED junction temperature should not exceed 125°C.
5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
6. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V≥ 4500 V 4500 Vrms for 1 second (leakage detection
current limit, II-O ≤ 5 µA).≤ 5 µA). 5 µA).
9. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V≥ 4500 V 4500 Vrms for 1 second (leakage detection
current limit, II-O ≤ 5 µA).≤ 5 µA). 5 µA).
10. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V≥ 6000 V 6000 Vrms for 1 second (leakage detection
current limit, II-O ≤ 5 µA).≤ 5 µA). 5 µA).
11. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
12. The dierence between tPHL and tPLH between any two ACPL-3130, ACPL-J313 or ACNW3130 parts under the same test condition.
13. Pins 1 and 4 need to be connected to LED common.
14. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in the high state (i.e., VO > 15.0 V).
15. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e., VO < 1.0 V).
16. This load condition approximates the gate load of a 1200 V/75A IGBT.
17. Pulse Width Distortion (PWD) is dened as |tPHL - tPLH| for any given device.
Figure 3. VOH vs. IOH.Figure 2. IOH vs. Temperature.
Figure 4. VOL vs. Temperature.
(V
OH
- V
CC
) - HIGH OUTPUT VOLTAGE DROP - V
-40
-4
T
A
- TEMPERATURE - °C
100
-1
-2
-20
0
0 2 0 40
-3
60 80
I
F
= 7 to 16 mA
I
OUT
= -100 mA
V
CC
= 15 to 30 V
V
EE
= 0 V
I
OH
- OUTPUT HIGH CURRENT - A
-40
1.0
T
A
- TEMPERATURE - °C
100
1.8
1.6
-20
2.0
0 2 0 40
1.2
60 80
I
F
= 7 to 16 mA
V
OUT
= (V
CC
- 4 V)
V
CC
= 15 to 30 V
V
EE
= 0 V
1.4
(V
OH
- V
CC
) - OUTPUT HIGH VOLTAGE DROP - V
0
-6
I
OH
- OUTPUT HIGH CURRENT - A
2.5
-2
-3
0.5
-1
1.0 1.5
-5
2.0
I
F
= 7 to 16 mA
V
CC
= 15 to 30 V
V
EE
= 0 V
-4
100
°
C
25
°
C
-40
°
C
VOL - OUTPUT LOW VOLTAGE - V
-40
0
T
A
- TEMPERATURE - °C
-20
0.25
0 2 0
0.05
100
0.15
0.20
0.10
40 60 80
V
F
(OFF) = -3.0 TO 0.8 V
I
OUT
= 100 mA
V
CC
= 15 TO 30 V
V
EE
= 0 V
IOL - OUTPUT LOW CURRENT - A
-40
0
T
A
- TEMPERATURE - °C
-20
4
0 2 0
1
100
2
3
40 60 80
V
F
(OFF) = -3.0 TO 0.8 V
V
OUT
= 2.5 V
V
CC
= 15 TO 30 V
V
EE
= 0 V
VOL - OUTPUT LOW VOLTAGE - V
0
0
I
OL
- OUTPUT LOW CURRENT - A
2.5
3
0.5
4
1.0 1.5
1
2.0
V
F(OFF)
= -3.0 to 0.8 V
V
CC
= 15 to 30 V
V
EE
= 0 V
2
100
°
C
25
°
C
-40
°
C
Figure 5. IOL vs. Temperature. Figure 6. VOL vs. IOL.
12
Figure 11. IFLH vs. Temperature. (ACNW3130) Figure 12. Propagation Delay vs. VCC.
Figure 13. Propagation Delay vs. IF. Figure 14. Propagation Delay vs. Temperature. Figure 15. Propagation Delay vs. Rg.
Figure 8. ICC vs. VCC.Figure 7. ICC vs. Temperature. Figure 9. IFLH vs. Temperature. (ACPL-3130)
Figure 10. IFLH vs. Temperature. (ACPL-J313)
I
CC
- SUPPLY CURRENT - mA
-40
1.5
T
A
- TEMPERATURE - °C
100
3.0
2.5
-20
3.5
0 2 0 40
2.0
60 80
V
CC
= 30 V
V
EE
= 0 V
I
F
= 10 mA for I
CCH
I
F
= 0 mA for I
CCL
I
CCH
I
CCL
I
CC
- SUPPLY CURRENT - mA
15
1.5
V
CC
- SUPPLY VOLTAGE - V
30
3.0
2.5
3.5
20
2.0
25
I
F
= 10 mA for I
CCH
I
F
= 0 mA for I
CCL
T
A
= 25 °C
V
EE
= 0 V
I
CCH
I
CCL
I
FLH
- LOW TO HIGH CURRENT THRESHOLD - mA
-40
0
T
A
- TEMPERATURE - °C
100
3
2
-20
4
0 2 0 40
1
60 80
5
V
CC
= 15 TO 30 V
V
EE
= 0 V
OUTPUT = OPEN
I
FLH
- LOW TO HIGH CURRENT THRESHOLD - mA
-40
0
T
A
- TEMPERATURE - °C
-20
5
0 2 0
1
100
2
3
40 60 80
V
CC
= 15 TO 30 V
V
EE
= 0 V
OUTPUT = OPEN
4
IFLH - LOW TO HIGH CURRENT THRESHOLD - mA
-40
0
TA - TEMPERATURE - ° C
-20
5
0 2 0
1
100
2
3
40 60 80
VCC = 15 TO 30 V
VEE = 0 V
OUTPUT = OPEN
4
Tp - PROPAGATION DELAY - ns
15
100
V
CC
- SUPPLY VOLTAGE - V
30
400
300
500
20
200
25
I
F
= 10 mA
T
A
= 25 °C
Rg = 10 �
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
T
PLH
T
PHL
T
p
- PROPAGATION DELAY - ns
6
100
I
F
- FORWARD LED CURRENT - mA
16
400
300
500
10
200
12
V
CC
= 30 V, V
EE
= 0 V
Rg = 10 Ω, Cg = 10 nF
T
A
= 25 °C
DUTY CYCLE = 50%
f = 10 kHz
T
PLH
T
PHL
148
Tp - PROPAGATION DELAY - ns
-40
100
TA - TEMPERATURE - °C
100
400
300
-20
500
0 2 0 40
200
60 80
TPLH
TPHL
IF = 10 mA
VCC = 30 V, V EE = 0 V
Rg = 10 Ω, Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
T
p
- PROPAGATION DELAY - ns
0
100
Rg - SERIES LOAD RESISTANCE - Ω
50
400
300
10
500
30
200
40
T
PLH
T
PHL
V
CC
= 30 V, V
EE
= 0 V
T
A
= 25 °C
I
F
= 10 mA
Cg = 10 nF
DUTY CYCLE = 50%
f = 10 kHz
20
13
Figure 17. Transfer Characteristics (ACPL-3130 /
ACNW3130)
Figure 18. Transfer Characteristics (ACPL-J313)
Figure 19. IF vs. VF. (ACPL-3130) Figure 20. IF vs. VF. (ACPL-J313 / ACNW3130)
Figure 21. IOH Test Circuit.
Figure 22. IOL Test Circuit.
Figure 16. Propagation Delay vs. Cg.
T
p
- PROPAGATION DELAY - ns
0
100
Cg - LOAD CAPACITANCE - nF
100
400
300
20
500
40
200
60 80
T
PLH
T
PHL
V
CC
= 30 V, V
EE
= 0 V
T
A
= 25 °C
I
F
= 10 mA
Rg = 10 �
DUTY CYCLE = 50%
f = 10 kHz
VO - OUTPUT VOLTAGE - V
0
0
IF - FORWARD LED CURRENT - mA
5
25
15
1
30
2
5
3 4
20
10
V
O
- OUTPUT VOLTAGE - V
0
0
I
F
- FORWARD LED CURRENT - mA
1
35
2
5
5
15
25
3 4
10
20
30
I
F
- FORWARD CURRENT - mA
1.10
0.001
VF - FORWARD VOLTAGE - VOLTS
1.60
10
1.0
0.1
1.20
1000
1.30 1.40 1.50
TA = 25°C
IF
VF
+
-
0.01
100
VF - FORWARD VOLTAGE - VOLTS
1.2 1.3 1.4 1.5
I
F
- FORWARD CURRENT - mA
1.71.6
1.0
IF
+
TA = 25°C
-
VF
0.1
0.01
0.001
10
100
1000
0.1 µF
V
CC
= 15
to 30 V
1
3
I
F
= 7 to
16 mA +
−
2
4
8
6
7
5
+
−
4 V
I
OH
0.1 µF
VCC = 15
to 30 V
1
3
+
-
2
4
8
6
7
5
2.5 V
IOL
+
-
14
Figure 23. VOH Test Circuit. Figure 24. VOL Test Circuit.
Figure 25. IFLH Test Circuit. Figure 26. UVLO Test Circuit.
Figure 27. tPLH, tPHL, tr, and tf Test Circuit and Waveforms.
Figure 28. CMR Test Circuit and Waveforms.
0.1 µF
V
CC
= 15
to 30 V
1
3
IF = 7 to
16 mA +
Ð
2
4
8
6
7
5
100 mA
V
OH
0.1 µF
V
CC
= 15
to 30 V
1
3
+
-
2
4
8
6
7
5
100 mA
V
OL
0.1 µF
V
CC
= 15
to 30 V
1
3
I
F
+
-
2
4
8
6
7
5
V
O
> 5 V
0.1 µF
V
CC
1
3
I
F
= 10 mA +
-
2
4
8
6
7
5
V
O
> 5 V
0.1 µF V
CC
= 15
to 30 V
10
Ω
1
3
I
F
= 7 to 16 mA
V
O
+
-
+
-
2
4
8
6
7
5
10 KHz
50% DUTY
CYCLE
500
Ω
10 nF
I
F
V
OUT
t
PHL
t
PLH
t
f
t
r
10%
50%
90%
0.1 µF
V
CC
= 30 V
1
3
I
F
V
O
+
-
+
-
2
4
8
6
7
5
A
+
-
B
V
CM
= 1500 V
5 V
V
CM
∆t
0 V
V
O
SWITCH AT B: I
F
= 0 mA
V
O
SWITCH AT A: I
F
= 10 mA
V
OL
V
OH
�t
V
CM
∆V
∆t
=
15
Applications Information
Eliminating Negative IGBT Gate Drive (Discussion applies to
ACPL-3130, ACPL-J313, and ACNW3130)
To keep the IGBT rmly o, the ACPL-3130 has a very
low maximum VOL specication of 0.5 V. The ACPL-3130
realizes this very low VOL by using a DMOS transistor
with 1 W (typical) on resistance in its pull down circuit.
When the ACPL-3130 is in the low state, the IGBT gate is
shorted to the emitter by Rg + 1 W. Minimizing Rg and
the lead inductance from the ACPL-3130 to the IGBT gate
and emitter (possibly by mounting the ACPL-3130 on a
small PC board directly above the IGBT) can eliminate the
need for negative IGBT gate drive in many applications as
shown in Figure 29. Care should be taken with such a PC
board design to avoid routing the IGBT collector or emitter
traces close to the ACPL-3130 input as this can result in
unwanted coupling of transient signals into the ACPL-
3130 and degrade performance. (If the IGBT drain must
be routed near the ACPL-3130 input, then the LED should
be reverse-biased when in the o state, to prevent the
transient signals coupled from the IGBT drain from turning
on the ACPL-3130.)
Figure 29. Recommended LED Drive and Application Circuit.
Selecting the Gate Resistor (Rg) to Minimize IGBT Switching
Losses. (Discussion applies to ACPL-3130, ACPL-J313 and
ACNW3130)
Step 1: Calculate Rg minimum from the IOL peak specication. The
IGBT and Rg in Figure 30 can be analyzed as a simple RC circuit
with a voltage supplied by the ACPL-3130.
The VOL value of 2 V in the previous equation is a
conservative value of VOL at the peak current of 2.5A (see
Figure 6). At lower Rg values the voltage supplied by the
ACPL-3130 is not an ideal voltage step. This results in
lower peak currents (more margin) than predicted by this
analysis. When negative gate drive is not used VEE in the
previous equation is equal to zero volts.
Figure 30. ACPL-3130 Typical Application Circuit with Negative IGBT Gate Drive.
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF V
CC
= 18 V
1
3
+
-
2
4
8
6
7
5
270 �
+5 V
CONTROL
INPUT
Rg
Q1
Q2
74XXX
OPEN
COLLECTOR
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF V
CC
= 15 V
1
3
+
-
2
4
8
6
7
5
Rg
Q1
Q2
V
EE
= -5 V
-
+
270 Ω
+5 V
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
==
−+
=
−−
≥
8Ω7.2Ω
2.5
2515
I
VVV
R
OLPEAK
OLEECC
g
∼
16
Step 2: Check the ACPL-3130 Power Dissipation and Increase Rg if
Necessary. The ACPL-3130 total power dissipation (PT) is equal to
the sum of the emitter power (PE) and the output power (PO):
For the circuit in Figure 30 with IF (worst case) = 16 mA, Rg
= 8 W, Max Duty Cycle = 80%, Qg = 500 nC, f = 20 kHz and
TA max = 85˚C:
PE Parameter Description
IFLED Current
VFLED On Voltage
Duty Cycle Maximum LED Duty Cycle
PO Parameter Description
ICC Supply Current
VCC Positive Supply Voltage
VEE Negative Supply Voltage
ESW(Rg,Qg) Energy Dissipated in the ACPL-3130 for each IGBT
Switching Cycle (See Figure 31)
f Switching Frequency
Figure 31. Energy Dissipated in the ACPL-3130 for Each IGBT Switching
Cycle.
The value of 4.25 mA for ICC in the previous equation was
obtained by derating the ICC max of 5 mA (which occurs at
-40°C) to ICC max at 85˚C (see Figure 7).
Since PO for this case is greater than PO(MAX), Rg must be
increased to reduce the ACPL-3130 power dissipation.
For Qg = 500 nC, from Figure 31, a value of ESW = 4.65 µW
gives a Rg = 10.3 Ω.
Esw - ENERGY PER SWITCHING CYCLE - µJ
0
0
Rg - GATE RESISTANCE - Ω
50
6
10
14
20
4
30 40
12
Qg = 100 nC
Qg = 500 nC
Qg = 1000 nC
10
8
2
V
CC
= 19 V
V
EE
= -9 V
( )
fQ;REVIPPP
DutyCycle
VIP
PPP
ggSWCCCCG)O(SWITCHINO(BIAS)O
FFE
OET
+=+=
=
+=
••
••
( ) ( ) ( )
93mW
85mW178mW
P-PP BIASOMAXOMAX SWITCHINGO
=
=
=
( )
( )
µW65.4
20kHz
93mW
P
EMAX SWITCHINGO
MAX SW
==
=f
-
( )
(CmW/8.4C15-250mWC@85PmW178
mW189
mW104mW85
20kHzµJ2.5V204.25mAP
23mW0.81.8V16mAP
MAX
O
O
E
°°=°>
=
+=
+=
== ••
••
)
•
17
Thermal Model
(Discussion applies to ACPL-3130, ACPL-J313 and ACNW3130)
Figure 32. Thermal Model.
The steady state thermal model for the ACPL-3130 is
shown in Figure 32. The thermal resistance values given
in this model can be used to calculate the temperatures
at each node for a given operating condition. As shown
by the model, all heat generated ows through qCA which
raises the case temperature TC accordingly. The value of
qCA depends on the conditions of the board design and is,
therefore, determined by the designer. The value of qCA =
83°C/W was obtained from thermal measurements using a
2.5 x 2.5 inch PC board, with small traces (no ground plane),
a single ACPL-3130 soldered into the center of the board
and still air. The absolute maximum power dissipation
derating specications assume a qCA value of 83°C/W.
From the thermal mode in Figure 32 the LED and detector
IC junction temperatures can be expressed as:
TJE = LED junction temperature
TJD = detector IC junction temperature
TC = case temperature measured at the center of the
package bottom
qLC = LED-to-case thermal resistance
qLD = LED-to-detector thermal resistance
qDC = detector-to-case thermal resistance
qCA = case-to-ambient thermal resistance
*qCA will depend on the board design and the placement
of the part.
Inserting the values for qLC and qDC shown in Figure 32
gives:
For example, given PE = 45 mW, PO = 250 mW, TA = 70°C
and qCA = 83°C/W:
TJE and TJD should be limited to 125°C based on the
board layout and part placement (qCA) specic to the
application
�
LD
= 442 °C/W
T
JE
T
JD
θ
LC
= 467 °C/W θ
DC
= 126 °C/W
θ
CA
= 83 °C/W*
T
C
T
A
θ
( )
( )
( )( )
ACA
LDDCLC
DCLC
DCADCLDLCEJE Tθ
θθθ
θθ
Pθθθ||θPT ++
++
+++=
( )
(
ACALCLDDCDCA
LDDCLC
DCLC
EJD Tθθθ||θPθ
θθθ
θ
θ
PT +++++
++
=
)
••
•
•
•
•
( ) ( )
ACADCAEJE TθC/W57PθC/W256PT ++°++°=
( ) ( )
ACADCAEJD TθC/W111PθC/W57PT ++°++°=
•
•
•
•
C120C70C/W140250C/W33945mW
TC/W140PC/W339PT ADEJE
°=°+°+°=
+°+°=
mW
C70C/W194250C/W14045
TC/W194PC/W140PT ADEJD
°+°+°=
+°+°=
mWmW
• •
•
•
•
•
••
18
Figure 36. Not Recommended Open Collector Drive Circuit.
The open collector drive circuit, shown in Figure 36,
cannot keep the LED o during a +dVcm/dt transient, since
all the current owing through CLEDN must be supplied
by the LED, and it is not recommended for applications
requiring ultra high CMRL performance. Figure 37 is an
alternative drive circuit which, like the recommended
application circuit (Figure 29), does achieve ultra high CMR
performance by shunting the LED in the o state.
Figure 35. Equivalent Circuit for Figure 29 During Common Mode Tran-
sient.
CMR with the LED On (CMRH)
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriving
the LED current beyond the input threshold so that it is not
pulled below the threshold during a transient. A minimum
LED current of 10 mA provides adequate margin over the
maximum IFLH of 5 mA to achieve 40 kV/μs CMR.
CMR with the LED O (CMRL)
A high CMR LED drive circuit must keep the LED o (VF
≤ VF(OFF)) during common mode transients. For example,
during a -dVcm/dt transient in Figure 35, the current
owing through CLEDP also ows through the RSAT and
VSAT of the logic gate. As long as the low state voltage
developed across the logic gate is less than VF(OFF), the LED
will remain o and no common mode failure will occur.
Figure 34. Optocoupler Input to Output Capacitance Model for Shielded
Optocouplers.
Figure 33. Optocoupler Input to Output Capacitance Model for Unshield-
ed Optocouplers.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
C
LEDO1
C
LEDO2
Rg
1
3
V
SAT
2
4
8
6
7
5
+
V
CM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING - dV
CM
/dt.
+5 V
+
-V
CC
= 18 V
¥ ¥ ¥
¥ ¥ ¥
0.1
µF
+
-
-
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1
I
LEDN
LED Drive Circuit Considerations for Ultra High CMR Per-
formance. (Discussion applies to ACPL-3130, ACPL-J313,
and ACNW3130)
Without a detector shield, the dominant cause of
optocoupler CMR failure is capacitive coupling from the
input side of the optocoupler, through the package, to the
detector IC as shown in Figure 33. The ACPL-3130 improves
CMR performance by using a detector IC with an optically
transparent Faraday shield, which diverts the capacitively
coupled current away from the sensitive IC circuitry.
However, this shield does not eliminate the capacitive
coupling between the LED and optocoupler pins 5-8
as shown in Figure 34. This capacitive coupling causes
perturbations in the LED current during common mode
transients and becomes the major source of CMR failures
for a shielded optocoupler. The main design objective of a
high CMR LED drive circuit becomes keeping the LED in the
proper state (on or o) during common mode transients.
For example, the recommended application circuit
(Figure 29), can achieve 40 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in the proper state are dis-
cussed in the next two sections.
19
Figure 39. Minimum LED Skew for Zero Dead Time.
Figure 38. Under Voltage Lock Out.
Under Voltage Lockout Feature. (Discussion applies to
ACPL-3130, ACPL-J313, and ACNW3130)
The ACPL-3130 contains an under voltage lockout (UVLO)
feature that is designed to protect the IGBT under fault
conditions which cause the ACPL-3130 supply voltage
(equivalent to the fully-charged IGBT gate voltage) to
drop below a level necessary to keep the IGBT in a low
resistance state. When the ACPL-3130 output is in the high
state and the supply voltage drops below the ACPL-3130
VUVLO– threshold (9.5 < VUVLO– < 12.0) the optocoupler
output will go into the low state with a typical delay, UVLO
Turn O Delay, of 0.6 µs.
When the ACPL-3130 output is in the low state and the
supply voltage rises above the ACPL-3130 VUVLO+ threshold
(11.0 < VUVLO+ < 13.5) the optocoupler output will go into
the high state (assumes LED is “ON”) with a typical delay,
UVLO Turn On Delay of 0.8 µs.
Dead Time and Propagation Delay Specications. (Discus-
sion applies to ACPL-3130, ACPL-J313, and ACNW3130)
The ACPL-3130 includes a Propagation Delay Dierence
(PDD) specication intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 29) are o.
Any overlap in Q1 and Q2 conduction will result in large
currents owing through the power devices between the
high and low voltage motor rails.
Figure 37. Recommended LED Drive Circuit for Ultra-High CMR.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn o of LED1)
so that under worst-case conditions, transistor Q1 has just
turned o when transistor Q2 turns on, as shown in Figure
35. The amount of delay necessary to achieve this condition
is equal to the maximum value of the propagation delay
dierence specication, PDDMAX, which is specied to be
350 ns over the operating temperature range of -40°C to
100°C.
Delaying the LED signal by the maximum propagation
delay dierence ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the dierence between the maximum and minimum
propagation delay dierence specications as shown in
Figure 40. The maximum dead time for the ACPL-3130 is
700 ns (= 350 ns - (-350 ns)) over an operating temperature
range of - 40°C to 100°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other and
are switching identical IGBTs.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
V
O
- OUTPUT VOLTAGE - V
0
0
(V
CC
- V
EE
) - SUPPLY VOLTAGE - V
10
5
14
10 15
2
20
6
8
4
12
(12.3, 10.8)
(10.7, 9.2)
(10.7, 0.1) (12.3, 0.1)
tPHL MAX
tPLH MIN
PDD* MAX = (t PHL - tPLH )MAX = t PHL MAX - tPLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
VOUT1
ILED2
VOUT2
ILED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
Figure 41. Thermal Derating Curve, Dependence of Safety Limiting Value
with Case Temperature per IEC/EN/DIN EN 60747-5-2 for ACPL-3130 (op-
tion 060) and ACPL-J313.
Figure 42. Thermal Derating Curve, Dependence of Safety Limiting Value
with Case Temperature per IEC/EN/DIN EN 60747-5-2 for ACNW3130.
Figure 40. Waveforms for Dead Time.
tPLH
MIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t PHL MAX - tPHL MIN ) + (t PLH MAX - tPLH MIN )
= (t PHL MAX - tPLH MIN ) - (t PHL MIN - tPLH MAX )
= PDD* MAX - PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
VOUT1
ILED2
VOUT2
ILED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
tPHL MIN
tPHL MAX
tPLH MAX
PDD* MAX
(t PHL- tPLH ) MAX
OUTPUT POWER - P
S
, INPUT CURRENT - I
S
0
0
T
S
- CASE TEMPERATURE - °C
200
600
400
25
800
50 75 100
200
150 175
P
S
(mW)
125
100
300
500
700 I
S
(mA) FOR ACPL-3130
OPTION 060
I
S
(mA) FOR ACPL-J313
OUTPUT POWER - P
S
, INPUT CURRENT - I
S
0
0
T
S
- CASE TEMPERATURE - °C
175
1000
50
400
12525 75 100 150
600
800
200
100
300
500
700
900 P
S
(mW)
I
S
(mA)
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited, in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies, Limited. All rights reserved. Obsoletes AV01-0461EN
AV01-0630EN - November 1, 2006