ADV MICRO PLA/PLE/ARRAYS 26E COML MIL PAL22V10-10/15 AmPAL22V10/A PALCE22V10H-15/25/Q-25 24-pin TTL/CMOS Versatile PAL Device D MM 0257526 029555 3 BMAND2 T-46-19-07 PY ~46~-19-13 Advanced Micro Devices DISTINCTIVE CHARACTERISTICS @ As fast as 10 ns propagation delay and 71 MHz tax M Low-power EE CMOS versions @ 10 macrocells programmable as registered or combinatorial, and active high or active low to match application needs @ Varied product term distribution allows up to 16 product terms per output for complex functions @ = =Global asynchronous reset and synchronous preset for Initialization Mm Power-up reset for Initialization and register preload for testabllity @ Easy design with PALASM software @ Programmable on standard PAL device programmers M 24-pin SKINNYDIP and 28-pin PLCC packages save space GENERAL DESCRIPTION The PAL22V10 provides user-programmable logic for replacing conventional SS!/MSI gates and flip-flops at a reduced chip count. The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. The product terms are connected to the fixed OR array with a varied distribution from 8 {016 across the outputs BLOCK DIAGRAM CLKilg (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be pro- grammed as registered or combinatorial, and active high or active ow. The output configuration is deter- mined by two fuses controlling two multiplexers in each macrocell. The entire PAL device family is supported by the PALASM software package. The PAL family is pro- grammed ori conventional PAL device programmers with appropriate personality and socket adapter mod- ules. See the Programmer Reference Guide for ap- proved programmers. heli. PROGRAMMABLE AND ARRAY V (44 x 132) AESET PRESET Oo vO; voz Oy VOq vOs vO? (Os VO, 18003-001A PAL, PALASM, and SKINNYOIP are registered trademarks of Advanced Micro Devices. This part is covered by various U.S. and foraign patents owned by Advanced Micro Devices. Publication # 14004 Rev. A Amandment 0 Issue Date: February 1990 2-237ADV MICRO PLA/PLE/ARRAYS es D MM O0e2575e6b O0e9556 5 MBAND2 PERFORMANCE OPTIONS Fea Commercial ~46] 9-07 . See T-46-19-13 35 Std M (pp, NS) 45 Gos 15 10 -10 90 180 Power (Icc, mA) OPERATING RANGES Commercial Military -10 -15 15 -20 A (25 ns) A (30 ns) Std (35 ns) Std (40 ns) H-15 H-25 H-25 H-30 Q-25 2-238 PAL22V10ADV MICRO PLA/PLE/ARRAYS 2C8E D MM O02575eb 002555? 7? MANDA CONNECTION DIAGRAMS OY Top View T~46-19-07 SKINNYDIP/FLATPACK PLCC/LCC - NS CLKMo[] 1 241] Vcc s ge 86 iQ 2 23 1] VO. a 2a $SQeQ bE} 3 22 {] vos L438 128 27 36 -\ is] 4 21] vo, VO7 taQ} 5 20 1] Vs Vs: isQ6 19 [] vos lef] 7 18 [] vO. Ws fe 17 1] vO NC Iis[} 9 16 [1] vo, VO4 lo[] 10 15 [] vo, Os hof} 14 141] vo 10, /O2 eno [] 12 3D ty 12 13 14 15 16 17 18 13003-002A 2 2 9 9 = g 13003-003A iid Note: Pin 1 is marked for orientation. PIN DESIGNATIONS CLK Clock GND Ground I Input vo Input/Output NC No Connect Vcc Supply Voltage PAL22V10ADV MICRO PLA/PLE/ARRAYS 28E D M@ 0257526 0029558 9 MBAMDA ORDERING INFORMATION Commercial Products aw AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: a. Family Type b. Technology c. Number of Array Inputs d. Output Type e. Number of Outputs f. Power Speed Operating Conditions g. h. Package Type i. J Programming Designator PAL CE 22 V 10 H-15 P C a. FAMILY TYPE PAL or AmPAL = Programmable Array Logic b. TECHNOLOGY CE = CMOS Electrically Erasable Blank = Bipolar c. NUMBER OF ARRAY INPUTS d. OUTPUT TYPE V = Versatile @, NUMBER OF OUTPUTS f. POWER Q = Quarter Power (55 mA Icc) H = Half Power (90 mA Icc) Blank = Full Power (180 mA Icc) Valld Combinations PAL22V10-10 PC, JC, DC PAL22V10-15 AmPAL22V10A AmPAL22V10 PALCE22V10H-15 PALCE22V10H-25 PALCE22V100-25 blank, 14 j. PROGRAMMING DESIGNATOR Blank = Initial Release /4 = First Revision (May require different programmer revisions) i. OPERATING CONDITIONS C = Commercial (0C to +75C) h. PACKAGE TYPE P = 24-Pin 300-mil Plastic SKINNYDIP (PD3024) = 28-Pin Plastic Leaded Chip Carrier (PL 028) D = 24-Pin 300-mil Ceramic: SKINNYDIP (CD3024) i. g. SPEED 10 -= 10nstpp 15 = 15nstpp 25 = 25nstpp A = 25nstpp Blank = 35 ns tpp Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device, Consult the local AMD sales office to contirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on AMD's standard military grade products. Note: Marked with AMD logo. 2-240 PAL22V10ADV MICRO PLA/PLE/ARRAYS 28 D MM 0257526 0029559 0 EMAMD2 ORDERING INFORMATION SGRTOLT.t FioaRI aa APL Products T-46-1 9-07 T-46~19-] 3 a AMD programmable logic products for Aerospace and Defense applications are available with several ordering options. APL (Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combina- tion) is formed by a combination of: a. Family Type Technoiogy Number of Array Inputs Output Type Number of Outputs Power Speed : Programming Designator Device Class Package Type Lead Finish err searpaos PAL CE 22. V 10H-25 /BLA L k. LEAD FINISH A = Hat Solder Dip ]. PACKAGE TYPE L = 24-Pin 300-mil Ceramic a. FAMILY TYPE PAL or AmPAL = Programmablo Array Logic b. TECHNOLOGY CE = CMOS Electrically Erasable SKINNYDIP (CD3024) Blank = Bipolar K = 24-Pin Ceramic Flatpack (CFLO24) / c. NUMBER OF 3 = 28-Pin Ceramic. ARRAY INPUTS Leadless Chip Carrier (CLO28) d. OUTPUT TYPE V = Versatile i. DEVICE CLASS /B= Class B e. NUMBER OF OUTPUTS h. PROGRAMMING DESIGNATOR | f. POWER Blank = Initial Release H = Half Power (100 mA Icc) E4 = First Revision Blank = Full Power (180-200 mA Icc) (May require different programmer revisions) g. SPEED 15 = 15nstpp 20 = 20nstpp 25 = 25nstpp 30 = 30nstpp A = 30 ns tpp Blank = 40 ns tpp Valid Combinations Valid Combinatlons PAL22V10-15 The Valid Combinations table lists configurations . planned to be supported in volume for this device. PAL22V10-20 ' Consult the local AMD sales office to confirm AmPAL22V10A IBLA, /BKA, /B3A availability of specific valid combinations, to AmPAL22V10 , , check on newly released combinations, and to obtain additional data on AMD's standard military PALCE22V10H-25 | blank grade products. PALCE22V10H-30_ | E4 Note: Marked with AMD logo. Group A Tests Group A Tests consist of Subgroups: 1, 2,3, 7, 8, 9, 10, 11. Military Burn-in Military burn-in is in accordance with the current revision of MIL-STD-883, Test Methods 1015, Conditions A through E. Test conditions are selectad at AMDs option. PAL22V10 2-241ADV MICRO PLA/PLE/ARRAYS cE D BM 0257526 0029560 ? MBAND2 FUNCTIONAL DESCRIPTION The PAL22V10 allows the systems engineer to imple- ment the design on-chip, by opening fuse links (or pro- gramming EE cells) to configure AND and OR gates within the device, according to the desired logic func- tion. Complex interconnections between gates, which previously required time-consuming layout, are lifted fromthe PC board and placed on silicon, where they can be easily modified during prototyping or production. Product terms with ail fuses opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. The PAL22V10 has 12 inputs and 10 VO macrocelis (Figure 1). The macrocell allows one of four potential output configurations; registered output or combinato- rial VO, active high or active low (see Figure 2). The con- figuration choice is made according to the user's design specification and corresponding programming of the configuration bits So - S:. Multiplexer controls are con- nected to ground (0) through a programmable bit, se- lecting the O" path through the multiplexer. Program- T-46-19-07 ming the fuse or erasing the bit disconnects.the control line from GND and it floats to Vcc (1), selecting the 1 path. The device is produced with a fuse or EE cell link ateach input to the AND gate array, and connections may be se- lectively removed by applying appropriate voltages to the circuit. Utilizing an easily-implemented program- ming algorithm, these products can be rapidly pro- grammed to any customized pattern. Information on ap- proved programmers can be found in the Programmer Reference Guide. Extra test words are pre-programmed during manufacturing fo ensure extremely high field pro- gramming yields, and provide extra test paths to achieve excellent parametric correlation. Variable Input/Output Pin Ratio The PAL22V10 has twelve dedicated input tines, and each macrocell output can be an i/O pin. Buffers for de- vice inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to Voc or GND. CLK Mg ely PROGRAMMABLE . AND ARRAY Y (44 x 132) tO 1 ry | AU RESET OUTPUT OUTPUT outpuT-+{ ou LOGIC LOGIC LOGIC LOGIC PMACRO DMAGRO PMACR P MACRO CELL CELL CELL CELL [| , PRESET vO, 06 vO5 13003-001A Figure 1. Block Diagram 2-242 PAL22V10 T~46-19-13ADV MICRO PLA/PLE/ARRAYS 28E 9 0257526 0025561 9 mMAMD2 Registered Output Configuration Combinatorial I/O Configuration Each macrocell of the PAL22V10 includes a D-type flip- Any macrocell can be contigured as combinatorial by flop for data storage and synchronization. The flip-flop selecting the multiplexer path that bypasses the flip-flop is loaded on the LOW-to-HIGH transition of the clock in- _ (81 =1). Inthe combinatorial configuration the feedback put. In the registered configuration (S; = 0), the array is from the pin. feedback is from of the flip-flop. jp 46.1 907 T-46-19-13 VOn S; So Output Configuration 0 0 Ragistered/Active Low 0 1 Ragistered/Active High 1 0 Combinatorial/Active Low 1 1 Combinatorial/Active High 0 = Unprogrammed fuse or programmed EE bit 1 = Programmed fuse or erased (charged). EE bit 13003-0044 Figure 2. Output Logic Macrocell Diagram So =0 So =0 $1 =0 Si=1 __s3- Figure 3a. Registered/Active Low Figure 3c. | Combinatorial/Active Low Figure 3b, Registered/Active High Figure 3d. Combinatorial/Active High 13003-009A PAL22V10 2-243ADV MICRO PLA/PLE/ARRAYS 2BE D ma 025752 0029562 0 MANDA Programmable Three-State Outputs Each output has a three-state output buffer with three- state control. A product term controls the buffer, allow- ing enable and disable to be a function of any product of device inputs or output feedback. The combinatorial output provides a bidirectional I/O pin, and may be con- figured as a dedicated input if the buffer is always dis- abled. Programmable Output Polarity The polarity of each macrocell output can be active high or active low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. it can also save DeMorganizing ef- forts. Selection is controlled by programmable bit So in the output macrocell, and affects both registered and com- binatorial outputs. Selection is automatic, based on the design specification and pin definitions. If the pin defini- tion and output equation have the same polarity, the out- put is programmed to be active high (So = 1). Preset/Reset For initialization, the PAL22V10 has additional Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous Preset (SP) product term is asserted high, the output registers will be loaded with a HIGH on the next LOW-to-HIGH clock transition. When the Asynchronous Reset (AR) product term is asserted high, the output registers will be immediately loaded with a LOW independent of the clock. Note that preset and reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected. Power-Up Reset All flip-flops power-up to a logic LOW for predictable system initialization. Outputs of the PAL22V10 will de- pend on the programmed output polarity. The Vcc rise must be monotonic and the reset delay time is 1-10 ps maximum. Register Preload The register on the PAL22V10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct load- ing of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired State. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. ee ON 7-46-19-07 Security Fuse After programming and verification, a PAL22V10 design can be secured by programming the security fuse or EE bit. Once programmed, this fuse defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. When the security fuse is programmed, the array will read as it every fuse is programmed, and preload will be disabled. For the CMOS PALCE22V10, a floating gate is used as the security bit. The bit can only be erasedin conjunction with erasure of the entire pattern. Quality and Testability The PAL22V 10 offers a very high level of built-in quality. Extra programmable fuses provide a means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry. The erasability of the CMOS PALCE22V10 allows direct testing of the device array to guarantee 100% program- ming and functional yields. Technology The bipolar PAL22V10 is fabricated with AMD's ad- vanced oxide-isolated bipolar process. This process re- duces parasitic capacitances and minimum geometries to provide higher performance. The array connections are formed with proven PtSi fuses for reliable operation. The PAL22V 10-10 uses TIW fuses. The CMOS PALCE22V10 is fabricated with AMD's ad- vanced EE CMOS process. The array connections are formed by electrically- erasable floating gates similar to those found in EEPROMs. Programming and Erasing The PAL22V10 can be programmed on standard logic programmers. Approved programmers are listed in ithe Programmer Reference Guide. The CMOS PALCE22V 10 may be erased to reset a pre- viously configured device back to its virgin state. Era- sure is automatically performed by the programming ~ hardware. No special erase operation is required. 2-244 PAL22V10 T-46-19-13.ADV MICRO PLA/PLE/ARRAYS 28E ) MM 0257526 GO295b3 2 mMAMD? LOGIC DIAGRAM T-46-19-07. T-46-19-13 SKINNYDIP (PLCC/LCC) Pinouts CLA g @ 7 1 L 10 : o 364 7 8 W112 15 16 19 20 23 26 27280 HN 8 39-40 43 14004-001A aT PAL22V10 2-245ADV MICRO PLA/PLE/ARRAYS eOE D BM O2575ceb 0029564 4 BH ANDe ABSOLUTE MAXIMUM RATINGS OPERATING RANGES ~ T_A6~-19-07. " T-46~19-73 Storage Temperature 65C to +150C Commercial (C) Devices . Ambient Temperature with Ambient Temperature (Ta) Power Applied -55C to +125C Operating in Free Air 0C to +75C Supply Voitage with Supply Voltage (Vcc) Respect to Ground 0.5 Vito +7.0V with Respect to Ground +4.75 V to +5.25 V DC Input Voltage (-10) 1.2 Vto Veo + 0.5 V Operating ranges define those limits between which the func- DC Input Voltage (-15) 0.5 V to Voc + 0.5 V tionality of the device is guaranteed. DC Input Current (-15) ~30 mA to +5 mA DC Output or I/O Pin Voltage -0.5 V to Vcc +0.5V Static Discharge Voitage 2001 V Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min. | Max. |] Unit Vou Output HIGH Voltage lon = -3.2 MA Vin = Vin or Vit 2.4 Vv Voc = Min. Vo Output LOW Voltage lon =16MA Vin = Vin or Vit ; 0.5 Vv Vcc = Min. Vin Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for all Inputs (Note 1) Vir Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 1) 7 Input Clamp Voltage lin=-18 MA, Vcc = Min. ~1.2 Vv IH Input HIGH Current Vin = 2.7 V, Veco = Max. (Note 2) 25) pA Ii Input LOW Current Vin = 0.4 V, Voc = Max. (Note 2) -100 |, HA I Maximum Input Current Vin = 5.5 V, Voc = Max. : 1} mA lozH Off-State Output Leakage Vout = 2.7 V, Vcc = Max. 100 | pA Current HIGH Vin = Vir or Vir (Note 2) lozt Off-State Output Leakage Vout = 0.4 V, Veco = Max. -100 | pA Current LOW Vin = Vin or Vit (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Vec = Max. (Note 3) -30 -90 | mA lec Supply Current Vin = 0 V, Outputs Open (lout = 0 mA) 180 | mA Vec = Max. Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. VO pin leakage is the worst case of Ii, and loz (or Ii and lozy). 3. Nat more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. Vout =0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-246 PAL22V10-10/15 (Coml)ADV MICRO PLA/PLE/ARRAYS 28E D M@ 0257526 0029565 & BAND ; 27% ~ OF a CAPACITANCE (Note 1) T-46-19-07 F * T-46-19-13S Parameter -10 -15 - Symbol Parameter Description Test Conditions Typ. Typ. Unit Cin Input Capacitance [Pins 1,13] Viy=2.0V Veo = 5.0 V 6 _9 Others Ta = 25C 6 pF Cour Output Capacitance Vout=2.0V | f=1MHz 8 9 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design i is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) PRELIMINARY MONE 15 Parameter : Symbol | Parameter Description Min. Max. | Unit tpo Input or Feedback to Combinatorial Output 15 | ns ts Setup Time from Input, Feedback or SP to Clock 10 ns tu Hold Time 0 ns tco Clock to Output 10 ns tor Clock to Feedback (Note 4) 2,5. ns tar Asynchronous Reset to Registered Output 20 ns tanw Asynchronous Reset Width 15 ns tara Asynchronous Reset Recovery Time 10 ns tspr Synchronous Preset Recovery Time 10 ns tw. LOW 6 ns twa Clock Width HIGH 6 ns Maximum External Feedback Its + tco) 50 MHz fax Frequency Internal Feedback i{ts_ + tcr) 80 MHz (Note 5) No Feedback ttwe + tw) 63. | MHz tea Input to Output Enable Using Product Term Controi_ | | 15 ns | ter input to Output Disable Using Product Term Control | 3 s 15 ns . Notes: 2. See Switching Test Circuit for test conditions. 3. Output delay minimums are measured under best-case conditions. 4. Calculated from measured fax internal. 5 . These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is moditied where frequency may be affected. PAL22V10-10/15 (Coml) 2-247ADV MICRO PLA/PLE/ARRAYS 28E D MH 0257524 0029Sbb 8 EXAMD2 p > ~ * ABSOLUTE MAXIMUM RATINGS OPERATING RANGES T-46-19-07 \ J-46-19-13. > Storage Temperature -65C to +150C Military (M) Devices (Note 1) a Supply Voltage with Ambient Temperature (Ta) Respect to Ground -0.5 V to +7.0 V Operating in Free Air 55C Min. DC input Voltage (-15) -1.2V to+7.0V Operating Case (Tc) DC Input Voltage (-20) 0.5 V to +5.5V Temperature 125C Max. DC Output or /O Pin Voltage -0.5 V to +7.0V Supply Voltage (Vcc) pc Input Current (-20) ~30 mA to +5 mA with Respect to Ground +4.50 V to +5.50 V Stresses above those listed under Absolute Maximum Rat- Oper ating ranges define those limits between which the func- ings may cause permanent device failure. Functionality at or tionality of the device is guaranteed. above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- Note: ity. Programming conditions may differ. Absolute Maximum a 0 50 Ratings are for system design reference; parameters given 1. Military products are tested at Tc = +25C, +125C, are not tested. and -55C, per MIL-STD-883, DC CHARACTERISTICS over MILITARY operating ranges unless otherwise specified (Note 2) Parameter Symbol Parameter Description Test Conditions Min. | Max. | Unit Vou Output HIGH Voltage lon =-2 MA Vin = Vin or Vit 2.4 Vv Vec = Min. Voi Output LOW Voltage lao =12mMA Vin =Vinor Vit 0.5 Vv Vcc = Min. ViH Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for all Inputs (Note 3) Vir Input LOW Voltage Guaranteed Input Logical LOW 08 Vv Voltage for all inputs (Note 3) Vi Input Clamp Voitage lin = 18 mA, Vcc = Min. -1.2 Vv li Input HIGH Current Vin = 2.7 V, Veco = Max. (Note 4) 25 | pA Ii Input LOW Current Vin = 0.4 V, Voc = Max. (Note 4) 100 | pA li Maximum Input Current Vin = 5.5 V, Veco = Max. ; 1 mA loz Off-State Output Leakage Vout = 2.7 V, Veo = Max. 100 |} pA Current HIGH Vin = Vin or Vir (Note 4) lozt Off-State Output Leakage Vout = 0.4 V, Veco = Max. -100 | pA Current LOW Vin = Vin or Vit (Note 4) Isc Output Short-Circuit Current Vout = 0.5 V, Vec = Max. (Note 5) ~30 -90] mA lec Supply Current Vin = 0 V, Outputs Open (lour = 0 mA) 200 | mA Veco = Max. Notes: 2. For APL Products, Group A, Subgroups 1, 2, and 3 are tested per MIL-STD-883, Method 5005, unless otherwise noted. 3. Vit and Vin are input conditions of output tests and are not themselves directly tested. Vi_ and Vix are absolute voltages with respact to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. 4. VO pin leakage is the worst case of In and lozz (or liq and lozy). 5. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second, Vout = 0.5 V has been chosen to avoid test problems caused by tester ground dagradation. 2-248 PAL22V10-15/20 (Mil)ADV MICRO PLA/PLE/ARRAYS 28E D MM 0257526 002957 T BANDE 7786-19-07. ~sT-46-19-13 CAPACITANCE (Note 1) T-46-19-07 BO Parameter -15 -20 Symbol Parameter Description Test Conditions Typ. _ Typ. Unit Cin Input Capacitance |Pins 1,13] Vin =2.0V Voc = 5.0 V 6 9 Others _ ORO 6 Ta = 25C = pF Court Output Capacitance Vout =2.0V | f=1MHz 8 9 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 2) PRELIMINARY Parameter po 15 +20 Symbol | Parameter Description Max. | Unit tep Input or Feedback to Combinatorial Output 20 ns ts Setup Time from Input, or Feedback to Clock ns ty Hold Time ns. tco Clock to Output 15 ns tor Clock to Feedback (Note 3 and 4) 13 ns tar Asynchronous Reset to Registered Output 25 ns tanw Asynchronous Reset Width (Note 5) ns tana Asynchronous Reset Recovery Time (Note 5) ns tspA Synchronous Preset Recovery Time (Note 4) ns tw. Clock Width Low 3 lock Wi two HIGH se ns Maximum External Feedback | 1/(ts + tco) f = 5t 31.2 MHz fax Frequency (Note 6) Internal Feedback its + tcr) 33.3 MHz tea Input fo Output Enable Using Product 20 ns Term Control (Note 4) . ten Input to Output Disable Using Product 20 ns Term Control (Note 4) Notes: 2. See Switching Test Circuit for test conditions. For APL products Group A, Subgroups 9, 10, and 11 are tested per MIL-STD-883, Method 5005, unless otherwise noted. 3. Calculated from measured fax internal. 4. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where these parameters may be affected. 5. tarnw and tara are not directly tested, but are guaranteed by the testing of ts and tar. 6. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. PAL22V10-15/20 (Mil!) 2-249ADV MICRO PLA/PLE/ARRAYS | ese >) mm 0257526 0024958 1 ESAMD2 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES T-46-1 9-07 Storage Temperature -65C to +150C Commercial (C) Devices i T-46~] 9-1] 3 Ambient Temperature with Ambient Temperature (Ta) Power Applied ~55C to +125C Operating in Free Air 0C to +75C Supply Voltage with Supply Voltage (Vcc) Respect to Ground 0.5 V to +7.0V with Respect to Ground +4.75 V to +5.25 V DC Input Voltage 0.5 Vto +5.5V oO . . _ . DC Input Current 30 mA to 45 mA perating ranges define those limits between which the func- tionality of the device is guaranteed. DC Output or I/O Pin Voltage -0.5 V to Vcc Max. Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating range t specified Parameter Symbol Parameter Description Vou Output HIGH Voltage Voi Output LOW Voltage Vin Input HIGH Voltage Guaranteed Input Logical Vv a Voltage for alt Inputs (Note Viv Input LOW Voltage 3, ~ | Guaranted input Logical LQW 08] V 8 Sse Voltage for all Input (Note 1) VI Input Clamp Voltage | Iin= 18 mA, Voe= Min. -12| V hn input HIGH Current = A | Vin = 2.7. , Voc = Max. (Note 2) 25 | pA ln Input LOW Current 3 25, . Vin= 0-4 V, Veo = Max. (Note 2) -100 | WA It Maximum Input Current Vin = 5.5 V, Voc = Max. 1 | mA lozH Off-State Output Leakage * | Vout = 2.7 V, Veco = Max. 100 | pA Current HIGH. t= Vin = Vinor Vit (Note 2) . loz Off-State Output Leakage Vout = 0.4 V, Vcc = Max. -100 | pA Current LOW Vin = Vin or Vi, (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Veco = Max. (Note 3) -30 90 |. mA lec Supply Current Vin = 0 V, Outputs Open (lout = 0 mA) 180 | mA Vcc = Max. Notes: 1. These are absolute values with respect to davice ground and all overshoots due to system and/or tester noise are included. 2. VO pin leakage is the worst case of IIL and lozt (or IH and lozn). 3. Not more thanone output should be tested at a time. Duration of the short-circuit should not exceed one second. Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-250 AmPAL22V10/A (Coml)ADV MICRO PLA/PLE/ARRAYS 26E D BM 0257526 0029569 3 BHAMDe CAPACITANCE (Note 1) 7 T=46-19-07 YS TaT9=3 Parameter Symbol Parameter Description Test Conditions _ Typ. Unit Cin Input Capacitance {Pins 1,13] Vin=2.0V Veo = 5.0 V 14 Others _ 9Ko, 6 Ta = 25C . pF Cour Output Capacitance VouT=2.0V | f=1MHz 9 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design |s modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges A Parameter Parameter Min. teo Input or Feedback to Combinatorial Output ts Setup Time from Input, Feedback or SP to Clock tH Hold Time Clock to or Feedback Asynchronous Reset to Asynchronous Reset Asynchronous Reset Synchronous Pre: tw twu AMD eh eB oy External 8 teas -~2} {fiput to OutpufEnable Using Prddlct Term Control ter to Out f Term Control Notes: 2. See Switching T test conditions. 3. These parameters not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. AmPAL22V10/A (Coml) 2-251ADV MICRO PLA/PLE/ARRAYS 2e6E D MM Oe2S75eb G0eI570 T MAND ABSOLUTE MAXIMUM RATINGS OPERATING RANGES 46-19-07 T-46-19-13. Storage Temperature 65C to +150C Military (M) Devices (Note 1) * : ~ Supply Voltage with Ambient Temperature (Ta) Respect to Ground 0.5 V to +7.0 V Operating in Free Air -55C Min. DC Input Voltage 0.5 V to+5.5V Operating Case (Tc) DC Output or VO Pin Voltage -0.5 V to Vcc Max. Temperature +125C Max. DC Input Current ~30 MA to +5 mA Supply Voltage (Vcc) ne Output Sink Current 100 mA (Note 6) with Respect to Ground +4.50 V to +5.50 V Sire sses above those listed under Absolute Maximum Rat- Operating ranges define those limits between which the fune- ings may cause permanent device failure. Functionality at or tionality of the device is guaranteed. above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- Note: ity. Programming conditions may differ. Absolute Maximum Ratings are for system design reference; parameters given are not tested. 1. Military products are tested. x DC CHARACTERISTICS over MILITARY operating ranges un (Note 2) Parameter Symbol Parameter Description Vou Output HIGH Voltage Voi Output LOW Voltage . Vin Input HIGH, Votage i Voltage forall inputs oar 3)" Vit . input Low Voltage # Guaranteed Input Logical LOW 0.8 Vv ST EA ALO? __ =f Veltage for all. Inputs (Note 3) Vics Input Clamp Voltage + | t= =18 mA, Vee = Min. j 12] V . bh Input HIGH Current.) ch Vin'= 2:7 V, Veco = Max. (Note 4) 25] pA tt 2 | Input LOW Current __[Vin = 0.4 V, Voc = Max. (Note 4) -100 | pA i Maximum input.Current_2/ Vin = 5.5 V, Voc = Max. 1] mA lozH Off-Stat Output Leakage Vout = 2.7 V, Vec = Max. 100 | pA Current HIGH." Vin = Vin or Vit (Note 4) loz Off-State Output Leakage Vout = 0.4 V, Vec = Max. -100] WA Current LOW Vin = Vin or Vit (Note 4) Isc Output Short-Circuit Current Vout = 0.5 V, Voc = Max. (Note 5) -30 ~90 | mA lec Supply Current Vin = 0 V, Outputs Open (lour = 0 mA) 180 | mA Vcc = Max. Notes: 2. For APL Products, Group A, Subgroups 1, 2, and 3 are tested per MIL-STD-883, Method 5005, unless otherwise noted. 3. Vit and Vix are input conditions of output tests and are not themselves directly tested. Vit and Vix are absolute voltages with respect to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. 4. VO pin leakage is the worst case of Ii, and lozi (or liq and 1ozH). 5. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. Vout =0.5V has been chosen to avoid test problems caused by tester ground degradation. 6. Not more than one output should sink 100 mA at a time. Duration should not exceed one second. 2-252 AmPAL22V10/A (Mil)ADV MICRO PLA/PLE/ARRAYS 28 D MM O257524 OO2Z957 1 MMAND2 CAPACITANCE (Note 1) ~ T~46-19-07 = TA6=T9273 Parameter ae Symbol Parameter Description Test Conditions Typ. Unit Cin Input Capacitance [Pins 1,13} Vin=2.0V Vec = 5.0 V _1 Others Ta = 25C 6 pF Court Output Capacitance Vout=2.0V ] f=1MHz 9 Note: 1, These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note A Parameter Parameter Min. Input or Feedback to Combinatorial Output Setup Time from Input, or Feedback to Clock Hold Time Clock to or Feedback Asynchronous Reset to Reg Asynchronous Reset Asynchronous Reset Clock nput.to trm Control Input T Notes: 2. See Switching T test conditions. 3. tanw and tara are ndt directly tested, but are guaranteed by the testing of ts and tar. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 5. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where these parameters may be affected, : AmPAL22V10/A (Mil) 2-253ADV MICRO PLA/PLE/ARRAYS e8F D MM 0257526 0029572 3 ME AND? ABSOLUTE MAXIMUM RATINGS OPERATING RANGES ____. : Storage Temperature -65C to +150C Commercial (C) Devices . T~46~1 9--07 Mo T-46~] 9-13 . Ambient Temperature with Ambient Temperature (Ta) ee Ff Power Applied 55C to +125C Operating in Free Air 0C to +75C Supply Voltage with Respect : . to Ground -0.5 V0 +7.0V Reooect to Cound with . DC Input Voltage (Except H-25) +4.75-V to +5.25 V (Except Pin 5) 0.5 V to Veco + 0.5 V Supply Voltage (Vcc) with . DC Input Voltage (Pin 5) ~0.6 Vito +11.0V Respect to Ground (H-25) +4.5 Vito +5.5V DC Output or I/O Pin . . _ " Operating Ranges define those limits between which the func- Voltage ~0.5 Vito Vec + 0.5 V tionality of the device is guaranteed. oo Static Discharge Voltage 2001 V Latchup Current (Ta = 0C to +75C) 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Pro- gramming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min. Max. | Unit Vou Output HIGH Voltage lod = -3.2 MA Vin = Vincor Vit 2.4 Vv Voc = Min. Vo Output LOW Voltage la =16MA Vin = Vin or Vit . O04 7 V Vcc = Min. - Vin Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for all Inputs (Note 1) Vit Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 1) ; Mu input HIGH Leakage Current) Vin = 5.5 V, Vcc = Max. (Note 2) 10. HA It Input LOW Leakage Current | Vin = 0 V, Vcc = Max. (Note 2) ~10 pA loz Off-State Output Leakage | Vout = 5.5 V, Vcc = Max., 10 pA Current HIGH Vin = Vit or Vin (Note 2) lozi Off-State Output Leakage Vout = 0 V, Veco = Max. ~10 HA Current LOW Vin= Vit or Vin (Note 2) / Isc Output Short-Circuit Vout = 0.5 V, Voc = Max. (Note 3) -30 } -150 mA Current lec Supply Current Vin = 0 V, Outputs Open H 90 mA (lout = 0 mA), Vcc = Max. Q 55 Notes: 1, Thase are absolute values with respect to the device ground and all avershoots due to system and tester noise are Included, 2. W/O pin leakage is the worst case of IL and lozi (or IH and loz). 3. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second, Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-254 PALCE22V10H-15/25, Q-25 (Coml)ADV MICRO PLA/PLE/ARRAYS 23E D mm O25752b 0029573 5S MBANDe CAPACITANCE (Note 1) T-46=19-07 . = T=46-19-13 Parameter Symbol Parameter Description Test Conditions Typ. Unit Cin Input Capacitance Vin = 2.0V Voc = 5.0 V 5 Ta = 25C pF Court Output Capacitance Vout = 2.0 V f=1 MHz 8 Note: : 1, These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified . Where capacitance may be affected. : SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) -15 25 Parameter Symbol | Parameter Description Min. | Max. Min. Max. | Unit tpp Input or Feedback to Combinatorial Output 15 , 25 ns ts Setup Time from Input, Feedback or SP to Clock 10 15 ns tH Hold Time 0 0 ns tco Clock to Output 10 15 ns ter Clock to Feedback (Note 3) 7 13 ns tar Asynchronous Reset to Registered Output 20 25 ns tanw Asynchronous Reset Width 15 25 ns taRA Asynchronous Reset Recovery Time 10 25 "AS {spr Synchronous Preset Recovery Time 10 25 ns tw. LOW 8 13 ns tw | HOCK Width (rig 8 13 Ts Maximum External Feedback Its + tco) 50 33.3 MHz Frequency {Max (Note 4) Internal Feedback Ii(ts_ + tcr) 58.8 35.7 MHz tea Input to Output Enable Using Product Term Control 15 25 ns ter Input to Output Disable Using Product Term Control 15 25 ns Notes: 2. See Switching Test Circuit for test conditions. 3. Calculated from measured fxax internal. 4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. PALCE22V10H-15/25, Q-25 (Com'l) 2-255ADV MICRO PLA/PLE/ARRAYS e&E D MM 0257524 go24574 ? MBANDe ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature 65C to +150C Military (M) Devices (Note 1 1-46-9297 7 Ambient Temperature Operating Case : no wee 2 ot. _ with Power Applied 55C to +125C Temperature (Tc) 55C to +125C f T-46-19-13 ~ Supply Voltage with Supply Voltage (Vcc) . . ue Respect to Ground 0.5 Vto +7.0V with Respect to Ground +4.5Vto+5.5V DC Input Voltage Operating ranges define those limits between which th func- (Except Pin 5) ~0.5 Vio Vec+0.5V tionality of the device is guaranteed. - DC Input Voltage (Pin 5) -0.6 V to +11.0 V DC Output or /O Pin Voltage -0.5VtoVec+0.5V a od cos r. 3s oC 125C in Di 1. Military products are tested at To = +25C, +125 Static Discharge Voltage 2001 V and 55C, per MIL-STD-883, Latchup Current (Ta = -55C to +125C) 100 MA Stresses above those listed under Absolute Maximum Rat- 7 ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. Absolute Maximum Ratings are for system design reference; parameters given are not tested. DC CHARACTERISTICS over MILITARY operating ranges unless otherwise specified (Note 2) Parameter Symbol Parameter Description Test Conditions Min, Max. Unit Vou Output HIGH Voltage lon = ~-2.0MA Vin = Vie or Vi 2.4 . Vv Vcc = Min. VoL Output LOW Voltage lo =12MA Vin = Vin or Vit 0.4 Vv Vec = Min. . Vin Input HIGH Voltage Guaranteed input Logical HIGH 2.0 Vv : Voltage for all Inputs (Note 3) : ; Vit Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 3) Ing Input HIGH Leakage Current | Vin = 5.5 V, Voc = Max. (Note 4) 10 uA he Input LOW Leakage Current | Vin = 0 V, Voc = Max. (Note 4) 10 BA lozH Off-State Output Leakage Vout = 5.5 V, Vec = Max. 10 / Current HIGH Vin = Visor Vi, (Note 4) HA loz. Off-State Output Leakage Vout = 0 V, Voc = Max. ~10 yA Current LOW Vin = Vin or Vi (Note 4) Isc Output Short-Circuit Current Vout =0.5V Vec = Max. ~30 -150 mA (Note 5) lec Supply Current Vin = 0 V, Outputs Open 100 mA (lour = 0 MA), Vec = Max. Notes: 2. For APL products, Group A, Subgroups 1, 2 and 3 are tested per MIL-STD-833, Method 5005, unless otherwise noted, 3. Vit and Vin are input conditions of output tests and are not themselves directly tested. Vi_ and Vin are absolute voltages with respect to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. 4. VO pin leakage is the worst case of I and lozt (or ket and loz). 5. Not more than ona output should be shorted at a time and duration of the short-circuit should not exceed one second. Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where Isc may be affected. 2-256 PALCE22V10H-25/30 (Mil)ADV MICRO PLA/PLE/ARRAYS 28 D MM 0257526 0029575 9 MMAND2 oo : . CAPACITANCE (Note 1) T=46-19-07. S ~-F-46-19-13 Parameter - Symbol Parameter Description Test Conditions _ Typ. Unit Cin Input Capacitance Vin=2.0V Veco = 5.0 V 8 Ta = 25C pF Cour Output Capacitance Vout = 2.0 V f=1 MHz 9 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. : SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 2) Parameter =25 =30 Symbol | Parameter Description Min. | Max. | Min. | Max. | Unit tep Input or Feedback to Combinatorial Output 25 ; 30 ns ts Setup Time from Input, Feedback or SP to Clock 20 |. 20 - ns tH Hold Time (Note 4) 0 0 _ns tco Clock to Output 20 20_| ns ter Clock to Feedback (Note 3) 18 18 ns_ tag Asynchronous Reset to Registered Output 30 35 ns tanw Asynchronous Reset Width (Note 4) 25 30 ns taRR Asynchronous Reset Recovery Time (Note 4) 25 30 ns tspr Synchronous Preset Recovery Time 25 30 ns t W 15 1 n we Clock width LES S as twa HIGH 15 15 ns Maximum External Feedback] its +tco) | 25 25 MHz fax Frequency : (Note 5) Internal Feedback tits +tcr) | 26 261 - | MHz tea Input to Output Enable Using Product 25 30 ns Term Control (Note 4) ter Input to Output Disable Using Product 25 30 ns Term Control (Note 4) Notes: 2. See Switching Test Circuit for test conditions. For APL products Group A, Subgroups 7, 8, 9, 10, and 11 are tested per MIL-STD-883, Method 5005, unless otherwise noted. 3. Calculated from measured fax internal. 4, These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where these parameters may be affected. 5. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. PALCE22V10H-25/30 (Mil) 2-257ADV MICRO PLA/PLE/ARRAYS CSE D MM 0257526 0029576 O MAND? 46-19-07 PRON SWITCHING WAVEFORMS T-46 T-46-19-13 Input or input or Feadback Vr Feedback Vr tpo ts tH Combinatorial Output Vr Clock Vr 12015-010A 'co Combinatorial Output Registered y Output T 12015-0124 Registered Output . CLK ts + ter [ TE | __ 1 | . | Clock Vr Logic |S.) Recister | I I ! 12149-025A tor | Clock to Feedback (fax Internal) bee ee 4 See Path at Right 12015-0214 Input Vr {WH teR tea Clock Vr Output ck Vou - 0.5V /77 Vr pe LT Von + 050 tw 12015-011A 12015-0134 Clock Width Input to Output Disable/Enable Input t . Input Asserting ABW Asserting Asynchronous Vr x Synchronous VT Reset Preset tAR > Registered Output Vr Clock tARA Registered Clock Vr Output Vr 13003-006A ~ 18003-007A Asynchronous Reset Synchronous Preset Notes: 1. Vrei 5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2-5 ns typical. (2-4 ns for 22V10-10) 2-258 PAL22V10ADV MICRO PLA/PLE/ARRAYS 28E ) MM 0257526 0029577 2 MMAMD2 KEY TO SWITCHING WAVEFORMS T-46-19-07 ON F-46-19-13. > WAVEFORM INPUTS OUTPUTS _ _ Must be Will be Steady Steady May Change Will be from H to L Changing from H to L May Change Will be SY from Lto H Changing from L to H Don't Care; Changing, YOOX Any Change State Permitted Unknown Center Line Does Not is High- Apply Impedance Off State KS000010-PAL SWITCHING TEST CIRCUIT 5V Si Ri Output Test Point : I : = = 12350-019A Commerciat Military Measured Specification $1 CL Ri Ra Ri Ro Output Value tpp, tco, ter Closed 15V tea ZH: Open 5OpF | 3002 | 3909 | 3902 | 7502 15V Z L: Closed CMOS: | CMOS: ter HZ: Open 5 pF 338.Q | 24802 | H-Z:Von-O.5V LZ: Closed LZ: VoL +0.5V PAL22V10 2-259ADV MICRO PLA/PLE/ARRAYS ede >) m 025752b 0029578 4 MAND INPUT/OUTPUT EQUIVALENT SCHEMATICS fT : ; ~ T-46~19-1 Bipolar Devices Only T-46-19-07 46-19-13 Typical Input Typical Output V cc ? + Voc 40 NOM Input Output Program/Verify Circuitry Input, Program/Varity/ Pins Test Circuitry 12468-017A Praload Circuitry = . 12468-018A 2-260 PAL22V10ADV MICRO PLA/PLE/ARRAYS 28E D MM 0257526 0029579 & MMAND2 T-46-19-07 7-46-19-13. ENDURANCE CHARACTERISTICS . ~ The PALCE22V10 is manufactured using AMD's ad- parts. As a result, the device can be erased and vanced Electrically Erasable process. This technology reprogrammed a feature which allows 100% testing at uses an EE cell to replace the fuse link used in bipolar the factory. : Endurance Characteristics Symbol} Parameter Min, Units Test Conditions 10 Years Max. Storage Temperature Min. Pattern Data R tion Tim tor in. Pattern Data Retention Time 20 Years Max. Operating Temperature (Military) N Min. Reprogramming Cycles 100 Cycles Normal! Programming Conditions INPUT/OUTPUT EQUIVALENT SCHEMATICS CMOS Devices Only Vcc ESD Program/Verify = Protection Circuitry Input Preload Feedback = Circuitry Input . Output 42197-013A PAL22V10 2-261ADV MICRO PLA/PLE/ARRAYS e6E D) MM O2575aL 0029580 2 MBAMD2 -46-~] 9. \ lf JOE. OUTPUT REGISTER PRELOAD T-46-19 v7 T-46-19-13 Bipolar Devices Only . Clock pin 1 from Vitp to Vip. The preload function allows the registers to be loaded from the output pins. This feature aids functional testing of sequential designs by allowing direct setting of output states. The procedure for preloading follows. . Remove Vitp/Vinp from all registered output pins. . Lower pins 2 and 3 to Vitp. N @O WM fF . Enable the output registers according to the 1. Raise Vcc to 5.0 V+0.5 V. programmed pattern. 2. Setpins 2 and 3 (and 13 for AMPAL22V10/A) to Vay 8. Verify VoL/Von at all registered output pins. Note that to disable outputs and enable preload. the output pin signal will depend on the output polarity. 3. Apply the desired value (Vitp/Vinp) to all registered output pins. Leave combinatorial output pins floating. Parameter Symbol Parameter Description Min, Rec. Max. | Unit ViH Super-level input voltage 10 11 12 Vv Vip Low-level input voltage 0 0 05 Vv Vine High-level input voltage 2.4 5.0 5.5 Vv to Delay time 100 200 1000. | ns VHH Pins 2,3 \ (and 13 for AmPAL22V10/A) \ Vite Registered utputs Clock 14004-002A Output Register Preload Waveform 2-262 PAL22V10ADV MICRO PLA/PLE/ARRAYS 286 D dm Q257524 002958, 4 mmAMDe OUTPUT REGISTER PRELOAD T-46-19-07 T-46-19-13 CMOS Devices Only 4. Clock pin 1 from Vite to Vinp. The preload function allows the registers to be loaded 5. Remove Vitp/Vine from all registered output pins. from the output pins. This feature aids functional testing ; , of sequential designs by allowing direct setting of output 6. Lower pin 5 to Vitp. . States. The procedure for preloading follows. 7, Enable the output registers according to the 1. Raise Vec to5.0V+t0.5V. programmed pattern. 2. Set pin 5 to Vix to disable outputs and enable 8. Verify Vor/Von at all registered output pins. Note that: preload. the output pin signa will depend on the output . . polarity. : 3. Apply the desired value (Vite/Vine) to all registered output pins. Leave combinatorial output pins floating. Parameter Symbol Parameter Description Min. Rec. Max. | Unit VHH Super-level input voltage 9.5 10 10.5 Vv Vite Low-level input voltage 0 0 05 Vv Vine High-level input voltage 3.0 4.0 Veco Vv teLo Setup and Hold Data to Preload (Pin 5) 50 50 ps tpsu Data Setup Prior to Applying Preload Latch Pulse 1.0 1.0* ps teow Data Hold After Latch Pulse 1.0 1.0* ps- teH Mode Hold After Latch Pulse 1.0 1.0 ps tew Latch Pulse Width 1.0 1.0" ys tvo VO Valid After Pin 5 Drops from Vin to TTL Levels 100 | us 7 - a Vin Rising Slew Rate (Pin 5) 10 100 | Vins at Vu Falling Slew Rate (Pin 5) 2.0 3.0 | Vius |. * Recommended value is as close to 1.0 ys + tolerance as practical, but not less than 1.0 ps. oO VHH Pin 5 \ . Vitp tPLD > tPLD tPH tvo, Registered \ OYOtt~<s:stOOO LEY SN iia wine utputs iH. Vi a [SSS=== ve tpsu tPDH (Poo rset eo Vine Clack \ tpw > Vip 14004-0034 Output Register Pretoad Waveform PAL22V10 2-263ADV MICRO PLA/PLE/ARRAYS 26E D MM 0257526 0029582 b MMAMD2 POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pat- tern. This feature is valuable in simplifying state ma- chine initialization. A timing diagram and parameter ta- ble are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways Vcc can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: 1. The Vcc rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and teed- back setup times are met. Parameter Symbol Parameter Description Max. Unit tea Power-up Reset Time Bipolar 1 . CMOS 10 Hs ts Input or Feedback Setup Time See Switching tw. Clock Width LOW Characteristics av Vee Power tea Registered Active-Low Output [Ly i+ ts cs Wk 12350-024A a Power-Up Reset Waveform 2-264 PAL22V10 eee ~FoA6-19-07 F=46-19-13