MT48LC4M16A2B4-7ELIT:G - Micron Technology, Inc.

Products and specifications discussed herein are subject to change by Micron without notice.

64Mb: x4, x8, x16 SDRAM

Features

PDF: 09005aef80725c0b/Source: 09005aef806fc13c Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

Synchronous DRAM

MT48LC16M4A2 – 4 Meg x 4 x 4 banks

MT48LC8M8A2 – 2 Meg x 8 x 4 banks

MT48LC4M16A2 – 1 Meg x 16 x 4 banks

For the latest data sheet, refer to Micron’s Web site: www.micron.com/sdram

Features

• PC100- and PC133-compliant

• Fully synchr onous; all signals registere d on positive

edge of system clock

• Internal pipe lined operatio n; column addres s can be

changed every clock cycle

• Internal banks for hiding row access/pr echarge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh modes: standard and low power

(not available on AT devices)

•Refresh

–64ms, 4,096-cycle refresh (15.6µs/row)

(commercial, industrial)

–16ms, 4,096-cycle refresh (3.9µs/row)

(automotive)

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

Table 1: Address Table

16 Meg x 4 8 Meg x 8 4 Meg x 16

Configuration 4 Meg x 4 x

4 banks 2 Meg x 8 x

4 banks 1 Meg x 16 x

4 banks

Refresh count 4K 4K 4K

Row

addressing 4K (A0–A11) 4K (A0–A11) 4K (A0–A11)

Bank

addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

Column

addressing 1K (A0–A9) 512 (A0–A8) 256 (A0–A7)

Notes: 1. Refer to Micron technical note: TN-48-05.

2. Off-center parting line.

3. Contact Micron for product availability.

Part Num ber Example:

MT48LC8M8A2TG-75:G

Options Marking

• Configurations

–16 Meg x 4 (4 Meg x 4 x 4 banks)

–8 Meg x 8 (2 Meg x 8 x 4 banks)

–4 Meg x 16 (1 Meg x 16 x 4 banks)

16M4

8M8

4M16

•Write recovery (

tWR)

–tWR = “2 CLK”1A2

•Plastic package – OCPL

–54-pin TSOP II (400 mil)

–54-pin TSOP II (400 mil) Pb-free,

RoHS-compliant

–

54-ball VFBGA 8mm x 8mm (x16 only)

–54-ball VFBGA 8mm x 8mm, Pb-fr ee,

RoHS-compliant (x16 only)

B43

• Timing (cycle time)

–7.5ns @ CL = 3 (PC133)

–7.5ns @ CL = 2 (PC133)

–6ns @ CL = 3 (x16 only)

-75

-7E

-6

• Self refresh

–Standard

–Low power None

• Operating temperature range

–Commercial (0°C to +70°C)

–Industrial (–40°C to +85°C)

–A utomotive (–40°C to +105°C)

None

AT3

•Design revision :G

PDF: 09005aef80725c0b/Source: 09005aef806fc13c Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

64Mb: x4, x8, x16 SDRAM

General Description

Notes: 1. FBGA Device Decoder: http://www.micron.com/support/FBGA/FBGA.asp

General Description

The Micron® 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory

containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a

synchronous inte rface (all signals are registered on the positive edge of the clock signal,

CLK). Each of the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns

b y 4 bits. Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows b y 512 columns

b y 8 bits . Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256

columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses beg in with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select

the bank; A0–A11 select the row). The address bits registered coincident with the READ

or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca-

tions, or the full page , with a burst terminate option. An auto precharge function may be

enabled to provide a self-timed row precharge that is initiated at the end of the burst

sequence.

The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-

tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also

allows the column address to be changed on every clock cycle to achieve a high-speed,

Table 2: Key Timing Parameters

CL = CAS (READ) latency

Speed Grade Clock Frequency

Access Time

Setup Time Hold TimeCL = 2 CL = 3

-6 166 MHz – 5.5ns 1.5ns 1ns

-7E 143 MHz – 5.4ns 1.5ns 0.8ns

-75 133 MHz – 5.4ns 1.5ns 0.8ns

-7E 133 MHz 5.4ns – 1.5ns 0.8ns

-75 100 MHz 6ns – 1.5ns 0.8ns

Table 3: 64Mb SDRAM Part Numbers

Part Numbers Architecture Package

MT48LC16M4A2TG 16 Meg x 4 54-pin TSOP II

MT48LC16M4A2P 16 Meg x 4 54-pin TSOP II

MT48LC8M8A2TG 8 Meg x 8 54-pin TSOP II

MT48LC8M8A2P 8 Meg x 8 54-pin TSOP II

MT48LC4M16A2TG 4 Meg x 16 54-pin TSOP II

MT48LC4M16A2P 4 Meg x 16 54-pin TSOP II

MT48LC4M16A2B414 Meg x 16 54-ball VFBGA

MT48LC4M16A2F414 Meg x 16 54-ball VFBGA

PDF: 09005aef80725c0b/Source: 09005aef806fc13c Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

64Mb: x4, x8, x16 SDRAM

Automotive Temperature

fully random access. Precharging one bank while accessing one of the other three banks

will hide the precharge cycl es and provide seamless, high-speed, ra ndom-access

operation.

The 64Mb SDRAM is designed to operate i n 3.3V memory systems. An auto refr esh mode

is provided, along with a power-saving, power-down mode. All inputs and outputs are

LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating perfor mance, including the

ability to synchronously burst data at a high data rate with automatic column-address

generation, the ability to interleave between internal banks in order to hide precharge

time, and the capabili ty to randomly change column addresses on each clock cycle

during a burst access.

Automotive Temperature

The automotive temperature (AT) option adheres to the following specifications:

• 16ms refresh rate

• Self refresh not supported

• Ambient and case temperatures cannot be less than –40°C or greater than 105°C

PDF: 09005aef80725c0b/Source: 09005aef806fc13c Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

64Mb: x4, x8, x16 SDRAM

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Automotive Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Pin/Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Burst Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

LOAD MODE REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

WRITEs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Burst Read/Single Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Temperature and Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

PDF: 09005aef80725c0b/Source: 09005aef806fc13c Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

64Mb: x4, x8, x16 SDRAM

List of Figur es

List of Figures

Figure 1: 16 Meg x 4 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 2: 8 Meg x 8 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3: 4 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 4: Pin Assignment (Top View) 54-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 5: Ball Assignment (Top View, Ball Down) x16, 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Figure 6: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 7: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 8: Acti vating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 9: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK ≤ 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 10: READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 11: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 12: Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 13: Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 14: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 15: READ-to-WRITE With Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 16: READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 17: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 18: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 19: WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 20: WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 21: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 22: WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 23: WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 24: Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 25: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 26: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 27: Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 28: Clock Suspend Duri ng REA D Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 29: READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 30: READ With Auto Pr echarge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 31: WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 32: WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 33: Example Temperature Test Point Location, 54-Pin TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 34: Example Temperature Test Point Location, 54-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 35: Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 36: Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 37: Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 38: Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 39: Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 40: READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 41: READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 42: Single READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 43: Single READ – With Aut o Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 44: Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 45: READ – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 46: READ – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 47: WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 48: WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 49: Single WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 50: Single WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 51: Alternating Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 52: WRITE – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 53: WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 54: 54-Pin Plastic TSOP II (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 55: 54-Ball VFBGA “F4/B4” Package, 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

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64Mb: x4, x8, x16 SDRAM

List of Tables

Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 2: Key Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3: 64Mb SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4: Pin/Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 5: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 6: CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 7: Truth Table 1 – Commands and DQM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 8: Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 9: Truth Table 3 – Current State Bank n, Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 10: Truth Table 4 – Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 11: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 12: Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 13: Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 14: DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 15: IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 16: TSOP Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 17: VFBGA Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 18: Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .48

Table 19: AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

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64Mb: x4, x8, x16 SDRAM

Functional Block Diagrams

Figure 1: 16 Meg x 4 SDRAM

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

COMMAND

DECODE

A0–A11,

BA0, BA1

DQM

ADDRESS

1024

(x4)

4096

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(4,096 x 1,024 x 4)

BANK0

ROW-

ADDRESS

LATCH

DECODER

4096

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–DQ3

4DATA

INPUT

DATA

OUTPUT

BANK1BANK2 BANK3

1 1

REFRESH

COUNTER

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64Mb: x4, x8, x16 SDRAM

Functional Block Diagrams

Figure 2: 8 Meg x 8 SDRAM

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

COMMAND

DECODE

A0–A11,

BA0, BA1

DQM

ADDRESS

512

(x8)

4096

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(4,096 x 512 x 8)

BANK0

ROW-

ADDRESS

LATCH

DECODER

4096

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–DQ7

8DATA

INPUT

DATA

OUTPUT

BANK1BANK2 BANK3

1 1

REFRESH

COUNTER

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64Mb: x4, x8, x16 SDRAM

Functional Block Diagrams

Figure 3: 4 Meg x 16 SDRAM

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

COLUMN-

ADDRESS

COUNTER/

LATCH

A0–A11,

BA0, BA1

DQML,

DQMH

ADDRESS

256

(x16)

4096

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(4,096 x 256 x 16)

BANK0

ROW-

ADDRESS

LATCH

DECODER

4096

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–DQ15

16 DATA

INPUT

DATA

OUTPUT

BANK1BANK2 BANK3

2 2

REFRESH

COUNTER

CONTROL

LOGIC

MODE REGISTER

COMMAND

DECODE

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64Mb: x4, x8, x16 SDRAM

Pin/Ball Assignments and Descriptions

Figure 4: Pin Assignment (Top View) 54-Pin TSOP

Notes: 1. The # symbol indicates signal is active LOW. A dash (-) indicates x8 and x4 pin function is

same as x16 pin function.

Figure 5: Ball Assignment (Top View, Ball Down) x16, 54-Ball VFBGA

Notes: 1. The balls at A4, A5, and A6 are absent from the physical package. They are included to illus-

trate that rows 4, 5, and 6 exist, but contain no solder balls.

VDD

DQ0

VDDQ

DQ1

DQ2

VssQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VssQ

DQ7

VDD

DQML

WE#

CAS#

RAS#

CS#

BA0

BA1

A10

VDD

Vss

DQ15

VssQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VssQ

DQ10

DQ9

VDDQ

DQ8

Vss

DQMH

CLK

CKE

A11

Vss

x8x16 x16x8 x4x4

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ7

DQ6

DQ5

DQ4

DQM

DQ3

DQ2

DQM

12345678

DQ14

DQ12

DQ10

DQ8

DQMH

NC/A12

DQ15

DQ13

DQ11

DQ9

CLK

A11

CKE

CAS#

BA0

DQ0

DQ2

DQ4

DQ6

DQML

RAS#

BA1

DQ1

DQ3

DQ5

DQ7

WE#

CS#

A10

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64Mb: x4, x8, x16 SDRAM

Pin/Ball Assignments and Descriptions

Table 4: Pin/Ball Descriptions

TSOP Pin

Numbers

VFBGA

Ball

Numbers Symbol Type Description

38 F2 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are

sampled on the positive edge of CLK. CLK also increments the internal

burst counter and controls the output regi st ers.

37 F3 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) th e CLK

signal. Deactiv ating the clock provides PRECHARGE power-down and

SELF REFRESH operation (all banks idle), ACTIVE power-down (row

active in any bank ), or CLOCK SUSPEND operation (burst/access in

progress). CKE is synchronous except after the device enters power-

down and self refresh modes, where CKE becomes asyn ch ro no us until

after exiting the same mode. The inpu t buffers, including CLK, are

disabled duri ng power-down and self refresh modes , providing low

standby power. CKE may be tied HIGH.

19 G9 CS# Input Chip select: CS# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when CS# is

registered HIGH, but READ/WRITE burst s already in progress will

continue and DQM will retain its DQ mask capability while CS#

remains HIGH. CS# provides for external bank selection on systems

with multiple banks. CS# is considered part of the command code.

16, 17, 18 F9, F7, F8 WE#, CAS#,

RAS# Input Command inputs: WE#, CAS#, and RAS# (along with CS#) define the

command being entered.

39 – x4, x8:

DQM Input Input/output mask: DQM i s an input mask signal for write accesses and

an output enable signal for read accesses. Input data is masked when

DQM is sampled HIGH during a WRITE cycle. The output buffers are

placed in a High-Z state (two-clock latency) when DQM is sampled

HIGH during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC

and DQMH is DQM. On the x16, DQML corresponds to DQ0–DQ7 and

DQMH corresponds to DQ8–DQ15. DQML and DQMH are considered

same state when referenced as DQM.

15, 39 E8, F1 x16:

DQML,

DQMH

20, 21 G7, G8 BA0, BA1 Input Bank address inputs: BA0 and BA1 define to which bank the ACTIVE,

READ, WRITE or PRECHARGE command is being applied.

23–26,

29–34, 22,

H7, H8, J8,

J7, J3, J2,

H3, H2, H1,

G3, H9, G2

A0–A11 Input Address inputs: A0–A11 are sampled during the ACTIVE command

(row-address A0–A11) and READ/WRITE command (column-address

A0–A9 [x4]; A0–A8 [x8]; A0–A7 [x16]; with A10 defining auto

precharge) to select one location out of the memory array in the

respective bank. A10 is sampled during a precharge command to

determine whether all banks are to be precharged (A10[HIGH]) or

bank selected by BA0, BA1 (A1[LOW]). The address inputs also provide

the op-code during a LOAD MODE REGISTER command.

2, 4, 5, 7, 8,

10, 11, 13,

42, 44, 45,

47, 48, 50,

51, 53

A8, B9, B8,

C9, C8, D9,

D8, E9, E1,

D2, D1, C2,

C1, B2, B1,

DQ0–DQ15 x16: I/O Data input/output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51 are

NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for

x4).

2, 5, 8, 11,

44, 47, 50,

–DQ0–DQ7 x8: I/O Data input/output: Data bus for x8 (2, 8, 47, 53 are NCs for x4).

5, 11, 44,

50 –DQ0–DQ3 x4: I/O Data input/output: Data bus for x4.

40 E2 NC – No connect: These pins should be left unconnected.

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64Mb: x4, x8, x16 SDRAM

Functional Description

In ge neral, the 64Mb SDRAM (4 M eg x 4 x 4 banks, 2 M eg x 8 x 4 b anks, and 1 Meg x 16 x 4

banks) is a quad-bank DRAM that operates at 3.3V and includes a synchronous interface

(all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s

16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits. Each of the

x8’s 16,777,216-bit banks is organized as 4,096 rows b y 512 columns b y 8 bits . Each of the

x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1

select the bank, A0–A11 select the row). The address bits (x4: A0–A9; x8: A0–A8; x16:

A0–A7) registered coincident with the READ or WRITE command are used to select the

starting column location for the burst access.

Prior to normal ope ration, the SDR AM must be initialized . The fo ll owing sections

provide detailed information covering device initialization, register definition,

command descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a predefined manner. Operational

procedures other than those specified may r esult in undefined operation. After power is

applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is

defined as a signal cycling within timing constraints specified for the clock pin), the

SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND

INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least

through the end of this pe riod, C O MMAND INHIBIT or NOP commands must be

applied.

Once the 100µs delay has been satisfied wi th at least one COMMAND INHIBIT or NOP

command having been applied, a PRECHARGE command should be applied. All banks

must then be pr echarged, thereby placing the device in the all banks idle state.

After the idle state, at least two AUTO REFRESH cycles must be performed. After the

AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-

ming. Because the mode register will pow er up in an unknown state, it must be loaded

prior to applying any operational command. If desired, the two AUTO REFRESH

commands can be issued after the LOAD MODE REGISTER command.

36 G1 NC – No connect: May be used as address inputs (A12) on the 256Mb and

512Mb devi ces.

3, 9, 43, 49 A7, B3, C7,

D3 VDDQ Supply DQ power: Isolated DQ power on the die for improved noise

immunity.

6, 12, 46,

52 A3, B7, C3,

D7 VSSQ Supply DQ ground: Isolated DQ ground on the die for improved noise

immunity.

1, 14, 27 A9, E7, J9 VDD Supply Power supply: +3.3V ±0.3V.

28, 41, 54 A1, E3, J1 VSS Supply Ground.

Table 4: Pin/Ball Descriptions

TSOP Pin

Numbers

VFBGA

Ball

Numbers Symbol Type Description

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64Mb: x4, x8, x16 SDRAM

Functional Description

The recommended power-up sequence for SDRAMs:

1. S i multaneously apply power to VDD and VDDQ.

2. Assert and hold CKE at a LVTTL logic LO W since all inputs and outputs are LVTTL-

compatible.

3. P rovide stable CLOCK signal. Stable clock is defined as a signal cycling within timing

constraints speci fie d for th e c loc k pin.

4. Wait at least 100µs prior to issuing any command other than a COMMAND INHIBIT

or NOP.

5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least

through the end of this period, 1 or more COMMAND INHIBIT or NOP commands

must be applied.

6. Perform a PRECHARGE ALL command.

7. Wait at least tRP time; during this time NOPs or DESELECT commands must be given.

All banks will complete their precharge, thereby placing the device in the all banks

idle state.

8. Issue an AUTO REFRESH command.

9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

10. Issue an AUTO REFRESH command.

11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

12. The SDRAM is no w ready for mode register programming. Because the mode register

will power up in an unknown state, it should be loaded with desired bit values prior to

applying any operational command. Using the LOAD MODE REGISTER command,

program the mode register. The mode register is programmed via the MODE REGIS-

TER SET command with BA1 = 0, BA0 = 0 and retains the stored information until it is

programmed again or the device loses power. Not programming the mode register

upon initialization will result in default settings which may not be desired. Outputs

are guar anteed High-Z after the LOAD MODE REGISTER c ommand is issued. O utputs

should be High-Z already before the LOAD MODE REGISTER command is issued.

13. Wait at least tMRD time, during which only NOP or DESELECT commands are

allowed.

At this point the DRAM is ready for any valid command.

Note: If desired, more than two AU TO REFRESH commands can b e is sue d in the se quence.

After steps 9 and 10 are complete, repeat them until the desired number of AUT O

REFRESH + tRFC loops is achieved.

Mode Register

The mode register is used to define the specific mode of operation of the SDRAM. This

definition includes the selection of a burst length, a burst type, a CL, an operati ng mode

and a write burst mode, as shown in Figure 6 on page 15. The mode register is

programmed via the LOAD MODE REGISTER command and will retain the stored infor-

mation until it is progra mmed again or the device loses power.

Mode r egister bits M0–M2 specify the burst length, M3 specifies the type of burst

(sequential or int erl eave d ), M4–M6 specify the CL, M7 and M8 specify the operating

mode, M9 specifies the WRITE burst mode, and M10 and M11 are reserved for future

use.

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64Mb: x4, x8, x16 SDRAM

Functional Description

The mode regi ster must be loaded when all banks are idle, and the controller mus t wait

the specified time before initiating the subsequent operation. Violating either of these

requirements will result in unspecified operation.

Burst Length

READ and WRITE accesses to the SDRAM are burst oriented, with the burst length (BL)

being programmable, as shown in Figure 6 on page15. The burst length determines the

maximum number of colu mn locati ons that can be ac cessed for a g iven READ or WRITE

command. BL = 1, 2, 4, or 8 locations are available for both the sequential and the inter-

leaved burst types, and a full-page burst is available for the sequential mode. The full-

page burst is used in conjunction with the BURST TERMINATE command to generate

arbitrary burst lengths.

Reserved states cannot be used because unknown operation or incompatibility with

future versions may result.

When a READ or WRITE comm and is issu ed , a block of col u m n s eq ual to the bu rst

length is effectivel y selected. All accesses for that burst take place within this block,

meaning that the burst will wrap within the block if a boundary is reached. The block is

uniquely selected by A1–A9 (x4), A1–A8 (x8) or A1–A7 (x16) when BL = 2; by A2–A9 (x4),

A2–A8 (x8) or A2–A7 (x16) when BL = 4; and by A3–A9 (x4), A3–A8 (x8) or A3–A7 (x16)

when BL = 8. The remaining (least significant) address bit(s) is (are ) used to select the

starting location within the block. Full-page bursts wrap within the page if the boundary

is reached.

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64Mb: x4, x8, x16 SDRAM

Functional Description

Figure 6: Mode Register Definition

Burst Type

Accesse s within a given b urst may be progr ammed to be eithe r sequential or interleaved;

this is referred to as the burst type and is selected via bit M3.

The ordering of accesse s within a burst is determi ned by the burst leng th, the burst type

and the starting column address, as shown in Table 5 on page 16.

3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

–

Defined

–

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS La tency BT

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M6–M0

M8 M7

Op Mode

A10

A11

Reserved WB

Write Burst Mode

Programmed Burst Length

Single Location Access

Program

BA0, BA1,

M11, M10 = “0, 0”

to ensure compatibility

with future devices.

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64Mb: x4, x8, x16 SDRAM

Functional Description

Notes: 1. For full-page accesses: y = 1,024 (x4); y = 512 (x8); y = 256 (x16).

2. For BL = 2, A1–A9 (x4), A1–A8 (x8), or A1–A7 (x16) select the block-of-two burst; A0 selects

the starting column within the block.

3. For BL = 4, A2–A9 (x4), A2–A8 (x8), or A2–A7 (x16) select the block-of-four burst; A0–A1

select the starting column within the block.

4. For BL = 8, A3–A9 (x4), A3–A8 (x8), or A3–A7 (x16) select the block-of-eight burst; A0–A2

select the starting column within the block.

5. For a full-page burst, the full row is selected and

6. A0–A9 (x4), A0–A8 (x8), or A0–A7 (x16) select the starting column.

7. Whenever a boundary of the block is reached within a given sequence above, the following

access wraps within the block.

8. For BL = 1, A0–A9 (x4), A0–A8 (x8), or A0–A7 (x16) select the unique column to be accessed,

and mode register bit M3 is ignored.

CAS Latency

CL is the delay, in clock cycles, between the registration of a READ command and the

availability of the first piec e of output data. The latency can be se t to two or thr ee cl ocks .

If a READ command is registered at clock edge n and the latency is m clocks, the data will

be available by clock edge n + m. The DQs will start driving as a result of the clock edge

one cycle earlier ( n + m - 1), and pro vided that the relevant access times ar e met, the data

will be val id b y clock edge n + m. F or example , assuming that the clock cy cle time is such

that all relevant access times are met, if a read command is registered at T0 and the

latency is programmed to two clocks, the DQs will start driving after T1 and the data will

be valid by T2, as shown in Figure 7 on page 17. Table 6 on page 17 indicates the oper-

ating frequencies at which each CL setting can be used.

Table 5: Burst Definition

Burst

Length Starting Column Address

Order of Accesses Within a Burst

Type = Sequential Type = Interleaved

2A0

00-1 0-1

11-0 1-0

4A1A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

8 A2A1A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full page (y) n = A0–A9/8/7

(location 0–y)

Cn, Cn + 1, Cn + 2

Cn + 3, Cn + 4...

…Cn - 1, Cn…

Not supported

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64Mb: x4, x8, x16 SDRAM

Functional Description

Reserved states should not be used as unkno wn operation or incompatibility with future

versions may result.

Figure 7: CAS Latency

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other comb i-

nations of values for M7 and M8 are reserved for future use and/or test modes. The

programmed burst length applies to both re ad and write bursts.

Test modes and reserved states should not be used because unknown operation or

incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0–M 2 applies to both read and write

bursts; when M9 = 1, the programmed burst length applies to read bursts, but write

accesses are single-location (nonburst) accesses.

Table 6: CAS La tency

Speed

Allowable Operating Frequency (MHz)

CL = 2 CL = 3

-6 – ≤166

-7E ≤133 ≤143

-75 ≤100 ≤133

CLK

T2T1 T3T0

CL = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1 T3T0

CL = 2

OUT

tOH

COMMAND NOPREAD

tAC

NOP

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64Mb: x4, x8, x16 SDRAM

Commands

Commands Truth Table 1 provides a quick reference of available command s. This is followed by a

written desc ription of each co mm and . Three additional Truth Tables appear following

“Operation” on page 21; these tables provide current state/next state information.

Notes: 1. A0–A11 define the op-code written to the mode register.

2. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.

3. A0–A9 (x4), A0–A8 (x8), or A0–A7 (x16) provide column address; A10 (HIGH) enables the

auto precharge feature (nonpersistent), while A10 (LOW) disables the auto precharge fea-

ture; BA0, BA1 dete rmine which bank is be ing read from or written to.

4. A10 (LOW): BA0, BA1 determine the bank being precharged. A10 HIGH: All banks pre-

charged and BA0, BA1 are “Don’t Care.”

5. Th is command is AUTO REFRESH if CKE is (HIGH), SELF REFRESH if CKE is LOW.

6. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except

for CKE.

7. Activa tes or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock

delay).

COMMAND INHIBIT

The command inhibit function prevents new commands from being executed by the

SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-

lected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM that is

selected (CS# is L O W). This prevents unwanted c ommands from bei ng r egister ed during

idle or wait states. Operations already in progress are not affected.

Table 7: Truth Table 1 – Commands and DQM Operation

CKE is HIGH for all commands shown except SELF REFRESH.

Name (Function) CS# RAS# CAS# WE# DQM ADDR DQs Notes

COMMAND INHIBIT (NOP) HXXXX X X

NO OPERATION (NOP) LHHHX X X

ACTIVE (Select bank and act iva t e ro w) LLHHXBank/rowX 2

READ

(Select bank and column, and start READ burst) LHLHL/H8Bank/colX 3

WRITE

(Select bank and column, and start WRITE burst) L H L L L/H8 Bank/col Valid 3

BURST TERMINATE LHHLX XActive

PRECHARGE

(Deactivate row in bank or banks) LLHLXCode X 4

AUTO REFRESH or SOFT REFRESH

(Enter self refresh mode) LLLHX X X5, 6

LOAD MODE REGISTER LLLLXOp-codeX 1

Write enable/output enable ––––L –Active7

Write inhibit/output High-Z ––––H –High-Z7

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64Mb: x4, x8, x16 SDRAM

Commands

LOAD MODE REGISTER

The mode register is loaded via inputs A0–A11. See mode register heading in “Register

Definition” on page 13. The L OAD MODE REGISTER command can only be issued whe n

all banks are idle, and a subsequent executable command cannot be issued until tMRD

is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a

subsequent access. The value on the BA0, BA1 inputs selects the bank, and the addr ess

provided on inputs A0–A11 s elec ts the row. This row remains active (or open) for

accesses until a pr ec har ge command i s issued to that bank. A precharge command must

be issued befor e opening a different row in the same bank.

READ

The READ command is used to initiate a burst r ead access to an activ e row. The value on

the BA0, BA1 inputs selects the bank, and the address pro vided on inputs A0–A9 (x4), A0–

A8 (x8), or A0–A7 (x16) selects the s tart ing column location. The value on input A10

determines whether auto pr echarge is used. If auto precharge is selected, the row being

accessed will be pr echarged at the end of the r ead burst; if auto pr echarg e is not selected,

the ro w will r emain open for subsequent accesses . R ead data appears on the DQs subject

to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was regis-

tered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM si gnal

was registered LOW, the DQs will provide valid data.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value

on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9 (x4),

A0–A8 (x8), or A0–A7 (x16) selects the starting column location. The value on input A10

determines whether auto pr echarge is used. If auto precharge is selected, the row being

accessed will be precharged at the end of the write burs t; if auto precharge is not

selected, the row will remain open for s ubsequent accesses . I nput data appearing on the

DQs is written to the memory array s ubje ct to the DQ M in put logic leve l appearing coin-

cident with the data. If a given DQM signal is registered LOW, the corresponding data

will be written to memory; if the DQM signal is r e gistered HIGH, the corr e sponding data

inputs will be ignored, and a write will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or

the open row in all banks. The bank(s) will be available for a subsequent row access a

specifie d time (tRP) after the pr echarge command is issued. Input A10 determines

whether one or all banks ar e to be prechar ged , and in the case where only one bank is to

be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as

“Don’t Care.” After a bank has been precharged, it is in the idle state and must be acti-

vated prior to any READ or WRITE commands being issued to that bank.

Auto Precharge

Auto precharge is a feature that performs the same individual-bank precharge function

described above, without r e quiring an explic it command. This is accomplishe d b y using

A10 to enable auto precharge in conjunction with a specific READ or WRITE command.

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64Mb: x4, x8, x16 SDRAM

Commands

A prechar ge of the bank/row that is addressed with the READ or WRITE command is

automatically performed upon completion of the READ or WRITE burst, except in the

full-page burst mode, where auto precharge does not apply. Auto precharge is nonper-

sistent in that it is either enabled or disabled for each individual READ or WRITE

command.

Auto precharge ensures that the precharge is initiated at the earliest valid stage within a

burst. The user must not issue another command to the same bank until the precharge

time (tRP) is completed. This is determined as if an explicit PRECHARGE command was

issued at the earliest possible time, as described for each burst type in “Operation” on

page 21.

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or full-page

bursts. The most recently re gistered READ or WRITE command prior to the BURST

TERMINATE command will be truncated, as shown in the Operation section of this data

sheet. The BURST TERMINATE co mm and does not precharge the row; the row will

remain open until a PRECHARGE command is issued.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analogous to

CAS#-BEFORE-RAS# (CBR) refresh in conv entional DRAMs. This command is nonper-

sistent, so it must be issued each time a refresh is required. All active banks must be

PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH

command should not be issued until the minimum tRP has been met after the

PRECHAR GE command as shown in the Operation section.

The addressing is generated by the internal refresh controller. This makes the address

bits “Don’t Care” during an AUTO REFRESH command. Regard less of device width, the

64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (commercial and indus-

trial) or 16ms (automotive). Providing a distributed AUTO REFRESH command every

15.625µs (commercial and industrial) or 3.906µs (automotive) will meet the refresh

requirement and ensure that each row is refreshed. Alternati vely, 4,096 AUTO REFRESH

commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms

(commercial and industrial) or 16ms (automotive).

SELF REFRESH

The SELF REFRESH co mm and can be use d to retain data in the SDRAM, even if the rest

of the system is powered down. When in the self r efresh mode, the SDRAM retains data

without external clocking.

The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE

is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the

SDRAM become “Don’t Care,” with the exception of CKE, which must remain LO W.

After self refr esh mode is engaged, the SDRAM provides its own internal clocking,

causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self

refresh mode for a minimum period equal to tRAS and may remain in self refresh mode

for an indefinite period beyond that.

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64Mb: x4, x8, x16 SDRAM

Commands

The procedur e for exit ing self r efresh requir es a seque nce of commands. F irst, CLK m ust

be stable (stable clock is defined as a signal cycling within timing constraints specified

for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SD RA M mus t

have NOP commands issued (a minimum of two clocks ) for tXSR, because time is

required for the completion of any internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every

15.625µs or less, as both SELF REFRESH and AUTO REFRESH utilize the row refresh

counter.

Self refresh is not supported on automotive temperature devices.

Operation

Bank/Row Activation

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row

in that bank must be “opened.” This is accomplished via the ACTIVE command, which

selects both the bank and the row to be activated (see Figure 8).

After opening a ro w (issuing an A CTIVE command), a RE AD or WRITE command may be

issued to that row, subject to the tRCD spec ification. tRCD (MIN) should be divided by

the clock period and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVE command on which a READ or WRITE command can be

entered. For example, a tRCD specifi cation of 20ns with a 125 MHz clock (8ns period)

results in 2.5 clocks, rounded to 3. This is reflected in Figure9 on page 22, which covers

any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to conv ert other

specificati o n lim i ts from tim e units to clock cycles).

A subsequent ACTIVE command to a differ ent row in the same bank can only be issued

after the previous active row has been “closed” (precharged). The minimum time

interval between successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is

being accessed, which resul ts in a r eduction of total r o w-access o verhead. The minimum

time interval between successive ACTIVE commands to different banks is defined by

tRRD.

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64Mb: x4, x8, x16 SDRAM

Commands

Figure 8: Activating a Specific Row in a Specific Bank

Figure 9: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK ≤ 3

READs

READ bursts are initiated with a READ command, as shown in Fi gure 10 on page 23.

The starting column and bank addresses are pr ovided with the READ command, and

auto precharge is either enabled or disabled for that burst access. If auto precharge is

enabled, the row being accessed is precharged at the completion of the burst. For the

generic READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will

be available following the CL after the READ command. Each subsequent data-out

element will be v ali d by the next positive clock edge. Figure 11 on page 24 shows g ener al

timing for each possible CL setting.

Upon completion of a burst, assuming no other commands have been initiated, the DQs

will go High-Z . A full-page burst will continue until terminated. (At the end of the page , it

will wrap to column 0 and continue.)

CS#

WE#

CAS#

RAS#

CKE

CLK

A0–A10, A11

ROW

ADDRESS

DON’T CARE

HIGH

BA0, BA1

BANK

ADDRESS

CLK

T2T1 T3T0

COMMAND NOPACTIVE READ or

WRITE

NOP

RCD (MIN)

tRCD (MIN) +0.5 tCK

tCK tCK tCK

DON’T CARE

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64Mb: x4, x8, x16 SDRAM

Commands

Data from any READ burst may be truncated with a subsequent READ com ma nd, and

data from a fixed-length READ burst may be immediately followed by data from a READ

command. In either case, a continuous flow of data can be maintained. The first data

element from the new burst follows either the last element of a completed burst or the

last desired data element of a longer burst which is being truncated.

The new READ command should be issued x cycles before the clock edge at whic h the

last desired data element is valid, where x = CL -1. This is shown in Figure12 on page 25

for CL = 2 and CL = 3; data element n + 3 is either the last of a burst of four or the last

desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore

does not re quire the 2n rule associated with a prefetch architecture. A READ command

can be initiated on any clock cycle following a previous READ command. Full-speed

random read accesses can be performed to the same bank, as shown in Figure 13 on

page 26, or each subsequent READ may be performed to a different bank.

Figure 10: READ Command

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A0–A9: x4

A0–A8: x8

A0–A7: x16

A10

BA0, BA1

DON’T CARE

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A11: x4

A9, A11: x8

A8, A9, A11: x16

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64Mb: x4, x8, x16 SDRAM

Commands

Figure 11: CAS Latency

CLK

T2T1 T3T0

CL = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1 T3T0

CL = 2

OUT

tOH

COMMAND NOPREAD

tAC

NOP

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64Mb: x4, x8, x16 SDRAM

Commands

Figure 12: Consecutive READ Bursts

Note: Each READ command may be to any bank. DQM is LOW.

DON’T CARE

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ

X = 1 cycle

CAS Latency = 2

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ NOP

X = 2 cycles

CAS Latency = 3

TRANSITIONING DATA

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64Mb: x4, x8, x16 SDRAM

Commands

Figure 13: Random READ Accesses

Note: Each READ command may be to any bank. DQM is LOW.

Data from any READ burst may be truncated with a subsequent WRITE command, and

data from a fixed-length READ burs t may be immediately followed by data from a

WRITE command (subject to bus turnaround limitations). Th e WRI TE burst may be

initiated on the clock edge immediately following the last (or last desired) data element

from the READ burst, provided that I/O contention can be avoided. In a given system

design, ther e may be a possibility that the device driving the input data will go Low-Z

before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur

between the last read data and the WRITE command.

The DQM input is used to avoid I/O contention, as shown in Figures14 and 15 on

page 27. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE

command (DQM latency is two clocks for output buffers) to suppress data-out from the

READ. Once the WRITE command is registered, the DQs will go High-Z (or rema in

High-Z), regardless of the state of the DQM signal, provided the DQM was active on the

clock just prior to the WRITE command that truncated the READ command. If not, the

second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in,

then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.

CLK

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP

BANK,

COL n

DON’T CARE

OUT

READ READ READ NOP

BANK,

COL aBANK,

COL xBANK,

COL m

CLK

OUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

OUT

READ READ READ NOP

BANK,

COL aBANK,

COL xBANK,

COL m

CAS Latency = 2

CAS Latency = 3

TRANSITIONING DATA

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64Mb: x4, x8, x16 SDRAM

Commands

The DQM signal must be de-asserted prior to the WRITE command (DQM latency is

zero clocks for input buffers) to ensure that the written data is not masked. Figure 14

shows the case where the clock frequency allows for bus contention to be avoided

without adding a NOP cycle, and Figure15 shows the case where the additional NOP is

needed.

Figure 14: READ-to-WRITE

Note: CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE

command may be to any bank. If a burst of one is used, then DQM is not required.

Figure 15: READ-to-WRITE With Extra Clock Cycle

Note: CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE

command may be to any bank.

DON’T CARE

READ NOP NOP WRITE

NOP

CLK

T2T1 T4T3T0

DQM

DQ DOUT n

COMMAND

DIN b

ADDRESS BANK,

COL nBANK,

COL b

TRANSITIONING DATA

DON’T CARE

READ NOP NOPNOP NOP

DQM

CLK

DQ D

OUT

T2T1 T4T3T0

COMMAND

ADDRESS BANK,

COL n

WRITE

BANK,

COL b

TRANSITIONING DATA

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Commands

A fixed-length READ burst may be followed by, or truncated with, a PRECHAR GE

command to the same bank (provided that auto pr echarge was not activated), and a full-

page burst may be truncated with a PRECHARGE command to the same bank. The

PRECHAR GE command should be issued x cycles before the clock e dge at which the last

desired data element is valid, where x = CL -1. This is shown in Figure16 for each

possible CL; data element n + 3 is eithe r the last of a burst of four or the last desired of a

longer burst. Following the PRECHARGE command, a subsequent command to the

same bank cannot be issued until tRP is met. Note that part of the row precharge time is

hidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to completion, a PRECHARGE

command issued at the optimum time (as desc ribed abov e) provi des the same operation

that would result from the same fixed-length burst with auto precharge. The disadvan-

tage of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command; the advantage of the

PRECHARG E command is that it can be used to truncate fixed-leng th or full-page bursts .

Full-page READ bursts can be truncated with the BURST TERMINATE command, and

fixed-length READ bursts may be truncated with a BURST TERMINATE command,

provided that auto precharge was not activated. The BURST TERMINATE command

should be issued x cycles before the clock edge at which the last desired data element is

valid, where x = CL = -1. This is shown in Figure17 on page 29 for each possible CL; data

element n + 3 is the last desired data element of a longer burst.

Figure 16: READ-to-PRECHARGE

Note: DQM is LOW.

CLK

DQ D

OUT

T2 T1 T4 T3 T6 T5 T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

PRECHARGE NOP

DON’T CARE

CLK

DQ D

OUT

T2 T1 T4 T3 T6 T5 T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

PRECHARGE NOP

X = 1 cycle

CL = 2

CL = 3

X = 2 cycles

TRANSITIONING DATA

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Commands

Figure 17: Terminating a READ Burst

Note: DQM is LOW.

WRITEs

WRITE bursts are initiated with a WRITE command, as shown in Figure 18 on page 30.

The starting column and bank addresses are pro vided with the WRITE command, and

auto prec harge i s either enabled or disabled for that acc ess . If auto pr e charge is enab led,

the row being accessed is precharged at the completion of the burst. F or the generic

WRITE commands us ed in the fol lowing illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element will be registered coincident with

the WRITE command. Subsequent data elements will be registered on each successive

positive clock edge. Upon completion of a fixed-le ngth burst, assuming no other

commands have been initiated, the DQs will remain High-Z, and any additional input

data will be ignored (see Figure19 on page 30). A full-page burst will continue until

terminated. (At the end of the page, it will wrap to column 0 and continue.)

Data for any WRITE burst may be truncated with a subsequent WRITE command, and

data for a fixed-length WRI TE burst may be immediately followed by data for a WRITE

command. The new WRITE command can b e issued on any c lock follo wi ng the pr evious

WRITE command, and the data provided coincident with the new command applies to

the new command.

DON’T CARE

CLK

OUT

T2 T1 T4 T3 T6 T5 T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

BURST

TERMINATE

ACTIVE

t RP

CLK

OUT

T2 T1 T4 T3 T6 T5 T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

BURST

TERMINATE

ACTIVE

t RP

X = 1 cycle

CL = 2

CL = 3

X = 2 cycles

BANK a,

COL n BANK a,

ROW

BANK

(a or all)

BANK a,

COL n BANK a,

ROW

BANK

(a or all)

TRANSITIONING DATA

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Commands

An example is sho wn in F igur e 20 on page 31. Data n + 1 is either the last of a burs t of two

or the last desir ed of a longer bur st. The 64Mb SDRAM uses a pipelined ar chitectu r e and

therefore does not require the 2n rule associated with a prefetch architecture. A WRITE

command can be initiat ed on any clock cycl e fol lowing a previous WRITE command.

Full-speed random write acce sses within a page can be performed to the same bank, as

shown in Figure21 on page 32, or each subsequent WRITE may be performed to a

different bank.

Figure 18: WRITE Command

Figure 19: WRITE Burst

Note: NOTE: BL = 2. DQM is LOW.

DON’T CARE

VALID ADDRESS

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A10

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

A0–A9: x4

A0–A8: x8

A0–A7: x16

A11: x4

A9, A11: x8

A8, A9, A11: x16

BA0, BA1

BANK

ADDRESS

CLK

DIN

T2T1 T3T0

COMMAND

ADDRESS

NOP NOP

DON’T CARE

WRITE

DIN

n + 1

NOP

BANK,

COL n

TRANSITIONING DATA

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Commands

Figure 20: WRITE-to-WRITE

Note: DQM is LOW. Each WRITE command may be to any bank.

Data for any WRITE burst may be truncated with a subsequent READ command, and

data for a fixed-length WRITE burst may be immedi ately follo wed by a subse quent READ

command. Af ter the REA D com mand is registered, the data inputs will be ignored, and

writes will not be executed. An example is shown in Figure 22 on page 32. Data n + 1 is

either the last of a burst of two or the last desire d of a longer burst.

Data for a fixed-length WRITE burst may be followed by, or truncated with, a

PRECHARGE command to the same bank (provided that auto pr echarge was not acti-

vated), and a full-page WRITE burst may be truncated with a PRECHARGE command to

the same bank. The PRECHARGE command should be issued tWR after the clock edge at

which the last desired input data element is registered. The auto precharge mode

requires a tWR of at least one clock plus time, regardless of frequency. In addition, when

truncating a WRITE burst, the DQM signal must be used to mask input data for the clock

edge prior to, and the clock edge coincident with, the PRECHARGE command. An

example is shown in F igur e23 on page 33. Data n + 1 is either the last of a burst of two or

the last desir ed of a longer burst. Following the PRECHARGE command, a subsequent

command to the same bank cannot be issued until tRP is met.

In the case of a fixed-length burst being executed to completion, a PRECHARGE

command issued at the optimum time (as desc ribed abov e) provi des the same operation

that would result from the same fixed-length burst with auto precharge. The disadvan-

tage of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command; the advantage of the

PRECHAR GE command is that it can be used to truncate fixed-length or full-page bursts.

CLK

T2T1T0

COMMAND

ADDRESS

NOPWRITE WRITE

BANK,

COL nBANK,

COL b

n + 1 D

DON’T CARE

TRANSITIONING DATA

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Commands

Figure 21: Random WRITE Cycles

Note: Each WRITE command may be to any bank. DQM is LOW.

Figure 22: WRITE-to-READ

Note: The WRITE command may be to any bank, and the READ command may be to any bank.

DQM is LOW. CL = 2 for illustrat ion.

DON’T CARE

CLK

DIN

T2T1 T3T0

COMMAND

ADDRESS

WRITE

BANK,

COL n

DIN

aDIN

xDIN

WRITE WRITE WRITE

BANK,

COL aBANK,

COL xBANK,

COL m

TRANSITIONING DATA

DON’T CARE

CLK

T2T1 T3T0

COMMAND

ADDRESS

NOPWRITE

BANK,

COL n

n + 1 D

OUT

READ NOP NOP

BANK,

COL b

NOP

OUT

b + 1

T4 T5

TRANSITIONING DATA

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Commands

Figure 23: WRITE-to-PRECHARGE

Note: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.

Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE

command. When truncating a WRITE burst, the inpu t data applied coincident with the

BURST TERMINATE command will be ignored. The last data written (provided that

DQM is LOW at that time) will be the input data applied one clock previous to the

BURST TERMINATE command. This is shown in Figur e24 on page 34, where data n is

the last desired data element of a longer burst.

PRECHARGE

The PRECHAR GE command (Figur e25 on page 34) is used to deactivate the open row in

a particular bank or the open row in all banks. The bank(s) will be available for a subse-

quent row access some specified time (tRP) after the PRECHARGE command is issued.

Input A10 determines whether one or all banks are to be precharged, and in the case

where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all

banks are to be pr echarged, inputs BA0, BA1 ar e tr eated as “ Don’t Car e .” After a bank has

been pre charged, it is in the idle state and must be activated prior to any READ or WRITE

commands being issued to that bank.

DON’T CARE

DQM

CLK

T2T1 T4T3T0

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

n + 1

ACTIVE

tRP

BANK

(a or all)

BANK a,

ROW

DQM

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

n + 1

ACTIVE

tRP

BANK

(a or all)

BANK a,

ROW

NOP

tWR @ tCLK ≥ 15ns

tWR = tCLK < 15ns

TRANSITIONING DATA

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Commands

Power-Down

Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND

INHIBIT when no accesses are in progress. If power-down occurs when all banks are

idle, this mode is referred to as precharge power -down; if power-down occurs when

there is a ro w activ e in any bank, this mode is referred to as active power-down. Entering

power-down deactivates the input and output buffers, excluding CKE, for maximum

power savings while in standby. The device may not remain in the power-down state

longer than the refresh period (tREF or tREFAT) since no refresh operations are

performed in this mode.

The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE

HIGH at the desired clock edge (meeting tCKS). See Figure26 on page35.

Figure 24: Terminating a WRITE Burst

Note: DQMs are LOW.

Figure 25: PRECHARGE Command

DON’T CARE

CLK

T2T1T0

COMMAND

ADDRESS

BANK,

COL n

WRITE BURST

TERMINATE NEXT

COMMAND

(ADDRESS)

(DATA)

TRANSITIONING DATA

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

DON’T CARE

HIGH

All Banks

Bank Selected

A0–A9

BA0,1 BANK

ADDRESS

VALID ADDRESS

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Commands

Figure 26: Power-Down

Clock Suspend

The clock suspend mode occurs when a column access/burst is in progress and CKE is

registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”

the synchronous logic.

For each positive clock edge on which CKE is sampled LOW, the next internal positive

clock edge is suspended. Any command or data pr esent on the input pins at the time of a

suspended internal clock edge is ignored; any data present on the DQ pins remains

driven; and burst counters are not incremented, as long as the clock is sus pen ded. (See

examples in Figures27 and 28 on page 36.)

Clock suspend mode is exited by registering CKE HIGH; the internal clock and related

operation will resume on the subsequent positive clock edge.

Burst Read/Single Write

The burst read/single write mode is entered by progr a mming the write burst mode bit

(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the

access of a single column location (burst of one), regardless of the programmed burst

length. READ commands access columns according to the programmed burst length

and sequence, just as in the normal mode of operation (M9 = 0).

DON’T CARE

tRAS

tRCD

tRC

All banks idle Input buffers gated off

Exit power-down mode.

()()

tCKS > tCKS

COMMAND

NOP ACTIVE

Enter power-down mode.

NOP

CLK

CKE

()()

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Commands

Figure 27: Clock Suspend During WRITE Burst

Figure 28: Clock Suspend During READ Burst

Note: For this example, CL = 2, BL = 4 or greater, and DQM is LOW.

Concurrent Auto Precharge

An access command (READ or WRITE) to another bank while an access command with

auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM

supports con current auto precharge. Micron SDRAMs support concurrent auto

precharge. Four cases where concurrent auto precharge occurs are defined below.

DON’T CARE

COMMAND

ADDRESS

WRITE

BANK,

COL n

NOPNOP

CLK

T2T1 T4T3 T5T0

CKE

INTERNAL

CLOCK

NOP

n + 1 D

n + 2

TRANSITIONING DATA

DON’T CARE

CLK

DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

DOUT

n + 1 DOUT

n + 2 DOUT

n + 3

CKE

INTERNAL

CLOCK

NOP

TRANSITIONING DATA

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64Mb: x4, x8, x16 SDRAM

Commands

READ with Auto Precharge

• Interrupted by a READ (with or without auto precharge ): A READ to bank m will inter-

rupt a READ on bank n, CL later. The precharge to bank n will be gin when the READ

to bank m is registered (Figure29 on page 37).

• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a READ on bank n when register ed. DQM s hould be us ed two clocks prior to

the WRITE command to prevent bus conten tion. The precharge to bank n will begin

when the WRITE to bank m is registered (Figure30 on page 38).

WRITE with Auto Precharge

• Interrupted by a READ (with or without auto precharge ): A READ to bank m will inter-

rupt a WRITE on bank n when registered, with the data-out appearing CL later. The

precharge to bank n will begin after tWR is met, where tWR begins when the READ to

bank m is registered. The last valid WRITE to bank n will be data-in registered one

clock prior to the READ to bank m (Figure31 on page 38).

• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a WRITE on bank n when registered. The precharge to bank n will begin

after tWR is met, where tWR begins when the WRITE to bank m is registered. The last

valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank

m (Figure32 on page 39).

Figure 29: READ With Auto Precharge Interrupted by a READ

Note: DQM is LOW.

DON’T CARE

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

READ - AP

BANK nNOP NOPNOPNOP

OUT

a + 1 D

OUT

d + 1

NOP

BANK n

CAS Latency = 3 (BANK m)

BANK m

ADDRESS

Idle

NOP

BANK n,

COL aBANK m,

COL d

READ - AP

BANK m

Internal

States t

Page Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active READ with Burst of 4 Precharge

RP - BANK ntRP - BANK m

CAS Latency = 3 (BANK n)

TRANSITIONING DATA

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Commands

Figure 30: READ With Auto Precharge Interrupted by a WRITE

Notes: 1. DQM is HIGH at T2 to prevent DOUT a +1 from contending with DIN d at T4.

Figure 31: WRITE With Auto Precharge Interrupted by a READ

Notes: 1. DQM is LOW.

CLK

DQ D

OUT

T2T1 T4T3 T6T5T0

COMMAND NOPNOPNOPNOP

d + 1

d + 2 D

d + 3

NOP

BANK n

BANK m

ADDRESS

Idle

NOP

DQM

BANK n,

COL aBANK m,

COL d

WRITE - AP

BANK m

Internal

States

Page

Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active WRITE with Burst of 4 Write-Back

RP -

BANK

ntWR -

BANK

CAS Latency = 3 (BANK n)

READ - AP

BANK n

DON’T CARETRANSITIONING DATA

DON’T CARE

CLK

T2T1 T4T3 T6T5T0

COMMAND WRITE - AP

BANK nNOPNOPNOPNOP

a + 1

NOP NOP

BANK n

BANK m

ADDRESS

BANK n,

COL aBANK m,

COL d

READ - AP

BANK m

Internal

States t

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active READ with Burst of 4

ttRP - BANK m

OUT

d + 1

CAS Latency = 3 (BANK m)

RP - BANK n

WR - BANK n

TRANSITIONING DATA

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Commands

Figure 32: WRITE With Auto Precharge Interrupted by a WRITE

Notes: 1. DQM is LOW.

Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous

clock edge.

2. Curre nt state is the state of the SDRAM immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of

COMMANDn.

4. All states an d se quences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for

clock edge n + 1 (provided that tCKS is met).

6. Exiting self refresh at clock edge n will put th e device in th e all banks idle state after tXSR is

met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring

during the tXSR period. A minimum of two NOP commands must be provided during tXSR

period.

7. After exiting clock suspend at clock edge n, the device will re sume op eration an d recogn ize

the next command at clock edge n + 1.

Table 8: Truth Table 2 – CKE

Notes 1–4 apply to entire table

CKEn-1 CKEnCurrent State COMMANDnACTIONnNotes

L L Power-Down X Maintain power-down

Self refresh X Maintain self refresh

Clock suspend X Maintain clock suspend

L H Power-Down COMMAND INHIBIT or NOP Exit power-down 5

Self refresh COMMAND INHIBIT or NOP Exit self refresh 6

Clock suspend X Exit clock suspend 7

H L All banks idle COMMAND INHIBIT or NOP Power-Down entry

All banks idle AUTO REFRESH Self refresh entry

Reading or writing WRITE or NOP Clock suspend entry

H H See Table 9 on page 40

DON’T CARE

CLK

T2T1 T4T3 T6T5T0

COMMAND

WRITE - AP

BANK nNOPNOPNOPNOP

d + 1

a + 1 D

a + 2

d + 2 D

d + 3

NOP

BANK n

BANK m

ADDRESS

NOP

BANK n,

COL aBANK m,

COL d

WRITE - AP

BANK m

Internal

States

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active WRITE with Burst of 4 Write-Back

WR - BANK ntRP - BANK ntWR - BANK m

TRANSITIONING DATA

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Commands

Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Tabl e 8 on page 39) and

after tXSR has been met (if the previous state was self refresh).

2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank,

and the commands shown are those allowed to be issued to that bank when in that state.

Exceptions ar e covered in the notes below.

3. Current state definitions:

4. The following states must not be interrupted by a command issued to the same bank. COM-

MAND INHIBIT or NOP commands or allowable commands to the other bank should be

issued on any clock edge occurring during these states. Allowable commands to the other

bank are determi ned by its current st ate and Table 9 and according to Tabl e 10 on page 42.

5. The following states must not be interrupted by any executable command; COMMAND

INHIBIT or NOP commands must be applied on each positive clock edge during these states.

Table 9: Truth Table 3 – Current State Bank n, Command to Bank n

(Notes 1–6 apply to entire table; notes appear below and on next pag e)

Current State CS# RAS# CAS# WE# Command (Action) Notes

Any HXXX

COMMAND INHIBIT (NOP/continue pr evious operation)

LHHH

NO OPERATION (NOP/continue previous operation)

Idle L L H H ACTIVE (Select and activate row)

LLLH

AUTO REFRESH 7

LLLL

LOAD MODE REGISTER 7

LLHL

PRECHARGE 11

Row activeLHLH

READ (Select column and start READ burst) 10

LHLL

WRITE (Select column and start WRITE burst) 10

LLHL

PRECHARGE (Deactivate row in bank or banks) 8

Read

(auto

precharge

disabled)

LHLH

READ (Select column and start new READ burst) 10

LHLL

WRITE (Select column and start WRITE burst) 10

LLHL

PRECHARGE (Truncate READ burst, start precharge) 8

LHHL

BURST TER MINATE 9

Write

(auto

precharge

disabled)

LHLH

READ (Select column and start READ burst) 10

LHLL

WRITE (Select column and start new WRITE burst) 10

LLHL

PRECHARGE (Truncate WRITE burst, start precharge) 8

LHHL

BURST TER MINATE 9

Idle: The bank has been precharged, and tRP has been met.

Row active: A row in the bank has been activated, and tRCD has been met . No data

bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has

not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has

not yet terminated or been terminated.

Precharging: Starts with registration of a PRECHARGE comm an d and ends when

tRP is met. After tRP is met, the bank will be in the idle state.

Row activating: Starts with registration of an ACTIVE command and ends when tRCD

is met. After tRCD is met, the bank will be in the row active state.

Read w/auto

precharge enabled: Starts with registration of a READ command with auto precharge

enabled and ends when tRP has been met. After tRP is met, the bank

will be in the idle state.

Write w /au to

precharge enabled: Starts with registration of a WRITE command with auto precharge

enabled and ends when tRP has been met. After tRP is met, the bank

will be in the idle state.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when

tRC is met. After tRC is met, the SDRAM will be in the all banks idle state.

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64Mb: x4, x8, x16 SDRAM

Commands

6. All states an d se quences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank -specific; if all banks are to be precharged, all must be in a valid

state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-

less of bank.

10. RE ADs or WRITEs listed in the Command (Action) column include READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

Accessing mode

when tMRD has been met. After tMRD is met, the SDRAM will be in the all

banks idle state.

Prechargi ng all: Starts with registration of a PRECHARGE ALL command and ends when

tRP is met. After tRP is met, all banks will be in the idle state.

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64Mb: x4, x8, x16 SDRAM

Commands

Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Tabl e 8 on page 39) and

after tXSR has been met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted; i.e., the current state is

for bank n and the commands shown are those allowed to be issued to bank m (assuming

that bank m is in such a state that the given command is allowable). Exceptions are covered

in the notes below.

3. Current state definitions:

4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued

when all banks are idle.

5. A BURST TERMINATE command cannot be issued to anot her bank; it applies to the bank

represented by the current state only.

Table 10: Truth Table 4 – Current State Bank n, Command to Bank m

(Notes 1–6 apply to entire table; notes appear below and on next pag e)

Current State CS# RAS# CAS# WE# Command (Action) Notes

Any HXXX

COMMAND INHIBIT (NOP/continue pr evious operation)

LHHH

NO OPERATION (NOP/continue previous operation)

Idle XXXX

Any command otherw ise allowed to bank m

Row

activating,

active, or

precharging

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start READ burst) 7

LHLL

WRITE (Select column and start WRITE burst) 7

LLHL

PRECHARGE

Read

(auto

precharge

disabled)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start new READ burst) 7, 10

LHLL

WRITE (Select column and start WRITE burst) 7, 11

LLHL

PRECHARGE 9

Write

(auto

precharge

disabled)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start READ burst) 7, 12

LHLL

WRITE (Select column and start new WRITE burst) 7, 13

LLHL

PRECHARGE 9

Read

(with auto

precharge)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start new READ burst) 7, 8, 14

LHLL

WRITE (Select column and start WRITE burst) 7, 8, 15

LLHL

PRECHARGE 9

Write

(with auto

precharge)

LLHH

ACTIVE (Select and activate row)

LHLH

READ (Select column and start READ burst) 7, 8, 16

LHLL

WRITE (Select column and start new WRITE burst) 7, 8, 17

LLHL

PRECHARGE 9

Idle: The bank has been precharged, and tRP has been met.

Row active: A row in the bank has been activated, and tRCD has been met . No

data bursts/accesses and no register accesse s are in progress.

Read: A READ burst has been initiated, with au t o pr echarge d i s a bled, and

has not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and

has not yet terminated or been terminated.

Read w/auto

precharge enabled: Starts with registration of a READ command with auto precharge

enabled, and ends when tRP has been met. After tRP is met, the

bank will be in the idle state.

Write w /au to

precharge enabled: Starts with registration of a WRITE command with auto precharge

enabled, and ends when tRP has been met. After tRP is met, the

bank will be in the idle state.

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Commands

6. All states an d se quences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command (Act ion ) col umn incl ud e READs or

WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.

8. Concurrent Auto precharge: Bank n wi ll initiate the auto precharge command when its

burst has been interrupted by bank m’s burst.

9. Burst in bank n continues as in itiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 12 on

page 25).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-

charge), th e WR ITE to bank m will interrupt th e READ on bank n when registered

(Figures 14 and 15 on page 27). DQM should be used one clock prior to the WRITE com-

mand to prevent bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 22

on page 32), with the data-out appearing CL later. The last valid WRITE to bank n will be

data-in registered one clock prior to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-

charge), th e WR ITE to bank m will interru pt th e WRI T E on bank n when registered

(Figure 20 on page 31). The last valid WRITE to bank n will be data-in registered one clock

prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),

the READ to bank m will interrupt the READ on bank n, CL later. The precharge to bank n

will begin when the READ to bank m is registered (Figure 29 on page 37).

15. For a READ with auto prec harge interrupted by a WRITE (with or wit hout auto precharge),

the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be

used two clocks prior to the WRITE command to prevent bus contention. The precharg e to

bank n will begi n when the WRITE to bank m is registered (Figur e 30 on page 38).

16. For a WRITE with auto precharge interrupted by a REA D (with or without auto precharge),

the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out

appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins

when the READ to bank m is registered. The last valid WRITE to bank n will be data-in regis-

tered one clock prior to the READ to bank m (Figure 31 on page 38).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),

the WRITE to bank m will interrupt the WRITE on bank n when registered. The precharge to

bank n will begi n after tWR is met, where tWR begins when the WRITE to bank m is regis-

tered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to

bank m (Figure 32 on page 39).

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Electrical Specifications

Stresses great er than those listed in Table 11 may cause permanent damage to the

device. This is a stress rating only, and functional operation of the device at these or any

other conditions above those indicated in the operational sections of this specification is

not implied. Exposure to absolute maximum rating condi tions for extended periods may

affect reli ability.

Temperature and Thermal Impedance

I t is imperative that the SDRAM device’s temperature specifications, shown in Figure12

on page 45, be maintained to ensure the junction temperatur e is in the proper operating

range to meet data sheet specifications. An important step in maintaining the proper

junction temperature is using the device’s thermal impedances correctly. The thermal

impedances are listed in Tabl e 13 on page 45 for the appl ic ab le die revision and pack-

ages being made available. The se thermal impedance values v a ry according to the

density, package, and particular design used for each device.

Incorr ectly using thermal impedances can produce significant errors. Read Micron tech-

nical note, TN-00-08, “Thermal Applications,” prior to using the thermal impedances

listed in Table 13. To ensure the compatibility of current and future designs, contact

Micron Applications Engineering to confirm the rmal impedance values.

The SDRAM device’s safe junction temperature range can be maintained when the TC

specification is not exceede d. I n applications wher e the device's amb ient temperatur e is

too high, use of forced air and/or heat sinks may be required to satisfy the case tempera-

ture specifications.

Table 11: Absolute Maximum Ratings

Parameter Min Max Units

Voltage on VDD, VDDQ supply relative to V SS –1V +4.6 V

Voltage on inputs, NC or I/O pins relative to VSS –1V +4.6 V

Operating temperature

TA (commercial)

TA (industrial)

TA (automotive)

–40

+85

+105

°C

Storage temperature (plastic) –55 +150 °C

Power dissipation –1W

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Electrical Specifications

Notes: 1. MAX operating case temperature, TC, is measured in the center of the package on the top

side of the device , as shown in Figure 33 and Figure 34 on page 46.

2. Device functionality is not guaranteed if the device exceeds maximum TC during operation.

3. All temperature specific ations must be satisfied.

4. The cas e temperature should be measured by gluing a thermocouple to the top center of

the component. This should be done with a 1mm bead of conductive epoxy, as defined by

the JEDEC EIA/JESD51 standards. Care should be taken to ensure the thermocouple bead is

touching the case.

5. Operating ambient temperature surroundi ng the package.

Notes: 1. For designs expected to last beyond the die revision listed, contact Micron Applications

Engineering to confirm thermal impedance values.

2. Thermal resistance data is sampled from multiple lots, and the values should be viewed as

typical.

3. These are estimates; actual results may vary.

Table 12: Temperature Limits

Parameter Symbol Min Max Units Notes

Operating case temperature:

Commercial

Industrial

Automotive

TC0

–40

105

°C 1, 2, 3, 4

Junction temperature:

Commercial

Industrial

Automotive

TJ0

–40

110

°C 3

Ambient temperature:

Commercial

Industrial

Automotive

TA0

-40

105

°C 3, 5

Peak reflow temperature TPEAK –260°C

Table 13: Thermal Impedance Simulated Values

Die Revision Package Substrate

θ JA (°C/W)

Airflow =

0m/s

θ JA (°C/W)

Airflow =

1m/s

θ JA (°C/W)

Airflow =

2m/s θ JB (°C/W) θ JC (°C/W)

G54-pin

TSOP 4-layer 70.5 61.2 57.2 54.6 13.7

54-ball

VFBGA 2-layer 80.6 67.7 61.5 46.1 4.9

4-layer 64 57.1 53.5 45.7

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Electrical Specifications

Figure 33: Example Temperature Test Point Location, 54-Pin TSOP: Top View

Figure 34: Example Temperature Test Point Location, 54-Ball VFBGA: Top View

22.22mm

11.11mm

Test point

10.16mm

5.08mm

8.00mm

4.00mm

Test point

4.00mm

8.00mm

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Electrical Specifications

Table 14: DC Electrical Characteristics and Operating Conditions

Notes 1, 5, 6 apply to entire table; notes appear on pages 50 and 51; VDD, VDDQ = +3.3V ±0.3V

Parameter/Condition Symbol Min Max Units Notes

Supply voltage VDD, VDDQ3 3.6 V

Input high voltage: Logic 1; All inputs VIH 2VDD + 0.3 V 22

Input low voltage: Logic 0; All inputs VIL –0.3 0.8 V 22

Input leakage current:

Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) II–5 5 µA

Output leakage current: DQs are disabled; 0V ≤ VOUT ≤ VDDQIOZ –5 5 µA

Output levels:

Output high voltage (Iout = –4mA)

Output low voltage (Iout = 4mA) VOH 2.4 – V

VOL –0.4V

Table 15: IDD Specifications and Conditions

Notes 1, 5, 6 apply to entire table; notes appear on pages 50 and 51; VDD, VDDQ = +3.3V ±0.3V

Parameter/Condition Symbol

Max

Units Notes-6 -7E -75

Operating current: active mode;

Burst = 2; READ or WRITE; tRC ≥ tRC (MIN) IDD1 150 125 115 mA 3, 18, 19,

Standby current: Power-down mode;

All banks idle; CKE = LOW IDD2222mA32

Standby current: Active mode;

CKE = HIGH; CS# = HIGH; All banks active after tRCD met;

No accesses in progress

IDD3 60 45 45 mA 3, 12, 19,

Operating current: Burst mode;

Page burst; READ or WRITE; All banks active IDD4 180 150 140 mA 3, 18, 19,

Auto refresh current:

CKE = HIGH; CS# = HIGH

tRFC = tRFC (MIN) IDD5 250 230 210 mA 3, 12, 18,

19, 32, 33

tRFC = 15.625µs IDD6333

tRFC = 3.906µs (AT) IDD6666

Self refresh current:

CKE ≤ 0.2V Standard IDD7111mA 4

Low power (L) 0.5 0.5 0.5

Table 16: TSOP Capacitance

Note 2 applies to entire table; notes appear on pages 50 and 51

Parameter Symbol Min Max Units Notes

Input capacitance: CLK CI12.53.5pF 29

Input capacitance: All other input-only pin s CI22.53.8pF 30

Input/output capacitance: DQs CIO 4.0 6.0 pF 31

Table 17: VFBGA Capacitance

Note 2 applies to entire table; notes appear on pages 50 and 51

Parameter Symbol Min Max Units Notes

Input capacitance: CLK CI1TBDTBDpF 29

Input capacitance: All other input-only pin s CI2TBDTBDpF 30

Input/output capacitance: DQs CIO TBD TBD pF 31

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Electrical Specifications

Table 18: Electrical Characteristics and Recommended AC Operating Conditions

Notes 5, 6, 8, 9, 11, 34 apply to entire table; notes appear on pages 50 and 51; VDD, VDDQ = +3.3V ±0.3V

AC Characteristics

Symbol

-6 -7E -75

Units NotesParameter Min Max Min Max Min Max

Access time from CLK

(positive edge) CL = 3 tAC(3) – 5.5 – 5.4 5.4 ns 27

CL = 2 tAC(2)–––5.4–6ns

Address hold time tAH 1 – 0.8 – 0.8 – ns

Address setup time tAS 1.5 – 1.5 – 1.5 – ns

CLK high-level width tCH 2.5 – 2.5 – 2.5 – ns

CLK low-level width tCL 2.5 – 2.5 – 2.5 – ns

Clock cycle time CL = 3 tCK(3) 6 – 7 – 7.5 – ns 23

CL = 2 tCK(2) – – 7.5 – 10 – ns 23

CKE hold time tCKH1 –0.8–0.8– ns

CKE setup time tCKS 1.5 – 1.5 – 1.5 – ns

CS#, RAS#, CAS#, WE#, DQM hold

time

tCMH1 –0.8–0.8– ns

CS#, RAS#, CAS#, WE#, DQM setup

time

tCMS 1.5 – 1.5 – 1.5 – ns

Data-in hold time tDH 1 – 0.8 – 0.8 – ns

Data-in setup time tDS 1.5 – 1.5 – 1.5 – ns

Data-out High-Z time CL = 3 tHZ(3) – 5.5 – 5.4 – 5.4 ns 10

CL = 2 tHZ(2) – – – 5.4 – 6 ns 10

Data-out Low-Z time tLZ1–1–1–ns

Data-out hold time (load) tOH2–3–3–ns

Data-out hold time (no load) tOHN 1.8 – 1.8 – 1.8 – ns 28

ACTIVE-to-PRECHARGE command tRAS 42 120,000 37 120,000 44 120,000 ns

ACTIVE-to-ACTIVE command period tRC 60 – 60 – 66 – ns

ACTIVE-to-READ or WRITE delay tRCD18–15–20– ns

Refresh period (4,096 rows) tREF – 64 – 64 – 64 ms

Refresh period–Automotive

(4,096 rows)

tREFAT –16–16–16ms

AUTO REFRESH period tRFC60–66–66– ns

PRECHARGE command period tRP 18 – 15 – 20 – ns

ACTIVE bank a to ACTIVE bank b

command

tRRD12–14–15– ns

Transition time tT 0.3 1.2 0.3 1.2 0.3 1.2 ns 7

WRITE recovery time tWR 1 CLK

+ 6ns –1 CLK

+ 7ns –1 CLK

+ 7.5ns ––24

12 – 14 – 15 – ns 25

Exit SELF REFRESH-to-ACTIVE

command

tXSR70–67–75– ns 20

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Electrical Specifications

Table 19: AC Functional Characteristics

Notes 5, 6, 8, 9, 11, 34 apply to entire table; notes appear on pages 50 and 51; VDD, VDDQ = +3.3V ±0.3V

Parameter Symbol -6 -7E -75 Units Notes

READ/WRITE command to READ/WRITE command tCCD111tCK 17

CKE to clock disable or power-down entry mode tCKED111tCK 14

CKE to clock enable or power-down exit setup mode tPED 1 1 1 tCK 14

DQM to input data delay tDQD000tCK 17

DQM to data mask during WRITEs tDQM000tCK 17

DQM to data High-Z during READs tDQZ222tCK 17

WRITE command to input data delay tDWD000tCK 17

Data-in to ACTIVE command tDAL 5 4 5 tCK 15, 21

Data-in to precharge command tDPL222tCK 16, 21

Last data-in to burst stop command tBDL111tCK 17

Last data-in to new READ/WRITE command tCDL111tCK 17

Last data-in to precharge command tRDL222tCK 16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH

command

tMRD222tCK 26

Data-out to High-Z from precharge command CL = 3 tROH(3)333tCK 17

CL = 2 tROH(2) – 2 2 tCK 17

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Notes

Notes 1. All v o ltages referenced to VSS.

2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test

biased at 1.4V.

3. IDD is dependent on output loading and cy cle rates. Specified value s are obtained

with minimum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indicate cycle time at which proper

operation over the full temperature range (0°C ≤ TA ≤ +70°C (commercial), –40°C ≤ TA

≤ +85°C (industrial), and –40°C ≤ TA ≤ +105°C (automotive) is ensured.

6. An initial pause of 100µs is required after power-up, follo wed by two AUTO REFRESH

commands, before prope r devi ce operation is ensured. (VDD and VDDQ must be pow-

ered up simultaneously. VSS and VSSQ must be at same potential.) Th e tw o AUTO

REFRESH command wake-ups should be repeated any time the tREF re fresh require-

ment is exceeded.

7. AC characteristics assume tT = 1ns.

8. In addition to meeting the transition rate specification, the clock and CKE must tr an-

sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.

9. Outputs measured at 1.5V with equivalent load:

10. tHZ defines the time at which the output achieves the open circuit condition; it is not

a reference to VOH or VOL. The last valid data elemen t will meet tOH befor e going

High-Z.

11. C timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V

crossover point. If the input transition time is longer than 1 ns, then the timing is ref-

erenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. CLK

should always be 1.5V referenced to crossover. Refer to Micron technical note

TN-48-09.

12. Other input signals are allowed to transition no more than once every two clocks and

are otherwise at valid VIH or VIL levels.

13. IDD specifications are tested after the device is properly initialized.

14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum

cycle rate.

15. Timing actually specified by tWR plus tRP; clock(s) specified as a re feren ce on ly a t

minimum cycle rate.

16. Timing actually specified by tWR.

17. Required clocks are specified by JEDEC functionality and are not dependent on any

timing parameter.

18. The IDD current will increase or decrease proportionally according to the amount of

frequency alteration for the test condition.

19. Addre ss transitions average one transition every two clocks.

20. CLK must be toggled a minimum of two times during this period.

21. Based on tCK = 7.5ns for -75 and -7E, tCK = 6ns for -6.

Q50pF

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Notes

22. VIH overshoot: VIH (MA X) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width

cannot be greater than one-thir d of the cycle rate . VIL undershoot: VIL (MIN) = –2V for

a pulse width ≤ 3ns.

23. The clock frequency must remain constant (stable clock is defi ned as a signal cycling

within timing constraints specified for the clock pin) during access or precharge

states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be

used to reduce the data rate.

24. Auto precharge mode only. The precharge timing budget (tRP) begins 6ns/7ns/7.5ns/

7ns after the first clock delay, after the last WRITE is executed.

25. Precharge mode only.

26. JEDEC and PC100 specify three clocks.

27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.

28. Parameter guaranteed by design.

29. PC100 specifies a maximum of 4pF.

30. PC100 specifies a maximum of 5pF.

31. PC100 specifies a maximum of 6.5pF.

32. For -75, CL = 3 and tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns; for -6, CL = 3 and

tCK = 6ns.

33. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6

limit is actually a nomina l value and does not result in a fail value.

34. The -6 speed grade does not support CL = 2.

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Timing Diagrams

Figure 35: Initialize and Load Mode Register

Notes: 1. If CS# is HIGH at clock HIGH time, all commands applied are NOP.

2. The mode regis ter may be loaded prior to the AUTO REFRESH cycles if desired.

3. JEDEC and PC100 specify three clocks.

4. Outputs are guaranteed High-Z after command is issued.

tCH

tCL

tCK

CKE

CLK

COMMAND

BA0, BA1 BANK

tRFC tMRD

tRFC

AUTO REFRESH AUTO REFRESH Program Mode Register

2, 3, 4

tCMH

tCMS

Precharge

all banks

()()

tRP

()()

tCKS

Power-up:

and

CLK stable

T = 100µs

MIN

PRECHARGE NOP AUTO

REFRESH NOP

LOAD MODE

()()

AUTO

REFRESH

ALL

BANKS

()()

High-Z

tCKH

()()

DQM /

DQML, DQMH

()()

()()()()

()()

NOP

()()

tCMH

tCMS tCMH

tCMS

A0–A9, A11 ROW

tAH

tAS

CODE

()()

A10 ROW

tAH

tAS

CODE

()()

ALL BANKS

SINGLE BANK

()()

DON’T CARE

T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3

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Timing Diagrams

Figure 36: Power-Down Mode

Notes: 1. Violating refresh requirements during power-down may result in a loss of data.

tCH

tCL

tCK

Two clock cycles

CKE

CLK

All banks idle, enter

power-down mode

Precharge all

active banks

Input buffers gated off while in

power-down mode

Exit power-down mode

()()

DON’T CARE

tCKS tCKS

COMMAND

tCMH

tCMS

PRECHARGE NOP NOP ACTIVENOP

()()

All banks idle

BA0, BA1

BANK

BANK(S)

()()

High-Z

tAH

tAS

tCKH

tCKS

DQM /

DQML, DQMH

()()

A0–A9, A11

ROW

()()

ALL BANKS

SINGLE BANK

A10

ROW

()()

T0 T1 T2 Tn + 1 Tn + 2

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Timing Diagrams

Figure 37: Clock Suspend Mode

Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.

2. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

tCH

tCL

tCK

tLZ

DQM /

DQML, DQMH

CLK

A0–A9, A11

BA0, BA1

A10

tOH

OUT

tAH

tAS

tAH

tAS

tAH

tAS

BANK

tDH

tAC tHZ

OUT

m + 1

COMMAND

tCMH

tCMS

NOPNOP NOP NOPNOPREAD WRITE

DON’T CARE

UNDEFINED

CKE

tCKS tCKH

BANK

COLUMN m

tDS

e + 1

NOP

tCKH

tCKS

tCMH

tCMS

COLUMN e

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

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Timing Diagrams

Figure 38: Auto Refresh Mode

Notes: 1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not

required.

tCH

tCL

tCK

CKE

CLK

tRFC1

()()

tRP

()()

COMMAND

tCMH

tCMS

NOPNOP

()()

BANK

ACTIVE

AUTO

REFRESH

()()

NOPNOPPRECHARGE

Precharge all

active banks

AUTO

REFRESH

tRFC1

High-Z

BA0, BA1 BANK(S)()()

()()

tAH

tAS

tCKH

tCKS

()()

NOP

()()

DQM /

DQML, DQMH

A0–A9, A11 ROW

()()

ALL BANKS

SINGLE BANK

A10 ROW

()()

T0 T1 T2 Tn + 1 To + 1

DON’T CARE

()()()()

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64Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 39: Self Refresh Mode

Notes: 1. No maximum time limit for self refresh mode. tRAS(MAX) applies to non-self refresh mode.

2. tXSR requires minimum of two clocks regardless of frequency and timing.

3. Self refr esh mode not supporte d on automotive temperature (AT) devices.

tCH

tCL

tCK

tRP

CKE

CLK

Enter self refresh mode

Precharge all

active banks

tXSR

CLK stable prior to exiting

self refresh mode

Exit self refresh mode

(Restart refresh time base)

()()()()

()()

DON’T CARE

COMMAND

tCMH

tCMS

AUTO

REFRESH

PRECHARGE NOP NOP or COMMAND

INHIBIT

()()

BA0, BA1

BANK(S)

()()

High-Z

tCKS

AUTO

REFRESH

tRAS(MIN)1

()()

tCKH

tCKS

DQM/

DQML, DQMH

()()

A0–A9, A11

()()

ALL BANKS

SINGLE BANK

A10

()()

T0 T1 T2 Tn + 1 To + 1 To + 2

()()

≥

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64Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 40: READ – Without Auto Precharge

Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual”

PRECHARGE.

2. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK(S) BANK

ROW

BANK

tHZ

tOH

DOUT m+3

tAC tOH

tAC

DOUT m+2DOUT m+1

tCMH

tCMS

PRECHARGE

NOPNOP NOPACTIVE NOP READ NOP ACTIVE

DISABLE AUTO PRECHARGE SINGLE BANKS

DON’T CARE

UNDEFINED

COLUMN m2

tCKH

tCKS

T0 T1 T2 T3 T4 T5 T6 T7 T8

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

COMMAND

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64Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 41: READ – With Auto Precharge

Notes: 1. For this example, BL = 4, and CL = 2.

2. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tHZ

tOH

OUT

m + 3

tAC tOH

tAC

OUT

m + 2D

OUT

m + 1

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP ACTIVENOP

tCKH

tCKS

COLUMN m2

T0 T1 T2 T4T3 T5 T6 T7 T8

DON’T CARE

UNDEFINED

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64Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 42: Single READ – Without Auto Precharge

Notes: 1. For this example, BL = 1, CL = 2, and the READ burst is followed by a “manual”

PRECHARGE.

2. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

3. PRECHARGE command no t allowed or tRAS would be violated.

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK

BANK(S) BANK

ROW

BANK

tHZ

tCMH

tCMS

NOPNOP3

NOP

PRECHARGE

ACTIVE NOP READ ACTIVE

NOP

DISABLE AUTO PRECHARGE

SINGLE BANKS

COLUMN m

tCKH

tCKS

T0 T1 T2 T3 T4 T5 T6 T7 T8

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

COMMAND

DON’T CARE

UNDEFINED

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64Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 43: Single READ – With Auto Precharge

Notes: 1. For this example, BL = 1, and CL = 2.

2. READ command not allowed or tRAS would be violated.

3. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD CAS Latency

tRC

DQM /

DQML, DQMU

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tHZ

tOH

DOUT m

tAC

COMMAND

tCMH

tCMS

NOP2READACTIVE NOP NOP2ACTIVENOP

tCKH

tCKS

COLUMN m3

T0 T1 T2 T4T3 T5 T6 T7 T8

NOP NOP

DON’T CARE

UNDEFINED

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Timing Diagrams

Figure 44: Alternating Bank Read Accesses

Notes: 1. For this example, BL = 4, and CL = 2.

2. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

DQM /

DQML, DQMH

CLK

A0–A9, A11

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

tOH

OUT

m + 3

tAC tOH

tAC

OUT

m + 2D

OUT

m + 1

COMMAND

tCMH

tCMS

NOP NOPACTIVE NOP READ NOP ACTIVE

tOH

OUT

tAC tAC

READ

ENABLE AUTO PRECHARGE

ROW

ACTIVE

ROW

BANK 0 BANK 0 BANK 3 BANK 3 BANK 0

CKE

tCKH

tCKS

COLUMN m

COLUMN b

T0 T1 T2 T4T3 T5 T6 T7 T8

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0 tRCD - BANK 0

CAS Latency - BANK 0

tRCD - BANK 3 CAS Latency - BANK 3

tRC - BANK 0

RRD

DON’T CARE

UNDEFINED

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64Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 45: READ – Full-Page Burst

Notes: 1. For this example, CL = 2.

2. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

3. Page left open; no tRP.

tCH

tCL tCK

tAC

tLZ

tRCD CAS Latency

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tOH

DOUT m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAC tOH

DOUT m+1

ROW

tHZ

tAC tOH

DOUT m+1

tAC tOH

DOUT m+2

tAC tOH

DOUT m-1

tAC tOH

DOUT m

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

()()

Full page completed

256 (x16) locations within same row

512 (x8) locations within same row

1,024 (x4) locations within same row

COMMAND

tCMH

tCMS

NOPNOP

NOP

ACTIVE NOP READ NOP BURST TERMNOP NOP

()()

NOP

()()

tAH

tAS

BANK

()()

BANK

tCKH

tCKS

()()

COLUMN m

T0 T1 T2 T4T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4

DON’T CARE

UNDEFINED

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64Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 46: READ – DQM Operation

Notes: 1. For this example, BL = 4, and CL = 2.

2. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

tCH

tCL

tCK

tRCD CAS Latency

DQM /

DQML, DQMH

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tCMS

ROW

BANK

ROW

BANK

tAC

OUT

tOH

OUT

m + 3D

OUT

m + 2

ttHZ LZ

tCMH

COMMAND

NOPNOP NOPACTIVE NOP READ NOPNOP NOP

tHZ

tAC tOH

tAH

tAS

tCMS tCMH

tAH

tAS

tAH

tAS

tCKH

tCKS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

DON’T CARE

UNDEFINED

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64Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 47: WRITE – Without Auto Precharge

Notes: 1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of

frequency.

3. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

DISABLE AUTO PRECHARGE

ALL BANKS

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM /

DQML, DQMH

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK

BANK BANK

ROW

BANK

tWR

tDH

tDS

m + 1 D

m + 2

m + 3

COMMAND

tCMH

tCMS

NOPNOP

NOP

ACTIVE NOP WRITE

NOPPRECHARGE ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

SINGLE BANK

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

DON’T CARE

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64Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 48: WRITE – With Auto Precharge

Notes: 1. For this example, BL = 4.

2. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tWR

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE NOP ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

tCKH

tCKS

NOP NOP

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

DON’T CARE

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64Mb: x4, x8, x16 SDRAM

Timing Diagrams

Figure 49: Single WRITE – Without Auto Precharge

Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of

frequency.

3. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

4. PRECHARGE command no t allowed or tRAS would be violated.

DON’T CARE

DISABLE AUTO PRECHARGE

ALL BANKS

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

tWR

tDH

tDS

COMMAND

tCMH

tCMS

ACTIVE NOP WRITE NOP4NOP4NOP

tAH

tAS

tAH

tAS

SINGLE BANK

tCKH

tCKS

COLUMN m3

T0 T1 T2 T4T3 T5 T6 T7 T8

PRECHARGE ACTIVE NOP

BANK BANK

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Timing Diagrams

Figure 50: Single WRITE – With Auto Precharge

Notes: 1. For this example, BL = 1.

2. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

3. WRITE command not allowed or tRAS would be violated.

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tWR

COMMAND

tCMH

tCMS

NOP3

NOP

ACTIVE NOP3

WRITE NOP

ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS

tCKH

tCKS

NOP

COLUMN m2

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

DON’T CARE

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Timing Diagrams

Figure 51: Alternating Write Accesses

Notes: 1. For this example, BL = 4.

2. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

DON’T CARE

tCH

tCL

tCK

CLK

DQ D

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOP

ACTIVE NOP WRITE

NOP NOP ACTIVE

tDH

tDS tDH

tDS

ACTIVE WRITE

tDH

tDS

b + 1 D

b + 3

tDH

tDS tDH

tDS

ENABLE AUTO PRECHARGE

DQM /

DQML, DQMH

A0–A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

ENABLE AUTO PRECHARGE

ROW

BANK 0 BANK 0 BANK 1

BANK 0

BANK 1

CKE

tCKH

tCKS

b + 2

tDH

tDS

COLUMN b

COLUMN m

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0 t

RCD - BANK 0

tWR - BANK 0

WR - BANK 1

tRCD - BANK 1

tRC - BANK 0

RRD

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

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Timing Diagrams

Figure 52: WRITE – Full-Page Burst

Notes: 1. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

2. tWR must be sati sf ied prior to PRECHARGE command.

3. Page left open; no tRP.

tCH

tCL tCK

tRCD

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMS

tAH

tAS

tAH

tAS

ROW

Full-page burst does

not self-terminate. Can

use BURST TERMINATE

command to stop.

2, 3

()()

Full page completed

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP

()()

DQ D

tDH

tDS

m + 1 D

m + 2 D

m + 3

tDH

tDS tDH

tDS

m - 1

tDH

tDS tDH

tDS

tAH

tAS

BANK

()()

BANK

tCMH

tCKH

tCKS

()()

256 (x16) locations within same row

512 (x8) locations within same row

1,024 (x4) locations within same row

COLUMN m1

T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3

DON’T CARE

()()

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Timing Diagrams

Figure 53: WRITE – DQM Operation

Notes: 1. For this example, BL = 4.

2. x16: A8, A9 and A11 = “Don’t Care”

x8: A9 and A11 = “Don’t Care”

x4: A11 = “Don’t Care”

DON’T CARE

tCH

tCL

tCK

tRCD

DQM /

DQML, DQMH

CKE

CLK

A0–A9, A11

BA0, BA1

A10

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

ENABLE AUTO PRECHARGE

m + 3

tDH

tDS

m + 2

tCMH

COMMAND

NOPNOP

NOP

ACTIVE NOP WRITE

NOPNOP

tCMS tCMH

tDH

tDS

tDH

tDS

tAH

tAS

tAH

tAS

DISABLE AUTO PRECHARGE

tCKH

tCKS

COLUMN m

T0 T1 T2 T3 T4 T5 T6 T7

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64Mb: x4, x8, x16 SDRAM

Package Dimensions

Figure 54: 54-Pin Plastic TSOP II (400 mil)

Notes: 1. All dimensions are in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusio n is

0.25mm per side.

SEE DETAIL A

0.10 +0.10

-0.05

0.15 +0.03

-0.02

2X R 1.00

2X R 0.75

0.80 TYP

(FOR REFERENCE

ONLY)

2X 0.71

0.50 ±0.10

PIN #1 ID

DETAIL A

22.22 ±.08

10.16 ±0.08

11.76 ±0.20

0.375 ±0.075 TYP

1.2 MAX

0.25

0.80

2X 0.10

2.80 GAGE PLANE

PLATED LEAD FINISH: 90% Sn, 10% Pb OR 100%Sn

PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC

PACKAGE WIDTH AND LENGTH DO NOT

INCLUDE MOLD PROTRUSION. ALLOWABLE

PROTRUSION IS 0.25 PER SIDE.

0.10

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although

considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

64Mb: x4, x8, x16 SDRAM

Package Dimensions

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Figure 55: 54-Ball VFBGA “F4/B4” Package, 8mm x 8mm

Notes: 1. All dimensions in millimeters.

2. Recommended pad = Ø 0.40mm SMD.

BALL A1 ID

0.65 ±0.05

SEATING PLANE

0.10 C

1.00 MAX

BALL A9

0.80

TYP

0.80 TYP

3.20

6.40

8.00 ±0.10

4.00 ±0.05

SOLDER BALL

DIAMETER REFERS

TO POST REFLOW

CONDITION. THE PRE-

REFLOW DIAMETER

IS 0.42.

54X Ø0.45 ±0.05

SOLDER BALL MATERIAL:

62% Sn, 36% Pb, 2% Ag OR

96.5% Sn, 3% Ag, 0.5% Cu

SOLDER MASK DEFINED BALL PADS:

Ø0.40

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE MATERIAL: PLASTIC LAMINATE

6.40

3.20

4.00 ±0.05

8.00 ±0.10

BALL A1 ID

BALL A1