WIZ830MJ Datasheet
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Document History Information
Revision
Data
Description
Ver.1.0
June 04, 2008
Release with WIZ830MJ Launching
Ver.1.1
July 29, 2008
Modified dimensions(Symbol B and C).
Ver.1.2
March 4, 2010
Pin number of A[9:0] modified in Chapter 2.3
Ver.1.3
January 28, 2013
Hardware revision(Rev1.1)
Changed just partlist at this revision
WIZ830MJ Datasheet
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WIZnet’s Online Technical Support
If you have something to ask about WIZnet Products, Write down your question
on Q&A Board in WIZnet website (www.wiznet.co.kr). WIZnet Engineer will give an
answer as soon as possible.
WIZ830MJ Datasheet
© Copyright 2008 WIZnet Co., Ltd. All rights reserved
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Table of Contents
1. Introduction .............................................................................. 5
1.1. Features ................................................................................................... 5
1.2. Block Diagram .......................................................................................... 5
2. Pin Assignments & descriptions ................................................... 6
2.1. Pin Assignments ....................................................................................... 6
2.2. Power & Ground ....................................................................................... 7
2.3. MCU Interfaces ........................................................................................ 7
2.4. Network Indicator LED Signals ................................................................. 8
2.5. Miscellaneous Signals .............................................................................. 8
3. Timing Diagrams ....................................................................... 9
3.1. Reset Timing ............................................................................................ 9
3.2. Register / Memory READ Timing .............................................................. 9
3.3. Register / Memory WRITE Timing .......................................................... 10
4. Dimensions ............................................................................. 11
5. Schematic .............................................................................. 12
6. Partlists .................................................................................. 13
WIZ830MJ Datasheet
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1. Introduction
WIZ830MJ is the network module that includes W5300 (TCP/IP hardwired chip, include PHY),
MAG-JACK (RJ45 with X’FMR) with other glue logics. It can be used as a component and no
effort is required to interface W5300 and Transformer. The WIZ830MJ is an ideal option for users
who want to develop their Internet enabling systems rapidly.
For the detailed information on implementation of Hardware TCP/IP, refer to the W5300
Datasheet.
WIZ830MJ consists of W5300 and MAG-JACK.
TCP/IP, MAC protocol layer: W5300
Physical layer: Included in W5300
Connector: MAG-JACK(RJ45 with Transformer)
1.1. Features
Supports 10/100 Base TX
High network performance : Up to 50Mbps
Supports half/full duplex operation
Supports auto-negotiation and auto cross-over detection
IEEE 802.3/802.3u Compliance
Operates 3.3V with 5V I/O signal tolerance
Supports network status indicator LEDs
Includes Hardware Internet protocols: TCP, IP Ver.4, UDP, ICMP, ARP, PPPoE, IGMP
Includes Hardware Ethernet protocols: DLC, MAC
Supports 8 independent connections simultaneously
Supports MCU bus Interface
Supports Direct/Indirect mode bus access
Supports 16/8 bit data bus width
Supports memory-to-memory DMA (only 16bit Data bus width & slave mode)
Supports Socket API for easy application programming
Supports hybrid TCP/IP stack(software and hardware TCP/IP stack)
Supports PPPoE connection (with PAP/CHAP Authentication mode)
More flexible allocation internal TX/RX memory according to application throughput
Interfaces with two 2.54mm pitch 2 x 14 header pin
1.2. Block Diagram
WIZ830MJ Datasheet
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2. Pin Assignments & descriptions
2.1. Pin Assignments
WIZ830MJ Datasheet
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I : Input O : Output
I/O : Bi-directional Input and output P : Power
2.2. Power & Ground
Symbol
Type
Pin No.
Description
VCC
P
J1:1, J2:1
Power : 3.3 V power supply
GND
P
J1:18, J2:10, J2:15,
J2:16, J2:23, J2:24
Ground
2.3. MCU Interfaces
Symbol
Type
Pin No.
Description
A[9:0]
I
J1:19 ~ J1:28
Address
Used as Address[9-0] pin
D[15:8]
I/O
J1:2 ~ J1:9
Data
16 bit-wide high data bus
In case of using 8 bit data bus, there are driven as
High-Z
D[7:0]
I/O
J1:10 ~ J1:17
Data
16 bit-wide low data bus
/CS
I
J2:19
Module Select : Active low.
/CS of W5300
/RD
I
J2:20
Read Enable : Active low.
/RD of W5300
/WR
I
J2:21
Write Enable : Active low
/WR of W5300
/INT
O
J2:18
Interrupt : Active low
After reception or transmission it indicates that the
W5300 requires MCU attention.
By writing values to the Interrupt Register(IR) of
W5300 the interrupt will be cleared by host.
All interrupts can be masked by writing values to
the IMR of W5300 (Interrupt Mask Register).
For more details refer to the W5300 Datasheet
BIT16EN
I
J2:2
16/8 bit data bus select.
High : 16 bit data bus
Low : 8 bit data bus.
WIZ830MJ Datasheet
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2.4. Network Indicator LED Signals
Symbol
Type
Pin No.
Description
/LINKLED
O
J2:3
Link LED
It indicates the link status of
media(10/100M).
/TXLED
O
J2:4
Transmit activity LED : Transmit
Enable
It notifies the output of transmit data
through TXOP/TXON
(Transmit Activity).
/RXLED
O
J2:5
Receive activity LED : Transmit Data
It notifies the input of receive data from
RXIP/RXIN (Receive Activity)
/COLLED
O
J2:6
Collision LED : Transmit Data
It notifies when collisions occur.
It is valid at half-duplex, and is ignored at
full-duplex.
/FDXLED
O
J2:7
Full duplex LED : Transmit Data
It outputs low at the full-duplex and
outputs high at the halfduplex
according to auto-negotiation or manual
configuration of OP_MODE[2:0].
/SPDLED
O
J2:8
Link speed LED : Transmit Data
It is asserted low at the 100Mbps and
high at the 10Mbps
according to auto-negotiation or manual
configuration of OP_MODE[2:0].
/ACTLED
O
J2:9
Activity LED
It notifies the output of transmit data
through TXOP/TXON or the input of
receive data from RXIP/RXIN.
2.5. Miscellaneous Signals
Symbol
Type
Pin No.
Description
/RESET
I
J2:17
Reset : This pin is active low input to
initialize or re-initialize W5300.
RESET should be held at least 2us after
low assert, and wait for at least 10ms
after high de-assert in order for PLL logic
to be stable
BRDY[3:0]
O
J2:11 ~ J2:14
Buffer Ready Indicator
BRDYn monitors TX/RX memory status
of each socket.
For more details refer to the W5300
Datasheet
NC
-
J2 : 22, J2:25, J2:26,
J2:27, J2:28
Not Connect
WIZ830MJ Datasheet
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3. Timing Diagrams
WIZ830MJ provides following interfaces of W5300.
-. Direct/Indirect mode bus access
3.1. Reset Timing
Description
Min
Max
1
Reset Cycle Time
2 us
-
2
PLL Lock-in Time
50us
10 s
3.2. Register / Memory READ Timing
Description
Min
Max
tADDRs
Address Setup Time after /CS and /RD low
-
7ns
tADDRh
Address Hold Time after /CS and /RD high
-
-
tCS
/CS Low Time
65ns
-
tCSn
/CS Next Assert Time
28ns
-
tRD
/RD Low Time
65ns
-
tDATAs
DATA Setup Time after /RD low
42ns
-
tDATAh
DATA Hold Time after /RD and /CS high
-
7ns
tDATAhe
DATA Hold Extension Time after /CS high
-
2XPLL_CLK
WIZ830MJ Datasheet
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3.3. Register / Memory WRITE Timing
Description
Min
Max
tADDRs
Address Setup Time after /CS and /WR low
-
7ns
tADDRh
Address Hold Time after /CS or /RD high
-
-
tCS
/CS low Time
50ns
-
tCSn
/CS next Assert Time
28ns
tWR
/WR low Time
50ns
tDATAs
Data Setup Time after /WR low
7ns
7ns + 7XPLL_CLK
tDATAf
Data Fetch Time
14ns
tWR – tDATAs
tDATAh
Data Hold Time after /WR high
7ns
-
WIZ830MJ Datasheet
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4. Dimensions
Symbols
Dimensions (mm)
Symbols
Dimensions (mm)
A
34.00
H
6.50
B
30.48
I
2.54
C
25.40
J
2.54
D
3.00
K
15.90
E
4.00
L
13.50
F
50.00
M
6.00
G
3.30
-
-
WIZ830MJ Datasheet
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5. Schematic
GH6
CON1
1
Title
Size Document Number Rev
Date: Sheet of
<Doc> REV.1.1
WIZ830MJ
B
1 1Monday, January 28, 2013
3V3A 3V3A
/WR
/CS
/RD
+
C9
3.3uF
GNDA
+C10
10uF/16V
+
C11
10uF/16V
C12
0.1uF
FB2 1uH
1V8_OUT
1V8D 1V8A
W5300
LQFP100(14X14)
U1
W5300
RSET_BG 1
VCC3A3 2
NC 3
GNDA
4
RXIP 5
RXIN 6
VCC1A8 7
TXOP 8
TXON 9
GNDA
10
VCC1V8 11
GND
12
1V8O 13
VCC3V3 14
GND
15
GNDA
16
VCC1A8 17
BIT16EN
18
TEST_MODE3
19
TEST_MODE2
20
TEST_MODE1
21
TEST_MODE0
22
OP_MODE0 23
OP_MODE1 24
OP_MODE2 25
VCC3V3 26
GND
27
DATA15
28
DATA14
29
DATA13
30
DATA12
31
DATA11
32
DATA10
33
DATA9
34
DATA8
35
VCC1V8 36
GND
37
DATA7
38
DATA6
39
DATA5
40
DATA4
41
DATA3
42
DATA2
43
DATA1
44
DATA0
45
VCC3V3 46
GND
47
ADDR9
48
ADDR8
49
ADDR7
50
ADDR6
51
ADDR5
52
ADDR4
53
ADDR3
54
ADDR2
55
ADDR1
56
ADDR0
57
VCC1V8 58
GND
59
/WR
60
/RD
61
/CS
62
VCC3V3 63
GND
64
/INT
65
/RESET
66
BRDY0
67
BRDY1
68
BRDY2
69
BRDY3
70
MII_RXC 71
VCC1V8 72
GND
73
MII_RXDV 74
MII_RXD0 75
MII_RXD1 76
MII_RXD2 77
MII_RXD3 78
MII_COL 79
/FDX 80
MII_CRS 81
MII_TXC 82
VCC3V3 83
GND
84
SPDLED/MII_TXD0 85
FDXLED/MII_TXD1 86
COLLED/MII_TXD2 87
RXLED/MII_TXD3 88
TXLED/MII_TXEN 89
LINKLED 90
OSC25I
91
VCC1V8 92
GND
93
VCC1V8 94
XTLN
95 XTLP
96
GND
97
NC 98
NC 99
NC 100
/INT
XTLP
XTLN
1V8_OUT
R1
12K(1%)
/RESET
3.3V 1V8D3V3A 1V8A
D15
TXOP
RSET_BG
D14
TXON
RXIN
D13
RXIP
D12
D10
/LINKLED
D11
D9
/SPDLED
D8
OP_MODE0
/FDXLED
D7
OP_MODE1
/COLLED
OP_MODE2
/RXLED
D5
/TXLED
D6
D4
GH4
CON9
1
2
3
4
5
6
7
8
9
D3
D2
D1
D0
A9
A8
A7
A6
A5
A4
A3
BIT16EN
A2
BRDY0
A1
BRDY1
A0
BRDY2
BRDY3
XTLP
XTLN
R3
1M
Y1
25MHz
C19 15p
C21 15p
1V8D
C13
0.1uF C14
0.1uF
C15
0.1uF
C16
0.1uF
C17
0.1uF
C18
0.1uF
R2
300(1%)
OP_MODE1
OP_MODE2
OP_MODE0
3.3V
Recommendatory part is 120R@100MHz
C22
0.1uF
R5
200
TXON
R6
49.9
RXIN
C23
0.1uF
R4
200
TXOP
C20
0.1uF
R7
49.9
U2
BS-RB10005
TD+
1
TD-
2
TCT
3
NC
4
NC
5
RCT
6
RD+
7
RD-
8
GRN+
10
GRN-
9
YEL+
12
YEL-
11
Shield
13
Shield
14
R8
49.9
RXIP
R9
49.9
FB4
FB_0805
3.3V
C1
0.1uF C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
3V3A
GH5
CON1
1
C6
10uF/16V
FB1 1uH
C8
10uF/16V
C7
0.1uF
3.3V
GNDA
GNDA
FB3 1uH
GH3
CON9
1
2
3
4
5
6
7
8
9
GNDA A6
A8
D1
D6
D8
D10
D12
D14
A4
A7
A9
D0
D2
D4
/ACTLED
/FDXLED
/RXLED
/LINKLED
A5
BRDY1
BRDY3
/WR
/RESET
/COLLED
/TXLED
BIT16EN
BRDY0
BRDY2
/SPDLED
/CS /INT
J1, J2 : 2.54mm pitch header
3.3V
/RD
J1
HEADER 14X2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
1
3
5
7
9
11
13
15
17
19
21
23
25
27
J2
HEADER 14X2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
1
3
5
7
9
11
13
15
17
19
21
23
25
27
3.3V
D9
D11
D13
D15
D3
D5
D7
R10 0
R11 0
R13 0
Not mounted
(auto-negotiaton)
/RXLED
D1
1SS181(SC-59)
3
1
2
/ACTLED
/TXLED
R12
4.7K
3.3V
A3
A1 A2
A0
/LINKLED
/ACTLED
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6. Partlist
Item
Q.ty
Reference
Part
Tech. Characteristics
Package
1
16
C1,C2,C3,C4,C5,C7,
C12,C13,C14,C15,C16,
C17,C18,C20,C22,C23
0.1uF
50V-20% Ceramic
CASE 0603
2
4
C6,C8,C10,C11
10uF/16V
16Vmin 10%
EIA/IECQ
3216
3
1
C9
3.3uF/16V
16Vmin 10%
EIA/IECQ
3216
4
2
C19,C21
15pF
50V-20% Ceramic
CASE 0603
5
1
D1
1SS181
SC-59
6
3
FB1,FB2,FB3
1uH Chip Ferrite Inductor
CASE 0805
7
1
FB4
120 Ohm Ferrite BEAD
120 Ohm /100MHz
CASE 0805
8
2
J1,J2
2X14 2.54mm DIP
STRAIGHT Header
2 X 14 2.54mm pitch
DIP
9
1
R1
12K (1%)
1/10W-1% SMD
CASE 0603
10
1
R2
300 (1%)
1/10W-1% SMD
CASE 0603
11
1
R3
1M
1/10W-5% SMD
CASE 0603
12
2
R4,R5
200
1/10W-5% SMD
CASE 0603
13
4
R6,R7,R8,R9
49.9 (1%)
1/10W-1% SMD
CASE 0603
14
0
R10,R11,R13
not mounted
1/10W-5% SMD
CASE 0603
15
1
R12
4.7K
1/10W-5% SMD
CASE 0603
16
1
U1
W5300
WIZnet Hardware TCP/IP
LQFP100
17
1
U2
BS-RB10005
Transformer + RJ-45
18
1
Y1
25MHz(SMD)
SMD Type, CL=18pF,
Industrial
SX-1
19
1
PCB REV1.1
FR4, 1.6T, 4Layer
