XC4000XLA/XV >: XILINX Field Programmable Gate Arrays February 1, 1999 (Version 1.0) Product Specification XC4000XLA/XV Family FPGAs XC4000XLA/XV Electrical Features Note: XC4000XLA devices are improved versions of * XLA devices require 3.0 - 3.6 Volts (VCC) XC4000XL devices. The XC4000XV devices have the * XV devices require 2.3- 2.7 Volts (VCCINT) same features as XLA devices, incorporate additional inter- and 3.0-3.6V (VCCIO) connect resources and extend gate capacity to 500,000 * 5.0 V TTL compatible I/O system gates. The XC4000XV devices require a separate * 3.3 VLVTTL, LVCMOS compliant I/O 2.5V power supply for internal logic but maintain 5V I/O * 5.0 V and 3.0 V PCI compliant I/O compatibility via a separate 3.3V I/O power supply. A gen- * 12-mA or 24-mA current sink capability eral description of the XC4Q00XLA/XV device architecture * Safe under all power-up sequences in included in the XC4000E and XC4000X Series (Descrip- * XLA devices consume 40% less power than do XL tion only) file, v1.4 (11/97) on the Xilinx WEBLINX at: devices http:/Awww.xilinx.com. * XV devices consume 65% less power than do XL devices * System-featured Field-Programmable Gate Arrays - Select-RAM memory: on-chip ultra-fast RAM with Optional input clamping to VCC (XLA) or VCCIO (XV) - Synchronous write option ngs . - Dual-port RAM option Additional XC4000XLA/XV Family F | - Flexible function generators and abundant flip-flops Features - Dedicated high-speed carry logic + Footprint Compatible with XC4000XL FPGAs Lower - Internal 3-state bus capability oo cost with improved performance and lower power. - 8 global low-skew clock or signal distribution * Advanced Technology 5 layer metal, 0.254 CMOS networks . process (XV) or 0.354 CMOS process (XLA) * Flexible array architecture ; ; * Highest Performance System performance beyond * Low power segmented routing architecture 100 MHz - Systems-oriented features * High Capacity Up to 500,000 system gates and - IEEE 1149.1-compatible boundary scan 270,000 synchronous SRAM bits - Individually programmable output slew rate * Low Power 3.3V/2.5V technology plus segmented - Programmable input pull-up or pull-down resistors routing architecture - Unlimited reprogrammability * Safe and Easy to Use Interfaces to any combination * Readback capability of 3.3 V and 5.0 V TTL compatible devices. - Program verification and internal node observability Table 1: XC4000XLA Series Field Programmable Gate Arrays Max Logic | Max. RAM Typical Number Required Logic Gates Bits Gate Range CLB Total of Max. Configur- Device Cells (No RAM) | (No Logic) | (Logic and RAM)* Matrix CLBs_ | Flip-Flops| User I/O | ation Bits XC4013XLA 1,368 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 192 393,632 XC4020XLA 1,862 20,000 25,088 13,000 - 40,000 28 x 28 784 2,016 224 521,880 XC4028XLA 2,432 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 256 668,184 XC4036XLA 3,078 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 288 832,528 XC4044XLA 3,800 44,000 51,200 27,000 - 80,000 40 x 40 1,600 3,840 320 1,014,928 XC4052XLA 4,598 52,000 61,952 33,000 - 100,000 44 x 44 1,936 4,576 352 1,215,368 XC4062XLA 5,472 62,000 73,728 40,000 - 130,000 48 x 48 2,304 5,376 384 1,433,864 XC4085XLA 7,448 85,000 100,352 | 55,000 - 180,000 56 x 56 3,136 7,168 448 1,924,992 XC40110XV 9,728 110,000 131,072 | 75,000 - 235,000 64 x 64 4,096 9,216 448 2,686,136 XC40150XV 12,312 150,000 165,888 | 100,000 -300,000} 72x72 5,184 11,520 448 3,373,448 XC40200XV 16,758 200,000 225,792 | 130,000 - 400,000 | 84x 84 7,056 15,456 448 4,551,056 XC40250XV 20,102 250,000 270,848 | 180,000 -500,000 | 92x92 8,464 18,400 448 5,433,888 * Maximum values of gate range assume 20-30% of CLBs used as RAM February 1, 1999 (Version 1.0) 6-161XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? Xilinx SRAM XC4000 Series FPGAs XC4000 Series high-performance, high-capacity Field Pro- grammable Gate Arrays (FPGAs) provide the benefits of custom CMOS VLSI, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. The result of fifteen years of FPGA design experience and feedback from thousands of customers, these FPGAs com- bine architectural versatility, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs. Figure 1: Cross Section of Xilinx 0.25 micron, 5 layer metal XC4000XV FPGA. Visible features are five layers of metallization, tungsten plug vias and trench isolation. The small gaps above the lowest layer are 0.25 micron polysilicon MOSFET gates. The excellent planarity of each metal layer is due to the use of chemical-mechanical polishing or CMP. In effect, each layer is ground flat before a new layer is added. XC4000XLA/XV FPGAs XC4000XLA/XV FPGAs use 5 layer metal silicon technol- ogy to improve performance while reducing device cost and power. In addition, |OB enhancements provide full PCI compliance and the JTAG functionality is expanded. XC4000XV FPGAs XC4000XV FPGAs incorporate all the features of the XLA devices but require a separate 2.5V power supply for inter- nal logic. I/O pads are still driven from a 3.3V power supply. The 2.5V logic supply is named VCCINT and the 3.3 V |O supply is named VCCIO. The XV devices also incorporate additional routing resources in the form of 8 octal-length segmented routing channels vertically and horizontally per row and column. Differences Between the XC4000XLA/XV and XC4000XL FPGAS The XC4000XLA/XV families of FPGAs are logically identi- cal to XC4000EX and XC4000XL FPGAs, however |/O, configuration logic, JTAG functionality, and performance have been enhanced. In addition, they deliver: * Improved Performance XLA/XV devices benefit from advance processing technology and a reduction in interconnect capacitance which improves performance over XL devices by more than 30%. * Lower Power XLA/XV devices have reduced power requirements compared to equivalent XL devices. * Shorter routing delays The smaller die of XLA/XV devices directly reduces clock delays and the delay of high-fanout signals. The reduction in clock delay allows improved pin-to-pin I/O specifications. * Lower Cost XLA/XV device cost is directly related to the die size and has been reduced significantly from that of equivalent XL devices. * Express mode configuration Express mode configuration is available on the XLA and XV devices. IOB Enhancements * 12/24 mA Output Drive The XLA/XV family of FPGAs allow individual lOBs to be configured as high drive outputs. Each output can be configured to have 24 mA drive strength as opposed to the standard default strength of 12 mA. * VCC Clamping Diode XLA and XV FPGAs have an optional clamping diode connected from each output to VCC (VCCIO for XV). When enabled they clamp ringing transients back to the 3.3V supply rail. This clamping action is required in 3.3V PCI applications. VCC clamping is a global option affecting all I/O pins. If enabled, TTL I/O compatibility is maintained, but full 5.0 Volt I/O tolerance is sacrificed. * Enhanced ESD protection An improved ESD structure allows XV devices to safely pass the stringent 5V PCI (4.2.1.3) ringing test. This test applies an 11V pulse to each IOB for 11 ns via a 55 ohm resistor. 6-162 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays Full 3.3V and 5.0V PCI compliance The addition of 12/24 mA drive, optional 3.3V clamping and improved ESD provides full compliance with either 3.3V or 5.0V PCI specifications. Three-State Register XC4000XLA/XV devices incorporate an optional register controlling the three-state enable in the IOBs.The use of the three-state control register can significantly improve output enable and disable time. FastCLK Clock Buffers The XLA/XV devices incorporate FastCLK clock buffers. Two FastCLk buffers are available on each of the right and left edges of the die. Each FastCLK buffer can provide a fast clock signal (typically < 1.5 ns clock delay) to all the IOBs within the IOB octant containing the buffer. The Fast- CLK buffers can be instantiated by use of the BUFFCLK symbols. (In addition to FastCLK buffers, the Global Early BUFGE clock buffers #1, #2, #5, and #6 can also provide fast clock signals (typically < 1.5 ns clock delay) to |OBs on the top and bottom of the die. XLA, XV Power Requirements XC4000XLA devices require 40% less power per CLB than equivalent XL devices. XC4000XV devices require 42% less power per CLB than equivalent XLA devices and 65% less power than XL devices The representative K-Factor for the following families can be found in Table 2. The K-Factor predicts device current for typical user designs and is based on filling the FPGA with active 16-Bit counters and measuring the device current at 1 MHz. This technique is described in XBRF14 A Simple Method of Estimating Power in XC4000XL/EX/E FPGAs. To predict device power (P) using the K-Factor use the following formula: P=V*K*N*F; where: P= Device Power V= Power supply voltage K= the Device K-Factor N = number of active registers F = Frequency in MHz Table 2: K-Factor and Relative Power. Power Power Relative Relative FPGA Family | K-Factor To XL To XLA XC4000XL 28 1.00 1.65 XC4000XLA 17 0.60 1.00 XC4000XV 13 0.35 0.58 XLA, XV Logic Performance XC4000XLA/XV devices feature 30% faster device speed than XL devices, and consistent performance is achieved across all family members. Tabie 3 illustrates the perfor- mance of the XLA devices. For details regarding the imple- mentation of these benchmarks refer to XBRF15 Speed Metrics for High Performance FPGAs. Table 3: XLA/XV Estimated Benchmark Performance February 1, 1999 (Version 1.0) Register - Register . Maximum Benchmarks Size Frequency 8-Bit 172 MHz Adder 16-Bit 144 MHz 32-Bit 108 MHz 2 Cascaded Adders 16-Bit 94 MHz 4 Cascaded Adders 16-Bit 57 MHz 1 Level 314 MHz 2 Level 193 MHz Cascaded 4LUTs 4 Level 108 MHz 6 Level 75 MHz 1 CLBs 325 MHz Interconnect 4 CLBs 260 MHz (Manhattan Distance) 16 CLBs 185 MHz 64 CLBs 108 MHz 128 CLBs 81 MHz Dual Port RAM 8-Bits by 16 172 MHz (Pipelined) 8-Bits by 256 | 172 MHz 6-163XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? Using Fast 1/0 CLKS There are several issues associated with implementing fast I/O clocks by using multiple FastCLK and BUFGE clock buffers for I/O transfers and a BUFGLS clock buffer for internal logic. Reduced Clock to Out Period - When transferring data from a BUFGLS clocked register to an IOB output register which is clocked with a fast I/O clock, the total amount of time available for the transfer is reduced. Using Fast Capture Latch in IOB input - It is necessary to transfer data captured with the fast I/O clock edge to a delayed BUFGLS clock without error. The use of the Fast Capture Latch in the lOBs provides this functionality. Driving multiple clock inputs - Since each FastCLK input can only reach one octant of IOBs it will usually be neces- sary to drive multiple FastCLK and BUFGE input pads with a copy of the system clock. Xilinx recommends that sys- tems which use multiple FastCLK and BUFGE input buffers use a Zero Delay clock buffer such as the Cypress CY2308 to drive up to 8 input pins. These devices contain a Phase locked loop to eliminate clock delay, and specify less than 250ps output jitter. PCB layout - The recommended layout is to place the PLL underneath the FPGA on the reverse side of the PCB. All 8 clock lines should be of equal length. This arrangement will allow all the clock line to be less than 2 cm in length which will generally eliminate the need for clock termination. Advancing the FPGAs clock - An additional advantage to using a PLL-equipped clock buffer is that it can advance the FPGA clocks relative to the system clock by incorporating additional board delay in the feedback path. Approximately 6 inches of trace length are necessary to delay the signal by 1 ns. Advancing the FPGAs clock directly reduces input hold requirements and improves clock to out delay. FPGA clocks should not be advanced more than the guaranteed mini- mum Output Hold Time (minus any associated clock jitter) or the outputs may change state before the system clock edge. For XLA and XV FPGAs the Output Hold Time is specified as a minimum Clock to Output Delay in the tables on pages 183, 182, 197, and 19%. The maximum recom- mended clock advance equals this value minus any clock jitter. Instantiating I/O elements- Depending on the design environment, it may be necessary to instantiate the fast I/O elements. They are found in the libraries as: BUFGE (1,0) - The Global Early Buffer * BUFGLS (1,0)- The Global Low Skew Buffer * BUFFCLK (I,O) - The FastCLK Buffer ILFFX (D, GF, CE, C, Q) - The Fast Capture Latch Macro Locating I/O elements - It is necessary to connect these elements to a particular I/O pad in order to select which buffer or fast capture latch will be used. Restricted Clock Loading - Because the input hold requirement is a function of internal clock delay, it may be necessary to restrict the routing of BUFGE to IOBs along the top and bottom of the die to obtain sub-ns clock delays. BUFGE 6 BUFGE 1 __ [> ey FCLK 1 in FCLK 2 FCLK 3 BUFGLS 2 BUEGE 5 BUFGE 2 ip <4 Figure 2: Location of FastCLK, BUFGE and BUFGLS Clock Buffers in XC4000XLA/XV FPGAs PLL Clock 0 BUFGE1 XC4000XLA Buffer BUFGE2 XC4000XV o2 BUFGED 03 BUFGE6 O4 FCLK1 05 FCLK2 FB O6 FCLK3 Ref O7 FCLK4 Figure 3: Diagram of XC4000XLA/XV FPGA Connected to PLL Clock Buffer Driving 4 BUFGE and 4 FasiCLK Clock Buffers. 6-164 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays JTAG Enhancements XC4000XLA/XV devices have improved JTAG functionality and performance in the following areas: IDCODE - The IDCODE register in JTAG is now supported. All future Xilinx FPGAs will support the IDCODE register. By using the IDCODE, the device connected to the JTAG port can be determined. The use of the IDCODE enables selective configuration dependent upon the FPGA found. The IDCODE register has the following binary format: vvvv :fff:fffa:aaaa:aaaa:ccece:ccce:cecl Where: c = the company code; a = the array dimension in CLBs; f =the Family code; v = the die version number Family Codes = 01 for XLA; = 02 for SpartanXL; = 03 for Virtex; = 07 for XV. Xilinx company code = 49 (hex) Table 4: IDCODEs assigned to XC4000XLA/XV FPGAs FPGA IDCODE XC4013XLA 0x00218093 XC4020XLA 0x0021c093 XC4028XLA 0x00220093 XC4036XLA 0x00224093 XC4044XLA 0x00228093 XC4052XLA 0x0022c093 XC4062XLA 0x00230093 XC4085XLA 0x00238093 XC40110XV 0x00e40093 XC40150XV 0x00e48093 XC40200XV 0x00e54093 XC40250XV 0x00e5c093 * Configuration State - The configuration state is available to JTAG controllers. * Configure Disable - The JTAG port can be prevented from reconfiguring the FPGA * TCK Startup - TCK can now be used to clock the start-up block in addition to other user clocks. * CCLK holdoff - Changed the requirement for Boundary Scan Configure or EXTEST to be issued prior to the release of INIT pin and CCLK cycling. Reissue configure - The Boundary Scan Configure can be reissued to recover from an unfinished attempt to configure the device. * Bypass FF - Bypass FF and IOB is modified to provide DRCLOCK only during BYPASS for the bypass flip-flop and during EXTEST or SAMPLE/PRELOAD for the lOB register. Differences between the XC4000XV and XC4000XLA FPGAs The high density of the XC4000XV family FPGAs is achieved by using advanced 0.25 micron silicon technol- ogy. A 2.5 Volt power supply (VCCINT) is necessary to pro- vide the reduced supply voltage required by 0.25 micron internal logic, however to maintain TTL compatibility a 3.3V power supply (VCCIO) is required by the I/O. To accommodate the higher gate capacity of XV devices, additional interconnect has been added. These differences are detailed below. * VCCINT (2.5 Volt) Power Supply Pins The XV family of FPGAs requires a 2.5V power supply for internal logic, which is named VCCINT. The pins assigned to the VCCINT supply are named in the pinout guide for the XC4000XV FPGAs and in Table 5 on page * VCCIO (3.3 Volt) Power Supply Pins Both the XV and XLA FPGAs use a 3.3V power supply to power the I/O pins. The I/O supply is named VCCIO in the XV family. Octal-Length Interconnect Channels The XC401 10XV, XC40150XV, XC40200XV, and XC40250XV have enhanced routing. Eight routing channels of octal length have been added to each CLB in both vertical and horizontal dimensions. XC4000XLA Socket Compatibility with XL FPGAs The XC4000XLA devices are generally available in the same packages as equivalent XL devices, however the range of packages available for the XC4085XLA has been extended to include smaller packages such as the HQ240. XC4000XV Socket Compatibility with XL/XLA FPGAs XC4000XV devices are available in five package options, pin-grid PG599 and ball-grid BG560, BG432, and BG352 and quad-flatpack HQ240. With the exception of the VCCINT power pins, XC4000XV FPGAs are compatible with XL and XLA devices in these packages if the following guidelines are followed: * Lay out the PCB for the XV pinout. * When an XL or XLA device is installed disconnect the VCCINT (2.5 V) supply. For the PG599, VCCINT should be connected to 3.3V. For BG560, BG432 and BG352 and HQ240 packages, the VCCINT voltage source should be left unconnected. The unused |/O pins in the February 1, 1999 (Version 1.0) 6-165XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XL/XLA devices connected to VCCINT will be pulled up Table 5: VCCINT (2.5 V) Pins in XV Packages to 3.3V. Care must be taken to insure that these pins are not driven when the XL/XLA device is operative. HQ240 BG352 BG432 BG560 PGS559 * When an XC4000XV is installed, the VCCINT pins must P198 D10 A10 E12 H12 be connected to a 2.5V power supply. P185 D5 AB2 AD2 H18 The differences between the XL and XV packages are P164 K4 AB30 AD32 H26 detailed below: P154 N3 AG28 AK31 H32 PG559 - XLA and XL devices in the PG599 package have P1397 We AH15 AM17 M8 56 VCC pins.The XC4000XV devices allocate 16 of these P116 AE3 AHS AKS M36 I/O pins to VCCINT (2.5V). P104 AC10 AJ10 AK11 V8 BG560 - XLA and XL devices in the BG560 package have P93 AC13 AK22 AN25 V36 448 I/O pins.The XC4000XV devices allocate 16 of these P77 AE19 B23 C24 AF8 I/O pins to VCCINT (2.5V). P55 AB24 B4 D6 AF36 BG432- XLA and XL devices in the BG432 package have P43 v24 C16 C17 AM8 352 I/O pins. The XC4000XV devices allocate 16 of these P27 N24 E28 E30 AM36 I/O pins to VCCINT (2.5V). P16 J24 K29 K32 AT12 BG352 - XLA and XL devices in the BG352 package have Pa D24 K3 J1 AT18 289 I/O pins. The XC4000XV devices allocate 15 of these P225 A20 R2 T3 AT26 I/O pins to VCCINT (2.5V). - - R29 U32 AT32 HQ240- XLA and XL devices in the HQ240 package have 193 I/O pins. The XC4000XV devices allocate 15 of these I/O pins to VCCINT (2.5V). 6-166 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA/XV I/O Signalling Standards XLA and XV devices are compatible with TTL, LVTTL, PCI 3V, PCI 5V and LVCMOS signalling. The various standards are illustrated in Tatie 6 and the signaling environment is illustrated in Figure 4. VCC Clamping XLA/XV devices are fully 5V TTL I/O compatible if VCC clamping is not enabled. The I/O pins can withstand input voltages up to 7V. With VCC clamping enabled, the XLA/XV devices will begin to clamp input voltages to one diode volt- age drop above VCC. In both cases negative voltage is clamped to one diode voltage drop below ground. XLA/XV devices maintain LVTTL I/O compatibility when VCC clamping is enabled, however full 5.0V TTL I/O com- patibility is sacrificed. Overshoot and Undershoot Ringing wave forms are allowed on XLA/XV inputs as long as undershoot is limited to -2.0V and overshoot is limited to +7.0V and current is limited to 100 mA for less than 10 ns. If VCC clamping is enabled then overshoot will begin to be clamped at VCC/VCCIO plus one diode voltage drop and undershoot will be clamped to ground minus one diode volt- age drop. In either case the current must be limited to 100 mA per pin for less than 10 ns. Table 6: l/O Standards supported by XC4000XLA and XV FPGAs Signaling vcc Standard Clamping | Output Drive} Vin_max Vin MIN ViL max Vou MIN VoL MAX TTL Not allowed 12/24 mA 5.5 2.0 0.8 2.4 0.4 LVTTL OK 12/24 mA 3.6 2.0 0.8 2.4 0.4 PCI5V Not allowed 24 mA 5.5 2.0 0.8 2.4 0.4 PCI3V Required 12 mA 3.6 50% of 30% of 90% of 10% of VCCNCCIO | VCCNVCCIO | VCC/VCCIO | VCC/VCCIO LVCMOS 3V OK 12/24 mA 3.6 50% of 30% of 90% of 10% of VCCNCCIO | VCCNVCCIO | VCC/VCCIO | VCC/VCCIO 5.0 V Power oe 3.3 V Power e e 2.5 V Power Voc 6 V) Vecio Vecint Voc (3.3 V) TTL LVTTL 5 Volt Device 1 = XC4000XV < 1 3.3 Volt Device _ LVTTL Ground | | | X7147 Figure 4: The Signalling Environment for XLA/XV FPGAS. For XLA devices the VCCIO and VCCINT supplies are replaced by a single 3.3 Volt VCC supply, however, all indicated I/O signalling is still supported. Express Configuration Mode Express configuration mode is similar to Slave Serial con- figuration mode, except that data is processed one byte per CCLK cycle instead of one bit per CCLK cycle. An external source is used to drive CCLK, while byte-wide data is loaded directly into the configuration data shift registers (Figure 5). A CCLK frequency of 10 MHz is equivalent to a 80 MHz serial rate, because eight bits of configuration data are loaded per CCLK cycle. Express mode does not sup- February 1, 1999 (Version 1.0) 6-167XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? port CRC error checking, but does support constant-field error checking. A length count is not used in Express mode. Express mode must be specified as an option to the BitGen program, which generates the bitstream. The Express mode bitstream is not compatible with the other configura- tion modes. Express mode is selected by a <010> on the mode pins (M2, M1, MO). The first byte of parallel configuration data must be avail- able at the D inputs of the FPGA a short setup time before the second rising CCLK edge. Subsequent data bytes are clocked in on each consecutive rising CCLK edge (Figure 6). Pseudo Daisy Chain As illustrated in Figures 5 and 6, multiple devices with dif- ferent configurations can be configured in a pseudo daisy chain provided that all of the devices are in Express mode. A single combined byte-wide data stream is used to config- ure the chain of Express mode devices. CCLK pins are tied together and DO-D7 pins are tied together as a data buss for all devices along the chain. A status signal is passed from DOUT of each device to the CS1 input of the device which follows it in the chain. Frame data is accepted only when CS1 is High and the devices configuration memory is not already full. The lead device in the chain has its CS1 input tied High (or floating, since there is an internal pullup). The status pin DOUT is initially High for all devices in the chain until the data stream header of seven bytes is loaded. This allows header data to be loaded into all devices in the chain simultaneously. After the header is loaded in all devices, their DOUT pins are pulled Low disabling configu- ration of all devices in the chain except the first device. As each device in the chain is filled, its DOUT goes High driv- ing High the CS1 input of the next device, thereby enabling configuration of the next device in the pseudo daisy chain. The requirement that all DONE pins in a daisy chain be wired together applies only to Express mode, and only if all devices in the chain are to become active simultaneously. All 4000XLA/XV devices in Express mode are synchro- nized to the DONE pin. User I/O for each device becomes active after the DONE pin for that device goes High (The exact timing is determined by BitGen options.) Since the DONE pin is open-drain and does not drive a High value, tying the DONE pins of all devices together pre- vents all devices in the chain from going High until the last device in the chain has completed its configuration cycle. If the DONE pin of a device is left unconnected, the device becomes active as soon as that device has been config- ured. Table 7: Pin Functions During Configuration (4000XLA/XV Express mode only) CONFIGURATION MODE USER <M2:M1:MO> OPERATION EXPRESS MODE PIN FUNCTION <0:1:0> M2(LOW) (H M2 M1 (HIGH) (1) M1 MO(LOW) (I) MO HDC (HIGH) v0 LDC (LOW) Tr) INIT v0 DONE DONE PROGRAM (1) PROGRAM CCLK (I) CCLK (I) DATA 7 (I) v0 DATA 6 (I) 0 DATA 5 (\) v0 DATA 4 (I) 0 DATA 3 (I) v0 DATA 2 ( 0 DATA 1 ( v0 DATA 0 (I) 0 DOUT SGCK4-I/0 TDi TDIV/O TCK TCK-/0 TMS TMS-I/0 TDO TDO-(O) CSi 0 Notes 1. A shaded table cell represents the internal pull-up used before and during configuration. 2. (I) represents an input; (O) represents an output. 3. INIT is an open-drain output during configuration. Because only XC4000XLA/XV, SpartanXL, and XC5200 devices support Express mode, only these devices can be used to form an Express mode pseudo daisy chain. 6-168 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays vcc 8 mo Mime M1 M2 - , : Daisy-Chained ) CS1 DOUT > DOUT DATA BUS 3~| DO-D7 8 > Optional vec Daisy-Chained 4000XLA/XV 4000XLA/XV 4.7K $ PROGRAM | PROGRAM PROGRAM INIT <> INIT DONE tt DONE CCLK A To Additional ccLK Daisy-Chained 99010800 Figure 5: Express Mode Circuit Diagram Table 8: Express Mode Programming Switching Characteristic Description Symbol Min Max Units INIT (High) setup time Tic 5 ys DO - D7 setup time Toc 20 ns CCLK DO - D7 hold time Tep 0 ns CCLK High time Toco 45 ns CCLK Low time Toei 45 ns CCLK Frequency Foc 10 MHz Preliminary February 1, 1999 (Version 1.0)XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? JLELELIL CCLK O Tc . INIT . _ [< Too @ @tp6 > | - ey BYTE BYTE BYTE BYTE BYTE BYTE BYTE Do-D7 (BYTE BYTE \ BYTE BYTE BYTE X BY 6 rx \_ < Header DOUT Header Loaded FPGA Filled csi 99010700 Note: CS1 must remain High throughout loading of the configuration data stream. In the pseudo daisy chain of Figure 5, the 7 byte data stream header is loaded into all devices simultaneously. Each devices data frames are then loaded in turn when its CS1 pin is driven High by the DOUT of the preceding device in the chain. Figure 6: Express Mode Programming Switching Waveforms Data Stream Format The data stream (bitstream) format is identical for all serial configuration modes, but different for the 4000XLA/XV Express mode. In Express mode, the device becomes active when DONE goes High, therefore no length count is required. Additionally, CRC error checking is not supported in Express mode. The data stream format is shown in Table 8. Express mode data is shown with DO at the left and D7 at the right. The configuration data stream begins with two bytes of eight ones each, a preamble code of one byte, followed by three bytes of eight ones each, and finally an end-of- header field check byte. This header of seven bytes is fol- lowed by the actual configuration data in frames. The length and number of frames depends on the device type. Each frame begins with a start field and ends with an end-of-frame field check byte. In all cases, additional start-up bytes of data are required to provide six, or more, clocks for the start-up sequence at the end of configuration. Long daisy chains require additional startup bytes to shift the last data through the chain. All startup bytes are dont-cares; these bytes are not included in bitstreams cre- ated by the Xilinx software. A selection of CRC or non-CRC error checking is allowed by the bitstream generation software. The 4000XLA Express mode only supports non-CRC error checking. The non-CRC error checking tests for a designated end-of-frame field check byte for each frame. non-CRC error checking tests for a designated end-of-frame field check byte for each frame. Table 9: 4000XLA/XV Express Mode Data Stream Format Express Mode Data Type (DO-D7) (4000XLA only) Fill Byte FFFFh Preamble Code 11110010b Fill Byte FFFFFFh End-of-Header 11010010b Field Check Byte Start Field 11111110b Data Frame DATA(n-1:0) End-of-Frame 11010010b Field Check Byte Extend Write Cycle FFD2FFFFFEH Start-Up Bytes FFFFFFFFFFFFh LEGEND: Unshaded Once per data stream Light Once per data frame Detection of an error results in the suspension of data load- ing and the pulling down of the INIT pin. The user must detect INIT and initialize a new configuration by pulsing the PROGRAM pin Low or cycling VCC. 6-170 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays Serial PROM Recommendation Table 16 shows the physical characteristics of each FPGA family member and the recommended Xilinx Serial PROM recommended for use as configuration storage. Table 10: Physical Characteristics and Recommended Serial PROM Max. CLB Total | Logic | Number |Max. RAM | Required Device : of Bits Configur- Serial PROM User I/O Matrix CLBs Cells : : : : Flip-Flops |(No Logic) |ation Bits XC4013XLA 192 24 x 24 576 1,368 1,536 18,432 393,632 XC17512L XC4020XLA 224 28 x 28 784 1,862 2,016 25,088 521,880 XC17512L XC4028XLA 256 32 x 32 1,024 2,432 2,560 32,768 668,184 XC1701L XC4036XLA 288 36 x 36 1,296 3,078 3,168 41,472 832,528 XC1701L XC4044XLA 320 40 x 40 1,600 3,800 3,840 51,200 1,014,928 XC1701L XC4052XLA 352 44 x 44 1,936 4,598 4,576 61,952 1,215,368 XC1702L XC4062XLA 384 48 x 48 2,304 5,472 5,376 73,728 1,433,864 XC1702L XC4085XLA 448 56 x 56 3,136 7,448 7,168 100,352 1,924,992 XC1702L XC40110XV 448 64 x 64 4,096 9,728 9,216 131,072 2,686,136 XC1704L XC40150XV 448 72x72 5,184 12,312 11,520 165,888 3,373,448 XC1704L XC40200XV 448 84 x 84 7,056 16,758 15,456 225,792 4,551,056 | XC1704L4+XC17512L XC40250XV 448 92 x 92 8,464 20,102 18,400 270,848 5,433,888 | XC1704L4+XC1702L February 1, 1999 (Version 1.0) 6-171XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX User I/O Per Package Table 141 shows the number of user |/Os available in each package for XC4000XLA/XV-Series devices. Call your local sales office for the latest availability information. Table 11: User I/O Pins Available by Device and Package Maximum I/O Acessible per Package Max | & S 3 + + 6 S is o rs ~ ~ q ql Ql Q a oO oF tf 10 LO Device MO} eZ [2 [Fi eze{ [Fie lslal[e<lala|& ja XC4013XLA 192 129 160 192 192 XC4020XLA 224 129 160 193 | 205 XC4028XLA 256 129 160 193 205 | 256 256 XC4036XLA 288 129 160 193 256 288 288 XC4044XLA 320 129 160 193 256 289 320 XC4052XLA 352 129 160 193 256 289 352 352 XC4062XLA 384 129 160 193 256 289 352 384 XC4085XLA 448 129 160 193 256 289 352 448 XC40110XV 448 178 274 | 336 432 XC40150XV 448 178 274 | 336 448 432 XC40200XV 448 336 432 XC40250XV 448 336 448 432 6-172 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays Product Availability XC4000XLA Product Availability Table 12 shows the planned packages and speed grades for XC4000XLA-Series devices. Call your local sales office for the latest availability information, or see the Xilinx WEBLINX at http:/Awww.xilinx.com for the latest revision of the specifications. Table 12: Component Availability Chart for XC4000XLA FPGAs PINS XC4013XLA XC4020XLA XC4028XLA XC4036XLA XC4044XLA XC4052XLA XC4062XLA XC4085XLA -09 -08 -07 -09 -08 -07 -09 -08 -07 -09 -08 -07 -09 -08 -07 -09 -08 -07 -09 -08 -07 -09 -08 -07 I) o}olo]o}o]e}e|BG25e} Pest o| nN Ceram. PGA PG299 wo QFP & High-Perf. Q304 & Ceram. PGA PG411 i Plast BGA BG432 NI a Ceram. PGA PG475 a Qn Ceram. PGA PG559 C = Commercial T, = 0 to +85C l= Industrial Ty = -40C to +100C February 1, 1999 (Version 1.0) 6-173XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4000XV Product Availability 49 Figure 13 shows the planned packages and speed grades for XC4000XV-Series devices. Call your local sales office for the latest availability information, or see the Xilinx WEBLINX at http:/Awww.xilinx.com for the latest revision of the specifications. Table 13: Component Availability Chart for XC4000XV FPGAs nN & S Q a a a PINS 84 10 10 160 | 160 6 | 176 | 208 Ceram. PGA Ceram. PGA Ceram. PGA Ceram. PGA PG299 PG475 PG559 PG411 -09 XC40110XV | -08 -07 -09 XC40150XV | -08 -07 -09 XC40200XV | -08 -07 -09 XC40250XV | -08 -07 C = Commercial T, = 0 to +85C l= Industrial T, = -40C to +100C 6-174 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA D.C. and Switching Performance Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered final. Occasionally, values are of mixed classification. These are highlighted in bold face and the tables involved include a note explaining the nature of the bold face entries. All specifications are subject to change without notice. Additional Specifications Except for pin-to-pin input and output parameters, the AC parameter delay specifications included in this document are derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. Absolute Maximum Ratings Symbol Description Values Units Vec Supply voltage relative to GND -0.5 to 4.0 Vv Vin Input voltage relative to GND (Note 1) -0.5 to 5.5 Vv Vis Voltage applied to 3-state output (Note 1) -0.5 to 5.5 Vv Voct Longest Supply Voltage Rise Time from 1 V to 3V 50 ms Tst Storage temperature (ambient) -65 to +150 C Tso. Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 C T Junction temperature Ceramic packages +150 C Plastic packages +125 C Notes: 1. Maximum DC overshoot or undershoot above V,, or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol Description Min Max Units Supply voltage relative to GND, Ty = 0 C to +85C Commercial 3.0 3.6 Vv Voc Supply voltage relative to GND, Ty = -40C to +100C | Industrial 3.0 3.6 Vv Vin High-level input voltage 50% of Veco 5.5 Vv Vit Low-level input voltage 0 30% of Voc Vv TIN Input signal transition time 250 ns Note: Atjunction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. Input and output measurement threshold is ~50% of Voc. February 1, 1999 (Version 1.0) 6-175XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX DC Characteristics Over Recommended Operating Conditions Symbol Description Min Max Units Vou High-level output voltage @ loy = -4.0 mA, Vee min (LVTTL) 2.4 Vv High-level output voltage @ Ioy = -500 pA, (LVCMOS) 90% Veco Vv Vo Low-level output voltage @ lo, = 24.0 mA, Vee min (LVTTL) (Note 1) 0.4 Vv Low-level output voltage @ Io, = 1500 nA, (LVCMOS) 10% Veco Vv Vopr Data Retention Supply Voltage (below which configuration data may be lost) 2.5 Vv leco Quiescent FPGA supply current (Note 2) 10 mA IL Input or output leakage current -10 +10 HA Input capacitance (sample tested) BGA, SBGA, PQ, HQ, MQ packages 10 pF CIN PGA packages 16 pF IRPU Pad pull-up (when selected) @ V,, = 0 V (sample tested) 0.02 0.25 mA IRPD Pad pull-down (when selected) @ V;, = 3.6 V (sample tested) 0.02 0.15 mA IRL Horizontal Longline pull-up (when selected) @ logic Low 0.3 2.0 mA Notes: 1. With up to 64 pins simultaneously sinking 24 mA 2. With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating 6-176 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA Clock Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature. Values apply to all XC4000XLA devices and expressed in nanoseconds unless otherwise noted. XC4000XLA Global Low Skew Clock Input to Clock K Speed Grade] All -09 -08 -07 Units Description Symbol Device Min | Max | Max | Max Delay from pad through Global Low Skew (GLS) clock Tets | XC4013XLA 2.4 2.1 1.9 ns buffer to any clock input, K. XC4020XLA 26 23 24 ns XC4028XLA 2.9 2.6 2.3 ns XC4036XLA 3.2 2.8 2.5 ns XC4044XLA 3.6 3.1 2.8 ns XC4052XLA 3.9 3.4 3.1 ns XC4062XLA 4.2 3.7 3.3 ns XC4085XLA 5.0 4.4 3.9 ns Preliminary XC4000XLA FastCLK Input to IOB Clock Input Speed Grade] All -09 -08 -07 Units Description Symbol Device Min | Max | Max | Max Delay from pad through FastCLK buffer to any IOB clock | Trop. | XC4013XLA 1.5 1.3 1.1 ns input. XC4020XLA 15 | 13[ 12] ns XC4028XLA 1.6 1.4 1.3] ns XC4036XLA 1.7 1.5 1.4] ns XC4044XLA 1.8 1.6 1.4] ns XC4052XLA 1.9 1.7 1.5] ns XC4062XLA 2.0 1.8 1.6] ns XC4085XLA 2.3 2.0 1.8] ns Note: Values in bold face are preliminary, all other values are advance. Preliminary February 1, 1999 (Version 1.0) 6-177XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4000XLA Clock Buffer Switching Characteristic Guidelines (Cont) XC4000XLA Global Early Clock Input to |OB Clock Input; BUFGE #s 1, 2, 5, and 6. Speed Grade] All -09 -08 -07 Units Description Symbol Device Min | Max | Max | Max Delay from pad through Global Early (GE) clock buffer to Tge | XC4013XLA 1.7 1.5 1.3 ns any IOB clock input for BUFGE #1, 2, 5, and 6. XC4020XLA 1.9 1.7 15 ns XC4028XLA 2.1 1.9 1.7 ns XC4036XLA 2.4 2.2 1.9 ns XC4044XLA 2.7 2.4 2.2 ns XC4052XLA 3.0 2.7 2.4 ns XC4062XLA 3.3 3.0 2.7 ns XC4085XLA 3.7 3.3 3.0 ns Preliminary XC4000XLA Global Early Clock Input to |OB Clock Input; BUFGE #s 3, 4, 7, and 8. Speed Grade] All -09 -08 -07 Units Description Symbol Device Min | Max | Max | Max Delay from pad through Global Early (GE) clock buffer to Tce XC4013XLA 2.4 2.1 1.9 ns any IOB clock input for BUFGE 3, 4, 7, and 8. XC4020XLA 2.6 2.3 2.1 ns XC4028XLA 2.9 2.6 2.3 ns XC4036XLA 3.2 2.8 2.5 ns XC4044XLA 3.6 3.1 2.8 ns XC4052XLA 3.9 3.4 3.1 ns XC4062XLA 4.2 3.7 3.3 ns XC4085XLA 5.0 4.4 3.9 ns Preliminary 6-178 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XLA devices and expressed in nanoseconds unless otherwise noted. Speed Grade -09 -08 -07 Units Description Symbol Min | Max Min | Max Min | Max Combinatorial Delays F/G inputs to X/Y outputs TiLo 1.4 1.0 0.9 ns F/G inputs via H to X/Y outputs TIHo 1.9 1.7 1.5 ns F/G inputs via transparent latch to Q outputs Tito 2.0 1.8 1.6 ns C inputs via SR/HO via H to X/Y outputs THHoo 1.7 1.6 1.4 ns C inputs via H1 via H to X/Y outputs THH10 1.6 1.4 1.3 ns C inputs via DIN/H2 via H to X/Y outputs THH20 1.7 1.6 1.4 ns C inputs via EC, DIN/H2 to YQ, XQ output (bypass) Tepyp 1.1 1.0 0.9 ns CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to Coyy Topcy 1.0 0.9 0.8 ns Add/Subtract input (F3) to Coyy Tascy 1.2 1.4 1.0 ns Initialization inputs (F1, F3) to Coyt TINCY 0.8 0.7 0.6 ns Cyy through function generators to X/Y outputs Tsum 1.7 1.5 1.3 ns Cy to Coyz, bypass function generators Tayp 0.1 0.1 0.1 ns Carry Net Delay, Coyt to Cin TNET 0.17 0.15 0.13 ns Sequential Delays Clock K to Flip-Flop outputs Q Texo 1.5 1.3 1.2 ns Clock K to Latch outputs Q TeKLo 1.5 1.3 1.2 ns Setup Time before Clock K F/G inputs Tick 0.7 0.7 0.6 ns F/G inputs via H Tick 1.4 1.3 1.2 ns C inputs via HO through H TuHHock 1.3 1.2 1.1 ns C inputs via H1 through H TuHick 1.2 1.4 1.0 ns C inputs via H2 through H THHeck 1.3 1.2 1.1 ns C inputs via DIN Tpick 0.6 0.6 0.5 ns C inputs via EC Teeck 0.7 0.6 0.5 ns C inputs via S/R, going Low (inactive) Trek 0.5 0.4 0.4 ns CIN input via F/G Tock 1.2 1.1 1.0 ns CIN input via F/G and H Teuek 2.0 1.7 1.6 ns Hold Time after Clock K All Hold Times | 00 | | 0.0 | | oo | | ns Clock Clock High time Tou 2.2 1.9 1.7 ns Clock Low time Tet 2.2 1.9 1.7 ns Set/Reset Direct Width (High) Trew 2.3 2.3 2.3 ns Delay from C inputs via S/R, going High to Q Trio 2.5 2.2 2.0 ns Global Set/Reset Minimum GSR Pulse Width Taw | 12.8 | | 11.4 | | 10.2 J ns Delay from GSR input to any Q Tura See page 789 for TRRI values per device. Toggle Frequency (MHz) (for export control) Frog | 227 | | 263 | | 294 MHz Preliminary February 1, 1999 (Version 1.0) 6-179XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4000XLA RAM Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XLA devices and are expressed in nanoseconds unless otherwise noted. . Speed Grade -09 -08 -07 Single Port RAM Units Size | Symbol | Min | Max | Min | Max | Min | Max Write Operation Address write cycle time (clock K period) 16x2 | Twcs 6.7 5.9 5.3 ns 32x1 Twets 6.7 5.9 5.3 ns Clock K pulse width (active edge) 16x2 | Twps 3.4 3.0 2.7 ns 32x1 Twpts 3.4 3.0 2.7 ns Address setup time before clock K 16x2 | Tass 1.5 1.3 1.2 ns 32x1 Tasts 1.5 1.3 1.2 ns Address hold time after clock K 16x2 | Tans 0.0 0.0 0.0 ns 32x11 TaHTS 0.0 0.0 0.0 ns DIN setup time before clock K 16x2 | Toss 1.5 1.3 1.2 ns 32x11 Tpsts 2.11 1.6 1.5 ns 8 DIN hold time after clock K 16x2 | Tous 0.0 0.0 0.0 ns 32x1 TpuTs 0.0 0.0 0.0 ns WE setup time before clock K 16x2 | Twss 1.4 1.3 1.1 ns 32x1 Twsts 1.3 1.2 1.1 ns WE hold time after clock K 16x2 | Twus 0.0 0.0 0.0 ns 32x1 Twuts 0.0 0.0 0.0 ns Data valid after clock K 16x2 | Twos 5.0 4.4 4.2 ns 32x11 Twots 5.8 5.2 4.7 ns Read Operation Address read cycle time 16x2 | Tre 2.6 2.6 2.6 ns 32x1 | Tact 3.8 3.8 3.8 ns Data Valid after address change (no Write En-| 16x2 | Tyo 1.1 0 0.9 ns able) 32x1 | TiHo 1.9 7 1.5 ns Address setup time before clock K 16x2 | Tick 0.7 0.7 0.6 ns 32x1 Tick 1.4 1.3 1.2 ns Advance 6-180 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XLA devices and are expressed in nanoseconds unless otherwise noted. Speed Grade --09 -08 -07 Dual Port RAM Units Size Symbol Min | Max | Min | Max | Min | Max Address write cycle time (clock K period) 16x1_ | Tweps 6.7 5.9 5.3 ns Clock K pulse width (active edge) 16x1__ | Tweps 3.4 3.0 2.7 ns Address setup time before clock K 16x1_ | Tasps 1.5 1.3 1.2 ns Address hold time after clock K 16x1_ | Taps 0.0 0.0 0.0 ns DIN setup time before clock K 16x1_ | Tpsps 1.7 1.6 1.4 ns DIN hold time after clock K 16x1_ | Topps 0.0 0.0 0.0 ns WE setup time before clock K 16x1_ | Twsps 1.4 1.3 1.1 ns WE hold time after clock K 16x1_ | Twups 0.0 0.0 0.0 ns Data valid after clock K 16x1_ | Twops 5.7 5.1 4.6 ns Preliminary XC4000XLA CLB RAM Synchronous (Edge-Triggered) Write Timing ILD T. T. IPAD > D Q l2 IK Internal Write Performed DATAI IPAD, 11 Address SX Data / X 12 Address SeXX oO Address Latched X6461 X6774, Single Port RAM Dual Port RAM February 1, 1999 (Version 1.0) 6-181XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4000XLA Pin-to-Pin Output Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. XC4000XLA Global Clock Input to Output Delay Speed Grade] All -09 -08 -07 Units Description Symbol Device Min | Max | Max | Max Global Low Skew (GLS) Clock Input to Output Delay us-| Ticxor | XC4013XLA 5.6 5.0 4.5 ns ing Output Flip-Flop XC4020XLA 58 | 52] 47] ns XC4028XLA 6.4 5.5 4.9 ns XC4036XLA 6.4 5.7 5.1 ns XC4044XLA 6.8 6.0 5.4 ns XC4052XLA 7.1 6.3 5.7 ns XC4062XLA 7.4 6.6 5.9 ns XC4085XLA 8.2 7.3 6.5 ns For output SLOW option add Tstow | All Devices 1.7 1.6 1.4 ns Preliminary Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. Output timing is measured at ~50% Vec threshold with 50 pF external capacitive load. For different loads, see Figure 7. Note: Values in bold face are preliminary, all other values are advance. XC4000XLA FastCLK Input to Output Delay for BUFNW, BUFSW, BUFNE, & BUFSE Speed Grade] All -09 -08 -07 Units Description Symbol Device Min | Max | Max | Max FastCLK Input to Output Delay using Output Flip-Flop =| Tickror | XC4013XLA 4.6 4.1 3.7 ns for FastCLK buffers BUFNW, BUFSW, BUFNE, and XC4020XLA 47 4.2 37 ns BUFSE. XC4028XLA 4.8 4.3 3.8 ns XC4036XLA 4.9 4.4 3.9 ns XC4044XLA 5.0 4.4 4.0 ns XC4052XLA 5.1 4.5 4.1 ns XC4062XLA 5.2 4.6 4.1 ns XC4085XLA 5.4 4.8 4.3 ns For output SLOW option add Tstow | All Devices 4.6 4.1 3.7 ns Preliminary Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. Output timing is measured at ~50% Vec threshold with 50 pF external capacitive load. For different loads, see Figure 7. Note: Values in bold face are preliminary, all other values are advance. 6-182 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA Pin-to-Pin Output Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. XC4000XLA Global Early Clock Input to Output Delay for BUFGE #s 1, 2, 5, and 6 Speed Grade] All -09 -08 -07 Units Description Symbol Device Min Max Max Max Global Clock Signal Input to Output Delay using TickEor | XC4013XLA 4.9 4.4 3.9 ns Global Early (GE) clock buffer to clock Output XC4020XLA 5.1 4.6 4.1 ns Flip-Flop for BUFGE #s 1, 2, 5, & 6. XC4028XLA 5.3 4.8 4.3 ns XC4036XLA 5.6 5.1 4.5 ns XC4044XLA 5.9 5.3 4.8 ns XC4052XLA 6.2 5.6 5.0 ns XC4062XLA 6.5 5.9 5.3 ns XC4085XLA 6.9 6.2 5.6 ns Preliminary Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. Output timing is measured at ~50% Vec threshold with 50 pF external capacitive load. For different loads, see Figure 7. XC4000XLA Global Early Clock Input to Output Delay for BUFGE #s 3, 4, 7, and 8 Speed Grade] All -09 -08 -07 Units Description Symbol Device Min Max | Max | Max Global Clock Signal Input to Output Delay using TickEor | XC4013XLA 5.7 5.1 4.5 ns Global Early (GE) clock buffer to clock Output XC4020XLA 5.9 5.3 4.7 ns Flip-Flop for BUFGE #s 3, 4, 7, & 8. XC4028XLA 6.1 5.4 4.9 ns XC4036XLA 6.3 5.6 5.0 ns XC4044XLA 6.5 5.8 5.2 ns XC4052XLA 6.8 6.0 5.4 ns XC4062XLA 7.0 6.3 5.6 ns XC4085XLA 7.5 6.7 6.0 ns Preliminary Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. Output timing is measured at ~50% Vec threshold with 50 pF external capacitive load. For different loads, see Figure 7. February 1, 1999 (Version 1.0) 6-183XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? Capacitive Load Factor Figure 7 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the speci- fied output delay if the load capacitance is different than 50 pF For example, if the actual load capacitance is 120 pF add 2.5 ns to the specified delay. If the load capac- itance is 20 pF, subtract 0.8 ns from the specified output delay. Figure 7 is usable over the specified operating conditions of voltage and temperature and is independent of the output slew rate control. Delta Delay (ns) O 20 40 60 80 Capacitance (pF) Figure 7: Delay Factor at Various Capacitive Loads 100 120 140 X8257 6-184 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA Pin-to-Pin Input Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. XC4000XLA Global Low Skew Clock, Set-Up and Hold IFF = Input Flip-Flop or Latch Notes: Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is Speed Grade 09 -08 -07 Units Description | Symbol | Device Min Min Min Input Setup and Hold Time Relative to Global Clock Input Signal No Delay XC4013XLA 1.0/3.0 0.8/2.6 0.2/2.5 ns Global Low Skew Clock and IFF Tpsn/Tpun | XC4020XLA 0.9/3.2 0.7/2.9 0.1/2.7 ns XC4028XLA 0.8/3.8 0.6/3.3 0.0/3.0 ns XC4036XLA 0.6 / 4.0 0.4/3.5 0.0/3.3 ns XC4044XLA 0.4/4.4 0.2/3.9 0.0/3.6 ns XC4052XLA 0.3 / 4.6 0.2/4.1 0.0/3.9 ns XC4062XLA 0.2 / 5.0 0.1/4.5 0.0/4.2 ns XC4085XLA 0.0/5.4 0.0/4.8 0.0/4.5 ns Partial Delay XC4013XLA 4.4/0.5 4.1/0.3 3.7/0.0 ns Global Low Skew Clock and IFF Tpsp/Tpyp | XC4020XLA 4.5/0.6 4.1/0.3 3.7/0.0 ns XC4028XLA 4.6/0.7 4.2/0.4 3.7/0.0 ns XC4036XLA 4.6/0.8 4.2/0.4 3.7/0.0 ns XC4044XLA 4.7/0.9 4.3/0.5 3.8/0.0 ns XC4052XLA 4.8/1.0 4.3/0.6 3.8/0.2 ns XC4062XLA 5.0/1.0 4.4/0.7 3.8/0.4 ns XC4085XLA 5.5/1.2 4.7/0.9 3.8/0.5 ns Full Delay XC4013XLA 4.4/0.0 4.1/0.0 3.7/0.0 ns Global Low Skew Clock and IFF Tpsp/Tpyp | XC4020XLA 4.6/0.0 4.2/0.0 3.8/0.0 ns XC4028XLA 4.8/0.0 4.4/0.0 3.9/0.0 ns XC4036XLA 4.9/0.0 4.5/0.0 4.0/0.0 ns XC4044XLA 5.0/0.0 4.6/0.0 4.1/0.0 ns XC4052XLA 5.2/0.0 4.7/0.0 4.2/0.0 ns XC4062XLA 5.5/0.0 4.9/0.0 4.3/0.0 ns XC4085XLA 6.0 / 0.0 5.2/0.0 4.4/0.0 ns Preliminary measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions. February 1, 1999 (Version 1.0) 6-185XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4000XLA Pin-to-Pin Input Parameter Guidelines (Cont.) Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. XC4000XLA FastCLK Input Set-Up and Hold for BUFNW, BUFSW, BUFNE, & BUFSE Speed Grade 09 08 -07 Units Description Symbol | Device Min Min Min Input Setup and Hold Time Relative to FastCLK Input Signal No Delay XC4013XLA J 0.0/ 3.2 0.0/ 2.9 0.0/ 2.6 ns FastCLK and IFF Tpsen/T PHEN XC4020XLA 0.0/ 3.3 0.0/ 3.0 0.0/ 2.7 ns XC4028XLA J 0.0/ 3.4 0.0/ 3.1 0.0/ 2.8 ns XC4036XLA J 0.0/ 3.5 0.0/ 3.2 0.0/ 2.9 ns XC4044XLA J 0.0/ 3.6 0.0/ 3.3 0.0/ 3.0 ns XC4052XLA J 0.0/ 3.7 0.0/ 3.4 0.0/ 3.1 ns XC4062XLA J 0.0/ 3.8 0.0/ 3.5 0.0/ 3.2 ns XC4085XLA J 0.0/ 3.9 0.0/ 3.6 0.0/ 3.3 ns Partial Delay XC4013XLA J 3.5/ 0.6 3.2/ 0.3 2.9/ 0.0 ns FastCLK and IFF Tpsep! pHEP XC4020XLA 3.7/ 0.4 3.4/ 0.2 3.1/ 0.0 ns XC4028XLA J 3.9/ 0.2 3.6/ 0.1 3.3/ 0.0 ns XC4036XLA J 4.1/ 0.0 3.8/ 0.0 3.5/ 0.0 ns XC4044XLA J 4.3/ 0.0 4.0/ 0.0 3.7/ 0.0 ns XC4052XLA J 4.5/ 0.0 4.2/ 0.0 3.9/ 0.0 ns XC4062XLA J 4.7/ 0.0 4.4/ 0.0 4.1/ 0.0 ns XC4085XLA J 5.1/ 0.0 4.8/ 0.0 4.5/ 0.0 ns Full Delay XC4013XLA J 3.5/ 0.6 3.2/ 0.3 2.9/ 0.0 ns FastCLK and IFF Tpsep/TpHrp | XC4020XLA J 3.8/ 0.4 3.5/ 0.2 3.2/ 0.0 ns XC4028XLA J 4.0/ 0.2 3.7/ 0.1 3.4/ 0.0 ns XC4036XLA J 4.3/ 0.0 4.0/ 0.0 3.7/ 0.0 ns XC4044XLA J 4.6/ 0.0 4.3/ 0.0 4.0/ 0.0 ns XC4052XLA J 4.9/7 0.0 4.6/ 0.0 4.3/ 0.0 ns XC4062XLA J 5.3/ 0.0 5.0/ 0.0 4.7/ 0.0 ns XC4085XLA J 6.1/ 0.0 5.8/ 0.0 5.5/ 0.0 ns Preliminary IFF = Input Flip-Flop Notes: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions. 6-186 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA BUFGE #s 1, 2, 5, and 6 Global Early Clock, Set-up and Hold for IFF and FCL Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. Speed Grade -09 -08 -07 Units Description | Symbol | Device Min Min Min Input Setup and Hold Time Relative to Global Clock Input Signal No Delay XC4013XLA 1.0/3.2 0.8/2.6 0.5/1.8 ns Global Early Clock and IFF Tpsen/TpHen | XC4020XLA 1.0/3.4 0.8/2.8 0.5/2.0 ns Global Early Clock and FCL Tprsen/TprHen | XC4028XLA 1.0/3.5 0.8/3.0 0.5/2.2 ns XC4036XLA 1.0/3.6 0.8/3.4 0.5/2.4 ns XC4044XLA 1.0/3.8 0.8/3.3 0.5/2.6 ns XC4052XLA 1.0/4.0 0.8/3.5 0.5/2.8 ns XC4062XLA 1.0/4.2 0.8/3.7 0.5/3.0 ns XC4085XLA 1.0/4.6 0.8/4.0 0.5/3.2 ns Partial Delay XC4013XLA 4.6/0.0 4.2/0.0 3.9/0.0 ns Global Early Clock and IFF Tpsep/TpHep | XC4020XLA 4.8/0.1 4.4/0.1 4.1/0.0 ns Global Early Clock and FCL Tpesep/TpeHep | XC4028XLA 4.9/0.1 4.6/0.1 4.4/0.0 ns XC4036XLA 5.0/0.2 4.7/0.1 4.5/0.0 ns XC4044XLA 5.5/0.3 5.1/0.2 4.8/0.0 ns XC4052XLA 5.8/0.3 5.3/0.2 5.0/0.0 ns XC4062XLA 6.2/0.4 5.6/0.2 5.2/0.0 ns XC4085XLA 6.5/0.5 5.9/0.3 5.4/0.0 ns Full Delay XC4013XLA 4.6/0.0 4.2/0.0 3.9/0.0 ns Global Early Clock and IFF Tpsep/TpHep | XC4020XLA 4.9/0.0 4.5/0.0 4.1/0.0 ns XC4028XLA 5.1/0.0 4.7/0.0 4.4/0.0 ns XC4036XLA 5.3/0.0 4.9/0.0 4.5/0.0 ns XC4044XLA 5.8/0.0 5.3/0.0 5.0/0.0 ns XC4052XLA 6.2/0.0 5.7/0.0 5.3/0.0 ns XC4062XLA 6.7/0.0 6.1/0.0 5.6/0.0 ns XC4085XLA 7.0/0.0 6.4/0.0 6.0/0.0 ns Preliminary IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Notes: Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions. February 1, 1999 (Version 1.0) 6-187XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC4000XLA BUFGE #s 3, 4, 7, and 8 Global Early Clock, Set-up and Hold for IFF and FCL Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted. Speed Grade -09 -08 -07 Units Description | Symbol | Device Min Min Min Input Setup and Hold Time Relative to Global Clock Input Signal No Delay XC4013XLA 0.8/3.2 0.6/2.6 0.4/2.0 ns Global Early Clock and IFF Tpsen/TpHen | XC4020XLA 0.8/3.4 0.6/2.8 0.4/2.2 ns Global Early Clock and FCL Tprsen/TprHen | XC4028XLA 0.8/3.5 0.6/3.0 0.4/2.4 ns XC4036XLA 0.8/3.6 0.6/3.4 0.4/2.6 ns XC4044XLA 0.8/3.8 0.6/3.3 0.4/2.8 ns XC4052XLA 0.8/4.0 0.6/3.5 0.4/3.0 ns XC4062XLA 0.8/4.2 0.6/3.7 0.4/3.2 ns XC4085XLA 0.8/4.6 0.6/4.0 0.4/3.4 ns Partial Delay XC4013XLA 4.4/0.0 4.0/0.0 3.6/0.0 ns Global Early Clock and IFF Tpsep/TpHep | XC4020XLA 4.6/0.1 4.2/0.1 3.8/0.0 ns Global Early Clock and FCL Tpesep/TpeHep | XC4028XLA 4.7/0.1 4.4/0.1 4.1/0.0 ns XC4036XLA 4.8/0.2 4.5/0.2 4.2/0.0 ns XC4044XLA 5.2/0.3 4.8/0.3 4.4/0.0 ns XC4052XLA 5.6/0.3 5.1/0.3 4.6/0.0 ns XC4062XLA 6.0/0.4 5.4/0.4 4.8/0.0 ns XC4085XLA 6.3/0.5 5.7/0.5 5.0/0.0 ns Full Delay XC4013XLA 4.4/0.0 4.0/0.0 3.6/0.0 ns Global Early Clock and IFF Tpsep/TpHep | XC4020XLA 4.7/0.0 4.3/0.0 3.8/0.0 ns XC4028XLA 4.9/0.0 4.5/0.0 4.1/0.0 ns XC4036XLA 5.1/0.0 4.7/0.0 4.2/0.0 ns XC4044XLA 5.6/0.0 5.1/0.0 4.6/0.0 ns XC4052XLA 6.0/0.0 5.5/0.0 4.9/0.0 ns XC4062XLA 6.5/0.0 5.9/0.0 5.2/0.0 ns XC4085XLA 6.8/0.0 6.2/0.0 5.6/0.0 ns , FCL = Fast Capture LatchIFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Notes: Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is Preliminary measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions. 6-188 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XLA IOB Input Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade 09 -08 -07 Units Description Symbol| Device Min | Max | Min | Max | Min | Max Clocks Clock Enable (EC) to Clock (IK) Tecik | All devices | 0.0 0.0 0.0 ns Delay from FCL enable (OK) active edge tolIFF | Tox | All Devices J 1.4 1.3 1.2 ns clock (IK) active edge Setup Times Pad to Clock (IK), no delay Tpick | All Devices | 1.2 1.0 0.9 ns Pad to Clock (IK), via transparent Fast Capture | Tpicxe | All Devices | 1.6 1.4 1.3 ns Latch, no delay Pad to Fast Capture Latch Enable (OK), no de-| Tpocx | All Devices | 0.8 0.7 0.6 ns lay Hold Times All Hold Times | All Devices | 0.0 | | 0.0 | | 0.0 | | ns Global Set/Reset Minimum GSR Pulse Width Turw | Alldevices | 12.8] | 11.4] | 10.2] | ns Global Set/Reset Delay from GSR input to any Q Trar | XC4013XLA 11.4 10.2 9.1 ns XC4020XLA 13.3 11.9 10.67 ns XC4028XLA 14.3 12.8 11.47 ns XC4036XLA 16.2 14.5 12.9] ns XC4044XLA 18.4 16.2 14.4] ns XC4052XLA 19.5 17.4 15.67 ns XC4062XLA 20.9 18.7 16.7] ns XC4085XLA 24.7 22.1 19.7] ns Propagation Delays Pad to 11, l2 Tpip All devices 1.0 0.9 0.8 ns Pad to |1, l2 via transparent input latch, node-} Tp, All devices 2.1 1.9 1.7 ns lay Pad to |1, I2 via transparent FCL and input TpeLI All devices 2.5 2.2 2.0 ns latch, no delay Clock (IK) to 11, 12 (flip-flop) TikRI All devices 1.1 1.0 0.9 ns Clock (IK) to 11, l2 (latch enable, active Low) TikKLI All devices 1.2 1.1 1.0 ns FCL Enable (OK) active edge to 11, 2 Toki | All devices 2.4 2.1 1.9 ns (via transparent standard input latch) Preliminary Notes: IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch * Indicates Minimum Amount of Time to Assure Valid Data. February 1, 1999 (Version 1.0) 6-189XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4000XLA IOB Output Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless otherwise noted. Values are expressed in nanoseconds unless otherwise noted. -09 -08 -07 - - - Units Description Symbol Min | Max | Min | Max | Min | Max Clocks Clock High Tou 2.2 1.9 1.7 ns Clock Low Tet 2.2 1.9 1.7 ns Propagation Delays Clock (OK) to Pad ToKPOF 3.2 2.9 2.6 ns Output (O) to Pad Tope 2.6 2.4 2.1 ns 3-state to Pad hi-Z (slew-rate independent) | Ttsyz 2.7 2.4 2.2 ns 3-state to Pad active and valid TTSONF 2.8 2.5 2.3 ns Output (O) to Pad via Fast Output MUX TorPpE 3.6 3.2 2.9 ns Select (OK) to Pad via Fast MUX TOKEPE 3.3 3.0 2.6 ns Setup and Hold Times Output (O) to clock (OK) setup time Took 0.3 0.3 0.3 ns Output (OQ) to clock (OK) hold time Toxo 0.0 0.0 0.0 ns Clock Enable (EC) to clock (OK) setup time] TEcox 0.0 0.0 0.0 ns Clock Enable (EC) to clock (OK) hold time | Toxec 0.0 0.0 0.0 ns Global Set/Reset Minimum GSR pulse width TwrRw 12.8 11.4 10.2 ns Delay from GSR input to any Pad Treo | XC4013XLA 14.4 12.8 11.5 XC4020XLA 16.3 14.5 13.0 XC4028XLA 17.3 15.4 13.8 XC4036XLA 19.4 17.4 15.3 XC4044XLA 21.0 18.8 16.8 XC4052XLA 22.5 20.1 17.9 XC4062XLA 23.9 21.3 19.0 XC4085XLA 27.7 24.7 22.1 Slew Rate Adjustment For output SLOW option add Tstow 1.7 1.6 1.4 ns Preliminary * Indicates Minimum Amount of Time to Assure Valid Data 6-190 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XV D.C. and Switching Performance Characteristics Definition of Terms In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as follows: Advance: Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. Values are subject to change. Use as estimates, not for production. Preliminary: Based on preliminary characterization. Further changes are not expected. Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. All specifications subject to change without notice. Additional Specifications Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are derived from measuring internal test patterns.All specifications are representative of worst- case supply voltage and junction temperature conditions. The parameters included are common to popular designs and typical applications. Absolute Maximum Ratings Symbol Description Value Units Vecint Supply voltage relative to GND -0.5 to 3.0 Vv Vecio Supply voltage relative to GND -0.5 to 4.0 Vv Vin Input voltage relative to GND (Note 1) -0.5 to 5.5 Vv Vis Voltage applied to 3-state output (Note 1) -0.5 to 5.5 Vv Vec Longest Supply Voltage Rise Time from 1 V to 3V 50 ms Tsta Storage temperature (ambient) -65 to +150 C Tso. Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 C ; Ceramic packages +150 C Ty Junction temperature - Plastic packages +125 C Notes: Maximum DC overshoot or undershoot above V,,. or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. February 1, 1999 (Version 1.0) 6-191XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX Recommended Operating Conditions Symbol Description Min Max Units Supply voltage relative to GND, Tj =0 C to +85C | Commercial 2.3 2.7 Vv VociNnT Supply voltage relative to GND, Ty = -40C to Industrial 2.3 2.7 Vv +100C Supply voltage relative to GND, Tj =0 C to +85C | Commercial 3.0 3.6 Vv Vecio Supply voltage relative to GND, Ty = -40C to Industrial 3.0 3.6 Vv +100C Vin High-level input voltage 50% of Voc 5.5 Vv Vit Low-level input voltage 0 30% of Veco Vv TIN Input signal transition time 250 ns Notes 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per C. Input and output measurement threshold is ~50% of Vcc. DC Characteristics Over Recommended Operating Conditions Symbol Description Min Max Units Vou High-level output voltage @ loy = -4.0 mA, Vee min (LVTTL) 2.4 Vv High-level output voltage @ Ioy = -500 pA, (LVCMOS) 90% Voc Vv Low-level output voltage @ Io, = 24.0 mA, Veg min (LVTTL) (Note 1) 0.4 Vv VoL | [owlevel output voltage @ Io, = 1500 pA, (LVCMOS) 10% Veo} V Vv Vecint Data Retention Supply Voltage (below which configuration data may be 2.1 Vv DRINT | ist) Vv Vecio Data Retention Supply Voltage (below which configuration data may be 2.5 Vv DRIO | lost) loco | Quiescent FPGA supply current (Note 2) 10 mA IL Input or output leakage current -10 +10 HA BGA, SBGA, PQ, HQ, & MQ packages 10 pF Cin Input capacitance (sample tested) PGA packages 16 pF IRPU Pad pull-up (when selected) @ V,, = 0 V (sample tested) 0.02 0.25 mA IRPD Pad pull-down (when selected) @ Vj, = 3.6 V (sample tested) 0.02 0.15 mA IRL Horizontal Longline pull-up (when selected) @ logic Low 0.3 2.0 mA Note 1: With up to 64 pins simultaneously sinking 24 mA. Note 2: With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating. 6-192 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XV Global Buffer Switching Characteristic Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade] All -09 -08 -07 Units Description Symbol Device Min | Max | Max | Max Delay from pad through Global Low Skew (GLS) Tes XC40110XV V7 6.7 5.8 ns clock buffer to any clock input, K. XC40150XV 7.8 6.8 59 ns XC40200XV 9.3 8.1 7.0 ns XC40250XV 9.4 8.2 7.1 ns Delay from pad through Global Early (GE) clock Tae 1256 XC40110XV 5.6 4.9 4.2 ns buffer to any OB clock input for BUFGE #s 1, 2, XC40150XV 57 5.0 43 ns 5 and 6. XC40200XV 61 | 53 | 46 | ns XC40250XV 6.2 5.4 4.7 ns Delay from pad through Global Early (GE) clock Tae 3478 XC40110XV 5.6 4.9 4.2 ns buffer to any IOB clock input for BUFGE #s 3, 4, XC40150XV 57 5.0 43 ns 7 and 8. XC40200XV 61 | 53 | 46 | ns XC40250XV 6.2 5.4 4.7 ns Delay from pad through FastCLK buffer to any TECLK XC40110XV 3.0 2.6 2.2 ns |OB clock input XC40150XV 3.1 | 27 | 23 | ns XC40200XV 3.4 3.0 2.6 ns XC40250XV 3.5 3.1 2.7 ns Advance February 1, 1999 (Version 1.0) 6-193XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4000XV CLB Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values are expressed in nanoseconds unless otherwise noted. Speed Grade -09 -08 -07 . Description Symbol Min | Max Min | Max Min | Max Units Combinatorial Delays F/G inputs to X/Y outputs TiLo 1.2 1.4 0.9 ns F/G inputs via H to X/Y outputs TiIHO 2.3 2.0 1.7 ns F/G inputs via transparent latch to Q outputs Tito 1.9 1.7 1.5 ns C inputs via SR/HO via H to X/Y outputs THHoo 1.5 1.3 1.4 ns C inputs via H1 via H to X/Y outputs THH1O 1.3 1.1 1.0 ns C inputs via DIN/H2 via H to X/Y outputs THH20 1.5 1.3 1.1 ns C inputs via EC, DIN/H2 to YQ, XQ output (bypassO Tepyp 0.8 0.7 0.6 ns CLB Fast Carry Logic Operand inputs (F1, F2, G1, G4) to Cour Topcy 2.5 2.2 1.9 ns Add/Subtract input (F3) to Coyy Tascy 3.1 27 2.4 ns Initialization inputs (F1, F3) to Coyt TINCY 1.9 1.6 1.4 ns Cjy through function generators to X/Y outputs TsuM 2.5 2.2 1.9 ns Cy to Coyz, bypass function generators Taye 0.3 0.3 0.2 ns Carry Net Delay, Coyt to Cin TNET 0.4 0.3 0.3 ns Sequential Delays Clock K to Flip-Flop outputs Q Texo 1.6 1.4 1.2 ns Clock K to Latch outputs Q TeKLo 1.6 1.4 1.2 ns Setup Time before Clock K F/G inputs Tick 1.5 1.3 1.2 ns F/G inputs via H Tinek 2.6 2.2 1.9 ns C inputs via HO through H THHock 1.8 1.5 1.3 ns C inputs via H1 through H Tuuick 1.6 1.4 1.2 ns C inputs via H2 through H TuHeck 1.8 1.5 1.3 ns C inputs via DIN Tpick 0.7 0.6 0.6 ns C inputs via EC Tecck 0.8 0.7 0.6 ns C inputs via S/R, going Low (inactive) Trek 0.4 0.4 0.3 ns CIN input via F/G Tock 2.8 2.4 2.1 ns CIN input via F/G and H Touc 3.8 3.3 2.9 ns Hold Time after Clock K All Hold Times 0.0 | | 0.0 | | 0.0 | ns Clocks Clock High time Tey 27 2.3 2.0 ns Clock Low time Tet 27 2.3 2.0 ns Set/Reset Direct Width (High) Trew 3.0 2.8 2.5 ns Delay from C inputs via S/R, going High to Q TRIo 2.9 2.5 2.2 ns Global Set/Reset Minimum GSR Pulse Width Tyrw | 18.4 | | 16.0 | | 13.9 ns Delay from GSR input to any Q Tura See page 201 for TRRI values per device Toggle Frequency (MHz) (for export control purposes) Frog | 188 | | 217 | | 250 MHz Advance 6-194 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XV RAM Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000XV devices and are expressed in nanoseconds unless otherwise noted. . Speed Grade -09 -08 -07 Single Port RAM Units Size | Symbol | Min | Max | Min | Max| Min | Max Write Operation Address write cycle time (clock K period) 16x2 Twes 9.6 8.4 7.3 ns 32x11 Twets | 9.6 8.4 7.3 ns Clock K pulse width (active edge) 16x2 Twps 4.8 4.2 3.7 ns 32x11 Twets | 4.8 4.2 3.7 ns Address setup time before clock K 16x2 Tass 2.6 2.3 2.0 ns 32x11 Tasts | 2.0 1.8 1.5 ns Address hold time after clock K 16x2 TaHs 0.0 0.0 0.0 ns 32x11 Tauts | 0.0 0.0 0.0 ns DIN setup time before clock K 16x2 Tpss 2.0 1.8 1.5 ns 32x11 Tosts | 2-5 2.2 1.9 ns DIN hold time after clock K 16x2 TpHs 0.0 0.0 0.0 ns 32x11 Tputs | 0.0 0.0 0.0 ns WE setup time before clock K 16x2 Twss 1.9 1.6 1.4 ns 32x11 Twsts | 1.8 1.5 1.3 ns WE hold time after clock K 16x2 Twus 0.0 0.0 0.0 ns 32x11 Twuts | 0.0 0.0 0.0 ns Data valid after clock K 16x2 Twos 6.2 5.4 4.7 ns 32x11 Twots 7.5 6.5 5.7 ns Read Operation Address read cycle time 16x2 Tre 4.5 3.1 3.1 ns 32x11 TretT 6.5 5.5 5.5 ns Data Valid after address change (no Write Enable) | 16x2 TiLo 1.2 1.1 0.9 ns 32x11 TiHO 2.3 2.0 1.7 ns Address setup time before clock K 16x2 Tick 1.5 1.3 1.2 ns 32x11 TIHCK 2.6 2.2 1.9 ns | Advance February 1, 1999 (Version 1.0) 6-195XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4000XV CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. Speed Grade -09 -08 -07 Dual Port RAM Units Size | Symbol] Min | Max | Min | Max | Min | Max Address write cycle time (clock K period) 16x1 Tweps | 9.6 8.4 7.3 ns Clock K pulse width (active edge) 16x1 Twepos | 4.8 4.2 3.7 ns Address setup time before clock K 16x1 Tasps | 2-6 2.3 2.0 ns Address hold time after clock K 16x1 Taups | 0.0 0.0 0.0 ns DIN setup time before clock K 16x1 Tpsps | 2.4 2.1 1.8 ns DIN hold time after clock K 16x1 Tpups | 0.0 0.0 0.0 ns WE setup time before clock K 16x1 Twsps | 1-9 1.6 1.4 ns WE hold time after clock K 16x1 Twups | 0.0 0.0 0.0 ns Data valid after clock K 16x1 Twopos 7.3 6.4 5.6 ns Advance Note: Timing for 16x1 option is identical to 16x2 RAM. XC4000XV CLB RAM Synchronous (Edge-Triggered) Write Timing WCLK (K) WE DATA IN DATA IN ADDRESS ADDRESS DATA OUT | DATA OUT X6474, X6461 Single Port RAM Dual Port RAM 6-196 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XV Pin-to-Pin Output Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. XC4000XV Global Clock Input to Output Delay Speed Grade] All -09 -08 -07 Units Description Symbol Device Min | Max | Max | Max Global Low Skew (GLS) Clock Input to Output Ticxor | XC40110XV 10.6 9.2 8.0 ns Delay using Output Flip-Flop. XC40150XV 10.7 9.3 8.1 ns XC40200XV 12.2 | 10.6 9.2 ns XC40250XV 12.3 | 10.7 9.3 ns For output SLOW option add Tstow | All Devices 1.7 1.6 1.4 ns Advance = Notes: Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible OB and CLB flip-flops are clocked by the global clock net. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with fewer number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs in FAST mode specification. Output timing is measured at ~50% Voc threshold with 50 pF external capacitive load. For different loads, see Figure 8. XC4000XV FastCLK Input to Output Delay for BUFNW, BUFSW, BUFNE, and BUFSE Speed Grade] All -09 -08 -07 Units Description Symbol Device Min | Max | Max | Max FastCLK Input to Output Delay using Output Tickror | XC40110XV 5.9 5.1 4.4 ns Flip-Flop for FastCLK buffers BUFNW, BUFSW, XC40150XV 6.0 5.2 4.5 ns BUFNE, and BUFSE. XC40200XV 6.3 5.5 4.8 ns XC40250XV 6.4 5.6 4.9 ns r Advance OFF = Output Flip Flop Notes: Listed above are representative values where one FastCLK input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the FastCLK net. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with fewer number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs in FAST slew mode specification. Output timing is measured at ~50% Vcc threshold with 50 pF external capacitive load. For different loads, see Figure &. February 1, 1999 (Version 1.0) 6-197XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC4000XV Pin-to-Pin Output Parameter Guidelines XC4000XV Global Early Clock Input to Output Delay for BUFGE #s 1, 2, 5, and 6 OFF = Output Flip Flop Notes: Speed Grade] All -09 -08 -07 Units Description Symbol Device Min | Max | Max | Max Global Clock Signal Input to Output Delay using | TickEor 1256 | XC40110XV 8.5 7.4 6.4 ns Global Early (GE) clock buffer to clock Output XC40150XV 86 75 65 ns Flip-Flop for BUFGE #s 1, 2, 5, and 6. XC40200XV 90 768 66 ns XC40250XV 9.1 7.9 6.9 ns Advance Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with fewer number of clock loads, the pad-to-lIOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs in FAST mode specification. Output timing is measured at ~50% Voc threshold with 50 pF external capacitive load. For different loads, see Figure 8. XC4000XV Global Early Clock Input to Output Delay for BUFGE #s 3, 4, 7, and 8 OFF = Output Flip Flop Notes: Speed Grade] All -09 -08 -07 Unit nits Description Symbol Device Min | Max | Max | Max Global Clock Signal Input to Output Delay using | TickEor 3478 | XC40110XV 8.5 7.4 6.4 ns Global Early (GE) clock buffer to clock Output XC40150XV 86 75 65 ns Flip-Flop for BUFGE #s 3, 4, 7, and 8. XC40200XV 9.0 7.8 6.8 ns XC40250XV 9.4 7.9 6.9 ns Advance Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For designs with fewer number of clock loads, the pad-to-lIOB clock pin delay as determined by the static timing analyzer (TRCE) can be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs in FAST mode specification. Output timing is measured at ~50% Vcc threshold with 50 pF external capacitive load. For different loads, see Figure &. Capacitive Load Factor Figure 8 shows the relationship between I/O output delay and load capacitance. It allows a user to adjust the speci- fied output delay if the load capacitance is different than 50 pF For example, if the actual load capacitance is 120 pF add 2.5 ns to the specified delay. If the load capac- itance is 20 pF, subtract 0.8 ns from the specified output delay. Figure 8 is usable over the specified operating conditions of voltage and temperature and is independent of the output slew rate control. 3 oO = N Delta Delay (ns) ' N Oo 20 40 60 80 100 120 140 Capacitance (pF) X8257 Figure 8: Delay Factor at Various Capacitive Loads 6-198 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XV Pin-to-Pin Input Parameter Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data, reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. XC4000XV Global Low Skew Clock, Set-Up and Hold Speed Grade 09 08 -07 Units Description | Symbol | Device Min Min Min Input Setup and Hold Time Relative to Global Clock Input Signal No Delay XC40110XV 0.0/6.8 0.0/5.9 0.0/5.1 ns Global Low Skew Clock and IFF Tpsn/TpHn | XC40150XV 0.0/6.9 0.0/6.0 0.0/5.2 ns Global Low Skew Clock and FCL XC40200XV 0.0/7.9 0.0/6.9 0.0/6.0 ns XC40250XV 0.0/8.7 0.0/7.6 0.0/6.6 ns Partial Delay XC40110XV 5.7/1.0 5.0/0.9 4.3/0.8 ns Global Low Skew Clock and IFF Tpsp/Tpyp | XC40150XV 5.8/1.0 5.1/0.9 4.4/0.8 ns Global Low Skew Clock and FCL XC40200XV 6.2/1.0 5.4/0.9 4.7/0.8 ns XC40250XV 6.6/1.0 5.8/0.9 5.0/0.8 ns Full Delay XC40110XV 6.5/0.0 5.7/0.0 4.9/0.0 ns Global Low Skew Clock and IFF Tpsp/TpHp | XC40150XV 6.6/0.0 5.8/0.0 5.0/0.0 ns XC40200XV 7.3/0.0 6.3/0.0 5.5/0.0 ns XC40250XV 7.9/0.0 6.9/0.0 6.0/0.0 ns Advance IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Notes: Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer (TRCE) to determine the setup and hold times under given design conditions. XC4000XV FastCLK Input Set-Up and Hold for BUFNW, BUFSW, BUFNE, & BUFSE Speed Grade 09 08 07 Units Description | Symbol | Device Min Min Min Input Setup and Hold Time Relative to FastCLK Input Signal No Delay XC40110XV 3.3/2.6 2.9/2.2 2.5/1.9 ns FastCLK and IFF Tpsen/Tpuen | XC40150XV | 3.3/2.7 | 29/23 | 25/20 | ns XC40200XV 3.3/2.9 2.9/2.5 2.5/2.2 ns XC40250XV 3.3/3.2 2.9/2.8 2.5/2.4 ns Advance IFF = Input Flip-Flop or Latch Notes: Setup time is measured relative to the FastCLK input signal with the fastest route and the lightest load. Hold time is measured relative to the FastCLK input signal using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions. February 1, 1999 (Version 1.0) 6-199XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC4000XV BUFGE #s 1, 2, 5, & 6 Global Early Clock, Set-Up and Hold for IFF and FCL IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Notes: Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions. XC4000XV BUFGE #s 3, 4, 7, & 8 Global Early Clock, Set-Up and Hold for IFF and FCL Speed Grade -09 -08 -07 Units Description Symbol | Device Min Min Min Input Setup and Hold Time Relative to Global Clock Input Signal No Delay XC40110XV J 0.7/5.2 0.6/4.5 0.5/3.9 ns Global Early Clock and IFF Tpsen/TpHen | XC40150XV 0.7/5.3 0.6/4.6 0.5/4.0 ns Global Early Clock and FCL Tpesen/T pFHEN | XC40200XV J 0.7/5.6 0.6/4.8 0.5/4.2 ns XC40250XV | 0.7/5.8 0.6/5.1 0.5/4.4 ns Partial Delay XC40110XV J 8.9/0.0 7.7/0.0 6.7/0.0 ns Global Early Clock andIFF Tpsep/TpHep | XC40150XV J 9.0/0.0 7.8/0.0 6.8/0.0 ns Global Early Clock and FCL Tpesep/TpeHep | XC40200XV J 9.7/0.0 8.4/0.0 7.3/0.0 ns XC40250XV | 10.3/0.0 9.0/0.0 7.8/0.0 ns FullDelay XC40110XV J 9.4/0.0 8.2/0.0 7.1/0.0 ns Global Early Clock and IFF Tpsep/TpHep | XC40150XV f 9.5/0.0 8.3/0.0 7.2/0.0 ns XC40200XV | 10.7/0.0 9.3/0.0 8.1/0.0 ns XC40250XV fF 11.9/0.0 | 10.4/0.0 9.0/0.0 ns Advance Speed Grade 09 08 -07 Units Description | Symbol | Device Min Min Min Input Setup and Hold Time Relative to Global Clock Input Signal No Delay XC40110XV 0.7/5.2 0.6/4.5 0.5/3.9 ns Global Early Clock and IFF Tpsen/TpHen | XC40150XV 0.7/5.3 0.6/4.6 0.5/4.0 ns Global Early Clock and FCL Tprsen/TprFHen | XC40200XV 0.7/5.6 0.6/4.8 0.5/4.2 ns XC40250XV 0.7/5.8 0.6/5.4 0.5/4.4 ns Partial Delay XC40110XV 8.9/0.0 7.7/0.0 6.7/0.0 ns Global Early Clock and IFF Tpsgep/Tpyep | XC40150XV 9.0/0.0 7.8/0.0 6.8/0.0 ns Global Early Clock and FCL Tprsep/TprHep | XC40200XV 9.7/0.0 8.4/0.0 7.3/0.0 ns XC40250XV J 10.3/0.0 9.0/0.0 7.8/0.0 ns FullDelay XC40110XV 9.4/0.0 8.2/0.0 7.1/0.0 ns Global Early Clock and IFF Tpsep/TpHep | XC40150XV 9.5/0.0 8.3/0.0 7.2/0.0 ns XC40200XV J 10.7/0.0 9.3/0.0 8.1/0.0 ns XC40250XV J 11.9/0.0 | 10.4/0.0 9.0/0.0 ns Advance IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch Notes: Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal using the furthest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the setup and hold times under given design conditions. 6-200 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4000XV IOB Input Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade. -09 08 -07 Units Description Symbol | Device Min | Max | Min | Max | Min | Max Clocks Clock Enable (EC) to Clock (IK) Tec | All Devices | 0.0 0.0 0.0 ns Delay from Fast Capture Latch enable (OK) active | Tox | All Devices | 2.0 1.8 1.5 ns edge to IFF clock (IK) active edge Setup Times Pad to Clock (IK), no delay Tpick | All Devices | 0.7 0.6 0.5 ns Pad to Clock (IK), via transparent Fast Capture Tpicke | Al Devices J 1.2 1.1 0.9 ns Latch, no delay Pad to Fast Capture Latch Enable (OK), no delay | Tpocx | All Devices J 0.2 0.2 0.1 ns Hold Times All Hold Times | All Devices [ 0.0 | | 0.0 | | 0.0 | ns Global Set/Reset Minimum GSR Pulse Width Turw_ | All Devices 718.4 16.0 13.9 ns Delay from GSR input to any Q Trre | XC40110XV 35.0 30.5 26.5 ns XC40150XV J 38.5 33.5 29.1 ns XC40200XV | 42.4 36.9 32.1 ns XC40250XV | 46.6 40.5 35.3 ns Propagation Delays Pad to 11, l2 Tpip All devices 0.1 0.1 0.1 ns Pad to |1, l2 via transparent input latch, no delay TpL| All devices 1.5 1.3 1.1 ns Pad to 11, l2 via transparent FCL and input latch, TpEL| All Devices 2.0 1.8 1.6] ns no delay Clock (IK) to 11, 12 (flip-flop) TikRI All Devices 1.1 0.9 0.8 ns Clock (IK) to I1, I2 (latch enable, active Low) TikLI All Devices 1.2 1.4 0.9 ns FCL Enable (OK) active edge to I1, I2 (via trans- ToKLl All Devices 2.8 2.5 2.1 ns parent standard input latch) Advance IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch. * Indicates Minimum Amount of Time to Assure Valid Data. February 1, 1999 (Version 1.0) 6-201XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC4000XV IOB Output Switching Characteristic Guidelines Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Speed Grade. -09 -08 -07 Units Description Symbol | Device Min | Max | Min | Max | Min | Max Clocks Clock High Tou 2.7 2.3 2.0 ns Clock Low Tet 2.7 2.3 2.0 ns Propagation Delays (See Note 1) Clock (OK) to Pad TOKPOF 3.0 2.6 2.3 | ns Output (OQ) to Pad Topr 1.6 1.4 1.2 ns 3-state to Pad hi-Z (slew-rate independent) TtsHz 3.7 3.2 2.8 ns 3-state to Pad active and valid TTSONF 4.1 3.6 3.1 ns Output (O) to Pad via Fast Output MUX OFPF 2.9 2.5 2.2] ns Select (OK) to Pad via Fast MUX OKFPF 2.5 2.2 1.9] ns Setup and Hold Times Output (O) to clock (OK) setup time Took 0.4 0.4 0.3 ns Output (OQ) to clock (OK) hold time Toxo 0.0 0.0 0.0 ns Clock Enable (EC) to clock (OK) setup time TEcoK 0.0 0.0 0.0 ns Clock Enable (EC) to clock (OK) hold time ToKEC 0.3 0.2 0.1 ns Global Set/Reset Minimum GSR pulse width TMRWw 18.4 16.0 13.9 ns Delay from GSR input to any Pad Treo | XC40110XV 37.1 32.2 28.0] ns XC40150XV 40.5 35.3 30.7] ns XC40200XV 44.4 38.6 33.6] ns XC40250XV 48.6 42.3 36.8] ns Slew Rate Adjustment For output SLOW option add TsLow | 1.7 | | 1.6 | 14] ns Advance Note: Output timing is measured at ~50% Vee threshold, with 50 pF external capacitive loads. * Indicates Minimum Amount of Time to Assure Valid Data. 6-202 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4013XLA Pinout Table XC4013XLA Pinout Table (Continued) XC4013XLA Pinout Table PADNAME __ | PQ160 | PQ208 | PQ240 | BG256 PADNAME | PQ160 | PQ208 | PQ240 | BG256 V0 - = P13 F2 VCC P142 | P183 | P212 | VCC" GND P10 | P14 | P14 | GND* /0 (A8) P143 | P1a4 | P213 | C10 VO, FCLK1 P11 | Pi5 | P15 | G3 /0 (AQ) Pi44 | P185 | P214 | D10 VO Pi2 | Pie | P16 | G2 I/O (A19) P145 | P186 | P215 | Ag VO (TMS) P13 | P17 | P17 Gi /0 (A18) Pi46 | P187 | P216 | Bo VO Pia | Pig | Pig | HS VO - Pisa | P217 | C9 Vcc = = Pi9 | Vcc VO - Pia9 | P2ie | D9 VO = - P20 H2 GND = | P219 | GND* VO = - P21 H1 I/O (A10) P147 | P190 | P220 | A8 GND = - P22 | GND* I/O (A11) Pi48 | Pi9i | P221 | Ba VO = P19 | P23 J2 VCC - | P222 | vcc* VO = p20 | Pea | J 0 - | P223 | AG VO P15 | P21 | P25 K2 VO - - P224 | C7 VO Pi | P22 | P26 K3 VO P149 | P192 | P225 | Be VO P17 | P23 | P27 Ki VO P150 | P193 | P226 | A5 VO Pig | P24 | P28 Li GND P151 | P194 | P227 | GND* GND Pig | Pes | Peo | GND" 0 - P195 | P228 Cb vcCc P20 P26 P30 | vcc 0 | Pi96 | P2290 | BS V0 P21 | P27 | P3t [2 0 P152 | P197 | P230 | A4 VO P22 | P28 | P32 L3 0 P153 | Pi98 | P231 | C5 VO P23 | P29 | P33 L4 I/O (A12) P154 | P199 | P232 | B4 VO P24 | P30 | P34 | M1 I/O (A13) P155 | P200 | P233 | A3 VO = P31 | P35 M2 GND = - | GND* VO = P32 | P36 M3 Vcc - - - VCC* GND - _ P37 GND VO - - p234 | D5 VO = - P38 Ni VO - - P235 | C4 VO = - P39 N2 VO P156 | P201 | P236 | B3 Vcc = = P40 | VCC 0 P157 | P202 | P237 | B2 VO P25 | P33 | P41 Pt I/O (A14) P158 | P203 | Pe3a | A2 VO P26 | P34 | P42 Po /O, GCK8 (A15) | P159 | P204 | P239 | C3 VO p27 | P35 | P43 | At VCC P160 | P205 | P240 | vcc* VO, FCLK2 P28 | P36 | P44 P3 GND P4 P2 P4 GND* GND P29 P37 P45 | GND* 0, GCK1 (A16) | P2 Pa Pa Bi V0 - - P46 1 V0 (A17) P3 P5 P3 C2 VO = - P47 R3 0 P4 P6 P4 D2 VO = P3s | Pas | 12 VO P5 P7 P5 D3 VO P39 | P49 U1 /O (TDI) P6 P8 P6 EA VO P30 P40 P50 T3 0 (TCK) P7 Pg P7 C1 VO P31 P41 P51 U2 VCC - - | vcc* GND = - TnD GND - - - GND* vcc - - - VCC* VO DB P70 Pa Di V0 P32 | P42 | P52 V1 V0 Bg P14 Bo 53 V0 P33 | P43 | P53 T4 0 - Pi2 | Pio Fo V0 P34. | P44 | P54 U3 0 - Pi3. | Pit Fy V0 P35 | P45 | P55 | V2 0 - Py. = V0 P36 | P46 | P56 | Wi February 1, 1999 (Version 1.0) 6-203XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4013XLA Pinout Table (Continued) XC4013XLA Pinout Table (Continued) PAD NAME PQ160 | PQ208 | PQ240 | BG256 PAD NAME PQ160 | PQ208 | PQ240 | BG256 0, GCK2 P37 P47 P57 V3 Vcc - - P101 | VCC* O (M1) P38 P48 P58 We2 /O P66 P86 P102 Y15 GND P39 P49 P59 GND* /O P67 P87 P103 vi14 | (MO) P40 P50 P60 Y1 /O P68 P88 P104 W15 Vcc P41 P55 P61 VCCc* /O P69 P89 P105 Y16 | (M2) P42 P56 P62 W3 GND P70 P90 P106 | GND* 0, GCK3 P43 P57 P63 Y2 /O - - P107 V15 I/O (HDC) P44 P58 P64 W4 /O - - P108 W16 VO P45 P59 P65 V4 /O - P91 P109 Y17 VO P46 P60 P66 U5 /O - P92 P110 V16 VO P47 P61 P67 Y3 /O P71 P93 P111 W17 VO (/LDC) P48 P62 P68 Y4 /O P72 P94 P112 Y18 Vcc - - - VCCc* GND - - - GND* GND - - - GND* Vcc - - - VCC* /O P49 P63 P69 V5 /O P73 P95 P113 U16 /O P50 P64 P70 W5 /O P74 P96 P114 V17 /O - P65 P71 Y5 /O P75 P97 P115 W18 /O - P66 P72 V6 /O P76 P98 P116 Y19 /O - - P73 W6 /O P77 P99 P117 V18 /O - - P74 Y6 0, GCK4 P78 P100 | P118 W19 GND P51 P67 P75 GND* GND P79 P101 P119 | GND* /O P52 P68 P76 W7 DONE P80 P103 | P120 Y20 /O P53 P69 P77 Y7 Vcc P81 P106 | P121 | VCC* /O P54 P70 P78 V8 /PROGRAM P82 P108 | P122 V19 /O P55 P71 P79 W8 I/O (D7) P83 P109 | P123 U19 Vcc - - P80 VCCc* (0, GCK5 P84 P110 | P124 U18 /O - P72 P81 Y8 /O P85 P111 P125 T17 /O - P73 P82 US /O P86 P112 | P126 V20 GND - - P83 GND* /O - - P127 U20 /O - - P84 Y9 /O - - P128 T18 /O - - P85 W10 Vcc - - - VCC* /O P56 P74 P86 V10 GND - - - GND* /O P57 P75 P87 Y10 I/O (D6) P87 P113 | P129 T19 /O P58 P76 P88 Y11 /O P88 P114 | P130 T20 /O (/INIT) P59 P77 P89 W114 /O P89 P115 | P131 R18 Vcc P60 P78 P90 VCCc* /O P90 P116 | P132 R19 GND P61 P79 P91 GND* /O - P117 | P133 R20 /O P62 P80 P92 V11 /O - P118 | P134 P18 /O P63 P81 P93 U11 GND P91 P119 | P135 | GND* /O P64 P82 P94 Y12 /O - - P136 P20 /O P65 P83 P95 W12 /O - - P137 N18 /O - P84 P96 V12 1/0, FCLK3 P92 P120 | P138 N19 /O - P85 P97 U12 /O P93 P121 P139 N20 GND - - P98 GND* Vcc - - P140 | VCC* /O - - P99 V13 I/O (D5) P94 P122 | P141 M17 /O - - P100 Y14 I/O (/CS0) P95 P123 | P142 M18 6-204 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4013XLA Pinout Table (Continued) XC4013XLA Pinout Table (Continued) PAD NAME PQ160 | PQ208 | PQ240 | BG256 PAD NAME PQ160 | PQ208 | PQ240 | BG256 GND - - P143 | GND* I/O, (CS1, A2) P127 | P165 | P187 A18 /O - P124 | P144 M20 I/O (A3) P128 | P166 | P188 A17 /O - P125 | P145 L19 Vcc - - - VCC* /O P96 P126 | P146 L18 GND - - - GND* /O P97 P127 | P147 L20 /O - - P189 C16 I/O (D4) P98 P128 | P148 K20 /O - - P190 B16 /O P99 P129 | P149 K19 /O P129 | P167 | P191 A16 Vcc P100 | P130 | P150 | VCC* /O P130 | P168 | P192 C15 GND P101 P131 P151 | GND* /O - P169 | P193 B15 I/O (D3) P102 | P132 | P152 K18 /O - P170 | P194 A15 1/0 (/RS) P103 | P133 | P153 K17 GND P131 P171 P196 | GND* /O P104 | P134 | P154 J20 /O P132 | P172 | P197 B14 /O P105 | P135 | P155 J19 /O P133 | P173 | P198 A14 /O - P136 | P156 J18 /O - - P199 C13 /O - P137 | P157 J17 /O - - P200 B13 GND - - P158 | GND* Vcc - - P201 VCC* I/O (D2) P106 | P138 | P159 H19 I/O (A4) P134 | P174 | P202 C12 /O P107 | P139 | P160 H18 I/O (Ad) P135 | P175 | P203 B12 Vcc - - P161 VCCc* GND - - P204 | GND* /O P108 | P140 | P162 G19 /O - P176 | P205 Al2 1/0, FCLK4 P109 | P141 P163 F20 /O P136 | P177 | P206 B11 /O - - P164 G18 1/0 (A21) P137 | P178 | P207 C11 /O - P165 F19 I/O (A20) P138 | P179 | P208 Al1 GND P110 | P142 | P166 | GND* I/O (A8) P139 | P180 | P209 A10 /O - - P167 F18 I/O (A7) P140 | P181 P210 B10 /O - - P168 E19 GND P141 P182 | P211 | GND* /O - P143 | P169 D20 /O - P144 | P170 E18 Vcc - - - D /O P111 P145 | P171 D19 Vcc - - - D11 /O P112 | P146 | P172 C20 Vcc - - - D15 GND - - - GND* Vcc - - - F4 Vcc - - - VCCc* Vcc - - - F17 I/O (D1) P113 | P147 | P173 E17 Vcc - - - K4 I/O (/RCK, P114 | P148 | P174 D18 Vcc - - - L17 RDY_/BUSY) VCC R4 /O P115 | P149 | P175 C19 VCC _ _ _ R17 /O P116 | P150 | P176 B20 VCC _ _ _ U6 I/O (DO, DIN) P117 | P151 P177 C18 VCC _ _ _ U10 I/O, GCK6 (DOUT) | P118 | P152 | P178 B19 VCC _ _ _ U15 CCLK P119 | P153 | P179 A20 VCC _ _ _ C14 Vcc P120 P154 P180 | VCC* vcc _ _ _ F1 O, TDO P121 P159 | P181 A19 VCC _ _ _ R2 GND P122 P160 P182 | GND* vcc _ _ _ E20 I/O (AQ, WS) P123 | P161 P183 B18 VCC _ _ _ P19 1/0, GCK7 (A1) P124 | P162 | P184 B17 VCC _ _ _ V7 /O P125 | P163 | P185 C17 VCC _ _ _ D7 /O P126 | P164 | P186 D16 February 1, 1999 (Version 1.0) 6-205XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4013XLA Pinout Table (Continued) XC4013XLA Pinout Table (Continued) PAD NAME PQ160 | PQ208 | PQ240 | BG256 PAD NAME PQ160 | PQ208 | PQ240 | BG256 Vcc - - - D14 GND - - - w14 Vcc - - - G17 GND - - - G20 Vcc - - - P17 Vcc - - - W20 NC - P1 P195 A7 Vcc - - - U14 NC - P3 - C8 Vcc - - - U7 NC - P51 - D12 Vcc - - - P4 NC - P52 - A13 Vcc - - - G4 NC - P53 - H20 NC - P54 - Y13 GND - - - Al NC - P102 - W13 GND - - - D4 NC - P104 - M19 GND - - - D8 NC - P105 - Ww9 GND - - - D13 NC - P107 - v9 GND - - - D17 NC - P155 - M4 GND - - - H4 NC - P156 - J3 GND - - - H17 NC - P157 - J4 GND - - - N4 NC - P158 - - GND - - - N17 NC - P206 - - GND - - - U4 NC - P207 - - GND - - - U8 NC - P208 - - GND - - - U13 12/18/98 GND - - - U17 GND - - - B7 GND - - - N3 6-206 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4020XLA Pinout Table XC4020XLA Pinout Table (Continued) XC4020XLA Pinout Table PAD NAME Paie6o | Paz0s | Pa240 | BG256 0 = = Pat H1 PAD NAME Pai6o | Paz0s | Pa240 | BG256 GND = = PDD GND* Vcc Pi42 | Piss | Pate VGC 10 = = a4 1/0 (A8) p143 | Pisa | P2i3 to 70 = = = 73 1/0 (A9) Pi44. | Piss | Poi4 Dio 70 = Pio Pa3 7p 1/0 (At9) Pi45 | Piss | Pats Ag 70 = P50 Pod 7 /0 (At8) Pi4e | Pis7 | P2i6 B9 70 Bis Pay pas Ke vO = pres | Pet7 ce 0 P16 P22 P26 K3 VO = Pigg | Pets Ds V0 P17 Pas P27 K1 GND = = Pets | GND* V0 P18 P24 P28 ut 1/0 (At0) Pi47_ | Piso | P220 Ag GND Pio PDE B59 GND* 10 (At1) P14 | Pi91 P2ot BS VOC B50 DDE B30 VOC VO = = = C8 VO P21 P27 P31 L2 VO = = = Ay 0 P22 Pas P32 13 vec = = Peee vec" 7) P23 P2g P33 L4 vO = = P2238 AG 7) P24 P30 P34 M1 vo = = Peed c7 7) = Pat P35 M2 0 Pi4a | Pig2 | Paes B6 70 = Pap P36 M3 0 Pis50 | Piss | P226 AS 70 = = ~ M4 GND P151 Pisa. | P2207 GND* GND = = 537 GND* 0 = Pi95 | P228 C6 10 = = P38 NI 0 = Pi96 | P29 BS 70 = = P39 ND 0 Pis2 | Pi9s7 | P230 A4 veo = = P40 VOC" 0 pis3 | Piss | Pest C5 10 pos P33 Pad Py 1/0 (At2) pis4 | Pisa | pase B4 70 P36 pad pap Pp 1/0 (At3) Piss | P200 | P233 AS 70 pay P35 Pa3 Ri GND = = = GND" 0, FCLK2 P28 P36 P44 P3 vec = = = voc" GND P29 P37 P45 GND* 0 = = P234 D5 70 = P46 Ty 0 = = P235 C4 70 = = pay Ra 0 156 | P201 P236 BS 70 = P38 Daa 73 0 Pis7 | P2o2 | P237 B2 70 = B39 P49 7 10 (A14) Piss | P203 | Pass A2 70 P30 P40 P50 73 0, GCK8 (A15)" Pisa | P204 | Paso C3 70 B31 Pat BBY Up Vcc P160 | P205 | Pado Vcc GND = = = GND* GND Pt Pe Pt GND* vec = = - vcc* 1/0, GCK1 (A16) Pe PA Pe Bt 70 p30 Pap pep Vi V0 (A17) PS PS Ps Ce i) P33 P43 P53 T4 0 PA P6 PA D2 10 P34 P44 P54 U3 vo PS P? PS b3 7) P35 P45 P55 v2 VO (TDI) P6 P P6 EA 0 P36 P46 P56 wi vO (TCK) P7 Po P7 ct V0, GCK2 P37 P47 P57 v3 vcc - - - Vcc* O (M1) P38 P48 P58 we GND = = = GND" GND P39 P4g P59 GND* vo Ps P10 Pe D1 1 (MO) P40 P50 PEO v1 vo Pe ptt Pe ES VCC Pat P55 Pet voce vo = P12 P10 E2 (M2) P42 P56 P2 Ws vO = P13 ptt Et 0, GCK3 P43 P57 P63 Y2 vO - - P12 F3 /O (HDC) P44 P58 P64 Ww4 vO = = P13 Fe 0 P45 P59 P65 v4 GND P10 P14 P14 GND* 70 P46 P60 P66 US 0, FCLK1 Pit P15 P15 G3 70 pay Pet Pay 13 vO pre P16 p16 Ge /0 (/LDC) P48 P62 P68 Y4 0 (TMS) P13 P17 P17 Gt veo = = = Yoo" 0 P14 P18 P18 H3 GND = = = GND* vec = = P19 veo" 0 P49 P63 P69 V5 vo = = P20 He 7) P50 Ped P70 W5 February 1, 1999 (Version 1.0) 6-207XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC4020XLA Pinout Table (Continued) XC4020XLA Pinout Table (Continued) PAD NAME PQ160 PQ208 PQ240 BG256 PAD NAME PQ160 PQ208 PQ240 BG256 VO - P65 P71 Y5 /PROGRAM P82 P108 P122 vig VO - P66 P72 V6 W/O (D7) P83 P109 P123 U19 VO - - P73 W6 VO, GCKS P84 P110 P124 U18 VO - - P74 Y6 VO P85 P1441 P125 TI7 GND P51 P67 P75 GND* VO P86 P1412 P126 veo VO P52 P68 P76 W7 VO - - P127 U20 VO P53 P69 P77 Y7 VO - - P128 T18 VO P54 P70 P78 V8 vec - - - vcc* VO P55 P71 P79 Ws GND - - - GND* vec - P80 vcc* W/O (D6) P87 P113 P129 T19 VO - P72 P81 Y8 VO P88 P114 P130 T20 VO - P73 P82 Ug VO P89 P1415 P1341 R18 GND - - P83 GND* VO P90 P116 P132 R19 VO - - - va VO - P117 P133 R2o VO - - - weg VO - P118 P134 P18 VO - - P84 Y9 GND Pot P119 P135 GND* VO - - P85 wi0 VO - - P136 P20 VO P56 P74 P86 V10 VO - - P137 N18 VO P57 P75 P87 Y10 VO, FCLK3 P92 P120 P138 N19 VO P58 P76 P88 Y11 VO P93 P1214 P139 N2o VO (/INIT) P59 P77 P89 wii vec - - P140 vcc* vec P60 P78 P90 vcc* W/O (D5) P94 P122 P1441 M17 GND P61 P79 P91 GND* W/O (/CS0) P95 P123 P142 M18 VO P62 P80 P92 Vit GND - - P143 GND* VO P63 P81 P93 Ut VO - - - M19 VO P64 P82 P94 Y12 VO - P124 P144 M20 VO P65 P83 P95 wie VO - P125 P145 L19 VO - P84 P96 vi2 VO P96 P126 P146 L18 VO - P85 P97 Ut2 VO P97 P127 P147 L20 VO - - - Y13 W/O (D4) P98 P128 P148 K20 VO - - - Ww13 VO P99 P129 P149 K19 GND - - P98 GND* vec P100 P130 P150 vcc* VO - - Pgg V13 GND P101 P1341 P1514 GND* VO - - P100 Y14 W/O (D3) P102 P132 P152 K18 vec - - P101 vcc* \/O (/RS) P103 P133 P153 K17 VO P66 P86 P102 Y15 VO P104 P134 P154 J20 VO P67 P87 P103 vi4 VO P4105 P135 P155 J19 VO P68 P88 P104 Wwi5 VO - P136 P156 J18 VO P69 P89 P105 Y16 VO - P137 P157 J17 GND P70 P90 P106 GND* VO - - - H20 VO - - P107 V1i5 GND - - P158 GND* VO - - P108 wi W/O (D2) P4106 P138 P159 H19 VO - P91 P109 Y17 VO P4107 P139 P160 H18 VO - P92 P110 Vi6 vec - - P1641 vcc* VO P71 P93 P1441 W17 VO P108 P140 P162 Gig VO P72 P94 P1412 Y18 VO, FCLK4 P109 P1441 P163 F2o GND - - - GND* VO - - P164 G18 vec - - - vcc* VO - - P165 F19 VO P73 P95 P113 U16 GND P4110 P142 P166 GND* VO P74 P96 P114 V17 VO - - P167 F18 VO P75 P97 P1415 wis VO - - P168 E19 VO P76 P98 P116 Y19 VO - P143 P169 D20 VO P77 Pgg P117 Vv18 VO - P144 P170 E18 VO, GCK4 P78 P100 P118 wig VO P4111 P145 P1741 D19 GND P79 P101 P119 GND* VO P112 P146 P172 C20 DONE P80 P103 P120 Y20 GND - - - GND* vec P81 P106 P1214 vcc* vec - - - vcc* 6-208 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4020XLA Pinout Table (Continued) XC4020XLA Pinout Table (Continued) PAD NAME PQ160 PQ208 PQ240 BG256 PAD NAME PQ160 PQ208 PQ240 BG256 VO (D1) P4113 P147 P173 E17 VCC - - - R2 \/O (/RCK, RDY_/BUSY) P114 P148 P174 D18 VCC - - - E20 VO P4115 P149 P175 ci19 VCC - - - P19 VO P116 P150 P176 B20 VCC - - - V7 \/O (DO, DIN) P117 P1514 P177 C18 VCC - - - D7-CORE VO, GCK6 (DOUT) P118 P152 P178 B19 VCC - - - D14-CORE CCLK P119 P153 P179 A20 VCC - - - G1i7 VCC P120 P154 P180 Vcc* VCC - - - P17 0, TDO P1214 P159 P1814 A19 VCC - - - weo GND P122 P160 P182 GND* VCC - - - U14-CORE \/O (AO, AWS) P123 P1641 P183 B18 VCC - - - U7-CORE VO, GCK7 (A1) P124 P162 P184 B17 VCC - - - P4 VO P125 P163 P185 C17 VCC - - - G4-CORE VO P126 P164 P186 D16 VO, (CS1, A2) P127 P165 P187 A18 GND - - - Al VO (A3) P128 P166 P188 A17 GND - - - D4 VCC - - - Vcc* GND - - - D8 GND - - - GND* GND - - - D13 VO - - P189 C16 GND - - - D17 VO - - P190 B16 GND - - - H4 VO P129 P167 P1914 A16 GND - - - H17 VO P130 P168 P192 C15 GND - - - N4 VO - P169 P193 B15 GND - - - N17 VO - P170 P194 A15 GND - - - U4 GND P1314 P1741 P196 GND* GND - - - Us VO P132 P172 P197 B14 GND - - - U13 VO P133 P173 P198 A14 GND - - - U17 VO - - P199 C13 GND - - - B7 VO - - P200 B13 GND - - - N3 VCC - - P201 Vcc* GND - - - wi4 VO - - - A13 GND - - - G20 VO - - - D12 VO (A4) P134 P174 P202 C12 NC - Pt P195 - VO (A5) P135 P175 P203 B12 NC - P3 - - GND - - P204 GND* NC - P54 - - VO - P176 P205 A12 NC - P52 - - VO P136 P177 P206 B11 NC - P53 - - VO (A21) P137 P178 P207 ct NC - P54 - - \/O (A20) P138 P179 P208 Ait NC - P102 - - VO (A6) P139 P180 P209 A10 NC - P104 - - VO (A7) P140 P1814 P210 B10 NC - P105 - - GND P144 P182 P2414 GND* NC - P107 - - NC - P155 - - VCC - - - D6 NC - P156 - - VCC - - - Di1 NC - P157 - - VCC - - - D15 NC - P158 - - VCC - - - F4 NC - P206 - - Vcc - - - F17 NC - P207 - - VCC - - - K4 NC - P208 - - VCC - - - Li7 12/18/98 VCC - - - R4 VCC - - - R17 VCC - - - U6 VCC - - - U10 VCC - - - U15 VCC - - - C14 VCC - - - FA February 1, 1999 (Version 1.0) 6-209XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX 6-210 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4028XLA Pinout Table XC4028XLA Pinout Table (Continued) XC4028XLA Pinout Table PAD NAME Ha160 | HQ208 | Ha240 | BG256 | HA304 | BG352 v0 - | Piz | Fe | P2e0 | Hea PAD NAME HQ160 | HQ208 | Ha240 | BG256 | Has04 | BG352 0 ~ ~ ~ | pees | aes vec P142 | Pis3 | Pet2 | vcct | P38 | voc* 10 = - | Pees | G2e /0 (A8) P143 | Pis4 | p213 | cio | P37 | Dt14 GND pio | pia | pia | Gnp* | Posy | GND* /0 (A) P144 | P15 | P214 | Dio | P36 | C14 10, FCLKi Pi1 | pis | pis | Ga | Pose | Je3 /0 (A19) P145 | Pise | P2is | Ag | P35 | At5 VO Piz | Pte | Pie | G2 | Pees | Je4 /0 (A18) Pi4e | Pis7 | Pete | Be | P34 | Bt5 10 (IMS) Pia | piy | piv | a1 | p2ea | H25 V0 | Pies | P2t7 | co | p33 | cis VO Pi4 | Pig | Pig | H3 | P283 | K23 VO | Piso | Peis | be | p32 | Dis vec = | Pig | vec* | P2e2 | voc* /O (A10) P147 | Pig0 | P2e0 | as | P31 | Ate 10 = - | p20 | He | Peso | Kea V0 (A11) Pi4g | Pigt | P2et | Bs | P30 | Bie V0 = - | pat [| H1 | Pe79 | J25 GND - - | @no*{ | GND* 0 = - | Pe7e | Lea vO - - - - P29 C16 VO - - - - P277 | Ked V0 - - - | pes | BI7 GND = | Pee | GND* GND* VO - - - ce | Per | C17 10 = - J4 | P276 | Las V0 - - - a7 | P26 | Bis 10 = - J3__| p275 | L26 vec - | Peee | vec* | P25 | voc* V0 Pig | p23 | v2 | Pa74 | me23 V0 - - | peas] ae | P23 | Cis 10 = p20 | p24 | Ji | P273 | M24 VO - | Peea | c7 | P22 | Diz V0 Pis | Pet | pas | Ka | P272 | Mas V0 Pi49 | Pig2 | pees | Be | P21 | aA20 V0 Pie | Pee | Pee | K3 | P271 | M26 VO Pis0 | Pig3 | Peze | As | P20 | Bt9 V0 Pi7 | pea | paz | Ki | P270 | N24 GND Pis1 | Pi94 | P2e7 | @ND* | P19 | GND* VO Pig | P24 | Pee | L1 | P269 | N25 "0 - - = = _ | P18 | Cts GND Pig | P25 | P29 | GND* | P268 | GND* "0 - - = -_ | Piz | bis voc p20 | P26 | P30 | voc* | P267 | vcc* vo - P195 | P228 c P16 A21 VO P24 P27 P31 L2 P266 | N26 VO | Pigs | Pee | Bs | P15 | B20 V0 p22 | pes | ps2 | 13 | Pees | P25 V0 Pis2 | Pi97 | P230 | a4 | P14 | C20 VO p23 | pea | p33 | L4 | P26a | P23 VO Pis3 | Pigs | Pest | cs | P13 | B21 V0 p24 | p30 | p34 | m1 | P263 | P24 VO (A12) Pis4 | Pigg | Pes2 | B4 | Pt2 | B22 0 ~ p31 | p35 | me | Pee2 | Ree /0 (A13) P155 | P2oo | P233 | az | Pio | C21 0 = p30 | psa | ma | P2611 Ros GND - - | @no*{ | GND* V0 = - m4 | P260 | R24 vec - - - | veer] | voec* V0 = = - P2s9 | R23 0 - - - - Pg D20 GND _ - P87 | GND* - GND* vO - - - - P8 A23 VO - - - - P258 | T26 V0 - | p234 | Ds | Pz | bat 10 = = | pes7 | 125 VO - | peas | ca | Pe | C22 V0 = - | pas [| nt | pase | T23 V0 Pis6 | P2ot | P23e | B3 | Ps | B24 10 = - | pao [| Ne | Pe5s | v26 VO Pis7 | Peo2 | p23s7 | Be | P4 | C23 VCC = | p4o | vcc* | p253 | voc* V0 (A14) Piss | P203 | Pass | az | P3 | D22 V0 p25 | p33 | p41 | Pi | P252 | ued V0, GCK8 (A15) Pis9 | P2o4 | pasa | c3 | P2 | C24 0 pos | p34 | pao | pe | posi | vos vec Pieo | P205 | Pe4o | vcct | Pi | voc* VO P27 | Pas | p43 | Ri | P250 | vad GND Pt Pe | Pt | GND* | P304 | GND* VO, FCLK2 pes | p36 | P44 | p3 | P29 | U23 0, GCK1 (A16) pe | P4 | Pe | Bi | P303 | bes GND pea | p37 | p45 | GNpD* | P24s | GND* 0 (A17) P3 [| Ps | P3 | c2 | P302 | Cas 10 = - | pea7 | yee V0 p4 | pe | p4 | D2 | P301 | Ded 10 = - | Peas | wes VO P5 P7 | P5 | D3 | P300 | E23 0 = | p4e | 11 | Peas | wea /O (TDI) Pe | ps | Pe | 4 | Pee9 | C26 10 = | p47 | R38 | P24a | ves VO (TCK) P7 | po | Pz | ci | P2e8 | E24 iO a pas | pas | 12 | p243 | AAZS V0 - = = ~__| Pee7 | Fea V0 - p39 | pag | ui | Pe42 | yes V0 - - = ~__| Pes6 | E25 V0 P30 | P4o | P50 | T3 | P241 | yea vcc - - - | vec*}| - | vec* VO P31 | P41 | P54 U2 | P240 | AA25 GND - - | @no*{ | GND* GND - - - |q@no*] - | GND* VO Ps | Pio | ps | Di | Pee5 | Dee vec = = [vec] | vec V0 Po | Pit | Pa | E38 | Pee4 | Gea 0 = - | P23e | AB25 VO - Pi2 | Pio | c2 | P2e3 | Fes 10 = = | Pese | aae4 V0 - Pig | P11 | E14 | Page| F26 V0 p32 | p42 | ps2 | vi | P237 | Y23 VO - | p12 | F3 | P2901 | Hes V0 p33 | p43 | ps3 | 14 | Pa3e | Ace6 February 1, 1999 (Version 1.0) 6-211XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4028XLA Pinout Table (Continued) XC4028XLA Pinout Table (Continued) PAD NAME HQ160 | HQ208 | HQ240 | BG256 | HQ304 | BG352 PAD NAME HQ160 | HQ208 | HQ240 | BG256 | HQ304 | BG352 VO P34 P44 P54 U3 P235 | AA23 VO - - - - P181 | AE11 VO P35 P45 P55 v2 P234 | AB24 VO - - - - P180 | AD11 VO P36 P46 P56 wi P233 | AD25 VO - - Pg9 V13 P179 | AF9 VO, GCK2 P37 P47 P57 V3 P232 | AC24 VO - - P100 | Y14 P178 | AD10 O (M1) P38 P48 P58 We P231 | AB23 VCC - - P101 | VCC* | P177 | VCC* GND P39 P49 P59 | GND* | P230 | GND* VO P66 P86 P102 | Y15 P175 | AE9Q | (MO) P40 P50 P60 Y1 P229 | AD24 VO P67 P87 P103 | V14 P174 | ADS VCC P44 P55 P1 vcc* | P228 | VCC* VO P68 P88 P104 | W15 | P173 | AC1O | (M2) P42 P56 P62 W3 P227 | AC23 VO P69 P89 P105 | Y16 P172 | AF7 VO, GCK3 P43 P57 P63 Y2 P226 | AE24 GND P70 Pg0 P106 | GND* | P171 | GND* VO (HDC) P44 P58 P64 Ww4 P225 | AD23 VO - - - - P170 | AE8 VO P45 P59 P65 v4 P224 | AC22 VO - - - - P169 | AD8 VO P46 P60 P66 U5 P223 | AF24 VO - - - V15 P168 | AC9 VO P47 P1 P67 Y3 P222 | AD22 VO - - - wi | P167 | AF6 VO (/LDC) P48 P62 P68 Y4 P221 | AE23 VO - - - Y17 P166 | AE7 VO - - - - P220 | AE22 VO - P92 P110 | V16 P165 | AD7 VO - - - - P219 | AF23 VO P71 P93 P1i1 | W17 | P164 | AE6 VCC - - - Vvcc* - Vcc* VO P72 P94 P112 | Y18 P163 | AES GND - - - GND* - GND* GND - - - GND* - GND* VO P49 P63 P69 V5 P218 | AD20 VCC - - - Vcc* - Vcc* VO P50 P64 P70 W5 P217 | AE21 VO - - - - P162 | AD6 VO - P65 P71 Y5 P216 | AF21 VO - - - - P4161 AC7 VO - P66 P72 V6 P215 | AC19 VO P73 P95 P113 | U16 P160 | AF4 VO - - P73 Ww P214 | AD19 VO P74 P96 P114 | V1I7 P159 | AF3 VO - - P74 Y6 P213 | AE20 VO P75 P97 P115 | W18 | P158 | ADS VO - - - - P212 | AF20 VO P76 P98 P116 | Y19 P157 | AE3 VO - - - - P211 | AC18 VO P77 Pg9 P117 | V18 P156 | AD4 GND P54 P67 P75 | GND* | P210 | GND* VO, GCK4 P78 P100 | P118 | W19 | P155 | AC5 VO P52 P68 P76 W7 P209 | AD18 GND P79 P101 | P119 | GND* | P154 | GND* VO P53 P69 P77 Y7 P208 | AE19 DONE P80 P103 | P120 | Y20 P153 | AD3 VO P54 P70 P78 V8 P207 | AC17 VCC P81 P106 | P121 | voc* | P152 | VCC* VO P55 P71 P79 Ws P206 | AD17 /PROGRAM P82 P108 | P122 | Vig P4151 AC4 VCC - - P8o | VCC* | P204 | VCC* \/O (D7) P83 P109 | P123 | U19 P150 | AD2 VO - P72 P81 Y8 P203 | AE18 VO, GCKS P84 P110 | P124 | U18 P149 | AC3 VO - P73 P82 Ug P202 | AF18 VO P85 P11 | P125 | T17 P148 | AB4 VO - - - - P201 | AE17 VO P86 P112 | P126 | V20 P147 | AD1 VO - - - P200 | AE16 VO - - P127 | U20 P146 | AA4 GND - - P83 | GND* - GND* VO - - P128 | 118 P145 | AA3 VO - - - v9 P199 | AF16 VO - - - - P144 | AB2 VO - - - wes P198 | AC15 VO - - - - P143 | AC1 VO - - P84 Y9 P197 | AD15 VCC - - - Vcc* - Vcc* VO - - P85 wio | P196 | AE15 GND - - - GND* - GND* VO P56 P74 P86 V10 P195 | AF15 \/O (D6) P87 P113 | Pi29 | Ti9 P142 Y3 VO P57 P75 P87 Y10 P194 | AD14 VO P88 P114 | P130 | T20 P144 AA2 VO P58 P76 P88 Y11 P193 | AE14 VO P89 P115 | P1314 R18 P140 | AA VO (/INIT) P59 P77 P89 wii P192 | AF14 VO Pg0 P116 | P132 R19 P139 Ww4 VCC P60 P78 Pgo | VCC* | P191 | VCC* VO - P117 | P133 | R20 P138 W3 GND P1 P79 P91 GND* | P190 | GND* VO - P118 | P134 P18 P137 Y2 VO P62 P80 P92 Vit P189 | AE13 VO - - - - P136 Y1 VO P63 P81 P93 Ut1 P188 | AC13 VO - - - - P4135 v4 VO P64 P82 P94 Y12 P187 | AD13 GND P91 P119 | P1385 | GND* | P134 | GND* VO P65 P83 P95 wi2 | P186 | AF12 VO - - P136 P20 P133 V3 VO - P84 P96 vi2 P185 | AE12 VO - - P137 | N18 P132 We VO - P85 P97 U12 P184 | AD12 VO, FCLK3 P92 P120 | P138 N19 P1314 U4 VO - - - Y13 P183 | AC12 VO P93 P121 | P139 N2o P130 U3 VO - - - Wwi3 | P182 | AF11 VCC P140 | vCC* | Pi29 | VCC* GND - - P98 | GND* - GND* W/O (D5) P94 P122 | P1414 M17 | P127 v2 6-212 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4028XLA Pinout Table (Continued) XC4028XLA Pinout Table (Continued) PAD NAME HQ160 | HQ208 | HQ240 | BG256 | Ha304 | BG352 PAD NAME HQ160 | HQ208 | HQ240 | BG256 | Ha304 | BG352 /0 (CSO) Pgs | P123 | P142 | Mia | Pi26] vi VO P125 | P163 | Pi85 | C17 | P72 | D5 Vo - - - - | P1265] ue Vo P126 | P1e4 | Pis6 | Die | P71 A3 V0 - - - | Pt24] Te /0, (CS1, A2) P127 | P1e5 | Pis7 | Ais | P70 | D GND - | P143*| GND* | - | GND* 1/0 (A3) P128 | Pies | Piss | Ai7 | Peo | C V0 - - - | Pt2e3] TH V0 - - - - Pes | B5 Vo - - - Mig | Pi22 | R4 Vo - - - - Pe7 | A4 V0 - P124 | Pi44 | M20 | Pt21 | R3 Vcc - - - |vec*] - | vec V0 - Pi125 | Pi45 | Lig | P120 | Re GND - - |a@np*] - | GND* V0 Pgs | P126 | Pi46 | Lig | Pti9 | R1 V0 - | Pisa | cie | Pes | c7 V0 Pe7 | P127 | P147 | Leo | Pita | P3 V0 - - | Piso | Bie | Pes | Be /0 (D4) Pgs | P128 | Pi4s | K20 | P117 | P2 V0 Pi29 | P1e7 | Piot | aie | Pe4 | As V0 Peg | P1290 | Pi49 | Kig | Pite | P4 V0 P130 | Pies | Pig2 | cis | P63 | Ds Vcc Pico | P130 | Pi50 | vcc* | P115 | vcc* V0 - Pisg | Pi93 | B15 | P62 | B7 GND Pio1 | P131 | Pi51 | GND* | P114 | GND* V0 - P170 | Pi94 | A15 | Pt A7 /0 (D3) Pio2 | P132 | Pi52 | Kis | P113 | Ne V0 - | Piss | | Peo | De /0 (/RS) P1o3 | P133 | Pi53 | K17 | P112 | N4 V0 - - - - Ps9 | cg V0 Pio4 | P134 | Pi54 | J2o | P111 | NB GND P131 | P171 | Pi96 | GND* | P58 | GND* V0 Pio5 | P135 | Pi55 | Jig | Ptto | M1 V0 P132 | P172 | Pi97 | B14 | P57 | BBs V0 - P136 | Pi56 | Jis | Ptoo | m2 V0 P133 | P173 | Pi9a | ai4 | P56 | Dito V0 - P137 | Pi57 | Ji7 | Ptos | M3 V0 - | Pisa | c13 | P55 | cto V0 - - - H2o | P1o7 | M4 V0 - | P200 | B13 | P54 | Bg V0 - - - Pio6 | Li vcc* - | P2o1 | vec* |] P52 | vcc* GND - - [anos] - | G@ND* V0 - - - Ai3 | P51 AQ V0 - - - | Ptos |] Le V0 - - - Di2 | P50 | D11 Vo - - - - | Pt04] 13 Vo - - - - P4g | Btt /0 (D2) Pios | P138 | Pis9 | Hig | Pto3 | 1 V0 - - - - P4g | Att Vo Pio7 | P139 | Pi60 | Hi8 | P102 ] k3 GND - - |G@np*]} - | GND* Vcc Pie1 | vcc* | Pio1 | vcc* 0 (A4) P134 | P174 | P202 | c12 | P47 | Di2 Vo Pios | P140 | Pi62 | Gig | Peo | Je /0 (A5) P135 | P175 | P203 | B12 | P46 | Ct2 VO, FCLK4 Piog | P141 | Pi63 | F20 | Pes | U3 V0 P176 | P205 | ai2 | P45 | Bi2 V0 - | Pt64 | Gis | P97 | ka V0 P136 | P177 | P206 | B11 | P44 | aAt2 V0 - | Pt65 | Fig | Pos | at /0 (A21) P137 | Pi7s | P207 | cit | P43 | C13 GND P1io | P142 | Pi66 | GND* | P95 | GND* /0 (A20) P138 | P179 | P208 | aii | P42 | B13 V0 - - - - Pe4 | He /0 (A6) P139 | P1so | P209 | Ato | P41 | A13 V0 - - - - Pe3 | H3 0 (A7) P14o | P1si | P2to | Bio | P4o | B14 V0 - | Pte7 | Fis | P92 | u4 GND P141 | P1s2 | P21 | GND* | P39 | GND* V0 - | Ptes | E19 | Pot F4 Vcc - - - D - A10 V0 - P143 | Piss | D20 | Ps0 | G2 Vcc - - - D11 - Ai7 V0 - P144 | Pi7o | E18 | Pso | G3 Vcc - - - D15 - | acta V0 P1i1 | P145 | Pi7t | Dig | Psa | Fe Vcc - - - F4 | Aczo V0 P112 | P14e | Pi72 | c2o | Pav | E2 Vcc - - - F17 - AC8 GND - - [anos] - | G@ND* Vcc - - - K4 | AFto Vcc - - - [veer] - | vec Vcc - - - L17 | AFI7 0 (D1) P113 | P147 | Pi73 | E17 | P86 | F3 Vcc - - - R4 - D7 VO (/RCK, RDY_/BUSY)| P114 | P148 | P174 | Dis | Pes | G4 Vcc - - - R17 - D13 V0 - - - - Ps4 | D2 Vcc - - - U6 - Dig V0 - - - - Ps3 | F4 Vcc - - - U10 - G23 V0 P115 | P149 | Pi75 | cig | Pa2 | E83 Vcc - - - U15 - H4 V0 P1i6 | P150 | P176 | Beo | Pst C2 Vcc - - - C14 - KA 1/0 (DO, DIN) P117 | P151 | Pi77 | cigs | Pso | D3 vcc - - - F4 - K26 VO, GCK6 (DOUT) P1ig | P152 | Piva | Big | P79 | 4 Vcc - - - R2 - N23 CCLK Pii9 | P153 | Pi79 | Azo | P78 | C3 vcc - - - E20 - P4 Vcc P120 | P154 | Piso | vcc* | P77 | vcc* Vcc - - - P19 - ud 0, TDO P121 | P15s9 | Pist | Aig | P76 | D4 vcc - - - V7 - U26 GND P122 | Piso | Pis2 | GND* | P75 | GND* Vcc - - - - - we23 1/0 (AO, AWS) P123 | Pie1 | Pis3 | Bis | P74 | B3 Vcc - - - - - Y4 VO, GCK7 (A1) P124 | Pi1e2 | Pis4 | B17 | P73 | C4 Vcc - - - D7 - B2 February 1, 1999 (Version 1.0) 6-213XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC4028XLA Pinout Table (Continued) XC4028XLA Pinout Table (Continued) PAD NAME HQ160 | HQ208 | HQ240 | BG256 | Ha304 | BG352 PAD NAME HQ160 | HQ208 | HQ240 | BG256 | Ha304 | BG352 VCC - - - D14 - B25 NC - Piss | - - L23 vcc - - - G17 - AE2 NC - Pecos | - - 73 Vcc - - - P17 | AE25 NC - Peo7 | - - - T4 vcc - - - w20 - - NC - Peos | - - T24 Vcc - - - ut4 - - NC - - - - - U25 vcc - - - U7 - - NC - - - - - AB3 Vcc - - - P4 - - NC - - - - - AC2 Vcc - - - G4 - - NC - - - - - AC6 NC - - - - | acti GND - - - Al - Al NC - - - - | Acie GND - - - D4 - A14 NC - - - - | acai GND - - - bs - Aig NC - - - - | aces GND - - - D13 - A2 NC - - - - | ADt6 GND - - - D17 - A22 NC - - - - | Ade1 GND - - - H4 - A25 NC - - - - | Ade26 GND - - - H17 - A26 NC - - - - - AE4 GND - - - N4 - AS NC - - - - | AEto GND - - - N17 - AS NC - - - - - C8 GND - - - U4 - ABI NC - - - - - L4 GND - - - Us | AB26 NC - - - - - K2 GND - - - U13 - AE1 12/18/98 GND - - - U17 | AE26 GND - - - B7 - AFI GND - - - N3 | AF13 GND - - - wi4 | AFi9 GND - - - G20 - AF2 GND - - - - | AF22 GND - - - - | AF25 GND - - - - | AF26 GND - - - - - AF5 GND - - - - - AF8 GND - - - - - Bi GND - - - - - B26 GND - - - - - 1 GND - - - - - E26 GND - - - - - H1 GND - - - - - H26 GND - - - - - Ni GND - - - - - P26 GND - - - - - wi GND - - - - - we26 GND - | P204] - - - GND - | P29] - - - NC - P4 - - P11 | At8 NC - P3 - - P24 | A24 NC - P54 - - P53 | B4 NC - P52 - | Ptoo | Bio NC - P53 - | P128 | B23 NC - P54 - - | Pti76] ct NC - Pio2 | - - | P205 | cs NC - P1o4 | | p254] crt NC - Pio5 | - | P2e1] D1 NC - Pio7 | - - D16 NC - P155 | - - - D25 NC - Pi5s6 | - - F23 NC - Pis7 | - - - J26 6-214 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4036XLA Pinout Table XC4036XLA Pinout Table (Continued) XC4036XLA Pinout Table PAD NAME Ha160 | Ha208 | Ha240] Ha3s04 | BG352| BG432 VCC = = = | vec* | vec* PAD NAME Ha160 | Ha208 | Ha240] Has04 | BG352| BG432 GND = = = Tenp* | enb* VCC P142 | Pis3 | P2t2 | P3s | vcc* | voce 0 pa | Pio | pa | pees | pee | Hee 1/0 (A8) P143 | Pisa | P23 | p37 | Dia | DI7 10 po | pit | po | poea | Goa | upg 1/0 (AQ) Pi44 | Piss | Pot4 | pae | ci4 | Atz7 70 pro 1 p10 | p203 | P25 1 a30 1/0 (A19) P145 | Pise | Pots | pas | ais | Cis 70 1533 | pi | poge | e208 1 30 1/0 (A18) Pi46 | Pis7 | P2te | p34 | Bis | Dis 0 = | pip | poa1 | Hoa | uea VO - P188 | P217 P33 C15 B18 0 _ _ P13 P290 H24 J29 0 - | Ptes | Pets | P32 | Dis | atg VO ~ _ | P2e9 | G25 | H31 1/0 (A10) P147 | Pig0 | P220 | P31 | Ate | Big 10 = = _ pose | aoe | u30 1/0 (A11) Pi4s | Pi91 | P221 | P30 | Bie | C9 GND pio | pia | pia | P287 | GND* | GND* voc - - - =p veces | vec VO, FCLK1 Pit | Pi5 | P15 | P286 | J23 | K28 GND = = = | GND* | GND* /0 Pi2 | Pie | P16 | P285 | J24 | Ke29 V0 = = ~_ | Pee | C16 | Dis /O (TMS) P13 | Piz | Pi7 | p2e4 | H25 | K30 V0 = = = P28 | Bi7 | Azo V0 Pi4 | pis | pts | pee3 | Ke3 | Kat VO = = = = D16 | B20 vcc - - Pig | P22 | vcc* | vcc* vO - - - - A18 C20 VO - - P20 | Peso | K24 L2g V0 = = ~_ | Per | ci7 | cat V0 - pat | p279 | J25 | L30 VO - - - P26 B18 A22 vO _ - - - J26 M29 VCC - | P222 | pes | vec* | voc 0 = = = [23 | M31 0 - - | P223 | P23 | cise | B22 0 = = | peva | Lea | Nat Vo - - P224 P22 D17 C22 VO _ _ _ P277 K25 N28 0 P149 | Pi92 | P225 | P2t | azo | B23 GND pop | | anp* | GND* V0 P150 | Pi93 | P226 | P20 | Big | Aza VOC = = = Tyee" | vee" GND P151 | P194 | P227 | Pi9 | GND* | GND* 10 = = _ pave | 125 | P30 0 - - - | Pts | cto | Dee VO ~ _ - | Pp275 | Lee | P28 V0 = = ~_ | Piz | D18 | C23 0 | pia | p23 | pev4a | mea | P29 0 - | Pt95 | Peee | Pte | Aoi | Bad 0 | pag | pea | pava | moa | Rat V0 - | P196 | P229 |} Pis | Bao | Ca4 /0 Pis | p21 | p25 | p272 | mes | R30 0 P152 | Pi97 | P230 | P14 | c20 | Az6 VO Pie | P22 | P26 | P271 | M26 | Ree 0 Pi53 | Pigs | P23t | p13 | Bat | C25 10 Pi7 | p23 | Pe7 | pe7o | Noa | Reg /0 (A12) Pi54 | Pi99 | P232 | Pi2 | Bee | Dad 0 Pia | Poa | pea | peso | Nos | 731 1/0 (A13) Pi55 | P200 | P233 | Pto | cai | B26 GND pig | pas | poo | P26a | GND* | GND* GND - = = = __|_GND* | GND* vec p20 | P26 | P30 | P267 | voc* | vcc* vcc = = = = | veo* | vec V0 pot | p27 | p31 | p266 | N26 | 130 V0 = = = Pa_| 20 | Aez /0 p22 | pes | P32 | P265 | P25 | T29 "0 - - = P8_ | A23 | 25 VO p23 | p29 | p33 | P264 | P23 | ust V0 = = = = A24 | C26 V0 p24 | ps0 | p34 | P263 | P24 | u30 VO - = = ~__| B23 | B27 VO - | p31 | p35 | p2e2 | Ree | ues V0 = - | P234 | P7 | Dat | Caz V0 7 p32 | p36 | P261 | R25 | U29 Vo - - P235 P6 C22 B28 0 _ _ _ P260 Rea V30 0 Pi56 | P201 | P23e | Ps | B24 | D27 VO ~ _ - | p259 | Res | ve9 0 P157 | P202 | P237 | Pa | ces | B29 VOC = = = Weer T vee" 1/0 (A14) Piss | P203 | P23s | P3 | D22 | C28 GND = p37 | en | ene /O, GCK8 (A15) Pi59 | P204 | Pasa | P2 | c24 | Des 70 = = pase | 7268 1 wa0 VCC P160 | P205 | P24o | Pi | voce | vcc* 0 = = | pes7 | t25 | wee GND Pt p2 | Pi | p304 | GND* | GND* 0 = = _ | yea | y30 /0, GCK1 (A16) P2 pa | Pe | P303 | D23 | Deg 0 = = = Tues | yea /0 (A17) Ps | ps | P3 | P3so2 |] c25 | C30 0 = _ | p3e_ | pase | 123 | yoe 0 Pa | Pe | P4 | P301 | Dea | E28 10 = 1 ps9 | poss | vee | AASO 0 P5 | Pz | Ps | P300 | E23 | E29 Voc = ~~ | pao | pasa | voo* | veo" /O (TDI) P6 | PS | PE | Pee9 | C26 | D30 0 p25 | p33 | pat | p252 | u2a | Aaze 0 (TCK) P7 P9 P7_ | Pe98 | E24 | D3t V0 Pes | p34 | p42 | P25t | ves | AB3t V0 = = = = D25_|_ E30 /0 p27 | p35 | p43 | p250 | ve4a | AB30 V0 = = = = Fe3 | E31 0, FCLK2 Pegs | p36 | p44 | Poag | U23 | AB29 VO = = ~ | Pee7 | Fea | Ges GND p29 | P37 | P45 | Peas | GND* | GND* 0 - - - | Pave | E25 | Gee VO ~ _ - | P2a7 | yee | AB2e February 1, 1999 (Version 1.0) 6-215XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC4036XLA Pinout Table (Continued) XC4036XLA Pinout Table (Continued) PAD NAME HQ160 | HQ208 | HQ240 | Ha304 | BG352| BG432 PAD NAME HQ160 | HQ208 | HQ240 | Ha304 | BG352| BG432 VO - - | P246 | wes | AC30 VCC - - - | vec* | vcc* Vo - - P4s | P245 | wed | AC29 Vo - - | Pig9 | AFi6 | AK19 V0 - - P47 | p244 | v23 | Aces V0 - - | Pigs | acis | AJt8 Vo - P3s | P4s | P243 | AAgz6 | AD29 Vo - - P84 | P197 | AD15 | ALt9 V0 - P39 | P4g | P242 | Y25 | AD28 V0 - - Pes | Pi96 | AE15 | AK18 Vo P30 | P4o | P50 | P241 | Y24 | AESO Vo P56 | P74 | P86 | P195 | AF15 | AH17 V0 P3i | P41 | P51 | P240 | AA25 | AE29 V0 P57 | P75 | P87 | Pi194 | ADI4 | Aut7 GND - - - | @ND* | GND* V0 P5s | P76 | Pas | Pi93 | AE14 | AJt6 Vcc - - - | vec | vcec* V0 (NIT) Psa | P77 | Peg | Pi92 | AF14 | AKt6 V0 - - | P2390 | AB25 | AF31 Vcc Peo | P7s | Pao | Pit | vcc* | voc* V0 - - | P23 | AA24 | AE28 GND Pei | P79 | Pgt | Pi1g90 | GND* | GND* V0 p32 | p42 | p52 | P237 | Y23 | AG3I V0 Pe2 | Pao | P92 | Pigg | AE13 | AL16 V0 P33 | P43 | P53 | P236 | AC26 | AF28 V0 Pe3 | Pai | P93 | Piss | AC13 | AH15 V0 - - - | AD26 | AG3o V0 Pe4 | ps2 | Pod | P187 | AD13 | AK15 V0 - - - | Ac25 | AG2e9 V0 Pes | Pa3 | P95 | Pi86 | AF12 | Au14 V0 P34 | P44 | P54 | P235 | AA23 | AH34 V0 - Ps4 | Pos | P185 | AE12 | AH14 V0 P35 | P45 | P55 | P234 | AB24 | AG28 V0 - Pes | Pez | Pis4 | AD12 | AKi4 V0 P36 | P46 | P56 | P233 | AD25 | AH30 V0 - - | P183 | Aci2 | AL13 VO, GCK2 P37 | P47 | P57 | P232 | AC24 | AU30 V0 - - | P1s2 | AFi1 | AK13 O (M1) p3s | P4s | P58 | P231 | AB23 | AH29 Vcc - - - | vec* | vcc* GND p3g | P49 | P59 | P230 | GND* | GND* GND - - P98 | @ND* | GND* | (MO) P4o | P50 | Peo | P229 | AD24 | AH28 V0 - - | P1gi | AE1t | AJt3 Vcc P41 | P55 | Pet | P228 | vcc* | voc* V0 - - | P180 | AD11 | AH13 | (M2) p42 | p56 | P62 | P227 | AC23 | AJ28 V0 - - - | AEto | AL12 V0, GCK3 P43 | P57 | P63 | P226 | AE24 | AK29 Vo - - - | actt | Akti2 0 (HDC) p44 | p58 | P64 | P225 | AD23 | AH27 V0 - - Peg | P17 | AFQ | AH12 Vo P45 | P59 | P65 | P224 | AC22 | AK28 Vo - | P1oo | P178 | AD1o | AJt1 V0 P4s | Peo | Pee | P223 | AF24 | AU27 Vcc - | Pitot | P177 | vec | vcc* Vo P47 | Pei | P67 | P222 | AD22 | AL2s Vo Pes | Pas | Pto2 | P175 | AEG | AL10 0 (LDC) P4g | Pe2 | Pes | P221 | AE23 | AH26 V0 Pe7 | ps7 | Pio3 | Pi74 | ADg | AKto V0 - - - | acet | AL27 V0 Pes | Pas | Pto4 | P173 | ACio | AJ10 V0 - - - | AD21 | AH25 V0 Peg | Pag | P1o5 | Pi72 | AF7 | Akg V0 - - | P220 | AE22 | Ak26 GND P7a | Pga | Pi06 | P171 | GND* | GND* V0 - - | P2tg | AF23 | AL26 V0 - - - | P170] Acs | ALs Vcc - - - | vec | vcec* V0 - - | Pte9 | ADs | AHt10 GND - - - | @ND* | GND* V0 - | P1o7 | Ptes | aco | Aug V0 P4g | P63 | Peg | P2i8 | AD20 | AH24 V0 - | Pios | P167 | AFe | AK8 V0 P50 | Pe4 | P70 | P2i7 | AE21 | Aves V0 - Pai | Ptog | Pt166 | AE7 | AK7 V0 - Pes | P71 | P2te | AF21 | AK25 V0 - Pg2 | P1to | Pi65 | AD7 | AL V0 - Pes | P72 | P2t5 | ACig | Au24 V0 P71 | P93 | Pi11 | Pi64 | AES | AU7 V0 - - P73 | P214 | ADig | AL24 V0 P72 | po4 | Ptt2 | P163 | AES | AH8 V0 - - P74 | P213 | AE20 | AH22 GND - - - | @ND* | GND* V0 - - | P2t2 | AF20 | Au23 Vcc - - - | vec* | vcc* V0 - - | Patt | Acts | AK23 V0 - - | Pt62] ADs | AK GND P51 | Pez | P75 | P210 | GND* | GND* V0 - - | Pt61 | ac7 | ALS V0 P52 | Pes | P76 | P209 | AD18 | Au22 V0 P73 | P95 | P113 | Pi6o | AF4 | AH7 V0 P53 | Peg | P77 | P208 | AEt9 | AK22 V0 P74 | Pgs | P114 | Pi59 | AF3 | AJ V0 P54 | P7o | P78 | P207 | ACI7 | AL22 V0 - - - - AE4 | AK5 V0 P55 | P71 | P79 | P206 | ADI7 | Au2t V0 - - - - | ace | AL4 Vcc - - Psa | P204 | vcc* | vcc* Vo P75 | Pov | P115 | P158 | ADS | AK4 V0 - P72 | Pai | P203 | AE18 | AH20 V0 P76 | Pos | Ptt | P157 | AE3 | AHS Vo - P73 | Ps2 | P202 | AF18 | AK24 Vo P77 | Pog | Pti7 | P156 | AD4 | AK3 V0 - - - | acte | Ak20 V0, GCK4 P7g | Ptoo | Piis | Pi55 | ACS | AU4 Vo - - - | ADt6 | AJt9 GND P7g | Pto1 | Pita | P154 | GND* | GND* V0 - - | P201 | AE17 | AL20 DONE Pso | P1o3 | Pi20 | P153 | AD3 | AH4 V0 - - | P200 | AEt6 | AHi8 Vcc Psi | Ptoe | P121 | P152 | vcc* | vcc* GND - - P83 | @ND* | GND* /PROGRAM Ps2 | Ptos | Pi22 | Pi51 | Ac4 | AH3 6-216 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4036XLA Pinout Table (Continued) XC4036XLA Pinout Table (Continued) PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 \/O (D7) P83 | P109 | P123 | P150 | AD2 AJ2 VO - - - - L4 M2 VO, GCKS P84 | P110 | P124 | P149 | AC3 | AG4 VO (D2) P106 | P138 | P159 | P103 J4 L2 VO P85 | P111 | P125 | P148 | AB4 | AG3 VO P107 | P139 | P160 | P102 K3 L3 VO P86 | P112 | P126 | P147 | AD1 AH2 Vcc - - P161 | P101 | VCc* | Vcc* VO - - - - AB3 AH1 VO P108 | P140 | P162 | P99 J2 K4 VO - - - - AC2 AF4 VO, FCLK4 P109 | P141 | P163 | P98 J3 K2 VO - - P127 | P146 | AA4 AF3 VO - - P164 | P97 K4 K3 VO - - P128 | P145 | AA3 | AG2 VO - - P165 | P96 Gt K4 VO - - - P144 | AB2 AE3 GND P110 | P142 | P166 | P95 | GND* | GND* VO - - - P143 | AC1 AF2 VO - - - P94 H2 J2 Vcc - - - - vcc* | VCC* VO - - - P93 H3 J3 GND - - - - GND* | GND* VO - - P167 | P92 J4 J4 W/O (D6) P87 | P113 | P129 | P142 Y3 AF1 VO - - P168 | P91 FA H1 VO P88 | P114 | P130 | P141 | AA2 AD4 VO - P143 | P169 | P90 G2 H2 VO Psg | P115 | P131 | P140 | AA AD3 VO - P144 | P170 | P89 G3 H3 VO Pgo | P116 | P132 | P139 Ww4 AE2 VO P1114 | P145 | P171 P88 F2 H4 VO - P117 | P133 | P138 W3 AC3 VO P112 | P146 | P172 | P87 E2 G2 VO - P118 | P134 | P137 Y2 AD1 GND - - - - GND* | GND* VO - - - P136 Y1 AC2 Vcc - - - - vcc* | VCc* VO - - - P135 v4 AB4 VO (D1) P113 | P147 | P173 | P86 F3 G4 GND P91 P119 | P135 | P134 | GND* | GND* VO (/RCK, RDY_/BUSY)} P114 | P148 | P174 | P85 G4 F2 VO - - P136 | P133 V3 AB3 VO - - - - D1 F3 VO - - P137 | P132 We AB2 VO - - - - C1 Et VO, FCLK3 Pg2 | P120 | P138 | P131 U4 AB1 VO - - - P84 D2 E3 VO P93 | P121 | P139 | P130 U3 AA3 VO - - - P83 F4 D1 Vcc - - P140 | P129 | vCCc* | VCC* VO P115 | P149 | P175 | P82 E3 E4 W/O (D5) P94 | P122 | P141 | P127 v2 AA2 VO P116 | P150 | P176 | P81 C2 D2 VO (/CSO) P95 | P123 | P142 | P126 v1 Y2 \/O (DO, DIN) P117 | P151 | P177 | P80 D3 C2 VO - - - - T4 Y4 VO, GCK6 (DOUT) P118 | P152 | P178 | P79 E4 D3 VO - - - - T3 Y3 CCLK P119 | P153 | P179 | P78 C3 D4 VO - - - P4125 U2 Ww4 Vcc P120 | P154 | P180 | P77 | VCC* | VCC* VO - - - P124 T2 W3 0, TDO P121 | P159 | P181 P76 D4 C4 GND - - P143* - GND* | GND* GND P122 | P160 | P182 | P75 | GND* | GND* Vcc - - - - vcc* | VCC* VO (AO, (WS) P123 | P161 | P183 | P74 B3 B3 VO - - - P4123 T1 v4 VO, GCK7 (A1) P124 | P162 | P184 | P73 C4 D5 VO - - - P4122 R4 V3 VO P125 | P163 | P185 | P72 D5 B4 VO - P124 | P144 | P1214 R3 Ut VO P126 | P164 | P186 |} P71 A3 C5 VO - P125 | P145 | P120 R2 U2 VO - - - - C5 BS VO P96 | P126 | P146 | P119 R1 U4 VO - - - - B4 c VO P97 | P127 | P147 | P118 P3 U3 VO, (CS1, A2) P127 | P165 | P187 | P70 D6 AS VO (D4) P98 | P128 | P148 | P117 P2 T1 VO (A3) P128 | P166 | P188 | P69 c D7 VO Pgg | P129 | P149 | P116 Pt T2 VO - - - P68 BS B6 Vcc P100 | P130 | P150 | P115 | VCC* | VCC* VO - - - P67 A4 AG GND P101 | P131 | P151 | P114 | GND* | GND* Vcc - - - - vcc* | VCc* \/O (D3) P102 | P132 | P152 | P113 N2 T3 GND - - - - GND* | GND* \/O (/RS) P103 | P133 | P153 | P112 N4 R1 VO - - P189 | P66 C7 D8 VO P104 | P134 | P154 | P111 N3 R2 VO - - P190 | P65 B6 C7 VO P105 | P135 | P155 | P110 M1 R4 VO P129 | P167 | P191 P64 AG B7 VO - P136 | P156 | P109 M2 R3 VO P130 | P168 | P192 | P63 D8 D9 VO - P137 | P157 | P108 M3 P2 VO - P169 | P193 | P62 B7 D10 VO - - - P4107 M4 P3 VO - P170 | P194 | P61 A7 cg VO - - - P4106 Lt P4 VO - - P195 | P60 D9 Bg Vcc - - - - vcc* | VCC* VO - - - P59 cg C10 GND - - P158 - GND* | GND* GND P131 | P171 | P196 | P58 | GND* | GND* VO - - - P4105 L2 N3 VO P132 | P172 | P197 | P57 B8 B10 VO - - - P4104 L3 N4 VO P133 | P173 | P198 | P56 D10 A10 VO - - - - K2 M1 VO - - P199 | P55 C10 ct February 1, 1999 (Version 1.0) 6-217XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4036XLA Pinout Table (Continued) XC4036XLA Pinout Table (Continued) PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 VO - - P200 | P54 Bg D12 GND - - - - AF1 B31 Vcc - - P201 P52 | VCC* | VCC* GND - - - - AF13 C1 VO - - - P54 AQ B11 GND - - - - AF19 | C31 VO - - - P50 Di1 C12 GND - - - - AF2 D16 VO - - - - ct C13 GND - - - - AF22 Gi VO - - - - B10 A12 GND - - - - AF25 | G31 VO - - - P49 B11 D14 GND - - - - AF26 Jt VO - - - P48 Ait B13 GND - - - - AF5 J34 GND - - - - GND* | GND* GND - - - - AF8 Pt Vcc - - - - vcc* | VCC* GND - - - - Bt P31 VO (A4) P134 | P174 | P202 | P47 D12 C14 GND - - - - B26 T4 VO (A5) P135 | P175 | P203 | P46 C12 A13 GND - - - - Et T28 VO - P176 | P205 | P45 B12 B14 GND - - - - E26 v1 VO P136 | P177 | P206 | P44 A12 D15 GND - - - - H1 V31 VO (A21) P137 | P178 | P207 | P43 C13 C15 GND - - - - H26 AC1 \/O (A20) P138 | P179 | P208 | P42 B13 B15 GND - - - - N1 AC31 VO (A6) P139 | P180 | P209 | P41 A13 B16 GND - - - - P26 AE1 VO (A7) P140 | P181 | P2to0 | P40 B14 A16 GND - - - - wi AE31 GND P141 | P182 | P2t1 P39 | GND* | GND* GND - - - - wee | AH16 Vcc - - - - A10 Al GND - - - - - AJ Vcc - - - - A17 Ait GND - - - - - AJ31 Vcc - - - - AC14 | A21 GND - - - - - AK1 Vcc - - - - AC20 | A31 GND - - - - - AK2 Vcc - - - - AC8 Di1 GND - - - - - AK30 Vcc - - - - AF10 | D21 GND - - - - - AK31 Vcc - - - - AF17 Lt GND - - - - - AL2 Vcc - - - - D7 L4 GND - - - - - AL3 Vcc - - - - D13 L28 GND - - - - - AL7 Vcc - - - - D19 L314 GND - - - - - ALQ Vcc - - - - G23 AA GND - - - - - AL14 Vcc - - - - H4 AA4 GND - - - - - AL18 Vcc - - - - K4 AA28 GND - - - - - AL23 Vcc - - - - K26 | AA31 GND - - - - - AL25 Vcc - - - - N23 | AH11 GND - - - - - AL29 Vcc - - - - P4 AH21 GND - - - - - AL30 Vcc - - - - Ut AL1 GND - P204 - - - Vcc - - - - U26 | AL11 GND - P219 - - - Vcc - - - - we3 | AL21 Vcc - - - - Y4 AL31 NC - Pt - P11 c8 D26 Vcc - - - - B2 C3 NC - P3 - P24 - A28 Vcc - - - - B25 C29 NC - P54 - P53 - B25 Vcc - - - - AE2 AJ3 NC - P52 - P4100 - D23 Vcc - - - - AE25 | AJ29 NC - P53 - P4128 - D20 NC - P54 - P176 - B21 GND - - - - Al A2 NC - P102 - P205 - B17 GND - - - - A14 A3 NC - P104 - P254 - C17 GND - - - - A19 A7 NC - P105 - P281 - C16 GND - - - - A2 AQ NC - P107 - - - A15 GND - - - - A22 A14 NC - P155 - - - B12 GND - - - - A25 A18 NC - P156 - - - D13 GND - - - - A26 A23 NC - P157 - - - A8 GND - - - - AS A25 NC - P158 - - - B8 GND - - - - A8 A29 NC - P206 - - - D6 GND - - - - AB1 A30 NC - P207 - - - A4 GND - - - - AB26 Bt NC - P208 - - - E2 GND - - - - AE1 B2 NC - - - - - F4 GND - - - - AE26 | B30 NC - - - - - FA 6-218 February 1, 1999 (Version 1.0)$< XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4036XLA Pinout Table (Continued) PAD NAME Ha@160 | Ha208 | Ha240] Has04 | BG352] BG432 NC - - - - - G3 NC - - - - - M4 NC = = = = = M3 NC - - - - - N2 NC = = = = = Ni NC - - - - - v2 NC = = = = = we NC = = = = = wi NC = = = = = Yt NC = = = = - | Aca NC = = = = - | ave NC = = = = | Ag4 NC = = = = - | aGi NC = = = = - | Ads NC = = = = | AH6 NC = = = = | AH9 NC = = = = - | Ads NC = = = = = | AKit NC = = = = | Aste NC = = = = | Adis NC = = = = = | ALtS NC = = = = = | ALt7 NC = = = = = | AKI7 NC = = = = | AHi9 NC - - - - - | AJzo NC = = = = = | Aka NC - - - - | AH23 NC = = = = | Ad26 NC - - - - | AKa7 NC = = = = | AF29 NC = = = = | AF30 NC = = = = | AD30 NC = = = = | AD31 NC = = = = = | Yat NC = = = = | wee NC = = = = | wat NC = = = = | vee NC = = = = | N30 NC = = = = | Nag NC = = = = | mee NC = = = = | M30 NC = = = = = Fat NC = = = = = Fa0 NC = = = = = F29 NC = = = = = F28 NC = = = = = C8 12/18/98 February 1, 1999 (Version 1.0) 6-219XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX 6-220 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4044XLA Pinout Table XC4044XLA Pinout Table (Continued) XC4044XLA Pinout Table PAD NAME Ha160 |HQ208/HQ240/Ha304/BG352| BG432 v0 - - - | des | E80 PAD NAME Ha160 |HQ208]HQ240/HQ304/BG352| BG432 0 = = = | p3 | E31 vec P142 | Pis3 | Pe12 | P38 | vcc* | voce V0 = | p207 | Fea | G28 /0 (A8) P143 | Pis4 | P213 | P37 | D14 | DI7 VO = | p20e| E25 | G29 /0 (A8) P144 | Piss | P2i4| P36 | c14 | Ai7 voc = = = Tyee" | vec* vO - - - - - C17 GND - - - | GND* | GND* V0 = = = = - | BI7 V0 - = - = ~__|_Fs0 /0 (A19) P145 | Pise | P2is | P35 | Ais | C18 0 = = = = _ | Fat /0 (A18) P14e | Pis7 | Pete | P34 | Bis | Dis VO Ps | Pto | Pe | P2905] Dee | H2e V0 | P1se | P217 | P33 | cis | Bis V0 Pa | Pit | Pa | P24] Gea | H29 VO | P1s9 | Peis | ps2 | Dis | ats V0 | Piz | Pio | P203 | Fe5 | G30 0 (A10) P147 | Pi90 | Pe2o | P31 | ate | Big 0 $13 1 Pit | p2e2 | Fee | H30 0 (A11) P14g | Pi91 | P221 | P30 | Bie | Ct9 10 = T pre | pae1 | nea | ape vec - - = =| veo" | vec" V0 - | P13 | Peso | Hea | Jes GND - - - | GND* | GND* vO - - P289 | G25 | H31 V0 - - | Paa | cie | Dig 0 = = p2ss | G26 | 430 VO - - | pes | B17 | Azo GND Pio | p14 | P14 | P287 | GND*| GND* V0 - = = = |_bt6 | Beo VO, FCLK1 P11 | pis | P15 | Pees | y23 | K28 V0 - = = ~_ | At8 | C20 [ie Piz | Pie | Pte | Pees | J24 | keg vo - - - P27 | C17 | C21 /O (TMS) P13 P17 | P17 | P284 | H25 | K30 VO - - - P26 | B18 | A22 vO P14 P18 | P18 | P283 | K23 | K31 vec - | p222 | pes | vec* | vcc* VCC | P19 | P2e2 | voce | vcc* VO - | P223| pes | cis | B22 V0 | P20 | Peso | k24 | Leo V0 - | P224| pee | Diz | cee V0 | P21 | Pe79 | ves | L30 V0 P149 | Pig2 | P225 | P21 | azo | B23 0 - = - - | J26 | M29 VO Pi50 | P193 | P226 | P20 | Big | A24 V0 = = - | tea | mat GND Pis1 | Pi94 | P227 | Pia | GND* | GND* VO - - | P27e | Lea | N31 VO - - | pis | cig | 22 V0 = = | P277 | kes | Nes V0 - - | P17 | Dis | c23 GND _ = | p22 | | enp*| GND* VO | Pi95 | Pees] Pie | A21 | Bad VCC = = - - | vec* | vec* V0 | Pi96 | P2290] Pis | B20 | C24 0 = = - = - | Neg VO - - - - | 023 10 ~ = | Ngo vO - - - - - B25 vO - - - P276 | L25 | P30 VO Pis2 | Pi97 | P230 | P14 | C20 | Aze V0 = = | P275 | Lae | P28 V0 Pis3 | Pi9a | P231 | P13 | Bat | C25 VO | Pig | P23 | P274 | M23 | P29 /0 (A12) Pis4 | Pisa | P23s2 | Pi2 | Bee | D24 V0 | P20 | p24 | P273 | mea | R31 /0 (A13) P155 | P200 | P233 | Pto | c2i | B26 VO Pis | Pet | p25 | P272] M25 | R30 GND - - = = _| GND* | GND* VO P16 | p22 | p26 | p271 | M26 | Ree vec - - = =| veo" | vec" V0 Piz | p23 | pez | P270 | Nea | R29 V0 - = = Po | 520 | Ae? [ie Pig | p24 | p2s | Peeg | nes | T31 V0 - - - | Ps | a23 | Des GND Pig | P25 | Pea | P268 | GND* | GND* VO - - - - | Aad | C26 vec P20 | P26 | P30 | P267 | vcc* | voc* 0 - = = 7 | B23 | Bez V0 pet | p27 | p31 | Pees | nee | T30 VO - | p234] P7 | Dai | ce V0 p22 | pee | ps2 | P265 | P25 | T29 V0 - | p235| Pe | C22 | B28 V0 p23 | p29 | P33 | P264 | P23 | U3t VO Pis6 | P201 | Pe3e | Ps | Bed | Daz 10 Poa | P30 | pad | P2e3 | Poa | U30 V0 Pis7 | p202 | Pe37 | P4 | cea | B29 VO - | pat | P35 | P262| Ree | U28 0 (A14) Piss | P203 | Pe3e | P3 | Dee | C28 V0 | p32 | p36 | Peet | Res | U29 VO, GCKB(A15) | P159 | P2o4 | P23a | Pe | C24 | Dee V0 = = | P2eo | Re4 | v30 vec Pi60 | P205 | Pe4o | P1 | vcc* | voce VO - - | Pesa | Rea | v29 GND Pt p2 | P1 | P304 | GND* | GND* V0 = - = - | ves V0, GCK1 (A16) p2 | pa | pe | P303] D23 | D29 0 - - - - -_ | wat 0 (A17) P3 | Ps | p3 | P302] C25 | C30 voc = = = Wee" | vec V0 p4 | Pe | p4 | P301 | De4 | E28 GND ~ | p37 | | @np*| GND* VO Ps | Pz | Ps | P300/ 23 | E29 V0 = = | Pees | Tae | wo /O (TDI) Pe | Ps | Pe | P299| C26 | D30 V0 = - | P2s7 | T25 | wee VO (TCK) P7 | Po | P7 | Pees] E24 | D3t V0 = = - - | Tea | Y30 February 1, 1999 (Version 1.0) 6-221XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4044XLA Pinout Table (Continued) XC4044XLA Pinout Table (Continued) PAD NAME HQ160 | HQ208| HQ240|HQ304 | BG352! BG432 PAD NAME HQ160 | HQ208 | HQ240| HQ304 | BG352 | BG432 VO - - - - U25 | Ye9 VO - - - P211 | AC18 | AK23 VO - - P38 | P256 | T23 Y28 GND P51 P67 P75 | P210 | GND* | GND* VO - - P39 | P255 | V26 | AA30 VO P52 P68 P76 | P209 | AD18 | AJ22 VCC - - P40 | P253 | VCC* | VCC* VO P53 P69 P77 | P208 | AE19 | AK22 VO P25 P33 P41 | P252 | U24 | AA2g VO P54 P70 P78 | P207 | AC17 | AL22 VO P26 P34 P42 | P251 | V25 | AB31 VO P55 P71 P79 | P206 | AD17 | AJ21 VO P27 P35 P43 | P250 | V24 | AB30 VCC - - P8o | P204 | VCC* | VCC* VO, FCLK2 P28 P36 P44 | P249 | U23 | AB29 VO - P72 P81 | P203 | AE18 | AH20 GND P29 P37 P45 | P248 | GND* | GND* VO - P73 P82 | P202 | AF18 | AK21 VO - - - P247 | Y26 | AB28 VO - - - - AC16 | AK20 VO - - - P246 | W25 | AC30 VO - - - - AD16 | AJ19 VO - - P46 | P245 | We4 | AC29 VO - - - P201 | AE17 | AL20 VO - - P47 | P244 |} V23 | AC28 VO - - - P200 | AE16 | AH18 VO - - - - - AD31 GND - - P83 - GND* | GND* VO - - - - - AD30 VCC - - - - Vcc* | VCC* VO - P38 P48 | P243 | AA26 | AD29 VO - - - P199 | AF16 | AK19 VO - P39 P49 | P242 |} Y25 | AD28 VO - - - P198 | AC15 | AJ18 VO P30 P40 P50 | P241 | Y24 | AE30 VO - - P84 | P197 | AD15 | AL19 VO P31 P44 P51 | P240 | AA25 | AE29 VO - - P85 | P196 | AE15 | AK18 GND - - - - GND* | GND* VO P56 P74 P86 | P195 | AF15 | AH17 VCC - - - - vcc* | VCC* VO P57 P75 P87 | P194 | AD14 | AJ17 VO - - - P239 | AB25 | AF31 VO - - - - - AK17 VO - - - P238 | AA24 | AE28 VO - - - - - AL17 VO P32 P42 P52 | P237 | Y23 | AG31 VO P58 P76 P88 | P193 | AE14 | AJ16 VO P33 P43 P53 | P236 | AC26 | AF28 VO (/INIT) P59 P77 Psg | P192 | AF14 | AK16 VO - - - - AD26 | AG30 VCC P60 P78 Pgo | P191 | VCC* | VCC* VO - - - - Ac25 | AG29 GND P1 P79 P91 | P190 | GND* | GND* VO P34 P44 P54 | P235 | AA23 | AH31 VO P62 P80 Pg2 | P189 | AE13 | AL16 VO P35 P45 P55 | P234 | AB24 | AG28 VO P63 P81 P93 | P188 | AC13 | AH15 VO P36 P46 P56 | P233 | AD25 | AH30 VO - - - - - AL15 VO, GCK2 P37 P47 P57 | P232 | AC24 | AJ30 VO - - - - - AJ15 O (M1) P38 P48 P58 | P231 | AB23 | AH29 VO P64 P82 P94 | P187 | AD13 | AK15 GND P39 P49 P59 | P230 | GND* | GND* VO P65 P83 P95 | P186 | AF12 | AJ14 | (MO) P40 P50 P6oO | P229 | AD24 | AH28 VO - P84 Pg6 | P185 | AE12 | AH14 VCC P44 P55 P61 | P228 | VCC* | VCC* VO - P85 P97 | P184 | AD12 | AK14 | (M2) P42 P56 P62 | P227 | AC23 | AJ28 VO - - - P183 | AC12 | AL13 VO, GCK3 P43 P57 P63 | P226 | AE24 | AK29 VO - - - P182 | AF11 | AK13 VO (HDC) P44 P58 P64 | P225 | AD23 | AH27 VCC - - - - Vcc* | VCC* VO P45 P59 P65 | P224 | AC22 | AK28 GND - - P98 - GND* | GND* VO P46 P60 P66 | P223 | AF24 | AJ27 VO - - P181 | AE11 | AJ13 VO P47 P1 P67 | P222 | AD22 | AL28 VO - - - P180 | AD11 | AH13 VO (/LDC) P48 P62 P68 | P221 | AE23 | AH26 VO - - - - AE10 | AL12 VO - - - - AC21 | AL27 VO - - - - AC11 | AK12 VO - - - - AD21 | AH25 VO - - Pgg | P179 | AF9 | AH12 VO - - P220 | AE22 | AK26 VO - - P100 | P178 | AD10 | AJ11 VO - - - P219 | AF23 | AL26 VCC - - P101 | P177 | VCC* | VCC* VCC - - - - vcc* | VCC* VO P66 P86 | P102 | P175 | AE9 | AL10 GND - - - - GND* | GND* VO P67 P87 | P103 | P174 | AD9 | AK10 VO P49 P63 Peg | P218 | AD20 | AH24 VO P68 P88 | P104 | P173 | AC10 | AJ10 VO P50 P64 P70 | P217 | AE21 | AJ25 VO P69 P89 | P105 | P172 | AF7 | AK9 VO - P65 P71 | P216 | AF21 | AK25 GND P70 P90 | P106 | P171 | GND* | GND* VO - P66 P72 | P215 | AC19 | AJ24 VO - - - P170 | AE8 | AL8& VO - - - - - AH23 VO - - - P169 | AD8 | AH10 VO - - - - - AK24 VO - - P107 | P168 | AC9Q | AJ9g VO - - P73 | P214 | AD19 | AL24 VO - - P108 | P167 | AF6 | AK8 VO - - P74 | P213 | AE20 | AH22 VO - - - - - AJ8 VO - - - P212 | AF20 | AJ23 VO - - - - - AH9 6-222 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4044XLA Pinout Table (Continued) XC4044XLA Pinout Table (Continued) PAD NAME HQ160 [HQ208]Ha240]Ha304 | BG352| BG432 PAD NAME HQ160 [HQ208/HQ240]Ha304 | BG352| BG432 /0 = Pat | Piog | Ptee | AE7 | AK7 /0 = = = = = v2 /0 - pg2 | Piio | P1e5 | aDz | AL6 /0 - - - | pres] tr | va 0 P71 | p93 | Pttt | Pie4] ace | Au7 0 - - - | Pte2[ R4 | v3 /0 p72 | pea | Ptt2 | Pie3] acs | AHs /0 | Pi24 | pi44]Pi21 [Rs | ut GND - - - | GND* | GND* 0 - | Pi25 | P145|Piz0| Re | U2 VCC - - - | veer | voc /0 ps6 | Pize| Pi4e|Pii9] Ai | ua 0 - - | Pte2| Abe | Ake 0 ps7 | P127| P147|Piie| P3 | us 0 - - - | Ptet | ac7z | ALS /0 (D4) Pgs | Pi2ze| Pi4s | Pitz] P2 | TH 0 P73 | P95 | P113 | Pieo | AF4 | AH7 0 psa | Pi29| Pi49|Pite]| Pr | Te 0 P74 | Poe | P114| Pisa] AF3 | Aue VCC Pico | P130 | Pt50 | P115 | vcc* | vcc* 0 - - - | aca | AKS GND Pio | P131 | P151 | P114 | GND* | GND* 0 - - - - | ace | AL4 /0 (D3) Pio2 | P132 | Pi52|P113] N2 | 13 0 P75 | Pov | Ptts | Pisa | ADS | AK4 /0 (RS) P1o3 | P133 | Pis3 | P112] N4 | Ri 0 P76 | pos | Ptte | Pis7| AES | AHS 0 Pio4 | P134] Pisa | P111] N3 | Re 0 P77 | ps | Ptt7 | Pise| aD4 | AK3 0 P1o5 | P135 | Pi55 | P10 | mi | R4 0, GCK4 P7s | Pico | Pits | Piss] acs | Au4 0 - | Pi3e | P156| Pio9 | m2 | R3 GND P79 | P1o1 | P1t9 | P154 | GND* | GND* 0 - | P137 | P157 | Pios | m3 | Pe DONE Pso | P103 | P120 | P153] ADS | AH4 0 - - - | Pto7| m4 | P3 VCC Pet | Pioe | Pt2t | P1s2 | vec* | vcc* 0 - - - | Ptoe|! o1 P4 /PROGRAM Pe2 | Pios | Pt22 | Pis1 | aca | AH3 0 - - - - - Nt /0 (D7) Pes | P1og | Pt23 | Piso] abe | Av2 0 - - - - - N2 0, GCKS Pea | P110 | Pt24 | Pi49 | aca | AG4 VCC - - - - | veces | vec* 0 Pes | P1i1 | P125 | Pi4e | apa | AG3 GND - - | piss] - | GND*| GND* 0 Pes | P1t2| Pi26 | P147 | abi | AH2 0 - - - |Ptos| te | NB /0 - - - | apa | Ant /0 - - - | Ptoa] wa | na 0 - - - - | ace | ara 0 - - - - Ko | Mt /0 - | pt27 | P146 | aaa | AF3 /0 - - - - L4 | Me 0 - - | Pt2e | P145 | Aas | AG2 /0 (D2) P1o6 | P13e | Pis59 | Pi03] ut L2 /0 - - | pt44 | aB2 | AES /0 Pio7 | P139 | Pteo | Pic2 | K3 | 13 0 - - - | pta3 | act | AFe2 VCC Ptet | P1o1 | vec* | vcc* VCC - - - - | veer | voce 0 Pios | P140 | Ptez| Peo | v2 | Kt GND - - - | GND* | GND* VO, FCLK4 Piog | P141 | Ptes| Pos | u3 | ke /0 (D6) Pe7 | P113 | Pi29 | P142] v3 | AFI 0 - - | ptea| Pov | K4 | k3 0 Pes | P114| P130 | P141 | aAa2 | AD4 0 - - |ptes| Poss | at | ka 0 Psa | P115 | P131 | P140 | aati | AD3 GND P110 | P142 | Ptes | P95 | GND*| GND* 0 P90 | P1te | P132 | P1309 | wa | AE2 0 - - - | pos | He | v2 0 - - - - - | ade 0 - - - | p93 | H3 | v3 0 - - - - - | aca 0 - - | pte7| ps2 | v4 | ua 0 | Pi1t17 | P133 | Piss | wa | acs 0 - - | ptes| Pot | FA H4 0 | Pita] P134|Ppi37 | v2 | aDt 0 - |P143| Pies] P90 | Ge | He 0 - - - | pi3e| v1 | ace 0 - |Pi44|Pi7o| ps9 | a@3 | H3 0 - - - | p135| v4 | aB4 0 Pitt | P145 | Pi71| Pes | Fe | Ha GND Pot | P19 | P135 | P134 | GND* | GND* 0 P12 | P146 | Pi7z2| Pe7 | E2 | Ge 0 - - | Ppt3e|Pi33] v3 | ABs 0 - - - - - G3 0 - | p137 | P132 | we | aAB2 0 - - - - - Fi /O, FCLK3 Pg2 | P120 | P13s | P131 | U4 | ABT GND - - - | GND* | GND* 0 p93 | Pi21 | Pi39 | P130 | U3 | AAS VCC - - - - | veces | vec* VCC - | Pt4o | P129 | vec* | vcc* /0 (D1) P113 | P147| Pi73| Pee | F3 | Ga /0 (D5) Pea | P122 | P141 | Pi27 | ve | aAa2 1/0 (/RCK, P114 | Pi4a | Piz4| Pes | G4 | Fe /0 (/CS0) pgs | P123 | P1422] Prize] vi | ye RDY_/BUSY) 0 - - - - T4 | Ya vO = = = = bi | FS 0 = = = = 73 1 ya /0 - - - - ci | et 0 - - - | pt25[ u2 | wa vO = = 7 | P84 | D2 | ES /0 - - | ptea] te | we vO = = ~_ | P83 | Fa | Dt GND = Trias) Ten TP enp* 0 P115 | P149 | Pi75| Pee | E38 | E4 Voc = = = Teer vee* 0 Pite | Piso | Ptze| Pet | c2 | De 0 = = = = we / (DO, DIN) P1i7 | P1s1 | Ptzz7| Pso | D3 | ce February 1, 1999 (Version 1.0) 6-223XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4044XLA Pinout Table (Continued) XC4044XLA Pinout Table (Continued) PAD NAME HQ160 | HQ208| HQ240|HQ304 | BG352! BG432 PAD NAME HQ160 | HQ208 | HQ240| HQ304 | BG352 | BG432 VO, GCK6 (DOUT) P118 | P152 | P178 | P79 E4 D3 VCC - - - - AF10 | D21 CCLK P119 | P153 | P179 | P78 C3 D4 VCC - - - - AF17 Lt VCC P120 | P154 | P180 | P77 | VCC* | VCC* VCC - - - - D7 L4 0, TDO P121 | P159 | P181 | P76 D4 C4 VCC - - - - D13 L28 GND P122 | P160 | P182 | P75 | GND* | GND* VCC - - - - D19 L314 \/O (AO, (WS) P123 | P161 | P183 | P74 B3 B3 VCC - - - - G23 | AA VO, GCK7 (At) P124 | P162 | P184 | P73 C4 D5 VCC - - - - H4 AA4 VO P125 | P163 | P185 | P72 D5 B4 VCC - - - - K4 AA28 VO P126 | P164 | P186 | P71 A3 C5 VCC - - - - K26 | AA31 VO - - - - C5 BS VCC - - - - N23 | AH11 VO - - - - B4 c VCC - - - - P4 | AH21 VO, (CS1, A2) P127 | P165 | P187 | P70 D6 AS VCC - - - - Ut AL1 VO (A3) P128 | P166 | P188 | P69 c D7 VCC - - - - U26 | AL11 VO - - - P68 BS B6 VCC - - - - we3 | AL21 VO - - - P67 A4 AG VCC - - - - Y4 | AL31 VCC - - - - vcc* | VCC* VCC - - - - B2 C3 GND - - - - GND* | GND* VCC - - - - B25 C29 VO - - P189 | P66 C7 D8 VCC - - - - AE2 | AJ3 VO - - P190 | P65 B6 C7 VCC - - - - AE25 | AJ29 VO P129 | P167 | P191 | P64 AG B7 VO P130 | P168 | P192 | P63 D8 D9 GND - - - - Al A2 VO - - - - c8 B8 GND - - - - A14 A3 VO - - - - - A8 GND - - - - A19 A7 VO - P169 | P193 | P62 B7 D10 GND - - - - A2 AQ VO - P170 | P194 | P61 A7 cg GND - - - - A22 A14 VO - - P195 | P60 D9 Bg GND - - - - A25 A18 VO - - - P59 cg C10 GND - - - - A26 | A23 GND P131 | P171 | P196 | P58 | GND* | GND* GND - - - - AS A25 VO P132 | P172 | P197 | P57 B8 B10 GND - - - - A8 A29 VO P133 | P173 | P198 | P56 Dio | Ato GND - - - - AB1 A30 VO - - P199 | P55 cio | C11 GND - - - - AB26 | Bt VO - - P200 | P54 Bg D12 GND - - - - AE1 B2 VCC - - P201 | P52 | VCC* | VCC* GND - - - - AE26 | B30 VO - - - P54 AQ B11 GND - - - - AF1 B31 VO - - - P50 Di1 C12 GND - - - - AF13] Ct VO - - - - ct C13 GND - - - - AF19 | C31 VO - - - - B10 A12 GND - - - - AF2 D16 VO - - - P49 B11 D14 GND - - - - AF22] Gi VO - - - P48 Ait B13 GND - - - - AF25 | G31 GND - - - - GND* | GND* GND - - - - AF26 Jt VCC - - - - vcc* | VCC* GND - - - - AF5 J34 VO (A4) P134 | P174 | P202 | P47 Di2 | C14 GND - - - - AF8 Pt VO (A5) P135 | P175 | P203 | P46 | C12 | A13 GND - - - - Bt P31 VO P176 | P205 | P45 B12 B14 GND - - - - B26 T4 VO P136 | P177 | P206 | P44 | At2 D15 GND - - - - Et T28 VO (A21) P137 | P178 | P207 | P43 | C13 |} C15 GND - - - - E26 v1 \/O (A20) P138 | P179 | P208 | P42 B13 B15 GND - - - - H1 V31 VO - - - - - A15 GND - - - - H26 | AC1 VO - - - - - C16 GND - - - - N1 AC31 VO (A6) P139 | P180 | P2o9 | P41 A13 B16 GND - - - - P26 | AE VO (A7) P140 | P181 | P210 | P40 B14 | A16 GND - - - - W1 = | AE31 GND P141 | P182 | P211 | P39 | GND* | GND* GND - - - - wee | AH16 VCC - - - - A10 Al GND - - - - - AJ VCC - - - - A17 | Att GND - - - - - AJ31 VCC - - - - AC14 | A21 GND - - - - - AK1 VCC - - - - AC20 | A311 GND - - - - - AK2 VCC - - - - Acs | D11 GND - - - - - AK30 6-224 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4044XLA Pinout Table (Continued) PAD NAME HQ160 [HQ208]H@240]Ha304|BG352] BG432 GND - - - - | aKat GND - - - - - | aA GND = = = = - | AL GND - - - - - | AL7 GND = = = = - | als GND - - - - - | Alta GND = = = = | Alta GND = = = = | Ales GND = = = = = | Ales GND = = = = a GND = = = = a GND = - [Petal - = = GND = - [P2oal - = = NC = PY - [|p] - | vee NC = P3 = | Pea | | age NC = pst | | ps3 | | veo NC = p52 | | Ptool | Bat NC = pss | | pi2e| | Bie NC = ps4 | |Pive] | D138 NC = |[Pio2| [p25] - D NC - |[Pioa] [pasa] A4 NC = [Pio | [pest] E2 NC - |[Pio7]> = = F4 NC - [Piss] - - - M4 NC - |[Pise> = = M3 NC - |[Ppis7] - - - | wi NC - [Piss]; = = Yt NC - | P2oe] - - - | Ac4 NC - | P2077] = | acai NC - | P2oe], = - | Ads NC = = = | AH6 NC = = = = = [aki NC = = = = | adte NC = = = = | AHi9 NC = = = = | aJ20 NC = = = = | As26 NC = = = = | AKa7 NC = = = = | AF29 NC = = = = | AF30 NC = = = = | wee NC = = = = = | yt NC = = = = | mee NC = = = = | 30 NC = = = = | Fe9 NC = = = = | Fes NC = = = = = C8 12/18/98 February 1, 1999 (Version 1.0) 6-225XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX 6-226 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4052XLA Pinout Table XC4052XLA Pinout Table (Continued) XC4052XLA Pinout Table PAD NAME |HQ160/HQ208|H@240[H@304 | BG352| BG432| BG560 Vcc p10 | P2os | P240 | P1 | voc* | voc" | vcc* PAD NAME [HQ160|HQ208 | HQ240[Ha@304 | BG352| BG432| BG560 GND py | po | pi | pa0a | anp* | Gnp* | GND* vec P142 | P183 | P2t2 | P38 | VCC* | voc" | voc" VO, GCKT (A16)| P2 | P4 | P2 | P303 | D23 | Dee | B33 /0 (A8) p143 | P1a4 | P213 | P37 | D14 | Di7 | At7 10 (A17) p3 | ps | p3 | ps02 | cas | ca0 | Feo /0 (AQ) p144 | Pta5 | P214 | P36 | Ct4 | Ai7 | B18 0 pa | pe | Pa | p301 | bea | E28 | E30 VO - - - - - C17 | C18 VO P5 P7 P5 | P3800 | E23 | E29 | D31 V0 - - : : -_ | Bi7 | E18 0 (TDN) pe | Ps | Pe | P209 | cee | D30 | F30 GND - - - - - GND* | GND* /0 (TCk) P7 Pg P7 | P2e98 | E24 | D31 C33 70 (A19) p145 | Ptge | P215 | P35 | ats | Cis | C19 GND : : : , Tenp* | enp* /0 (A18) p146 | P1387 | P216 | P34 | Bis | Dis | Dig 70 : : : : T #28 | G29 V0 - | piss | Petz | p33 | cis | B18 | E19 10 : - - - - | Feo | E31 V0 - | Piso | Pets | P32 | Dis | ato | B20 0 : - - - | bes | E30 | p32 0 (A10) p147 | P1g0 | P220 | P3t | ate | Bia | C20 10 : : : 153 1 E31 1 30 0 (A11) p14s | P191 | P221 | P30 | Bie | Cia | Deo 10 . : - | pee7 | Fea | Gee | Fat Wee - - - -__ vec" | vec* | vec" "0 - - - | Pess | E25 | Geo | Has GND - - : 7 | GND* | GND" | GND" voc - - - - | voc* | vco* | vec* V0 - - - | pea | cie [ dia | aat GND : : : - | GND* | Gnp* | GND* V0 - - - | pes | Biz | a20 | E20 0 : : - - - | F30 | H30 vO - - - - D16 B20 B21 VO - - - - - F31 G31 0 - - - - Aig | C20 | C21 0 P8 | P10 | P8 | P295 | De6 | Hes | Jeg re) - - - - - Bai | bat VO Pg | Pit | Pg | P294 | G24 | Hee | F33 V0 - - : : ~__| deo | Bee VO - | P12 | Pio | P2e3 | Fes | G30 | G32 GND - - : : 7__ | GND* | GND* V0 - | P13 | Pit | P2e2 | Fee | H30 | uso vO - - - | pe7 | c17 | cat | c23 GND : - - - - | GND* | GND* V0 - - - | p26 | Bis | a22 | E22 10 . - | p12 | Peet | He3 | ses | K30 vcc - - P222 | P25 | VCC* | VCC* | VCC* 0 - - P13 | P290 | H24 | J29 | H33 V0 - - | P223 | p23 | crs | B22 | Bea 0 , : - | pesa | Ges | Hat | Lee V0 - - | pee4 | pee | Diz | C22 | Dea iO : ; - | Pees | G2e | uso | Kat V0 p149 | P192 | P225 | Pet | azo | B23 | C24 GND pig | Pia | pia | poay | @ND* | GND* | GND* VO P150 | P193 | P226 | P20 | Big | Aad | A25 0, FCLK1 Pit | Pis | Pis | Pease | Jos | Kee | L30 GND P151 | P194 | P227 | Pig | GND* | GND* | GND* 10 Pi2 | pie | Pie | Pees | J2a | Keo | K32 V0 - - -_ | Pis | C19 | 22 | E23 0 (TMS) p13 | P17 | P17 | pesa | Hes | K30 | 33 vO - : 7 Pt | O18 | C23 | Bas V0 p14 | Pig | Pte | p2s3 | Kea | K31 | M29 V0 - | Pigs | Pees | Pte | a2t | Bea | Dea voc : - | pia | p2e2 | vec | voce | voce V0 - | Pige | Peeo | pis | B20 | cea | cas 10 . - | p20 | peso | Kea | Leo | 32 GND - - - : 7__ | GND* | GND* V0 - - | Pat | P27a | 425 | L30 | mat V0 - - - - - | Des | E25 @ND : : - - - | GND* | GND* vO - - - - - B25 C27 VO - - - - - M30 | Neg V0 pis2 | P197 | P230 | P14 | cao | aze | Dee 0 : : - - - | mes | 133 V0 pis3 | Pos | P231 | P13 | B21 | C25 | B28 10 : - - - | J26 | mee | ma2 /0 (A12) Pis4 | Poo | p232 | P12 | B22 | Dea | B29 70 ; ; ; 1753 1 wai | p29 /0 (A13) piss | P2oo | P233 | Pio | cet | B26 | E26 10 : : Tpove Dea Twat} P30 GND - - : ~__| GND* | GND* | GND* v0 - - - | pe77 | Kas | N28 | N33 vec - - - - | vec* | voor | vec GND : - | Pee | - | @np* | GND* | GND* vO - - - ps | p20 | a27 | ces VGC : : : - | vec* | vec | vco* V0 - - - ps | A23a | D256 | D27 10 : - - - - | N29 | P3t vO - - - - | a2a | cee | B30 10 : - - - - | N30 | P32 VO - - - : B23 _| Bev | cee "0 - - - | Pe76| Las | P30 | Ree V0 - - - : ~__| A286 | E27 V0 - - - | pe7s | Lee | Pee | R30 0 - - - - - D26 | A3t 0 - P19 | P23 | P274 | M23 | P29 | R31 GND - - - : 7__| GND* | GND" V0 - | P20 | Pea | P273 | Mea | R31 | R33 V0 - - | pe34 | P7 | bet | ce7 | Des @ND : : - - - | GND* | GND* VO - - | Peas | Pe | C22 | Bee | C30 "0 P15 | P2i | Pas | pe72 | mas | R30 | 731 V0 Pis6 | P2o1 | P236 | P5 | Baa | D27 | Des 0 P16 | p22 | p26 | p271 | moe | Ree | T20 V0 Pis7 | P2o2 | pea7 | Pa | cea | B29 | E28 iO Pi7 | p23 | P27 | Pe7o| Nea | Ree | Use 70 (A14) Piss | P203 | Peas | P3 | Dee | ces | D30 70 pig | Poa | Poe |} Poo | nos | rar | uat 0, GCK8 (A15) | P159 | P204 | P23a | Pe | cea | Des | E29 GND Pig | p25 1 p29 | poss | GND* | GND* | GND* February 1, 1999 (Version 1.0) 6-227XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4052XLA Pinout Table (Continued) XC4052XLA Pinout Table (Continued) PAD NAME = | HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 PAD NAME | HQ160)HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 Vcc P20 P26 P30 | P267 | VCC* | VCC* | VCC* | (MO) P40 P50 P60 | P229 | AD24 | AH28 | AJ29 VO Pat P27 P31 P266 | N26 T30 U29 Vcc P41 P55 P1 P228 | VCC* | VCC* | VCC* VO P22 P28 P32 | P265 | P25 T29 U30 | (M2) P42 P56 P62 | P227 | AC23 | AJ28 | AN32 VO P23 P29 P33 | P264 | P23 U31 V31 VO, GCK3 P43 P57 P63 | P226 | AE24 | AK29 | AJ28 VO P24 P30 P34 | P263 | P24 U30 V29 VO (HDC) P44 P58 P64 | P225 | AD23 | AH27 | AK29 GND - - - - - GND* | GND* VO P45 P59 P65 | P224 | AC22 | AK28 | AL30 VO - P31 P35 | P262 | R26 U28 V30 VO P46 P60 P66 | P223 | AF24 | AJ27 | AK28 VO - P32 P36 | P2614 R25 U29 | W33 VO P47 P1 P67 | P222 | AD22 | AL28 | AM31 VO - - - P260 | R24 Vv30 | W31 VO (/LDC) P48 P62 P68 | P221 | AE23 | AH26 | AJ27 VO - - - P259 | R23 veg | W30 GND - - - - - GND* | GND* VO - - - - - v28 | Weg VO - - - - - AK27 | AN31 VO - - - - - Wws31 Y32 VO - - - - - AJ26 | AL29 Vcc - - - - vcc* | VCC* | VCC* VO - - - - AC21 | AL27 | AK27 GND - - P37 - GND* | GND* | GND* VO - - - - AD21 | AH25 | AL28 VO - - - P258 | T26 | W30 | Y31 VO - - - P220 | AE22 | AK26 | AJ26 VO - - - P257 | T25 | Weg | Y30 VO - - - P219 | AF23 | AL26 | AM30 VO - - - - - Wes | AA32 Vcc - - - - vcc* | vCc* | Vcc VO - - - - - Y31 | AA31 GND - - - - GND* | GND* | GND* VO - - - - T24 Y30 | AA3O VO P49 P63 P69 | P218 | AD20 | AH24 | AM29 VO - - - - U25 Y29 | AB32 VO P50 P64 P70 | P217 | AE21 | AJ25 | AK26 GND - - - - - GND* | GND* VO - P65 P71 P216 | AF21 | AK25 | AL27 VO - - P38 | P256 | T23 Y28 | AA29 VO - P66 P72 | P215 | AC19 | AJ24 | AJ25 VO - - P39 | P255 | V26 | AA3O | AB31 VO - - - - - AH23 | AN29 Vcc - - P40 | P253 | VCC* | VCC* | VCC* VO - - - - - AkK24 | AN28 VO P25 P33 P44 P252 | U24 | AA29 | AC31 GND - - - - - GND* | GND* VO P26 P34 P42 | P251 | V25 | AB31 | AB29 VO - - P73 | P214 | AD19 | AL24 | AL25 VO P27 P35 P43 | P250 | V24 | AB3O | AD32 VO - - P74 | P213 | AE20 | AH22 | AJ23 VO, FCLK2 P28 P36 P44 | P249 | U23 | AB29 | AC30 VO - - - P212 | AF20 | AJ23 | AN26 GND P29 P37 P45 | P248 | GND* | GND* | GND* VO - - - P211 | AC18 | AK23 | AL24 VO - - - P247 | Y26 | AB28 | AD31 GND P51 P67 P75 | P210 | GND* | GND* | GND* VO - - - P246 | W25 | AC30 | AE33 VO P52 P68 P76 | P209 | AD18 | AJ22 | AK23 VO - - P46 | P245 | We4 | AC29 | AC29 VO P53 P69 P77 | P208 | AE19 | AK22 | AN25 VO - - P47 | P244 | V23 | AC28 | AE32 VO P54 P70 P78 | P207 | AC17 | AL22 | AJ22 GND - - - - - GND* | GND* VO P55 P71 P79 | P206 | AD17 | AJ21 | AL23 VO - - - - - AD31 | AG33 Vcc - - P80 | P204 | VCC* | VCC* | VCC* VO - - - - - AD30 | AH33 VO - P72 P81 P203 | AE18 | AH20 | AM24 VO - P38 P48 | P243 | AA26 | AD29 | AE29 VO - P73 P82 | P202 | AF18 | AK21 | AK22 VO - P39 P49 | P242 | Y25 | AD28 | AG31 GND - - - - - GND* | GND* VO P30 P40 P50 | P241 | Y24 | AE30 | AF30 VO - - - - - AJ20 | AK21 VO P31 P44 P54 P240 | AA25 | AE29 | AH32 VO - - - - - AH19 | AM22 GND - - - - GND* | GND* | GND* VO - - - - AC16 | AK20 | AJ20 Vcc - - - - vcc* | VCC* | VCC* VO - - - - AD16 | AJ19 | AL21 VO - - - P239 | AB25 | AF31 | AJ32 VO - - - P201 | AE17 | AL2o | AN21 VO - - - P238 | AA24 | AE28 | AF29 VO - - - P200 | AE16 | AH18 | AK20 VO - - - - - AF30 | AH31 GND - - P83 - GND* | GND* | GND* VO - - - - - AF29 | AG30 Vcc - - - - vcc* | VCC* | VCC* VO P32 P42 P52 | P237 | Y23 | AG31 | AK32 VO - - - P199 | AF16 | AK19 | AL20 VO P33 P43 P53 | P236 | AC26 | AF28 | AJ31 VO - - - P198 | AC15 | AJ18 | AJ19 GND - - - - - GND* | GND* VO - - P84 | P197 | AD15 | AL19 | AM20 VO - - - - AD26 | AG30 | AG29 VO - - P85 | P196 | AE15 | AK18 | AK19 VO - - - - AC25 | AG29 | AL33 VO P56 P74 P86 | P195 | AF15 | AH17 | AL19 VO P34 P44 P54 | P235 | AA23 | AH31 | AH30 VO P57 P75 P87 | P194 | AD14 | AJ17 | AN19 VO P35 P45 P55 | P234 | AB24 | AG28 | AK31 GND - - - - - GND* | GND* VO P36 P46 P56 | P233 | AD25 | AH30 | AJ30 VO - - - - - AK17 | AL18 VO, GCK2 P37 P47 P57 | P232 | AC24 | AJ30 | AH29 VO - - - - - AL17 | AM18 O (M1) P38 P48 P58 | P231 | AB23 | AH29 | AK30 VO P58 P76 P88 | P193 | AE14 | AJ16 | AK17 GND P39 P49 P59 | P230 | GND* | GND* | GND* VO (/INIT) P59 P77 P89 | P192 | AF14 | AK16 | AJ17 6-228 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4052XLA Pinout Table (Continued) XC4052XLA Pinout Table (Continued) PAD NAME = |HQ160|HQ208 | HQ240 | HQ304 | BG352 | BG432| BG560 PAD NAME |HQ160/HQ208] HQ240 | HQ304 | BG352 | BG432 | BG560 VCC Peo | P78 | Psa | P1941 | vcc* | vcc* | vcc* DONE Pso | P103 | P120 | P1538 | AD3 | AH4 | AJ5 GND Pei | P79 | P91 | P190 | GND* | GND* | GND* vcc Psi | P1o6 | P121 | P152 | vec* | vec* | vcc* V0 Pe2 | Pso | P92 | Pis9 | AE13 | AL16 | AL17 /PROGRAM Ps2 | Ptos | P122 | Pi51 | acd | AH3 | AM1 Vo Pes | Pst | P93 | P188 | AC13 | AH15 | AM17 /0 (D7) Ps3 | Ptog | P123 | P1s50 | AD2 | AJ2 | AHS V0 - - - - - | AL15 | AN17 VO, GCK5 Ps4 | Ptto | P124 | Pi49 | aca | AG4 | Aud Vo - - - - - | AJt5 | AKt6 Vo P85 | Pitt | P125 | P148 | AB4 | AG3 | AK3 GND - - - - - | GND* | GND* V0 Pse | P112 | P126 | P147 | AD1 | AH2 | AH4 V0 Pe4 | ps2 | P94 | P187 | ADi3 | AK15 | AM16 V0 - - - - AB3 | AH1 | ALt V0 Pe5 | ps3 | P95 | Pise | AF12 | Au14 | AL15 V0 - - - - Ac2 | AF4 | AGS V0 - P84 | P96 | P185 | AE12 | AH14 | AK15 GND - - - - - | GND* | GND* V0 - Pes | P97 | P1a4 | ADI2 | AK14 | AU15 V0 - - | Pte7 | Pi46 | aad | AF3 | AU3 V0 - - - | P183 | Act2 | AL13 | AN15 V0 - - | Pt28 | P145 | AA3 | AG2 | AK2 V0 - - - | Pig2 | AF11 | AK13 | AM14 V0 - - - - - AG1 | AG4 Vcc - - - - | veer | vec | vec* V0 - - - - - AE4 | AH3 GND - - P98 - | GND* | GND* | GND* V0 - - - | Pt44 | AB2 | AES | AF5 V0 - - - | Pist | AEt1 | Asi3 | AL14 V0 - - - | Pt43 | act | AF2 | Aue V0 - - - | P1go | AD11 | AH13 | AK14 vec - - - - | vec* | vec* | vcc* V0 - - - - | AIO | AL12 | Aut4 GND - - - - | GND* | GND* | GND* V0 - - - - | acit | Aki2 | AN13 /0 (D6) Ps7 | P113 | P129 | Pi42 | v3 | AF1 | AJt V0 - - - - - | Ast2 | AM13 V0 Pss | P114 | P130 | Pi41 | AA2 | AD4 | AF4 V0 - - - - - | AKit | ALI3 V0 Psg | P115 | P131 | P140 | AA1 | AD3 | AG3 GND - - - - - | GND* | GND* V0 Peo | Ptte | P132 | Pi39 | w4 | AE2 | AES V0 - - Peg | P179 | AFO | AH12 | AK12 V0 - - - - - AD2 | AH1 V0 - - | Ptoo | P17s | AD1o | AJt1 | AN14 V0 - - - - - Ac4 | AF3 Vcc - - | P1ot | P177 | voces | voce | vec* GND - - - - - | GND* | GND* V0 Pes | ps6 | Pto2 | P175 | AEQ | ALio | AJt2 V0 - | Ptti7 | P133 | P138 | w3 | Ac3 | AE3 Vo Pe7 | P87 | P103 | P174 | AD9 | AKiO | ALt1 Vo - | Pits | P134] P137 | Ye | ADI | Acs V0 Pes | Pgs | P1o4 | P173 | ACto | Auto | AK11 V0 - - - | Pi36] v1 | Ace | AE1 Vo Peg | Psg | P105 | P172 | AF7 | AK@ | AM1O Vo - - - | P1385 | v4 | AB4 | AD3 GND P70 | P90 | Ptoe | P171 | GND* | GND* | GND* GND Pei | Pti9 | P135 | P134 | GND* | GND* | GND* V0 - - - | P170 | AEs | AL8 | ALt1O V0 - - | P136 | P133 | v3 | aB3 | Ac4 V0 - - - | Pi6a | ADs | AH1o | Aut V0 - - | P137 | P132 | we | AB2 | AD2 V0 - - | P1o7 | Pt6s | ace | Aug | ANO VO, FCLK3 Pg2 | P120 | P138 | Pi31 | U4 | AB1 | ABS V0 - - | Pios | Pte7 | AFe | Aks | AK1O V0 Pe3 | Pi21 | P139 | Pi30 | U3 | AA3 | AC3 GND - - - - - | GND* | GND* vec - - | P140 | P129 | vec* | vec* | voc* V0 - - - - - AJ8 | AN7 1/0 (D5) Po4 | Pt22 | P141 | Pi27 | ve | aAa2 | AAS V0 - - - - - AH9 | AJg /0 (/CS0) Pes | P123 | P142 | Pi2z6 | v1 y2 | AB3 V0 - Pai | Piog | Ptes | AE7 | AK7 | AL7 GND - - - - - | GND* | GND* V0 - Pg2 | P110 | P165 | AD7 | AL6 | AK8 V0 - - - - T4 Y4 | AB2 V0 P71 | P93 | Pi11 | Pie4 | AEs | Au7 | ANG V0 - - - - T3 Y3 | AA4 V0 P72 | Pod | P112 | Pie3 | AES | AH8 | AM6 V0 - - - - - Yi | AA3 GND - - - - | GND* | GND* | GND* V0 - - - - - wi Y5 Vcc - - - - | veer | vec | vec* V0 - - - | Pt25 | u2 | wa | y3 V0 - - - | Pi62 | AD6 | Ake | Aus V0 - - - | Ptea] Te | ws | ye V0 - - - | Piet | ac7z | ALS | AL6 GND - - | P143*| - | GND* | GND* | GND* V0 P73 | P95 | P113 | Pie6o | AF4 | AH7 | AK7 vec - - - - | vec* | vec* | vcc* V0 P74 | Pos | P114] Pi59 | AF3 | Ave | AMS V0 - - - - - we | ws V0 - - - - AE4 | AK5 | AM4 V0 - - - - - ve | w4 V0 - - - - Ace | AL4 | Au7 V0 - - - | Pte3] TH v4 | w3 GND - - - - - | GND* | GND* Vo - - - | Pte2] R4 | v3 | wt V0 - - - - - AH6 | ALS V0 - | P124 | P144 | Pi2t | R3 ud V3 Vo - - - - - AJ5 | AK6 Vo - | P125 | P145 | P120 | Re U2 V5 V0 P75 | P97 | P115 | P158 | ADS | AK4 | ANS GND - - - - - | GND* | GND* Vo P76 | P98 | P116 | P157 | AES | AHS | AK5 Vo Pes | P126 | P146 | P119 | Ri U4 | v4 V0 P77 | P9g | P117 | Pi56 | AD4 | AK3 | Ads V0 Pe7 | P127 | P147 | P118 | P3 us | ve V0, GCK4 P7s | Pioo | P118 | P155 | Acs | Au4 | AL4 /0 (D4) Peg | P128 | P148 | P117 | P2 T1 U5 GND P79 | P1o1 | Pt19 | P154 | GND* | GND* | GND* V0 Peg | Pi29 | P149 | Pite | Pt T2 U4 February 1, 1999 (Version 1.0) 6-229XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC4052XLA Pinout Table (Continued) XC4052XLA Pinout Table (Continued) PADNAME [HQ160/HQ208 | Ha240 | H@304 | BG352 | BG432| BG560 PAD NAME [HQ160/H@208 | Ha240|HQ304 | BG352 | BG432| BG560 Vcc P100 | P130 | P1s0 | P115 | voc | voce | voc" v0,GcKe | Ptis | P152 | Pi7e| P79 | c4 | D3 | D4 GND Pio1 | P131 | P151 | P1714 | GND* | GND* | GND* (DOUT) /0 (D3) Pio2 | P132 | Pisa | P113[ ne | T3 | us CCLK P19 | P1538 | Pt79 | P78 | C3 | D4 | C4 1/0 (RS) P1o3 | P133 | P1s3 | Pi12 | n4 | Rt | Te vec P120 | Pis4 | Piso | P77 | vCC* | vec" | vec" V0 Pio4 | Pisa | Pisa | Piit[ na | Re | 74 9, TDO Piet | Pis9 | P181 | P76 | D4 | C4 | EG 70 ios | pias | Piss | Pii0 | mt | Ra 1 GND Pi122 | Pie0 | Pts2 | P75 | GND* | GND* | GND* GND : : : , Tenp* | np* 0 (AO, ws) | Pi23 | Piet | P13 | P74 | Bs | Ba | Ds 10 Tpise | pise | P109 | we 1 R313 VO, GCK7 (A1) | P124 | Pie2 | Pisa | P73 | ca | DS | a2 iO Tpia7 | pis7 | Pioa 1a | pa PR V0 Pi25 | Pies | Piss | P72 | Ds | B4 | De VO , ; Trioy | wa 1 p31 Rs V0 P126 | Pie4 | Piss | P71 | as | cs | As i) - - - | Pioe] Lt | Pa | pa vO : : : : : Aa | E7 "0 - - - - - Nt | P3 vO : : : : : D | cs iO : : : : : No 1 Pa GND - - - - - | GND* | GND* vec - - - - | vec* | veer | veo* vO : : : : ch | BS | B4 GND - - | Piss | - | GND* | GND* | GND* vO : : : : B4 | ce | 07 10 : : Tpios |e tna Nt VO, (CS1, A2) | Pi27 | Pies | P17 | P70 | De | as | ce 10 : : Tpioa | 1a} ona | ps 1/0 (A3) Pi2s | Pies | Piss | Pes | ce | D7 | Es iO ; : : : Ko |owi} OND V0 - - - | Pes | Bs | Be | B5 iO ; : : : la 1 ome 1 Ng V0 - - - | Pev | a4 | AG | AS VO ; ; ; : 7 wa NS vec - - - - | vec* | vec | vco* VO ; ; ; : : wa 13 GND - - - - | GND* | Gnp* | GND* GND : : : : Tenp* | anp* 7) - - | Piso | Pes | c7 | De | de /0 (D2) Pio6 | pias | Pis9 | Pto3 | ut Le | M4 vO : -_ | Pt90] Pes | Be | C7 | C7 V0 Pio7 | P139 | Pieo | Pto2 | 3 | ia | U4 vO Pleo | P167 | Piet | Pea | AG | B7 | E9 Voc : T pier | Pioi | vec" | vee | vec" ro) pP130 | Pies | Pis2 | Pes | Ds | Do | a6 i) Pios | Piao | P162 | poo | J2 | Ki | ka vO : : : : cs_ | BB | B vO,FCLK4 | Pio9 | Pi41 | Pie3 | Pos | ua | Ke | 14 vO : : : : : As | D9 i) - - | Pies] pov | Ka | Ka | at GND : : : : 7__ | GND* | GND* VO : Tpies | pss Tar | oka 1 KS 0 - | Pies | Piss | Pee | B7 | Dito | Ent GND Pito | P142 | Pies | Pas | GND* | GND* | GND* vO ~ | Pt170 | Pis4 | Pet | Av | C8 | Ag iO ; : Tpea | ne 1 ue 1s V0 - - | Pi95| Peo | Do | Bo | cto iO ; : se a V0 - - - | ps9 | co | cio | pit iO ; Tpie7 | pon | ua) ual Ka GND Piat | Pi7t | Ptg6 | P58 | GND* | GND* | GND* iO ; Tpies | pst lors tna) aa V0 P132 | Pi72 | Pte7 | P57 | Bs | Bto | Bto GND : : : : Tenp* | anp* V0 P133 | P173 | Pes | P56 | Dio | ato | E12 v0 - | Pi43 | Pi69 | P90 | Ge | He | at vO : 7 | Pt99 | P55 | cto | C11 | Ct i) - | Pi44]Pi70] pss | as | Hs | FA vO : - | P200 | P54 | Bo | Di2 | Bt i) Piit | pias | pi7i | pas | Fe | Ha | Js vec : ~__ | Peot | ps2 | vec" | vec" | vec" i) p1i2 | piae | pt72 | ps7 | E2 | Ge | as vO : : 7 | Pst | ao | Bit | te iO ; , : : : aa Ha V0 - - - | Pso | pit | c12 | att VO ; ; ; : : a GND - - - - - | GND* | GND* GND - - - - | GND* | GND* | GND* vO : : : : 7 | bts | 613 voc : : : yee vee T vee" 7) - - - - - | Bio | E14 /0 (D1) P113 | Pi47 | P173 | Pss | F3 | G4 F3 VO - 7 7 7 Cit | C13 | A13 VO (RCK, P114 | pias | Piva | pss | Ga | Fe | Ga vO : : : : Bio | At2 | Di4 RDY_/BUSY) V0 - - - | pao | Bit | D14 | c14 V0 - - - - pi | F3 | De V0 - - - | pas | ait | B13 | B14 V0 - - - - cr | et | 3 GND - - - - | GND* | Gnp* | GND* V0 - - - - - Fa | Gs vec - - - - | vec* | vec | vco* 0 - - - - - E2 | C1 1/0 (AA) Pisa | Pi74 | 202 | pa7 | Di2 | cia | E15 GND - - - - - | GND* | GND* 1/0 (AS) P1356 | Pi75 | P203 | Pas | ct2 | ata | D15 0 - - - | Pea | de | es | F4 0 - | P176 | P20s | Pas | Bia | B14 | C15 V0 - - - | Pes | F4 | D1 | D3 V0 P136 | P177 | P206 | P44 | ata | D15 | At5 V0 P115 | Pi49 | Pi7s | ps2 | es | c4 | B3 1/0 (A21) P137 | Pize | P207 | P43 | c13 | c15 | ct6 V0 P116 | Piso | Pi76 | ps1 | ce | De | FS /0 (A20) pias | Pi79 | P20s | P42 | B13 | Bis | Ete VO (DO, DIN) | P1t7 | P151 | Pi77 | Pso | D3 | ce | E4 GND - - - - - | GND* | GND* V0 - - - - - | ats | Bt7 6-230 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4052XLA Pinout Table (Continued) XC4052XLA Pinout Table (Continued) PAD NAME = |HQ160|HQ208 | HQ240 | HQ304 | BG352 | BG432| BG560 PAD NAME |HQ160/HQ208| HQ240 | HQ304 | BG352 | BG432 | BG560 VO - - - - - ci6 | C17 GND - - - - As | Aza | Bi 0 (A6) P139 | Piso | P20 | P41 | A13 | Bie | E17 GND - - - - ABi | A30 | B6 0 (A7) P140 | Pist | P210 | P4o | B14 | ate | D17 GND - - - - | aBee] Bt Bg GND P141 | Pis2 | P211 | P39 | GND* | GND* | GND* GND - - - - AE1 | Be | B15 Vcc - - - - Aio | At A4 GND - - - - | AE26 | B30 | B23 Vcc - - - - Ai7 | Ati | Ato GND - - - - AF1 | B31 | B27 Vcc - - - - [acta] aet | ate GND - - - - | ari3s| ci | B31 Vcc - - - - | ac2o] a3 | A22 GND - - - - | aria | c31 | ce Vcc - - - - Acs | Di1 | A26 GND - - - - AF2 | Die | E14 Vcc - - - - | AFto | Det | A30 GND - - - - | are2| a1 | F32 Vcc - - - - | ari7{ ut B2 GND - - - - | ares | G31 | Ge Vcc - - - - D7 4 | B13 GND - - - - | aree| ut | G33 Vcc - - - - Di3 | Les | Big GND - - - - AF5 | J3t1 | 32 Vcc - - - - Dig | Lat | B32 GND - - - - Ars | P4 KA Vcc - - - - G23 | AAt | C3 GND - - - - B1 | P31 L2 Vcc - - - - H4 | aad | C32 GND - - - - Bes | T4 | M33 Vcc - - - - K1 | AA28 | D4 GND - - - - E1 | Tes | Pt Vcc - - - - K26 | AA31 | D33 GND - - - - E26 | vi | P33 Vcc - - - - N23 | AHi1 | H1 GND - - - - Hi | v3i | R32 Vcc - - - - P4 | AH21 | K33 GND - - - - Hee | Aci | T1 Vcc - - - - ui | ALt | M1 GND - - - - N1 | AC31 | v33 Vcc - - - - u26 | ALI1 | N32 GND - - - - Pes | AE1 | we Vcc - - - - we3 | AL21 | R2 GND - - - - wi | AE3t | Y1 Vcc - - - - y4 | AL31 | 133 GND - - - - wee | AH16 | Y33 Vcc - - - - B2 - v1 GND - - - - - AJ1 | AB1 Vcc - - - - B25 - w32 GND - - - - - | Ad31 | AC32 Vcc - - - - AE2 - AA2 GND - - - - - AK1 | AD33 Vcc - - - - | Aces | - | AB33 GND - - - - - AK2 | AE2 Vcc - - - - - - AD1 GND - - - - - | AK30 | AGI Vcc - - - - - - | AF33 GND - - - - - | AK31 | AG32 Vcc - - - - - - AK1 GND - - - - - AL2 | AH2 Vcc - - - - - - | AK33 GND - - - - - AL3 | AJ33 Vcc - - - - - - AL2 GND - - - - - AL7 | AL32 Vcc - - - - - - AL3 GND - - - - - ALQ | AM3 Vcc - - - - - - AM2 GND - - - - - | ALi4 | AM14 Vcc - - - - - - | AM15 GND - - - - - | ALis | AM19 Vcc - - - - - - | amet GND - - - - - | AL23 | AM25 Vcc - - - - - - | Amg2 GND - - - - - | AL25 | AM28 Vcc - - - - - - AN4 GND - - - - - | AL2g | AM33 Vcc - - - - - - AN8 GND - - - - - | AL30 | AM7 Vcc - - - - - - | ANt12 GND - - - - - - AN2 Vcc - - - - - - | AN18 GND - - - - - - AN5 Vcc - - - - - - | AN24 GND - - - - - - | ANtO Vcc - - - - - - | AN30 GND - - - - - - | AN14 Vcc - - - - - c3 | AL3t GND - - - - - - | ANt6 Vcc - - - - - cea | 5 GND - - - - - - | AN20 Vcc - - - - - AJ3 | C31 GND - - - - - - | AN22 Vcc - - - - - | Ad2o | AK4 GND - - - - - - | AN27 GND - - | Pata] - - - - GND - - - - Al A2 A7 GND - - | P24] - - - - GND - - - - Ai4 | a3 | At2 GND - - - - Aig | a7 | At4 NC - Pt - P14 - ca | A28 GND - - - - A2 AQ | At18 NC - P3 - P24 - - A27 GND - - - - A22 | At4 | A20 NC - P51 - P53 - - D25 GND - - - - A25 | Ais | A24 NC - P52 - | Ptoo | - - C26 GND - - - - A26 | A23 | A29 NC - P53 - | Pte] - - A23 GND - - - - AS | A25 | A32 NC - P54 - | Pi76] - - D22 February 1, 1999 (Version 1.0) 6-231XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4052XLA Pinout Table (Continued) XC4052XLA Pinout Table (Continued) PAD NAME = | HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 PAD NAME = | HQ160)HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 NC - P102 - P205 - - C22 NC - - E32 NC - P104 - P254 - - E214 NC - - AC2 NC - P105 - P2841 - - D13 NC - - Al NC - P107 - - - - B12 NC A33 NC - P155 - - - - C12 NC AN1 NC - P156 - - - - E13 NC AN33 NC - P157 - - - - A8 NC A19 NC - P158 - - - - B8 NC D18 NC - P206 - - - E10 NC E24 NC - P207 - - - - c8 NC B26 NC - P208 - - - - H5 NC K5 NC - - - - - - E2 NC H2 NC - - - - - - J4 NC NC - - - - - - H3 NC NC - - - - - - M5 NC NC - - - - - - L3 NC NC - - - - - - M2 NC NC - - - - - - N4 NC NC - - - - - - Y4 NC NC - - - - - - AA NC NC - - - - - - AC1 NC NC - - - - - - AB4 NC NC - - - - - - AF2 NC NC - - - - - - AD5 NC NC - - - - - - AG2 NC NC - - - - - - AE4 NC NC - - - - - - AL8 NC NC - - - - - - AK NC NC - - - - - - AM8 NC NC - - - - - - AJ10 NC NC - - - - - - AL12 NC NC - - - - - - AM12 NC NC - - - - - - AJ13 NC NC - - - - - - AK13 NC NC - - - - - - AN23 NC NC - - - - - - AL22 NC NC - - - - - - AJ21 NC NC - - - - - - AM23 NC NC - - - - - - AM27 12/18/98 NC - - - - - - AJ24 NC - - - - - - AL26 NC - - - - - - AK25 NC - - - - - - AE30 NC - - - - - - AF31 NC - - - - - - AD29 NC - - - - - - AF32 NC - - - - - - AC33 NC - - - - - - AB30 NC - - - - - - Y29 NC - - - - - - AA33 NC - - - - - - N31 NC - - - - - - N30 NC - - - - - - M30 NC - - - - - - L314 NC - - - - - - K29 NC - - - - - - H31 NC - - - - - - E33 6-232 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4062XLA Pinout Table XC4062XLA Pinout Table (Continued) XC4062XLA Pinout Table PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 V0 p56 | P201 | P236 | P5 | B24 | D27 | De9 PAD NAME Ha16o0 | Ha208 | Ha240 | Haso4 | BGs52 | BG432 | Bas6o 0 P4157 | P202 | Pe37 | Pa c23 | B29 | E28 Vcc P142 | P183 | P212 | P38 | VCC* | VCC* | VCC* /0 (A14) P158 | P203 | Pe3s | P3 | Dee | cee | D30 /0 (A8) P143 | P184 | P2i3 | P37 | Di4 | Di7 | At7 0, GCKs (A15) | P159 | P204 | P239 | P2 | C24 | D2e | E29 1/0 (AQ) p144 | P1a5 | P214 | P36 | c14 | Ai7 | Bis Voc P160 | p205 | P2a0 | P11 veo" |} vec" | vec" 0 - - : : 7 | or? | C8 GND Pi | P2 | Pi | P304 | GND* | GND* | GND* V0 - - - - - Bi7 | E18 VO, GCK1 (A16)| P2 | P4 | P2 | P3803] D23 | D29 | B33 vO - - : : : -_ | bts 0 (A17) p3 | P5 | p3 | P302] cas | c30 | Fe9 0 - - - - - - A19 VO P4 P6 P4 | P3801] D24 | E28 | E30 GND - - - : 7__| GND" | GND" V0 Ps | P7 | Ps | P300| E23 | E29 | pat 0 (A19) p145 | P1g6 | P215 | P35 | ais | cis | Cr9 V0 (TD) pe | pa | Pe | P2090] cee | p30 | F30 0 (A18) p146 | P187 | P2t6 | P34 | B15 | Dis | Dig 0 (TOK) py | pe 1 p71 pee | Eaa 1 bai | ca3 V0 - | piss | Pat7 | p33 | c15 | Bie | E19 GND : : - - - | GND* | GND* vO - | piso | Pets] p32 | D15 | ate | B20 0 : : - - - | Fea | Gag 0 (A10) P147 | P190 | P220 | P3t | aie | B19 | C20 10 : ; ; : p39 | E31 0 (Att) p148 | P1917 | P221 | P30 | Bie | cia | D20 10 : : - - | p25 | E30 | Ds2 Vcc - - - - | vecr | veces | vec" V0 : : - - | Fe3 | E31 | G30 GND - - - ~__| GND* | GND* | GND* "0 - - - | P2e7 | Fe4 | Gee | Fat V0 - - - | pea | c1e | pig | aet 0 : : - | pee6 | E25 | Gao | He9 V0 - - - | pes | B17 | a20 | E20 Voc : : - - | vec | veces | vec 0 - - : ~_ | 16 | B20 | Bet GND - - - - | @ND* | GND* | GND* vO - - - - A18 | C20 | C21 VO - - - - - F30 | H30 vO - - - - - B21 D214 vO - - - - - F31 G31 V0 - - : : -__| 20 | Bee 0 ps | Pio | Pa | Pees] Des | Hee | ues GND - - - - -__ | GND* | GND* VO Pg | P11 | PQ | P294 | G24 | Heg | F33 10 - - - P27 | C17 | C21 | C23 VO - P12 | P10 | P293 | F25 | G30 | G32 0 - - - P26 | B18 | A22 | E22 0 - P13 | P11 | Pe92 |} F26 | H30 | J30 Vcc - - | P222 | p25 | vcc* | vec* | voc* GND : : - - - | GND* | GND* V0 - - | p223| p23 | cis | Bee | Bea V0 : : - - - - | H32 V0 - - | p2ea | pee | Diz | cee | Dea 10 : : - - - - | vat V0 P149 | P92 | P225 | Pat | azo | B23 | C24 iO , - | pte | pest | Hea | ues | K30 0 P150 | P193 | P226 | P20 B19 A24 A25 VO . . P13 | Pega | Hea J29 H33 GND P151 | P194 | P227 | Pig | GND*| GND* | GND* 0 : : Tpas9 | aos | nat |} 129 0 - - - P18 | Ci9 | D22 | E23 0 - - - P288 | G26 | J30 | K31 V0 - - -_ | Piz | bis | C23 | B25 GND Pio | P14 | P14 | P287 | GND* | GND* | GND* V0 -__ | P15 | Paes | Pi6 | A2i | Bed | Dad VO, FCLK1 Pit | P15 | P15 | Pese | v23 | Kes | L30 V0 -__| P196 | Peeg | P15 | B20 | C24 | C25 0 Pi2 | P16 | P16 | Pess | Je4 | Keo | K32 0 - - - - - : B26 /0 (TMS) P13 | Pi7 | P17 | P284] H25 | K30 | J33 V0 - - : : : ~__| Ee4 VO P14 | pis | Pig | P2e3| K23 | K31 | M2g GND - - - : 7__ | GND" | GND" voc - - | P19 | Pae2 | voor | vec* | vec VO - - : : ~_ | b23 | E25 VO - - | Peo | Peso] Kea | Leo | L32 V0 - - : : | B26 | Ce? V0 - - | Pat | Pave] u2s | L30 | M31 V0 P152 | P197 | P230 | P14 | C20 | az6 | 026 GND : : : 7 Tnp* | @nb* V0 P153 | P198 | P231 | P13 | B21 | C25 | B28 V0 : : - - - | M30 | Nee 0 (A12) P154 | P199 | p232 | P12 | B22 | Dea | B29 10 : : - - - | mes | 133 0 (A13) P155 | P200 | P233 | P10 | cai | B26 | E26 0 : : , |-s2e | we2o | 32 GND - - - - | GND*| GND* | GND* 10 : : - - | Lea | mat | P29 Vcc - - - | vec* | vec* | vec" v0 - - - | pave | tea | Nat | P30 0 - - - Pg | D20 | A27 | C28 0 - - - P277 | K25 | N28 | N33 V0 - - - ps | ae3 | Des | Dez GND : - | pee | - | anp* | @np* | GND* V0 - - - - | a24a | C26 | B30 Voc : : - - | vec | veces | vec V0 - - - - | B23 | Bez | C29 V0 : : - - - | Neo | P31 vO - - - - - A28 | E27 VO - - - - - N30 | P32 V0 - - : : - | 026 | A831 V0 - - - | P276| Les | P30 | Ree GND - - - : 7__| GND" | GND" V0 - - - | P2756 | 26 | Pea | R30 V0 - - | pe34] pz | Dat | ca7 | Des 10 - | Pig | P23 | Pe74 | mes | Peo | R31 10 - - P235 | P6 | C22 | B28 | C30 VO - P20 | P24 | P273 | M24 | R31 | R33 February 1, 1999 (Version 1.0) 6-233XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC4062XLA Pinout Table (Continued) XC4062XLA Pinout Table (Continued) PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 GND - - - - - | GND* | GND* V0 - - - - - | AF29 | AG30 V0 P15 | Pat | P25 | P272 | M25 | R30 | T31 V0 p32 | p42 | P52 | P237 | 23 | AG31 | AK32 V0 P16 | p22 | P26 | P271 | M26 | Ree | T29 V0 P33 | P43 | P53 | P236 | Acz6 | AF28 | AJ31 V0 - - - - - - T30 GND - - - - - | GND* | GND* V0 - - - - - - 732 V0 - - - - | AD26 | AG30 | AG29 V0 P17 | p23 | P27 | P270 |] N24 | R29 | U32 V0 - - - - | aces | AG29 | AL33 V0 Pig | P24 | P28 | P26e9] Nes | 131 | U3t V0 P34 | P44 | P54 | P235 | AA23 | AH31 | AH30 GND Pig | P25 | P29 | P268 | GND* | GND* | GND* V0 P35 | P45 | P55 | P234 | ABad | AG2s | AK31 Vcc P20 | P26 | P30 | P267 | vcc* | vec* | voc" V0 P36 | P46 | P56 | P233 | AD25 | AH30 | AJ30 V0 P21 | p27 | P31 | P26e6] N26 | T30 | U29 VO, GCK2 P37 | P47 | P57 | P232 | AC24 | AJ30 | AH29 V0 P22 | pes | P32 | P265] P25 | T29 | U30 O (M1) P3s | P48 | P58 | P231 | AB23 | AH29 | AK30 V0 - - - - - - U33 GND P3g | P49 | P59 | P230 | GND* | GND* | GND* V0 - - - - - - V32 | (MO) P4o | P50 | Peo | P229 | AD24 | AH28 | AJ29 V0 P23 | P29 | P33 | P264] P23 | ust | v3t vec P41 | P55 | Pet | P228 | vcc* | vec* | voc" Vo P24 | P30 | P34 | P263] P24 | U30 | ve29 | (M2) P42 | P56 | P62 | P227 | AC23 | AJ2s | AN32 GND - - - - - | GND* | GND* V0, GCK3 P43 | P57 | P63 | P226 | AE24 | AK29 | AJ28 Vo - P31 | P35 | P262 | Ree | U28 | v30 0 (HDC) P44 | P58 | P64 | P225 | AD23 | AH27 | AK29 V0 - P32 | p36 | P261 | R25 | U29 | w33 V0 P45 | P59 | Pes | P224 | Acz2 | Ak28 | AL30 Vo - - - | P26o | R24 | v30 | wt Vo P4s | Peo | P66 | P223 | AF24 | AJ27 | AK28 V0 - - - | Pasa] R23 | vee | w3o V0 P47 | Pei | Pez | P222 | AD22 | AL2s | AM31 V0 - - - - - ves | wee 0 (LDC) P4g | Pe2 | Pes | P221 | AE23 | AH26 | AJ27 V0 - - - - - | wat | 32 GND - - - - - | GND* | GND* Vcc - - - - | vcee*] vec* | vec V0 - - - - - | AK27 | AN31 GND - - P37 - | GND* | GND* | GND* V0 - - - - - | Ad26 | AL29 V0 - - - | pass | T26 | wo | 34 V0 - - - - | ac21 | AL27 | Ak27 V0 - - - | P257 | T25 | wee | Y30 V0 - - - - | AD21 | AH25 | AL28 V0 - - - - - | wee | AaA32 V0 - - - | P220 | AE22 | Ak26 | Au26 V0 - - - - - 31 | AA31 V0 - - - | P2ia | AF23 | AL26 | AM30 V0 - - - - T24 | Y30 | AA30 vec - - - - | vcec* | vec* | vec* V0 - - - - u25 | Y2e | AB32 GND - - - - | GND* | GND* | GND* GND - - - - - | GND* | GND* V0 P4g | Pes | Peg | P218 | AD20 | AH24 | AM29 V0 - - P3s | p256 | T23 | yee | AA29 V0 P50 | Ped | P70 | P217 | AE21 | AJ25 | AK26 V0 - - P3g | p255 | v26 | AA30 | AB3t V0 - Pes | P71 | P2t6 | AF21 | AK25 | AL27 Vcc - - P4o | p2s3 | vcc* | vec* | voc" V0 - Pes | P72 | P215 | ACi9 | AJ24 | Au25 V0 P25 | p33 | P41 | P252 | U24 | AA | AC31 V0 - - - - - | AH23 | AN29 V0 P26 | p34 | P42 | P251 | ves | AB31 | AB29 V0 - - - - - | AK24 | AN28 V0 P27 | p35 | P43 | P250 | ve4 | AB30 | AD32 GND - - - - - | GND* | GND* VO, FCLK2 Pes | p36 | P44 | P249 | U23 | AB29 | AC3O V0 - - - - - - | AM26 GND Peg | p37 | P45 | P248 | GND* | GND* | GND* V0 - - - - - - | AK24 Vo - - - | p247| Y26 | AB28 | AD31 Vo - - P73 | P214 | AD19 | AL24 | AL25 V0 - - - | P246 | wes | Ac3o | AE33 V0 - - P74 | P213 | AE20 | AH22 | Au23 Vo - - P46 | P245 | weed | Ac29 | ACe9 Vo - - - | P2i2 | AF20 | Au23 | AN26 V0 - - P47 | P244 | v23 | aces | AES2 V0 - - - | P2tt | acis | Ak23 | AL24 Vo - - - - - - | AD30 GND P51 | Pe7 | P75 | P210 | GND* | GND* | GND* V0 - - - - - - | AES1 V0 P52 | Pes | P76 | P209 | AD18 | AJ22 | AK23 GND - - - - - | GND* | GND* V0 P53 | Peg | P77 | P208 | AEt9 | AK22 | AN25 V0 - - - - - | AD31 | AG33 V0 P54 | P70 | P78 | P207 | ACt7 | AL22 | AJ22 V0 - - - - - | AD30 | AH33 V0 P55 | P71 | P79 | P206 | AD17 | AJ21 | AL23 V0 - P3s | Pas | P243 | AaAz6 | AD29 | AE29 vec - - Pso | P204 | vcc* | vec* | voc" V0 - P3g | P4g | P242 | Y25 | AD28 | AG31 V0 - P72 | Pai | P203 | AE18 | AH20 | AM24 V0 P30 | P4o | P50 | P241 | Y24 | AE30 | AF30 V0 - P73 | Ps2 | P202 | AF18 | AK21 | AK22 V0 P31 | P41 | P51 | P240 | AA25 | AE29 | AH32 GND - - - - - | GND* | GND* GND - - - - | GND* | GND* | GND* V0 - - - - - | Ad2o | AK21 Vcc - - - - | vcee*] vec* | vec V0 - - - - - | AH19 | AM22 V0 - - - | P23a | AB25 | AF31 | Au32 V0 - - - - | acte | AkK20 | Au20 V0 - - - | P23s | Aa24 | AE2s | AF29 V0 - - - - | abDt16| Auta | ALet V0 - - - - - | AF80 | AH31 V0 - - - | P201 | AE17 | AL20 | AN24 6-234 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4062XLA Pinout Table (Continued) XC4062XLA Pinout Table (Continued) PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 V0 - - - | P200 | AE16 | AHi8 | AK20 V0 - Pai | Piog | Pi66 | AE7 | AK7 | AL7 GND - - P83 - | GND* | GND* | GND* V0 - P92 | P110 | P165 | AD7 | ALe | Aks Vcc - - - - | vcee*] vec* | vec V0 P71 | P93 | P111 | P164| AES | Au7 | ANG V0 - - - | Pig99 | AF16 | AK19 | AL20 V0 P72 | Pod | Pi12 | P163] AES | AHs | AM6 V0 - - - | P198 | Aci5 | Auts | Aut9 GND - - - - | GND* | GND* | GND* V0 - - P84 | P197 | AD15| AL19 | AM20 vec - - - - | vcec* | vec* | vec* V0 - - Pes | P196 | AE15 | AKi8 | AKi9 V0 - - - | P162] AD6 | Ake | Aus V0 P56 | p74 | Pg6 | P195 | AF15 | AH17 | ALt9 V0 - - - | Piet] ac7 | ALS | ALe V0 P57 | P75 | P87 | P194 | AD14 | AJ17 | AN19 V0 P73 | Pas | P113 | P160 | AF4 | AH7 | AK7 GND - - - - - | GND* | GND* V0 P74 | Pos | P114 |] P159 | AF3 | Ade | AMS V0 - - - - - - | Adis V0 - - - - AE4 | AK5 | AM4 V0 - - - - - - | AK18 V0 - - - - | ace | AL4 | Au7 V0 - - - - - | AKi7 | ALt8 GND - - - - - | GND* | GND* V0 - - - - - | ALI7 | AMi8 V0 - - - - - | AH6 | ALS Vo P58 | P76 | P88 | P193 | AE14 | AJi6 | AK17 Vo - - - - - AJS | AK6 0 (NIT) Psa | p77 | Psa | Pi92 | AF14 | AKt6 | AJ17 V0 P75 | P97 | P115 | P158 | ADS | AK4 | ANS Vcc Peo | P78 | P90 | P191 | vcc* | vec* | vec" Vo P76 | Pos | Pit6 | P157 |] AE3 | AHS | AK5 GND Pei | P79 | P91 | P190 | GND*| GND* | GND* V0 P77 | P99 | Pi17 | P156] AD4 | AK3 | AJ6 Vo Pe2 | Pso | P92 | P189 | AE13 | ALi6 | AL17 VO, GCK4 P78 | P100 | Pi18 | P155] ACS | AJ4 | AL4 V0 Pe3 | Psi | P93 | Piss | Act3 | AH15 | AM17 GND P7g | P1o1 | Pita | P154 | GND* | GND* | GND* V0 - - - - - | AL15 | ANI7 DONE Pso | P103 | Pi20 | P153 |] AD3 | AH4 | Ads V0 - - - - - | Adis | AK16 vec Psi | P1o6 | Pi21 | P152 | vcc* | vec* | voc" V0 - - - - - - | Adt6 /PROGRAM | P82 | Ptos | P122 | P151 | Ac4 | AH3 | AM1 V0 - - - - - - | ALt6 /0 (D7) Ps3 | P1o9 | P123 | P150 | AD2 | AJ2 | AHS GND - - - - - | GND* | GND* VO, GCK5 Ps4 | P110 | Pi24 | Pt149 | aca | aca | Aud V0 Pe4 | pg2 | Pod | P187 | AD13 | AKi5 | AM16 V0 Pes | P111 | P125 | P148 | AB4 | AG3 | AK3 V0 Pes | ps3 | P95 | Pise | AF12 | Aui4 | AL15 V0 Pgs | P112| P126 | P147] AD1 | AH2 | AH4 V0 - Ps4 | Pge | P185 | AE12 | AH14 | AK15 V0 - - - - AB3 | AHt | AL1 V0 - Pes | Pg7 | Pi84 | ADi2| AK14 | AU15 V0 - - - - | ace | AF4 | acs V0 - - - | P183 | Aci12] AL13 | AN15 GND - - - - - | GND* | GND* V0 - - - | P1g2 | AF11 | AK13 | AM14 V0 - - | P127]Pi46] AA4 | AFS | AU3 Vcc - - - - | vcee*] vec* | vec V0 - - | P12] P145 | Aas | AG2 | Ak2 GND - - P98 - | GND* | GND* | GND* V0 - - - - - | aai | aca V0 - - - | Pi18t | AE11 | Au13 | AL14 V0 - - - - - | AE4 | AH3 V0 - - - | P180 | AD11 | AH13 | AK14 V0 - - - | P144] AB2 | AES | AFS5 V0 - - - - | AE10| ALt2 | Aut4 V0 - - - | P143] act | AF2 | Au2 V0 - - - - [acti] Ak12 | AN13 vec - - - - | vcec* | vec* | vec* V0 - - - - - | Adt2 | AM13 GND - - - - | GND* | GND* | GND* V0 - - - - - | AKt1 | AL13 /0 (D6) Ps7 | P113 | Pi29 | P142] 3 | Art | AJt GND - - - - - | GND* | GND* Vo Pes | P114 | P130 | P141 | AA2 | AD4 | AF4 V0 - - Peg | P179 | AF9 | AH12 | AKi2 V0 Psg | P115 | P131 | P140 | AAt | AD3 | AG3 Vo - - | P100 | P178 | AD1O | Adi1 | AN11 Vo Pgo | P116 | P132 | P1390] w4 | AE2 | AES Vcc - - | Ptot | P177 | vec | vec | vcc* V0 - - - - - | AD2 | AH1 Vo Pes | Ps6 | P102 | P175 | AEQ | AL1o | AJ12 Vo - - - - - | aca | AF3 V0 Pe7 | ps7 | P103 | P174 | AD9 | AKto | AL11 GND - - - - - | GND* | GND* V0 Pes | Pgs | P104 | P173 | AC1o | AJ1o | AK11 V0 - - - - - - AFI V0 Peg | Psg | P105 | P172| AF7 | Akg | AMtO V0 - - - - - - | AD4 GND P70 | P90 | P106 | P171 | GND* | GND* | GND* V0 - | P117 | P133 | P138 | w3 | Ac3 | AE3 V0 - - - | P170 | AEs | AL8 | ALO V0 - | P1is | P134]P137] v2 | ADI | Acs V0 - - - | Pi6a] ADs | AHt0 | Aut4 V0 - - - | P136] Yt | Ace | Act V0 - - | P107] P168] Aco | Aug | ANO V0 - - - | P135] v4 | AB4 | AD3 V0 - - | Ptos | Pt167| Are | Aka | AKO GND Pei | P119 | P135 | P134 | GND* | GND* | GND* V0 - - - - - - | Amg V0 - - | P136]P133] v3 | AB3 | Ac4 V0 - - - - - - ALQ V0 - - | P137 | P132] we | AB2 | AD2 GND - - - - - | GND* | GND* VO, FCLK3 Pg2 | P120 | Pi38 | P131 | U4 | AB1 | ABS V0 - - - - - AJs | AN7 V0 P93 | P121 | Pi39 | P130 | Us | AAs | AC3 V0 - - - - - | AHg | Aug vec - - | P1490 | P129 | vec* | vec* | vec* February 1, 1999 (Version 1.0) 6-235XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4062XLA Pinout Table (Continued) XC4062XLA Pinout Table (Continued) PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 1/0 (D5) Pe4 | Pi22 | P141 | P127] ve | AA2 | AAS /0 - - - | pos | H3 | v3 | we /0 (/CS0) Pgs | P123| P142 | P126] v1 | ye | ABS /0 - - | Ppie7| Po2 | v4 | ua | Ka GND - - |pia3*| - - | GND* | GND* /0 - - | pies | Pot | Ft | wt | us /0 - - - - T4 | v4 | AB2 /0 - - - - - - H2 /0 - - - - T3 | Y3 | AA4 /0 - - - - - - K5 /0 - - - - - 1 | AAS GND - - - - - | GND*| GND* /0 - - - - - wi | 5 /0 - | p143|Pie9| Peo | a2 | He | Gi /0 - - - | pt25| u2 | wa | y3 /0 - |p144|Pi7o| peo | @3 | H3 | Ft /0 - - - | pte4| Te | wa | ye /0 Pit1 | p145 | Pi71 | Pes | Fe | H4 | us GND - - - - | GND*| GND* | GND* /0 Pi12 | P146 | Pi72| ps7 | G2 | Ge | a3 vcc - - - - | vecr | vce* | vec* /0 - - - - - @3 | H4 /0 - - - - - we | Ws /0 - - - - - FA F2 /0 - - - - - ve | w4 GND - - - - | GND* | GND* | GND* /0 - - - | pies] tr | v4 | ws VCC - - - - | vec* | vce* | vec* /0 - - - | ptee| ra | va | wt 1/0 (D1) P113 | P147 | Pi73 | Pse | F3 | G4 | F3 /0 - | pte4|pi44 | pi21} R3 | ut | v3 VOURCK, | P114|P148]Piz4| pss | G4 | Fe | G4 /0 - | p125|P145 | pi2z0] Re | u2 | vs RDY_/BUSY) GND - - - - Tenp* Tl enp* V0 - - - - bi | F3 | De V0 pgs | Pize | Pi46[Pita[ At | ua | v4 VO : : : - | or | Et | &8 0 pe7 | Pi27 | pi47[Pite{ p3 | u3 | v2 VO : : : : ~ | Fa | 0 - - - - - - Ue /0 - - - - - E2 | C1 0 - - - - - - 7 GND - - - - - | GND*| GND* /0 (D4) pes | Pi2s | pias | pii7[ p2 | t1 | us VO : : ~_| P84 | be | Fo | 0 peg | Piza | Pi4o|[Pite| pi | T2 | ua VO : : ~_ | Pes | Fa | bt | 08 VCC P100 | P130 | P150 | P115 | voc* | vcc* | vcc* vO P11s | P149 | P75 | Pe2 | ES | E4 | B38 GND P1071 | P131 | P151 | P114 | GND* | GND* | GND* vO P16 | P1so | P176 | Per | c2 | D2 | FS 70 (D3) Pica | p1a2 | Pisa | pita Lo} 731 u3 VO (DO, DIN) | Ptt7 | P151 | Piz7 | Pso | D3 | ce | E4 vOURs) | Pi03 | P133| Piss] Pii2| Na | Rt | 72 "Coun. P118 | P12 | P1768 | P79 | 4 | D3 | D4 7 - - - - - - = CCLK P119 | P153 | P179 | P78 | c3 D4 | ca 70 S104 3134 o164 oi x =D 4 vcc P120 | P154 | P1so | P77 | vec* | vcc* | vcc* 0, TDO Pi21 | Pisa | Pisi | P7e | D4 | ca | Ee /0 P1o5 | P135 | P155] Pio] mi | R4 | Rt SND Sno PGND GND Ptz2 | Pt60 | P1s2 | P75 | GND* | GND* | GND* - - - - - 0 (AO, Ws) | P123 | Pie1 | P1s3 | P74 | Bs B3 | DS /0 - | p136|P156] Pio9} m2 | R3 | RB 0 Saar Perey biog toma tp /O, GCK7 (A1) | P124 | Pie2 | Pisa] P73 | ca | Ds | a2 - /0 P125 | Pte3 | Pis5 | P72 | D5 | B4 | De /0 - - - | pto7| m4 | pP3 | Rs /0 Pi26 | Pte4 | Pise | P71 | as | cs | a3 /0 - - - | Ptoe| Lu Pa | P2 /0 - - - - - A4 | E7 /0 - - - - - Ni | P3 /0 - - - - - De | C5 /0 - - - - - Ne | P4 vec vec? | vcc* | voc* en - - - - _| GND*| eX - - - - VO - - - - C5 BS B4 GND - - |piss| - | GND*| GND*| GND* /0 Pios | Le | Na | Nf vo - - - - Ba | C8 | 07 - - - /O, (C81, A2) | P127 | P165 | P1s7] P7o | De | a5 | ce /0 - - - |pto4| 3 | N4 | P5 0 eK /0 (A3) Pi2z8 | P1e6 | Piss | Peo | ce | D7 | Es - - - - VO - - - Pes | BS B BS /0 - - - - L4 | m2 | NB 0 NE /0 - - - | pez | a4 | ae | AS - - - - - Vcc - - - - | vec* | voc* | voc* /0 - - - - - M4 | M3 SND Sno Tn GND - - - - | GND* | GND* | GND* - - - - - VO - - | pisa9 | Pes | c7 D8 D8 /0 (D2) Pto6 | P138 | P159 | P103] Jt Le | M4 /0 Pto7 | P139 | P10 | P1o2} K3 | v3 | ut vo - ~_{ Pio | Pes | B6 | O7 | /0 Pi29 | Pte7 | P191 | Pea | As | B7 | E9 vcc - - | Ptet | Ptot | vec* | vec* | vec* /0 P130 | Ptes | Pig2 | Pes | Ds | Do | A6 /0 Ptos | P140 | P1e2 | poo | 2 | Ki | ke /0 - - - - cs | Bs | B7 VO, FCLK4 | Ptog | Pi41 | P1e3 | Pos | us | Ke | La /0 P1e4| poz | K4 | K3 | uf vo - - - - - Ag _| D8 - - GND - - - - - | @npd* | GND* /0 - - |ptes| Pos | at | Ka | kB /0 - - - - - - | Dio GND Pt10 | P142 | P16e | Pas | GND*| GND* | GND* 70 ae /0 - - - | pea | He | v2 | Ls 6-236 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4062XLA Pinout Table (Continued) XC4062XLA Pinout Table (Continued) PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 V0 - | Pisa] Pi93] Pe2 | B7 | Dio | E11 Vcc - - - - AE2 | - AA2 V0 - | P170]Pi94] Pe1 | a7 | co | ag vec - - - - |aAe25] - | AB33 V0 - - | P1195] Peo | De | Bo | cto vec - - - - - - | ADI V0 - - - Psa | co | cto | D114 vec - - - - - - | AF33 GND P131 | P171 | Pi96 | P58 | GND* | GND* | GND* vec - - - - - - AK1 V0 P132 | P172 | Pi97| P57 | Bs | Bio | Bto vec - - - - - - | AK33 V0 P133 | P173 | Pig9a | P56 | Dio | Ato | E12 vec - - - - - - AL2 V0 - - | Pi99] P55 | cio | cit | crt vec - - - - - - AL3 V0 - - | P200] P54 | Ba | Di2 | Bt vec - - - - - - | Ame Vcc - - | P2ot | P52 | vec* | vec* | vcc* vec - - - - - - | AM15 V0 - - - P51 | ag | Bit | D12 vec - - - - - - | amet V0 - - - P50 | D141 | C12 | Att vec - - - - - - | AM32 GND - - - - - | GND* | GND* vec - - - - - - | AN4 V0 - - - - - D1i3 | C13 vec - - - - - - | ANS Vo - - - - - B12 | E14 vcc - - - - - - | AN12 V0 - - - - ci1 | c13 | A13 vec - - - - - - | AN18 Vo - - - - Bio | Ai2 | D14 vcc - - - - - - | AN24 V0 - - - Pag | B11 | D14 | C14 vec - - - - - - | AN30 Vo - - - P4g | Ait | Bi3 | B14 vcc - - - - - c3 | AL3t GND - - - - | GND* | GND* | GND* vec - - - - - ceg | E5 Vcc - - - - | vcee*] vec* | vec vec - - - - - AJ3 | C31 0 (A4) P134 | P174 | P202 | P47 | Di2 | C14 | E15 vec - - - - - | Ad2a | AK4 /0 (A5) P135 | P175 | P203 | P4e | ci2 | Ai3 | D15 V0 - | P176|P205| P45 | Bi2 | Bi4 | C15 GND - - - - Al A2 | A7 V0 P136 | P177 | P206 | P44 | at2 | D15 | At5 GND - - - - Ai4 | a3 | At12 0 (A214) P137 | P17s | P207 | P43 | ci3 | c15 | C16 GND - - - - Aig | a7 | At4 1/0 (A20) P138 | P17a | P208 | P42 | B13 | Bi5 | E16 GND - - - - A2 | ag | Ais GND - - - - - | GND* | GND* GND - - - - A22 | At4 | A20 V0 - - - - - - D16 GND - - - - A25 | Ais | A24 V0 - - - - - - B16 GND - - - - A26 | A23 | A29 V0 - - - - - Ai5 | Bi7 GND - - - - AS | A25 | A32 V0 - - - - - ci6 | C17 GND - - - - As | Aza | Bt /0 (A6) P139 | Piso | P209 | P41 | Ai3 | Bi6 | E17 GND - - - - ABi | A30 | B /0 (A7) P140 | Pist | P210 | P4o | B14 | Ate | D17 GND - - - - | aBee| Bt Bg GND P141 | Pig2 | P2t1 | P39 | GND*| GND* | GND* GND - - - - AE1 | B2 | B15 Vcc - - - - Aio | At A4 GND - - - - | Ae26|] B30 | B23 Vcc - - - - Ai7 | Att | Ato GND - - - - AF1 | B31 | B27 Vcc - - - - [acta] A2t | ate GND - - - - |ari3s] ci | B31 Vcc - - - - |aczo] a31 | Az2 GND - - - - | aria] c31 | ce Vcc - - - - | acs | Dit | Age GND - - - - AF2 | Di6 | E14 Vcc - - - - | AF1o | D21 | A30 GND - - - - | are2] a1 | Fe82 Vcc - - - - | aAFi7] uu B2 GND - - - - | AF25| G31 | Ge Vcc - - - - D7 | L4 | B13 GND - - - - | ar26] u1 | G33 Vcc - - - - Di3 | Les | B19 GND - - - - AF5 | J31 | 32 Vcc - - - - Dig | 131 | B32 GND - - - - AF8 | P4 KA Vcc - - - - G23 | AA1 | C3 GND - - - - B1 | P31 | Le Vcc - - - - H4 | AA4 | C32 GND - - - - Bes | T4 | M33 Vcc - - - - K1 | AA28 | D1 GND - - - - E1 | Tas | P41 Vcc - - - - K26 | AA31 | D33 GND - - - - E26 | vi | P33 Vcc - - - - N23 | AH11 | H14 GND - - - - Hi | v31 | R32 Vcc - - - - P4 | AH21 | K33 GND - - - - H26 | Aci | 11 Vcc - - - - ui | ALt | M1 GND - - - - Ni | Ac31] v33 Vcc - - - - u26 | AL11 | N32 GND - - - - Pee | AE1 | we Vcc - - - - | we3 | ALe1 | Re GND - - - - wit | ae31] Yt Vcc - - - - y4 | AL31 | 133 GND - - - - | wee | AHi6 |] Y33 Vcc - - - - B2 - v1 GND - - - - - AJi | ABI Vcc - - - - B25 - | wee GND - - - - - | Au31 | Acs2 February 1, 1999 (Version 1.0) 6-237XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4062XLA Pinout Table (Continued) XC4062XLA Pinout Table (Continued) PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 PAD NAME HQ160 | HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 GND - - - - - AK1 | AD33 NC - - - - - - AL8 GND - - - - - AK2 | AE2 NC - - - - - - AK9 GND - - - - - AK30 | AG NC - - - - - - AM8 GND - - - - - AK31 | AG32 NC - - - - - - AJ10 GND - - - - - AL2 | AH2 NC - - - - - - AL12 GND - - - - - AL3 | AJ33 NC - - - - - - AM12 GND - - - - - AL7 | AL32 NC - - - - - - AJ13 GND - - - - - ALQ | AM3 NC - - - - - - AK13 GND - - - - - AL14 | AM11 NC - - - - - - AN23 GND - - - - - AL18 | AM19 NC - - - - - - AL22 GND - - - - - AL23 | AM25 NC - - - - - - AJ21 GND - - - - - AL25 | AM28 NC - - - - - - AM23 GND - - - - - AL29 | AM33 NC - - - - - - AM27 GND - - - - - AL30 | AM7 NC - - - - - - AJ24 GND - - - - - - AN2 NC - - - - - - AL26 GND - - - - - - AN5 NC - - - - - - AK25 GND - - - - - - AN10 NC - - - - - - AE30 GND - - - - - - AN14 NC - - - - - - AF31 GND - - - - - - AN16 NC - - - - - - AD29 GND - - - - - - AN20 NC - - - - - - AF32 GND - - - - - - AN22 NC - - - - - - AC33 GND - - - - - - AN27 NC - - - - - - AB30 GND - - P204 - - - - NC - - - - - - Y29 GND - - P219 - - - - NC - - - - - - AA33 NC - - - - - - N31 NC - Pt - P14 - c8 A28 NC - - - - - - N30 NC - P3 - P24 - - A27 NC - - - - - - M30 NC - P54 P53 - - D25 NC - - - - - - L34 NC - P52 - P100 - - C26 NC - - - - - - K29 NC - P53 - P128 - - A23 NC - - - - - - H31 NC - P54 - P176 - - D22 NC - - - - - - E33 NC - P102 - P205 - - C22 NC - - - - - - E32 NC - P104 - P254 - - E214 NC - - - - - - Al NC - P105 - P2841 - - D13 NC - - - - - - A33 NC - P107 - - - - B12 NC - - - - - - AN1 NC - P155 - - - - C12 NC - - - - - - AN33 NC - P156 - - - - E13 NC - - - - - - AC2 NC - P157 - - - - A8 12/18/98 NC - P158 - - - - B8 NC - P206 - - - - E10 NC - P207 - - - - c8 NC - P208 - - - - H5 NC : 7 - - - E2 NC : 7 - - - J4 NC - - - - - - H3 NC - - - - - - | MS NC - - - - - - L3 NC - - - - - - | Me NC - - - - - - N4 NC - - - - - - | 4 NC - - - - - - AA NC : - - - - - | act NC - - - - - - AB4 NC - - - - - - | AF2 NC - - - - - - | ADS NC - - - - - - | age NC - - - - - - AE4 6-238 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4085XLA Pinout Table XC4085XLA Pinout Table (Continued) XC4085XLA Pinout Table PAD NAME |HQ160|HQ208 |] Ha240| Ha304 | BG352| BG432|BG560 v0 - - - pa | Deo | ae7 | C28 PAD NAME |HQ160|HQ208 | Ha240|H@304 | BG352| BG432| BG560 0 : : : ps | A23 | D25 | Dez vec P142 | P1a3 | P212 | p38 | vcc* | vcc* | voc* 0 : : - - | Aea | cee | B30 1/0 (A8) P143 | Pta4 | P2i3 | p37 | D14 | Di7 | at7 0 : : : - | p23 | Be7 | cee 1/0 (AQ) P144 | Pta5 | P2i4 | p36 | ci4 | ai7 | Bt8 0 - : : - - | a2e | E27 vO - - - - - C17 C18 vO - - - - - D26 A31 V0 - - - - - | B17 | Ets GND : : - - | GND* | GND* | GND* V0 - - : : : -_ | bts v0 - - | pe34 | P7 | Det | C27 | Des VO - - : : : - | AIS V0 - - | P235 | Pe | cae | Bes | C30 GND - - : 7__| GND* | GND" | GND" v0 pPis6 | Peot | Pass | Ps | Boa | De7 | Des vo (ats) | P145 | Piss | Pats | P35 | ats | cia | cis 0 Pis7 | Poon | paay | pa | ca3 | B29 | Epa vo (ata) | P146 | Pis7 | Pete | P34 | Bis | Dis | Dis 0 (A14) | Piss | Pe0a | Peas | Pa | Dee | ces | bao VO -__[ P88 | Pei7 | P33 | cis | Bi | E19 VO, GCK8 (A15)| Pi59 | P204 | Paso | P2 | cea | Das | E29 V0 -__ | P189 | Pais | P32 | Did | A19 | B20 vec P160 | P205 | P240 | Pi | voc | vec* | vcc* vO (Ato) | P147 | Piso | P220 | P31 | ate | Bis | C20 GND pr 1 ps | p11 pao | anp* | GNb* | GND vo(att) | P148 | Pi91 | Peet | P30 | Bie | cis | Deo 0, GCKi (Ate)| Pe | Pa | pe | P303 | b23 | bee | Bae vcc - - - >| vec* | vec* | vec* 0 (A17) P3 P5 P3 | P3802 | C25 | C30 | F29 GND - - : >| GND* | GND* | GND" v0 pa | pe | P4 | P30t | Dea | E28 | E30 0 - - - Peg | C16 | DI9 | A2t 0 P5 P7 P5 | P3800 | E23 | E29 | D31 VO - - - Pes | Bi7 | A20 | E20 VO (TDN) Pe | Ps | Pe | P299| c2ze | D30 | F30 VO - - : 7 | pte | 820 | Bat VO (TCK) p7 | po | Pv | pees | E24 | Dai | ca3 vO - - - - | ais | ceo | cet GND - : - | GND* | GND* | GND* vO - - - - - B21 D21 VO - - - - - F28 G29 vO - - - - - D20 B22 VO - - - - - Feg E31 VO - - - - - - Eat VO - - - - D25 E30 D32 vO - - - - - - C22 vO - - - - F23 E31 G30 GND - - - - | GND* | GND* | GND* V0 : : - | pe97 | Fea | Gea | Fst V0 - - - : : : bee V0 - - - | Pees | E25 | G2o | Hee V0 - - - - : -__ | A238 VCC - - - - | vec* | veo* | voce V0 - - - | Pe7 | ci7 [ cat | ces GND - : - | GND* | GND* | GND* V0 - - - | Pes | Bis | aze | E22 V0 - : : - - - E32 vec - - | Pee2 | p25 | vcc* | vcc* | voc* 0 : : - - - - E33 V0 - - | Pees | p23 | cis | B22 | B24 V0 - : : - - | F30 | H30 V0 - - | Pee4 | pee | Di7 | c22 | be3 0 - : : - - | Fat | G31 V0 P149 | Ptg2 | P225 | P21 | azo | B23 | Cea 10 Pa | Pto | pe | P2905 | b2e | Hee | Jeg V0 Pis0 | P193 | P226 | P20 | Big | A24 | Aas 10 Bo | Pty | pa | Peed | Goa | Hos 1 33 GND Pis1 | P94 | P227 | Pig | GND* | GND* | GND* 10 - | Pt2 | Pio | P2903 | Fes | Gao | ae 10 - - - P18 | Cig | D22 | E23 VO - P13 | Pit | P292 | F2 | H30 | J30 V0 - - - | P17 | p18 | ces | Bes Voc - : : - | vec | veo* | vcc* V0 - | Pigs | Paes | P16 | a2i | Boa | Ded GND - : - | GND* | GND* | GND* V0 - | Pi96 | P22 | P15 | B20 | Coa | cas V0 - : : - - - H31 VO - - - - - - | B26 V0 - - : : : : Kee V0 - - - - - - | E24 0 ; : : - - | Hae VO - - - - - - C26 V0 - - : : : : J34 V0 - - : : : : bes VO - - | P12 | P2e1 | He3 | vee | k30 GND - - - - GND* | GND* | GND* 0 - - P13 | P290 | H24 | J29 | H33 vec - - - -__ vec" | vec" | vec" "0 - - - | peso | Gas | H31 | Las V0 - - - : : -_ | Ae? V0 - - - | pees | Gee | u30 | Kat VO - : : : : : A286 GND Pio | P14 | P14 | P27 | GND* | GND* | GND* 0 - - - - - De3_| Ees VO,FCLK1 | P11 | P15 | P15 | Pese | J23 | Kes | L30 fe) - - - - - B25 | C27 VO Pi2 | P16 | P16 | P285 | J24 | K29 | K32 0 Pis2 | Pi97 | P230 | P14 | C20 | A26 | 026 vocms) | P13 | Piz | P17 | P2e4 | Hes | K30 | 433 V0 Pis3 | Pigs | Peat | pis | Bat | cas | B28 0 pia | pis | pie | poea | kg 1 Kai) eo vo (at2) | P154 | Pies | P23s2 | Pi2 | Bee | Dea | Bes Veo : 1pi9 | page | veo" | veo | vec" vo (at3) | P155 | P200 | P233 | Pio | cat | Bese | E26 0 : : : , 7 7 [34 GND - - - - GND* | GND* | GND* vO - - - - - - M30 vec - - - - | veo* | vec | vec* 10 : - | P20 | Peso | Kea | L290 | Lae February 1, 1999 (Version 1.0) 6-239XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4085XLA Pinout Table (Continued) XC4085XLA Pinout Table (Continued) PAD NAME | HQ160/ HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 PAD NAME | HQ160/ HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 VO - - Pai P279 | J25 L30 M31 VO P26 P34 P42 | P2514 V25 | AB31 | AB29 GND - - - - GND* | GND* | GND* VO P27 P35 P43 | P250 | V24 | AB30 | AD32 VO - - - - - M30 N29 VO, FCLK2 P28 P36 P44 | P249 | U23 | AB29 | AC30 VO - - - - - M28 L33 GND P29 P37 P45 | P248 | GND* | GND* | GND* VO - - - - - - N30 VO - - - P247 | Y26 | AB28 | AD31 VO - - - - - - N31 VO - - - P246 | W25 | AC30 | AE33 VO - - - - J26 M29 M32 VO - - P46 | P245 | We4 | AC29 | AC29 VO - - - - L23 M31 P29 VO - - P47 | P244 | V23 | AC28 | AE32 VO - - - P278 | L24 N31 P30 VO - - - - - - AD30 VO - - - P277 | K25 N28 N33 VO - - - - - - AE31 GND - - P22 - GND* | GND* | GND* VO - - - - - - AF32 VCC - - - - vcc* | vcc* | VCC* VO - - - - - - AD29 VO - - - - - N29 P31 GND - - - - GND* | GND* | GND* VO - - - - - N30 P32 VCC - - - - vcec* | vcc* | VCc* VO - - - P276 | L25 P30 R29 VO - - - - - - AF31 VO - - - P275 | L26 P28 R30 VO - - - - - - AE30 VO - P19 P23 | P274 | M23 P29 R31 VO - - - - - AD31 | AG33 VO - P20 P24 | P273 | M24 R31 R383 VO - - - - - AD30 | AH33 GND - - - - GND* | GND* | GND* VO - P38 P48 | P243 | AA26 | AD29 | AE29 VO P15 Pai P25 | P272 | M25 R30 T31 VO - P39 P49 | P242 | Y25 | AD28 | AG31 VO P16 P22 P26 | P271 | M26 R28 T29 VO P30 P40 P50 | P241 Y24 | AE30 | AF30 VO - - - - - - T30 VO P31 P44 P54 P240 | AA25 | AE29 | AH32 VO - - - - - - T32 GND - - - - GND* | GND* | GND* VO P17 P23 P27 | P270 | N24 R29 U32 VCC - - - - vcec* | vcc* | VCc* VO P18 P24 P28 | P269 | N25 T31 U31 VO - - - P239 | AB25 | AF31 | AJ32 GND P19 P25 P29 | P268 | GND* | GND* | GND* VO - - - P238 | AA24 | AE28 | AF29 VCC P20 P26 P30 | P267 | VCC* | VCC* | VCC* VO - - - - - AF30 | AH31 VO Pai P27 P31 P266 | N26 T30 U29 VO - - - - - AF29 | AG30 VO P22 P28 P32 | P265 | P25 T29 U30 VO P32 P42 P52 | P2387 | Y23 | AG31 | AK32 VO - - - - - - U33 VO P33 P43 P53 | P236 | AC26 | AF28 | AJ31 VO - - - - - - V32 GND - - - - GND* | GND* | GND* VO P23 P29 P33 | P264 | P23 U31 V31 VO - - - - AD26 | AG30 | AG29 VO P24 P30 P34 | P263 | P24 U30 V29 VO - - - - AC25 | AG29 | AL33 GND - - - - GND* | GND* | GND* VO P34 P44 P54 | P235 | AA23 | AH31 | AH30 VO - P31 P35 | P262 | R26 U28 V30 VO P35 P45 P55 | P234 | AB24 | AG28 | AK31 VO - P32 P36 | P2614 R25 U29 | W33 VO P36 P46 P56 | P233 | AD25 | AH30 | AJ30 VO - - - P260 | R24 V30 | W31 VO, GCK2 P37 P47 P57 | P232 | AC24 | AJ30 | AH29 VO - - - P259 | R23 veg | Ww30 O (M1) P38 P48 P58 | P231 | AB23 | AH29 | AK30 VO - - - - - v28 | We29 GND P39 P49 P59 | P230 | GND* | GND* | GND* VO - - - - - Wws31 Y32 | (MO) P40 P50 P6oO | P229 | AD24 | AH28 | AJ29 VCC - - - - vcc* | vcc* | VCC* VCC P41 P55 P1 P228 | VCC* | VCC* | VCC* GND - - P37 - GND* | GND* | GND* | (M2) P42 P56 P62 | P227 | AC23 | AJ28 | AN32 VO - - - P258 | T26 Ws30 | Y31 VO, GCK3 P43 P57 P63 | P226 | AE24 | AK29 | AJ28 VO - - - P257 | T25 weg | Y30 VO (HDC) P44 P58 P64 | P225 | AD23 | AH27 | AK29 VO - - - - - - AA33 VO P45 P59 P65 | P224 | AC22 | AK28 | AL30 VO - - - - - - Y29 VO P46 P60 P66 | P223 | AF24 | AJ27 | AK28 VO - - - - - Wes | AA32 VO P47 P1 P67 | P222 | AD22 | AL28 | AM31 VO - - - - - Y31 | AA31 VO (/LDC) P48 P62 P68 | P221 | AE23 | AH26 | AJ27 VO - - - - T24 Y30 | AA3O GND - - - - GND* | GND* | GND* VO - - - - U25 Y29 | AB32 VO - - - - - AK27 | AN31 GND - - - - GND* | GND* | GND* VO - - - - - AJ26 | AL29 VO - - P38 | P256 | T23 Y28 | AA29 VO - - - - AC21 | AL27 | AK27 VO - - P39 | P255 | V26 | AA30 | AB31 VO - - - - AD21 | AH25 | AL28 VO - - - - - - AB30 VO - - - P220 | AE22 | AK26 | AJ26 VO - - - - - - AC33 VO - - - P219 | AF23 | AL26 | AM30 VCC - - P40 | P253 | VCC* | VCC* | VCC* VCC - - - - vcec* | vcc* | VCc* VO P25 P33 P44 P252 | U24 | AA29 | AC31 GND - - - - GND* | GND* | GND* 6-240 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4085XLA Pinout Table (Continued) XC4085XLA Pinout Table (Continued) PAD NAME | HQ160/ HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 PAD NAME | HQ160/ HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 VO P49 P63 Pg | P218 | AD20 | AH24 | AM29 VO - - - - - AJ15 | AK16 VO P50 P64 P70 | P217 | AE21 | AJ25 | AK26 VO - - - - - - AJ16 VO - P65 P71 P216 | AF21 | AK25 | AL27 VO - - - - - - AL16 VO - P66 P72 | P215 | AC19 | AJ24 | AJ25 GND - - - - GND* | GND* | GND* VO - - - - - AH23 | AN29 VO P64 P82 P94 | P187 | AD13 | AK15 | AM16 VO - - - - - AK24 | AN28 VO P65 P83 P95 | P186 | AF12 | AJ14 | AL15 VO - - - - - - AK25 VO - P84 P96 | P185 | AE12 | AH14 | AK15 VO - - - - - - AL26 VO - P85 P97 | P184 | AD12 | AK14 | AJ15 VCC - - - vcc* | vcc* | VCC* VO - - - P183 | AC12 | AL13 | AN15 GND - - - - GND* | GND* | GND* VO - - - P182 | AF11 | AK13 | AM14 VO - - - - - - AJ24 VCC - - - - vcec* | vcc* | VCc* VO - - - - - - AM27 GND - - P98 - GND* | GND* | GND* VO - - - - - - AM26 VO - - - P181 | AE11 | AJ13 | AL14 VO - - - - - - AK24 VO - - - P180 | AD11 | AH13 | AK14 VO - - P73 | P214 | AD19 | AL24 | AL25 VO - - - - AE10 | AL12 | AJ14 VO - - P74 | P213 | AE20 | AH22 | AJ23 VO - - - - AC11 | AK12 | AN13 VO - - - P212 | AF20 | AJ23 | AN26 VO - - - - - AJ12 | AM13 VO - - - P211 | AC18 | AK23 | AL24 VO - - - - - AK11 | AL13 GND P54 P67 P75 | P210 | GND* | GND* | GND* VO - - - - - - AK13 VO P52 P68 P76 | P209 | AD18 | AJ22 | AK23 VO - - - - - - AJ13 VO P53 P69 P77 | P208 | AE19 | AK22 | AN25 GND - - - - GND* | GND* | GND* VO P54 P70 P78 | P207 | AC17 | AL22 | AJ22 VO - - - - - - AM12 VO P55 P71 P79 | P206 | AD17 | AJ21 | AL23 VO - - - - - - AL12 VCC - - P80 | P204 | VCC* | VCC* | VCC* VO - - Pgg | P179 | AF9 | AH12 | AK12 VO - P72 P81 P203 | AE18 | AH20 | AM24 VO - - P100 | P178 | AD1O | AJt1 | AN11 VO - P73 P82 | P202 | AF18 | AK21 | AK22 VCC - - P101 | P177 | VCC* | VCC* | VCC* VO - - - - - - AM23 VO P66 P86 | P102 | P175 | AES | AL10 | AJ12 VO - - - - - - AJ21 VO P67 P87 | P103 | P174 | ADS | AKiO | AL11 GND - - - - GND* | GND* | GND* VO P68 P88 | P104 | P173 | AC10 | AJ10 | AK11 VO - - - - - - AL22 VO P69 Psg | P105 | P172 | AF7 AKS | AM10 VO - - - - - - AN23 GND P70 Pgo | P106 | P171 | GND* | GND* | GND* VO - - - - - AJ20 | AK21 VO - - - P170 | AE8 AL8 | AL10 VO - - - - - AH19 | AM22 VO - - - P169 | AD8 | AH10 | AJt11 VO - - - - AC16 | AK20 | AJ20 VO - - P107 | P168 | AC9 AJ9 AN9 VO - - - - AD16 | AJ19 | AL21 VO - - P108 | P167 | AF6 AK8 | AK10 VO - - - P201 | AE17 | AL20 | AN21 VO - - - - - - AM9 VO - - - P200 | AE16 | AH18 | AK20 VO - - - - - - ALQ GND - - P83 - GND* | GND* | GND* VO - - - - - - AJ10 VCC - - - - vcc* | vcc* | VCC* VO - - - - - - AM8 VO - - - P199 | AF16 | AKi9 | AL20 GND - - - - GND* | GND* | GND* VO - - - P198 | AC15 | AJ18 | AJ19 VCC - - - - vcec* | vcc* | VCc* VO - - P84 | P197 | AD15 | AL19 | AM20 VO - - - - - - AK9 VO - - P85 | P196 | AE15 | AK18 | AK19 VO - - - - - - AL8 VO P56 P74 P86 | P195 | AF15 | AH17 | AL19 VO - - - - - AJ8 AN7 VO P57 P75 P87 | P194 | AD14 | AJ17 | AN19 VO - - - - - AH9 AJQ GND - - - - GND* | GND* | GND* VO - P91 P109 | P166 | AE7 | AK7 AL7 VO - - - - - - AJ18 VO - Pg2 |} P110 | P165 | AD7 AL6 AK8 VO - - - - - - AK18 VO P71 P93 | P111 | P164 | AE6 AJ7 AN6 VO - - - - - AK17 | AL18 VO P72 P94 | P112 | P163 | AES | AH8 | AM6 VO - - - - - AL17 | AM18 GND - - - - GND* | GND* | GND* VO P58 P76 P88 | P193 | AE14 | AJ16 | AK17 VCC - - - - vcec* | vcc* | VCc* VO (INIT) P59 P77 Psg | P192 | AF14 | AK16 | AJ17 VO - - - P162 | AD6 | AK6 AJ8 VCC P60 P78 Pgo |} P191 | VCC* | VCC* | VCC* VO - - - P161 | AC7 ALS AL6 GND P1 P79 P91 P190 | GND* | GND* | GND* VO P73 P95 | P113 | P160 | AF4 | AH7 | AK7 VO P62 P80 Pg2 | P189 | AE13 | AL16 | AL17 VO P74 Pg | P114 | P159 | AF3 AJ6 AM5 VO P63 P81 P93 | P188 | AC13 | AH15 | AM17 VO - - - - AE4 | AK5 | AM4 VO - - - - - AL15 | AN17 VO - - - - AC6 AL4 AJ7 February 1, 1999 (Version 1.0) 6-241XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC4085XLA Pinout Table (Continued) XC4085XLA Pinout Table (Continued) PAD NAME = |HQ160|HQ208 | HQ240 | HQ304 | BG352| BG432 | BG560 PAD NAME |HQ160|HQ208 | HQ240 | HQ304 | BG352| BG432| BG560 GND - - - - | GND* | GND* | GND* VO - - - - - Yi | AAS Vo - - - - - AH6 | ALS Vo - - - - - wi Y5 V0 - - - - - AJ5 | AK6 V0 - - - - - - AAI Vo P75 | Pe7 | P115 | P158 | ADS | AK4 | AN3 Vo - - - - - - Y4 V0 P76 | Pos | P1i6 | P157 | AES | AHS | AK5 V0 - - - P125 | u2 | wa | yY3 Vo P77 | Peg | P117 | P156 | AD4 | AK3 | AJB Vo - - - P124| T2 | w3 | ye V0, GCK4 P7g | Ptoo | P1i8 | P155 | acs | AJ4 | AL4 GND - - - - | GND* | GND* | GND* GND P7g | Pto1 | P1149 | P154 | GND* | GND* | GND* Vcc - - - - | vec* | vec* | vec* DONE Pso | Pto3 | P120 | P153 | AD3 | AH4 | AU5 V0 - - - - - we | WS5 Vcc Psi | Ptoe | P121 | P152 | vcc* | vcc* | vcc* V0 - - - - - ve | w4 /PROGRAM | P82 | Pios | P122 | P151 | Ac4 | AH3 | AM1 V0 - - - P123 | 11 v4 | w3 /0 (D7) Ps3 | Ptog | P123 | P150 | AD2 | AJ2 | AHS V0 - - - P122 | R4 v3 | wi VO, GCK5 ps4 | Ptto | Pi24 | P149 | aca | a4 | Au4 V0 - P124 | P144 | Pi21 | R3 ud V3 V0 Pes | Pitt | P125 | P148 | AB4 | AG3 | AK3 V0 - P125 | P145 | P120 | R2 U2 V5 V0 Pgs | P112 | P126 | P147 | AD1 | AH2 | AH4 GND - - - - | GND* | GND* | GND* V0 - - - - AB3 | AH1 | AL1 V0 Pes | P126 | P146 | P1i9 | Ri u4 | v4 V0 - - - - Ac2 | AF4 | AGS5 V0 P97 | P127 | P147 | P1is | P3 us | v2 GND - - - - | GND*] GND* | GND* V0 - - - - - - U2 V0 - - P127 | Pi4e | AA4 | AF3 | AU3 V0 - - - - - - ut V0 - - Pi2s | P145 | Aas | AG2 | AK2 /0 (D4) Peg | Pi28 | P148 | P117 | P2 T1 U5 V0 - - - - - AGi | AG4 V0 Peg | Pt29 | P149 | P1ie | P14 T2 U4 V0 - - - - - AE4 | AH3 Vcc P100 | P130 | Piso | P115 | vec* | vcc* | vcc* V0 - - - P144 | AB2 | AES | AFS5 GND Pi1o1 | P131 | P151 | P114 | GND* | GND* | GND* V0 - - - P143 | aci | AF2 | Au2 /0 (D3) Pi1o2 | P132 | P152 | P113 | N2 T3 U3 vcc - - - - | vee* | vec* | vec* 1/0 (RS) P103 | P133 | P153 | P112 | N4 Ri T2 GND - - - - | GND*] GND* | GND* V0 - - - - - - T3 /0 (D6) Ps7 | P113 | P129 | P142 | v3 | AFT | Aut Vo - - - - - - T5 V0 Pgs | P114 | P130 | P141 | Aa2 | AD4 | AF4 V0 P104 | P134 | P154 | P1141] N3 R2 T4 Vo Peg | P115 | P131 | P140 | AA1 | AD3 | AG3 Vo P105 | P135 | P155 | P110 | M1 R4 Ri V0 Pgo | Ptt | P132 | P139 | w4 | AE2 | AES GND - - - - | GND* | GND* | GND* V0 - - - - - AD2 | AH1 V0 - P136 | Pi56 | Piog | m2 R3 R3 V0 - - - - - Ac4 | AF3 V0 - P137 | P157 | Pios | M3 P2 R4 V0 - - - - - - AE4 V0 - - - Pio7 | M4 P3 R5 V0 - - - - - - AG2 V0 - - - Pios | 1 P4 P2 Vcc - - - - | vcce* | vec* | voce V0 - - - - - Ni P3 GND - - - - | GND*] GND* | GND* V0 - - - - - N2 P4 V0 - - - - - - AD5 Vcc - - - - | vec* | vec* | vec* V0 - - - - - - AF2 GND - - Piss | - | GND* | GND* | GND* V0 - - - - - - AF V0 - - - P105 | L2 N3 Nt V0 - - - - - - AD4 V0 - - - Pio4 | 13 N4 P5 V0 - P117 | P133 | Pi38 | w3 | Ac3 | AE3 V0 - - - - K2 M1 N2 V0 - P1ig | P134 | P137 | y2 | AD1 | ACS V0 - - - - L4 M2 N3 V0 - - - P136 | yt | Ac2 | AE1 V0 - - - - - - N4 V0 - - - P135 | v4 | AB4 | AD3 V0 - - - - - - M2 GND Pei | Ptig9 | P135 | P134 | GND* | GND* | GND* V0 - - - - - M3 N5 V0 - - P136 | P133 | v3 | AB3 | Ac4 V0 - - - - - M4 | M3 V0 - - P137 | P132 | we | AB2 | AD2 GND - - - - | GND* | GND* | GND* VO, FCLK3. | P92 | P120 | Pi38 | P131 | U4 | ABI | ABS /0 (D2) P106 | P138 | Pis9 | Pio3 | a1 L2 M4 V0 P93 | Pi21 | P139 | P1390 | U3 | AAs | ACc3 V0 P107 | P139 | Piso | P1o2 | K3 3 uy vcc - - P1490 | Pt29 | vcc* | vcc* | vcc* Vo - - - - - - 3 V0 - - - - - - AB4 V0 - - - - - - M5 Vo - - - - - - ACI vcc - - P161 | Pto1 | vcc* | vcc* | vcc* /0 (D5) Pe4 | Pt22 | P141 | P127 | ve | Aa2 | AAS V0 P1o08 | P140 | Pi62 | Peo | ue KA K2 /0 (/CS0) Pes | P123 | P142 | P126 | v1 y2 | AB3 VO, FCLK4 | Pio9 | P141 | Pi63 | Pos | 43 K2 L4 GND - - P143. | - | GND* | GND* | GND* V0 - - P1e4| Pav | K4 K3 Jf V0 - - - - T4 Y4 | AB2 V0 - - P165 | Pgs | Gt K4 K3 V0 - - - - T3 Y3 | AA4 GND P110 | P142 | P1e6 | P95 | GND* | GND* | GND* 6-242 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4085XLA Pinout Table (Continued) XC4085XLA Pinout Table (Continued) PAD NAME [HQ160/HQ208/Ha240/ Ha304 | BG352| BG432| BaS60 PAD NAME |HQ160]HaQ208/Ha240/ Ha304 | BG352/ BG432] BG560 VO - - - Poa | Ho J2 L5 VO P130 | Pies | Pi92 | Pes | Ds D9 AG VO - - - P93 | H3 J3 J2 VO - - - - c8 B8 B7 VO - - P1e7 | P92 | J4 J4 K4 VO - - - - - A8 D9 VO - - Pies | Pot F4 H1 J3 VO - - - - - - C8 VO - - - - - - H2 VO - - - - - - E10 VO - - - - - - K5 vec - - - - - | vee* | voc* VO - - - - - - H3 GND - - - - - | GND* | GND* VO - - - - - - J4 VO - - - - - - BS GND - - - - | GND* | GND* | GND* VO - - - - - - A8 vcc - - - - | vee* | vec* | vec* VO - - - - - - D10 VO - P143 | Pieg | P90 | Ge H2 Gi VO - - - - - - cg VO - Pi44 | Piva | ps9 | G3 H3 F4 VO - Pie9 | Pi93 | Pe2 | B7 | Dio | E11 VO P1i1 | Pi45 | P171 | Pass | Fe H4 J5 VO - P170 | Pi94 | Pet AZ cg AQ VO Pi12 | Pi4e | P172 | ps7 | E2 Ge G3 VO - - Pi95 | Peo | Dg Bo | Cto VO - - - - - G3 H4 VO - - - P59 | ca | cio | pit VO - - - - - F4 F2 GND P131 | Pi71 | Pi96 | P58 | GND* | GND* | GND* VO - - - - - - E2 VO P132 | Pi72 | Pi97 | P57 | Bs | Bio | Bio VO - - - - - - H5 VO P133 | Pi73 | Pigs | P56 | Dio | Ato | E12 GND - - - - | GND* | GND* | GND* VO - - Pi99 | P55 | cio | cit | cit vcc - - - - | vee* | vec* | vec* VO - - P200 | P54 | Bo | Di2 | Bit VO (D1) P113 | Pi47 | P173 | Pas | F3 G4 F3 vcc - - P201 | P52 | vec* | vec | voc* VOURCK, | P114 | Pi4s | P174 | Pas | G4 F2 G4 VO - - - P51 Ag | Bit | Di2 RDY_/BUSY) /0 - - - P50 | Dit | C12 | Att VO - - - - D1 F3 D2 iO 7 7 7 7 7 7 E45 VO - - - - Ct Et E3 VO 7 7 7 7 7 7 tp vO : : : : : Fa | GS GND - - - - | GND* | GND* | GND* VO - - - - - E2 Ct 10 7 7 7 7 7 7 Bip GND - - - - | GND* | GND* | GND* iO 7 7 7 7 7 7 DiS VO - - - Ps4 | D2 E3 F4 VO 7 7 7 7 7 Dis | 073 VO - - - Ps3 | F4 D1 D3 iO 7 7 7 7 7 Bia | E14 VO P115 | Pi49 | P175 | ps2 | 8 E4 B3 iO 7 7 7 7 cit | cia | Ata VO Pi1i6 | Pi50 | P176 | Pat C2 D2 F5 iO 7 7 7 7 Bio | Ai2 | Dia VO (DO, DIN) | P117 | P151 | Piz77 | Pso | D3 C2 E4 iO 7 7 7 pag | Bit | bia | a4 WO,acke | Ptis | P152 | Pizs | P79 | Ea D3 D4 iO 7 7 7 Pas | Ai? | B13 | Bid (DOUT) - - - CCLK P119 | P153 | P179 | P7a | c3 D4 C4 GND - - - ~_| GND" | GND" | GND vcc - - - - | vee* | vec* | vec* vcc Pi120 | Pi54 | P1so | P77 | voc* | vcc* | vec* 5 Tb0 sorb piso bPiar bP pve 1 a Ga =5 VO (A4) P134 | Pi74 | P2o2 | p47 | Di2 | cia | E15 /O (AS) P135 | Pi75 | P203 | P46 | ci2 | ais | D15 GND Pi22 | Pieo | Pts2 | P75 | GND* | GND* | GND* VO (AG, WS) | P123 | Piet | P1s3 | P74 | BS B3 D5 vo - Pi7 | Pe0s | Pas | Bie | Bia | Cts 0, GCK7 | P124 | P162 | Pisa | P73 | ca D5 A2 vo P16 | Pi77 | Pe0e | Pad | At2 | DIS | ANS (at)" /O (A21) P137 | Pizs | P207 | P43 | c13 | ci5 | ci V0 piss | Pia3 | pias | P72 | Ds Ba D /O (A20) Pi38 | Pi79 | P20s | P42 | Bis | Bi5 | E16 V0 Pi26 | P1e4 | Piss | P71 | a3 | cs | a3 GND : : : -__ | GND* | GND* | GND* VO - - - - - A4 E7 vO 7 7 7 7 7 7 D16 VO - - - - - D C5 VO 7 7 7 7 7 7 B16 GND - - - Tenp* | Gnp* | Gnp* VO - - - - - A1i5 | B17 VO - - - - C5 B5 B4 /O 7 7 7 7 7 C16 C17 VO : : : : Ba an D7 /O (A6) P139 | Piso | P209 | Pai | ai3 | Bie | 17 0, (C81, A2) | Pi27 | Pies | Pie? | P70 | De AS wn VO (A7) Piao | Pis1 | P210 | P4o | Bia | Ate | DI7 0 (A3) Pi2g | Pis6 | P1388 P69 C6 D7 E8 GND P141 | P182 | P211 P39 | GND* | GND* | GND* VO - - - Pes | B5 B B5 vec - - - - Ato | At AA VO . . . P67 A4 AG A5 VCC - - - - A17 Ait A10 VGC - - - yee" | veo" | vec" VCC - - - - |acia| aot | ate GND . . . . GNbD* | GND* | GND* VCC - - - - AC20 A31 A22 VO - - Pis9 | Pee | C7 D8 D8 vec 7 7 7 7 Ac8 | Dit | A26 VO - - P190 | P65 B C7 C7 vec 7 7 7 7 AF10 | D21 | A30 VO Pi29 | Pie7 | Pi91 | Pea | AG B7 E9 vec 7 7 7 ARIZ | OU B2 February 1, 1999 (Version 1.0) 6-243XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC4085XLA Pinout Table (Continued) XC4085XLA Pinout Table (Continued) PAD NAME | HQ160/ HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 PAD NAME | HQ160/ HQ208 | HQ240 | HQ304 | BG352 | BG432 | BG560 VCC - - - - D7 L4 B13 GND - - - - AF26 Jt G33 VCC - - - - D13 L28 B19 GND - - - - AF5 J34 J32 VCC - - - - D19 L314 B32 GND - - - - AF8 Pt K4 VCC - - - - G23 AA C3 GND - - - - Bt P31 L2 VCC - - - - H4 AA4 C32 GND - - - - B26 T4 M33 VCC - - - - K4 AA28 D1 GND - - - - Et T28 P4 VCC - - - - K26 | AA31 D383 GND - - - - E26 v1 P33 VCC - - - - N23 | AH11 H4 GND - - - - H1 V31 R32 VCC - - - - P4 AH21 | K33 GND - - - - H26 | AC1 T1 VCC - - - - Ut AL1 M1 GND - - - - N1 AC31 | V33 VCC - - - - U26 | AL11 N32 GND - - - - P26 AE1 we VCC - - - - we3 | AL21 R2 GND - - - - wi AE31 Y1 VCC - - - - Y4 AL31 | 133 GND - - - - wee | AH16 | Y33 VCC - - - - B2 - v1 GND - - - - - AJt AB VCC - - - - B25 - W32 GND - - - - - AJ31 | AC32 VCC - - - - AE2 - AA2 GND - - - - - AK1 | AD33 VCC - - - - AE25 - AB33 GND - - - - - AK2 AE2 VCC - - - - - - AD1 GND - - - - - AK30 | AG1 VCC - - - - - - AF33 GND - - - - - AK31 | AG32 VCC - - - - - - AK1 GND - - - - - AL2 AH2 VCC - - - - - - AK33 GND - - - - - AL3 | AJ33 VCC - - - - - - AL2 GND - - - - - AL7 | AL32 VCC - - - - - - AL3 GND - - - - - ALQ | AM3 VCC - - - - - - AM2 GND - - - - - AL14 | AM11 VCC - - - - - - AM15 GND - - - - - AL18 | AM19 VCC - - - - - - AM21 GND - - - - - AL23 | AM25 VCC - - - - - - AM32 GND - - - - - AL25 | AM28 VCC - - - - - - AN4 GND - - - - - AL29 | AM33 VCC - - - - - - AN8 GND - - - - - AL30 | AM7 VCC - - - - - - AN12 GND - - - - - AN2 VCC - - - - - - AN18 GND - - - - - - AN5 VCC - - - - - - AN24 GND - - - - - - AN10 VCC - - - - - - AN30 GND - - - - - - AN14 VCC - - - - - C3 AL31 GND - - - - - - AN16 VCC - - - - - C29 E5 GND - - - - - - AN20 VCC - - - - - AJ3 C31 GND - - - - - - AN22 VCC - - - - - AJ29 | AK4 GND - - - - - - AN27 GND - - P204 - - - - GND - - - - Al A2 A7 GND - - P219 - - - - GND - - - - A14 A3 Al2 GND - - - - A19 A7 A14 NC - Pt - P14 - c8 At GND - - - - A2 AQ A18 NC - P3 - P24 - - A33 GND - - - - A22 A14 A20 NC - P54 - P53 - - AN1 GND - - - - A25 A18 A24 NC - P52 - P100 - - AN33 GND - - - - A26 A23 A29 NC - P53 - P128 - - AC2 GND - - - - AS A25 A32 NC - P54 - P176 - - - GND - - - - A8 A29 B1 NC - P102 - P205 - - - GND - - - - AB1 A30 B6 NC - P104 - P254 - - - GND - - - - AB26 Bt B9 NC - P105 - P2841 - - - GND - - - - AE1 B2 B15 NC - P107 - - - - - GND - - - - AE26 | B30 B23 NC - P155 - - - - - GND - - - - AF1 B31 B27 NC - P156 - - - - - GND - - - - AF13 ct B31 NC - P157 - - - - - GND - - - - AF19 | C31 c2 NC - P158 - - - - - GND - - - - AF2 D16 E14 NC - P206 - - - - - GND - - - - AF22 Gi F32 NC - P207 - - - - - GND - - - - AF25 | G31 G2 NC - P208 - - - - - 6-244 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC4085XLA Pinout Table (Continued) [| PAD NAME |HQ160/HaQ208/Ha240|Ha304 | BG352| BG432|BG560| 12/18/98 * Note: Pads labelled GND* or VCC are internally bonded to Ground or VCC planes within the associated package. They have no direct connection to any specific package pin. February 1, 1999 (Version 1.0) 6-245XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40110XV Pinout Table XC40110XV Pinout Table (Continued) XC40110XV Pinout Table PAD EPIC t Name |Pap#|'1@240| Ba352 | BG432 | Ba560 | PG559 NAME |paps|H@240| Ba352 | BG432 | BaS60 | Pass vo | 3%] - | c7 | cat | cas | Rs vecio | - | P240 [vccio*| vccior | vccio* | vccio* = = - - - = = V0 acs 1 | p239| cea | p28 E29 E3 SND - - - Snow }Gnp GND vo (Ai4)| 2 | P238 | Dee | C28 D30 F4 veclo | - - -__ | vecio" | vecio"| __- VO 3 | P2e37| ca3 | B29 E28 J7 VO A : : : C22 US VO 4 | pe36| Boa | D27 D29 D2 VO 42 : : : E21 v2 VO 5 | P235| c22 | B28 C30 K8 VO 43 | - : D20 B22 U7 VO 6 | P234| D21 | C27 D28 H6 VO 44 | - : B21 p21 U3 VO 7 , : , , - 0 45 - Ais | C20 C21 Y2 VO 5 : : : : - 0 46 - D16 B20 B21 V4 veclo |. - Tyee" | vecio - 0 47 - Bi7 | A20 E20 V6 GND - - - @ND* | GND* 1) GND* 0 48 - ci6e | D19 A21 W5 VO 5 : : : : - GND - - | G@ND* | GND* | GND* | GND* 10 10 : : - - - vecio | - - |vecio*l vecior | vecio* | vccio* VO 7 : : D26 rer G5 VO (A11)| 49 | P221] Bie | ci19 D20 w7 70 43 - - 138 E57 = V0 (A10)| 50 | P220] At6 B19 C20 4 70 43 - 553 B37 29 Hd 0 51 | P218] Di5 | A19 B20 AAI 70 14 - hod | G36 530 Gl 0 52 | P217] C15 B18 E19 Y6 70 15 - 133 | D235 537 35 V0 (A18)| 53 | P216| B15 Di8 D19 AB2 70 16 - 5201 D7 C28 7 VO (A19)| 54 | P215| A15 | C18 C19 8 vecio | - - |vecio*| vecio* | vcecio* | vccio* vO 98 , : : - : GND - - | GND* | GND* | GND* | GND* VO 56 : - : VO (A13) | 17 | P233 | C21 B26 E26 J3 GND : : : GND" | GND* | GND* Vo (A12)| 18 | P232] B22 D24 B29 K4 veclo | - : -_ | veclo" | VCCIo" - VO 19 | P231 | B21 C25 B28 H2 VO 37 : - : VO 20 | P2301 C20 A26 D26 L5 VO 58 : - : V0 21 - - B25 C27 a VO 99 : : A19 AA3 VO 22 - - D23 E25 M6 VO 60 : D18 AAS VO 33 : : , ADA KB 0 61 - - BI7 E18 ACI 10 >A : : - Ay WT 0 62 - - C17 C18 AA7T vecio |. Tyeeio*l vecio* | vecio* | vecior vo (Ag) | 63 | P214[ cia | At7 B18 AB4 GND - - - GND* | GND* | GND* vo (As) | 64 | P213| Di4 | Di7 Ai7 ABG6 10 35 : : - 525 a vecio | - | P212 [vecio*| vccio* | vccio* | vccio* VO 36 : : : G06 13 GND - | P211| GND* | GND* | GND* | GND* VO a7 : : : Fad rr VO (A7) | 65 | P210| B14 | At6 D17 AC3 10 3B : : - 536 Md VO (A6) | 66 | P209| A13 B16 E17 AC5 VO 39 | P2290 | B20 1 G24 G25 Ba VCCINT | - - - _ [VCCINT*|VCCINT*| VCCINT* v0 30 | P228| A21 | B24 D24 N5 VO 67 | - : : : AD2 VO 31 - | Dis | c23 B25 Rt V0 68 | - - AIS Bi7_ | Ac7 vo | 32 / - | cio | Dee | E23 N3 vO | 8 | - - Big | AF2 vecio | - - - [vecior|vecior | - VO 7o | - - : DI6_| AD4 GND - | P227| GND* | GND* | GND* | GND* VO a : - : V0 33 | P226] Big | Ao4 A25 R7 VO 72 : : - - V0 34 - , , ; PA vecio | - - - | vecio* | vccio* : VCCINT | - | P2251 A20 |VCCINT*|VCCINT*|VCCINT* GND : : GND* | GND* | GND* V0 35 | P224] Di7 | C22 D23 T2 VO 3 : : - - VO 36 | P223] C18 B22 B24 T8 VO 74 : - : vecio | - | P222 [vccio*| vccio* | vccio* | vccio* VO (A20) | 75 | P208 | B13 B15 E16 AD6 10 37 : Bia | ABD E50 AS VO (A21)| 76 | P207] C13 | C15 C16 AE5 6-246 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40110XV Pinout Table (Continued) XC40110XV Pinout Table (Continued) PAD | EPIC PAD | EPIC NAME. | pAD#|H@240| BG352 | BG432 | BG560 | PGS59 NAME. | PAD#|H@240| BG352| BG432 | BGS560 | PGS59 VO 77 | P206 | A12 D15 A15 AF4 VO (A3) | 115 | Piss | ce D7 E8 BAT VO 73 | P205| B12 Bi4 C15 AGI V0, 116 | Pis7| D6 IG c AU5 70 (A5) | 79 | P203] C12 Ai3 D15 AD8 (CS1,A2) VO (A4) | 80 | P202] D12 C14 E15 AG3 VO 117 : Ba C6 D7 AY2 vecio | - - |vcecio*| vecio* | vecio* | vccio* VO 118 C5 BS B4 AT6 GND - - | GND* | Gnpo* | GND* | GND* VO 119 " " 7 7 7 VO 81 - Alt B13 B14 AH4 VO 120 : 7 7 /O 82 - B11 D14 C14 AE7 GND 7 GND* | GND" | GND* /O 83 - B10 Ai12 D14 AH2 veclo | - >| vecio* | vecio* 7 VO 84 - C11 C13 A13 AF6 VO 121 : 7 7 /O 85 - - B12 E14 AJt VO 122 7 7 7 /O 86 - - D13 C13 AG5 VO 123 D6 cs AP8 vO 87 : : : Dia AJ3 0 124] - - A4 E7 AR7 VO 88 ; : : Bip AKA 1/0 125] - - C5 A3 AY4 vecio |. ; ~ Tyecio* | vecio* : 1/0 126 | Piss | A3 - - BB2 GND : : : GNp* | GND* | GND* vccINT | - | Pi85| D5 [VCCINT*/VCCINT*|VCGCINT* VO 89 ; : : C12 AG? VO GCK7 | 127 | Pi84 | C4 D5 A2 AV6 VO 90 - - - E13 AK2 (At) 70 31 - OT a3 Mi AE 00 us) 128 | Pis3 | B3 B3 D5 AT8 VO 92 - AQ B11 D12 AL3 GND Tpig2 | Gnp* | GND* | GND* | GnD* vecio | - | P201 |vccio*| vccior | vecio* | vccio* . 1DO |. | Pist | ba CA = BAS vO | 93 | P200| Bo | DI2 | Bil | AM4 vecio | - | Piso{ - | vecior | vccio | vccio" VO 94 | Pi99| Cio CH CH ANI CCLK Tr179 1 63 D4 CA BAS vccINT | - | Pi98 | Dio [VccINT|VCCINT*|VCCINT* yo acks| 129 | Pi7e | E4 D3 D4 BBA VO 95 - - - - AL5 (DOUT) VO 96 | Pi97| B8 B10 B10 AH8 VO (DO, | 130 | P177 | Ds C2 E4 AY6 GND - | Pig96] GND* | GND* | GND* | GND* DIN) VCCIO - - - vccio* | vccio* - VO 131 | P176 c2 D2 F5 BC3 Vo 97 - C9 C10 D114 AJ7 0 132 | P175 E3 E4 B3 AW7 vO gg | Pi95| D9 BO C10 AP2 vO 133 : F4 D1 D3 BBS VO 99 | Pi94| A7 cg AQ AN3 VO 134 - D2 E3 F4 AUS 0 100 | Pi93 | B7 D10 E11 AP4 VO 135 | - 7 7 vO 101 - - - cg AR1 vO 136 : : : : : VO joo |. : : D10 ANS vecio | - - - | vecior | vccio" - VO 103 | : AB AM6 GND - - - GND* | GND* | GND* vO 104 - - - B8 AK8 vO 137 : : : : : GND - - - GND* | GND* | GND* vO 138 : : : : : vecio | - - |vecio*| vccio* | vccio* | vccio* VO 139 : : E2 C1 AT10 Vo 105 - - - E10 AL7 oO 140 - - F4 G5 AV8 VO joe |. : : C8 ATO 0 144 - C1 E1 E3 AY8 VO 107 - - A8 D9 AR3 oO 142 - D1 F3 D2 BC7 VO jos | Ba B7 AUt VOURCK,| 143 | Pi74 | G4 F2 G4 AW9 VO jo9 | Pig2| Ds D9 AG AT4 ae VO | 110 | Piot | AG B7 E9 AV2 VO (D1) | 144 | P173 | F3 G4 F3 BAQ VO 111 | Pi90 | Be C7 C7 AR5 veclo | - Tye" | vecio* | vecio* VO 112 | Piso | C7 D8 D8 AN7 GND - - - GND* | Gnp* | GND* GND - - | @Np* | GND* | GND* | GND* 0 745} - - 7 AUT vcclo | - - |vecio*] vccior | vecior | vccio" 0 146 1 - - = AYi0 VO 113] - A4 AG IG AW3 0 tay 1 - Fi = BBS VO 4] - B5 B6 B5 AV4 0 {48} - G3 Hd AWI1I February 1, 1999 (Version 1.0) 6-247XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40110XV Pinout Table (Continued) XC40110XV Pinout Table (Continued) PAD | EPIC PAD | EPIC NAME |paps#|4@240| BG352 | BG432 | BG560 | Pas59 NAME |pAps#|4@240/ BG352| BG432 | Ba560 | Pas59 VO 149] - - G2 G3 BC9 0 185 | P155 | M1 R4 Ri AW21 VO 150 | - - H4 J5 AV12 0 ise | - - - T4 AU21 GND - - - - - - 0 187 | - - - T5 BB22 VO 151 | Pi72| E2 H3 FA AU13 0 iss | - - - - AY22 VO 152 | Pi71| Fe H2 Gi AT14 0 is9 | - - - - - vecio | - - - | vecior | vecio* | vecio* 0 j90 | - - - - - GND - - - GND* | GND* | GND* vecint | - | Pi54[ N83 [VCCINT*/VCCINT*|VCCINT* VO 153] - - - J4 BATI vO RS) | 191 | P1538] N4 Ri T2 AV22 VO 154] - - - H3 AY12 VO (D3) | 192 | P152 | N2 T3 U3 BA23 VO 155 | P170| G3 - K5 BB10 GND - | P1541 - GND* | GND* | GND* VO 156 | P1e9| G2 - H2 AW13 vecio | - | P150 - | vecio* | vecio* | vecio* VO 157 | Pies | FI H1 J3 BC11 0 193 | P149 | Pi T2 U4 AW23 VO 158 | P1e7| Ja J4 KA AU15 VO (D4) | 194 | Pias | Pe TH U5 AY24 VO 159] - H3 J3 J2 BB14 0 195] - - - - - VO 160 | - H2 J2 L5 AT16 0 joe | - - - - - vecio | - - - | vecio* | vecio* - 0 197 | - - - Ut BC23 GND - | Pies | GNp* | GND* | GND* | GND* 0 jos | - - - U2 BA27 VO 161 | Pie5| Gi KA K3 BA13 0 199 | Pi47 | P83 U3 V2 AU23 VO 162] - - - - AY14 0 200 | Pi46] Rt U4 V4 AV24 vecint | - | Pie4| Ka [VCCINT*|VCCINT*|VCCINT* vecio | - - - | vecio* | vecio* - 0, 163 | Pie3| 43 K2 L4 BC15 GND - - - GND* | GND* | GND* FCLK4 vo | 201 | P145 | R2 U2 v5 AY26 vO | 164 | P162| Je KI Ke | AW15 vo | 202 | P144| RB Ut v3 BB24 vecio | - | Pie1 |vccio*| vecio* | vecio* | vccio* 10 503 | Ra v3 Wi AW25 vO | 165] - - - M5 | BAIS vo | 204 - TH v4 w3 | BB26 vO | 166] - - - Ls AUI7 vo | 205[ - - v2 w4 | AT24 VO 167 | Pieo| K3 L3 Li BB16 10 506 | : wo WS BADO VO (D2) | 168 | Pi59 | 4 L2 M4 AY16 10 507 | : : : : GND - - - GND* | GND* | GND* vO 708 | : : : : veclo | - 7 [vector | vecio" vecio | - - [vecio*| vecio* | vecio* | vecio* VO 169 | - M4 M3 AW17 GND - | Pi43 | @np* | GND* | GND* | GND* VO 170 | - M3 NS AV18 0 209 | - T2 ws Y2 AY28 VO 1714 M2 BAI7 0 210 | - U2 Ww4 3 AU25 VO 173 | - L4 M2 N3 AU19 vO o12 |. : : AAI BCO7 VO 174] - K2 M1 N2 BB18 10 3139 | : Wi Y5 AWw27 VO 175] - L3 N4 P5 AY18 10 aia |e : v1 AAS Bp2e vO 176 | - Le N3 N1 AW19 0 215 | - T3 3 AAA BAS1 GND - | Pi58 | G@ND* | GND* | GND* | GND* vO oie |. TA YA AB2 | AY30 vecio | - - [vecio*| vecio* | vecio* | vecio* voclo |. - TyeeIo* | vec" | vecio* VO Ww7 | GND - - - GND* | GND* | GND* VO 178 | - vO VCs0)| 217 | P1422] V1 Y2 ABS | AW29 VO 179 | - Ne P4 AV20 0 (D5) | 218 | Piai | ve AA2 AAS BC29 VO iso | - - Nt P3 AT20 v0 a19 | : : AGI AU27 VO 181 - Li P4 P2 BB20 vO 200 |. : : AB4 BA33 VO 182 | - M4 P3 RS AY20 vecio | - | P140 |vccio*| vecio* | vecio* | vecio* VO 183 | Pi57 | M3 P2 R4 Bca1 0 221 | P139 | U3 AA3 AC3 AY32 VO 184 | Pis | M2 R3 R3 BA21 0, 222 | Pi38] U4 ABI ABS | AW31 GND - - - GND* | GND* | GND* FCLK3 vecio | - - - | vecio* | vecio* - vecint | - | P1387 | we [VCCINT*|VCCINT*|VCCINT* 6-248 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40110XV Pinout Table (Continued) XC40110XV Pinout Table (Continued) PAD | EPIC PAD | EPIC NAME |paps#|4@240| BG352 | BG432 | BG560 | Pas59 NAME |pAps#|4@240/ BG352| BG432 | Ba560 | Pas59 VO p23 | - - - - BB30 0 259 | - - - - AV42 VO 224 | Pi3s6e | V3 AB3 Ac4 | BA35 0 260 | P115] ADS | AK4 AN3 | AR37 GND - | P135 | GND* | GND* | GND* | GND* 0 261 - - AJ5 AK6 AP36 vecio | - - - | vecio* | vecio* - 0 262 | - - AH6 AL5 AT38 VO 225 | - V4 AB4 AD3. | AT28 0 263 | - - - - - VO 226 | - YI AC2 AE1 AU29 0 264 | - - - - - VO 227 | Pisa | 2 AD1 AC5 BC33 vecio | - - - | vecio* | vecio* - VO 228 | P1338] W3 AC3 AES | AY34 GND - - - GND* | GND* | GND* VO 229 | - - - AD4 | BB34 0 265 | - - - - - VO 230 | - - - AFI AW33 0 266 | - - - - - VO 231 - - - AF2 AU31 0 267 | - AC6 AL4 AJ7 AU39 VO 232 | - - - AD5 | AV32 0 268 | - AE4 | AK5 AM4 | AU43 GND - - - GND* | GND* | GND* 0 269 | P114| AFS AJ6 AM5 | BA43 vecio | - - [vecio*| vecio* | vecio* | vecio* 0 270 | P1138] AF4 | AH7 AK7 AT42 VO 233 [| - - - AG2 | AT30 0 271 - Ac7 | AL5 AL6 AR39 VO 234 [ - - - AE4 | AU33 0 272 [| - AbD6 | AK6 AJ8 AN37 VO 235 | - - AC4 AF3. | AW35 vecio | - - [vecio*| vecio* | vecio* | vecio* VO 236 | - - AD2 AH1 BC35 GND - - | @Nd* | GND* | GND* | GND* VO 237 | P132 | wa AE2 AES | AY36 0 273 |P112] AES | AH8 AM6 | AT40 VO 238 | P131 | AAt ADS AG3 | BB36 0 274 | P111| AES AJ7 AN6 | AP40 VO 239 |P130] AA2 | AD4 AF4 | AV36 0 275 |P110| AD7 | AL6 AK8 | AR43 0 (D6) | 240 | Pi29 | Ys AFI AJl AU35 0 276 | P109| AE7 | AK7 AL7 | AN39 GND - - - GND* | GND* | GND* 0 277 | - - AHO AJ AP42 vecio | - - - | vecio* | vecio* | vecio* 0 278 | - - AJ8 AN7 | AM38 VO 241 - ACI AF2 AJ2 AT34 0 279 | - - - AL8 AN43 VO 242 [ - AB2 | AES AF5 | AW37 0 280 | - - - AK9 AL37 VO 243 [| - - - - - vecio | - - [vecio*| vecio* | vecio* | vecio* VO 244 | - - - - - GND - - - GND* | GND* | GND* VO 245 [| - - AE4 AH3 BC37 0 281 - - - AMs | AK36 VO 246 | - - AGI AG4 | AY38 0 2g2 | - - - AJiO. | AR41 VO 247 | Pi28] AAS | AG2 AK2 BB38 0 283 [| - - - AL9 AL41 VO 248 | P127| AA4 | AF3 AJ3 BA41 0 284 | - - - Amo | AN41 GND - - - GND* | GND* | GND* 0 285 | P108| AF6 AK8 | AKiO | AK42 vecio | - - - | vecio* | vecio* - 0 286 | P1i07| AC9 AJ ANQ | AM40 VO 249 | - - - - - 0 287 | - Abs | AH10 | AJ11 AJ43 VO 250 | - - - - - 0 ose | - AES AL8 ALIO | AJ37 VO 251 - Ac2 | AF4 AGS | AY40 vecio | - - - | vecio* | vecio* - VO 252 [ - AB3 | AH1 ALI BB40 GND - | Pt06 | GND* | GND* | GND* | GND* VO 253 | P126 | AD1 AH2 AH4 | AT36 0 289 |P105| AF7 | AKO9 | AM10 | AL39 VO 254 | P125] AB4 | AGS AK3 BA39 0 290 | - - - - AH36 1/0, GCK5| 255 | Pi24 | aca | AG4 AJA AV38 vecint | - | P104 | Acio [VCCINT*|VCCINT*|VCCINT* VO (D7) | 256 | Pi23 | AD2 AJ2 AH5 BC41 0 291 | P103 | AD9 | AKio | AL11 | AH42 /PRO- - | Pi22/ aca | AHS AM1 BB42 0 292 |P102] AEg | ALiO | AJi2 | AJ39 GRAM vecio | - | Pi01 |vccio*| vecio* | vecio* | vecio* vecio | - | Pi21 |vccio*| vecio* | vecio* | vccio* vO 593 | Pi00 | ADio | Adit | AN11 | AK4O DONE 7 | P120 | AD3 | AH4 AJS Ay42 0 294 | Pog | AFO | AH12 | AKi2 | AG41 GND - | Pi19 | G@Np* | GND* | GND* | GND* 10 505 | : : ALi2 | Addi 0, G@CK4| 257 | P118 | ACS AJ4 AL4 | AW41 vO 706 | : : AMi2 | AH40 VO 258 | P1i17] AD4 | AK3 AJ6 AV40 GND - - - GND* | GND 1 GNb* vecint | - | Pi16 | AE3 [VCCINT*|VCCINT*|VCCINT* voclo |. - TyeeIo* | veo" - February 1, 1999 (Version 1.0) 6-249XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40110XV Pinout Table (Continued) XC40110XV Pinout Table (Continued) PAD EPIC PAD EPIC NAME. | PAD# HQ240| BG352 | BG432 | BG560 | PG559 NAME | PAD# HQ240| BG352 | BG432 | BG560 | PG559 VO 297 - - - AJ13 AG37 GND - P83 | GND* | GND* GND* GND* VO 298 - - - AK1i3 AG43 VO 337 - AE16 AH18 AK20 V38 VO 299 - - AK11 AL13 AG39 VO 338 - AE17 AL20 AN21 U39 VO 300 - - AJ12 AM13 AF38 VO 339 - AD16 AJ19 AL21 V42 VO 301 - AC11 AKi2 AN13 AF42 VO 340 - AC16 AK20 AJ20 R41 VO 302 - AE10 AL12 AJ14 AD42 VO 341 - - AH19 AM22 U43 VO 303 - AD11 AH13 AK14 AF40 VO 342 - - AJ20 AK21 P40 VO 304 - AE11 AJ13 AL14 AE37 VO 343 - - - AN23 T42 GND - P98 | GND* | GND* GND* GND* VO 344 - - - AL22 U37 vcclo - - veclo*) VCCcIOo* | VCCIO* | VCCIO* vceclo - - - vecio* | vCcio* | VCCIO* VO 305 - AF 11 AK1i3 AM14 AE39 GND - - - GND* GND* GND* VO 306 - AC12 AL13 AN15 AD40 VO 345 - - - AJ21 R39 VO 307 | P97 | AD12 AK14 AJ15 AC43 VO 346 - - - AM23 N41 VO 308 | P96 | AE12 AH14 AK15 AD38 VO 347 | P82 | AF18 AK21 AK22 R43 VO 309 | P95 | AF12 AJ14 AL15 AC41 VO 348 | P81 AE18 AH20 AM24 M40 VO 310 | P94 | AD13 AK15 AM16 AD36 vceclo - P80 | VCCIO*| VCCIO* | VCCIO* - VO 311 - - - - - VO 349 | P79 | AD17 AJ21 AL23 N39 VO 312 - - - - - VO 350 | P78 | AC17 AL22 AJ22 T36 GND - - - GND* GND* GND* VCCINT - P77 | AE19 |VCCINT*|VCCINT*| VCCINT* vcclo - - - veclo* | VCCIO* - VO 351 - - - - P42 VO 313 - - - - - VO 352 | P76 | AD18 AJ22 AK23 R37 VO 314 - - - - - GND - P75 | GND* | GND* GND* GND* VO 315 - - - AL16 AC39 vceclo - - - vocio* | VCCIO* - VO 316 - - - AJ16 AC37 VO 353 - AC18 AK23 AL24 L41 VO 317 - - AJ15 AKi6 AB40 VO 354 - AF20 AJ23 AN26 L43 VO 318 - - AL15 AN17 AB42 VO 355 | P74 | AE20 AH22 AJ23 K40 VCCINT - P93 | AC13 | VCCINT*|VCCINT*| VCCINT* VO 356 | P73 | AD19 AL24 AL25 K42 VO 319 - - - - AB38 VO 357 - - - AK24 L39 VO 320 | P92 | AE13 AL16 AL17 AA41 VO 358 - - - AM26 J43 GND - P91 GND* | GND* GND* GND* VO 359 - - - AM27 M38 vcclo - P90 |VCCIO*) VCCIO* | VCCIO* | VCCIO* VO 360 - - - AJ24 P36 VO (INIT)| 321 P89 | AF14 AKi6 AJ17 AA39 GND - - - GND* GND* GND* VO 322 | P88 | AE14 AJ16 AK17 AA37 vceclo - - veclo*| VCCcio* | VCCIO* | VCCIO* VO 323 - - AL17 AM18 Y40 VO 361 - - - AL26 N37 VO 324 - - AK17 AL18 Y38 VO 362 - - - AK25 H42 VO 325 - - - AK18 AA43 VO 363 - - AK24 AN28 J41 VO 326 - - - AJ18 W39 VO 364 - - AH23 AN29 G43 VO 327 - - - - - VO 365 | P72 | AC19 AJ24 AJ25 H40 VO 328 - - - - - VO 366 | P71 AF21 AK25 AL27 F42 vcclo - - - veclo* | VCCIO* - VO 367 | P70 | AE21 AJ25 AK26 J39 GND - - - GND* GND* GND* VO 368 | P69 | AD20 AH24 AM29 L37 VO 329 - - - - - GND - - GND* | GND* GND* GND* VO 330 - - - - - vceclo - - veclo*| VCCcio* | VCCIO* | VCCIO* VO 331 P87 | AD14 AJ17 AN19 v40 VO 369 - AF23 AL26 AM30 E41 VO 332 | P86 | AF15 AH17 AL19 Y36 VO 370 - AE22 AK26 AJ26 F40 VO 333 | P85 | AE15 AK18 AKi9 U41 VO 371 - AD21 AH25 AL28 C43 VO 334 | P84 | AD15 AL19 AM20 Y42 VO 372 - AC21 AL27 AK27 G39 VO 335 - AC15 AJ18 AJ19 T40 VO 373 - - AJ26 AL29 D42 VO 336 - AF16 AKi9 AL20 W37 VO 374 - - AK27 AN31 H38 vcclo - - veclo*) VCCcIOo* | VCCIO* | VCCIO* VO 375 - - - - - 6-250 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40110XV Pinout Table (Continued) XC40110XV Pinout Table (Continued) PAD | EPIC PAD | EPIC NAME. | pAD#|H@240| BG352 | BG432 | BG560 | PGS59 NAME. | PAD#|H@240| BG352| BG432 | BGS560 | PGS59 VO 376 | - - - - - 0 412] - - - AD30 H28 GND - - - GND* | GND* | GND* 0 413 | P47 | v23 | Ac28 | AES2 B34 vecio | - - - | vecio* | vccio* - 0 414 | Pas | wea | ace9 | Ac29 C31 /O 377 | - - - - - 0 4i5 | - w25 | AC30 | AE33 A33 /O 378 | - - - - - 0 416] - y26 | AB28 | AD31 D30 VO (V/LDC)| 379 | Pes | AE23 | AH26 | AJ27 K36 vecio | - - - | vecio* | vccio* - VO 380 | Pe7v | AD22 | AL28 | AMai1 J37 GND - | P45 | @np* | GND* | GND* | GND* /O 381 | Pes | AF24 | AJ27 | AK28 B42 /0, 417 | P44 | U23 | AB29 | AC30 E29 VO 382 | Pes | Ac22 | AK28 | AL30 D40 FOLK2 VO (HDC)| 383 | Ped | AD23 | AH27 | AK29 C41 VO 418 : : : : cag vO. GcK3} 384 | pes | AEDa | akoo | Asoa F3a vecint | - | P43 | v24a |VvcCCINT*|VCCINT*|VCCINT* (M2) ~ | pes | acea | agse | AN32 36 0 4i9 | P42 | v25 | AB3i | AB29 B30 vecio | - | Pei |vccio*| vecio* | vccio* | vccio* VO 420 | P4i | U2d | AA29 | ACSI G27 (MO) - | peo | Apea | AH28 | AJ29 G39 vecio | - | P40 |vccio*| vecio* | vecio* | vccio* GND - | P59 | GND* | GND* | GND* | GND* VO 421 : : AC33 D28 O (M1) - | P58 | AB23 | AH29 | AK30 D38 VO 422 : : AB30 A2g 0, GCK2| 385 | P57 | Ac24 | aAuso | AH29 E37 VO 423 | P39 | V26 | AA30 | AB31 E27 /O 386 | P56 | AD25 | AH30 | AJ30 B40 VO 424 | P38 | 123 Y28 AA29 F26 VCCINT | - P55 | AB24 [VCCINT*|VCCINT*|VCCINT* GND 7 7 : GND" | GND" | GND* vO 387 |. : : , 34 vecio | - - - | vecio* | vccio* - /O 388 | P54 | AA23 | AH31 | AH30 G35 VO 425 U25 Y29 AB32 C27 VO 389 - AC25 | AG29 | AL33 F36 ie) 426 " T24 30 AA30 B28 VO 390 - AD26 | AG30 | AG29 D36 VO 427 : Y31 AAS1 G25 vO 394 : : : 7 , 0 428] - - wee | AA32 A27 vO 392 |. : : , , 0 429] - - - Y29 D26 vecio | - - - vccio* | VCCIO* - VO 430 : : 7 AA33 B26 GND : : : GNp* | GND* | GND* 0 431 - T25 we29 Y30 E25 /O 393 | P53 | Ac26 | AF28 | A381 E35 VO 432 T26 Wws30 Y31 F24 VO 394 | P52 | y23 | AG31 | AK32 At GND - | P87 | GND" | GND* | GND" | GND* vO 395 |. : AF29 | AG30 G33 vecio | - - |vecio*| vecio* | vecio* | vccio* /O 396 - - AF380 | AH31 B38 VO 433 : : 7 : VO 397 . . . . . VO 434 - - - - - vO 308 |. : : , , 0 435 | - - ws 32 H24 /O 399 - AA24 | AE28 | AF29 D34 VO 436 : v28 weg B24 VO 400 - AB25 | AF31 AJ32 E33 VO 437 R23 v29 Ww30 D24 vecio | - - |vecio*| vecio* | vecio* | vccio* VO 438 R24 v30 ws A23 GND : - T@npb* | Gnp* | GND* | GND* 0 439 | P36 | R25 U29 Ww33 C23 VO 401 | P51 | AA25 | AE29 | AH32 F32 ie) 440 | P35 | R26 U28 V30 E23 VO 402 | P50 | y24 | AE30 | AF30 G3t GND 7 : GND* | GND" | GND* VO 403 | P49 | Y25 | AD28 | AG31 A37 veclo |_- : >| vecio* | vecio* : /O 404 | Pas | AA26 | AD29 | AEZ9 H30 VO 441 | P34 | Ped U30 ve9 G23 VO 405 |. : AD30 | AH33 B36 0 442 | P33 | P23 U31 v31 B22 /O 406 - - AD31 | AG33 C33 VO 443 : : v32 D22 /O 407 - - - AE30 C35 VO 444 : : U33 A21 VO 408 - - - AF31 D32 VO 445 : : 7 : vecio | - - |vecio*| vecio* | vecio* | vccio* VO 446 : : 7 : GND : : : GNp* | GND* | GND* 0 447 | P32 | P25 T29 U30 F22 VO 409 |. : : AD29 = 0 448 | P31 | N26 T30 U29 C21 vO aio! : : AF32 Gag vecio | - | P30 |vccio*| vecio* | vecio* | vccio* vO Ait : : : AESI A35 GND - | P29 | GND* | GND* | GND* | GND* February 1, 1999 (Version 1.0) 6-251XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40110XV Pinout Table (Continued) XC40110XV Pinout Table (Continued) PAD | EPIC PAD | EPIC NAME |paps#|4@240| BG352 | BG432 | BG560 | Pas59 NAME |pAps#|4@240/ BG352| BG432 | Ba560 | Pas59 VO 449 | P28 | N25 T31 U31 E21 0 487 | Pi1 | F26 - K29 E11 VO 450 | - - - - D20 0 488 | Pi0 | F25 - H31 G13 vecint | - | P27 | Nea [VCCINT*|VCCINT*|VCCINT* GND - - - GND* | GND* | GND* VO 451 - - - - - vecio | - - [vecio*| vecio* | vecio* | vecio* VO 452 | - - - - - 0 489 | P9 | Go4 H30 J30 Fi2 VO 453 [| - - - T32 C17 0 490 | Ps | p26 G30 G32 H14 VO 454 [ - - - T30 Get 0 491 - - H29 F33 Git VO 455 | P26 | M2e | Res T29 F20 0 492 | - - H28 J29 A7 VO 456 | P25 | M25 | R30 T31 D18 0 493 | - - F31 G31 E9 vecio | - - - | vecio* | vecio* - 0 494 [ - - F30 H30 B6 GND - - - GND* | GND* | GND* 0 495 | - - - E33 D8 VO 457 | Pea | Mea | R31 R33 E19 0 496 | - - - E32 F8 VO 458 | P23 | M23 P29 R31 B20 GND - - | @Nd* | GND* | GND* | GND* VO 459 | - L26 P28 R30 H20 vecio | - - [vecio*| vecio* | vecio* | vecio* VO 460 | - L25 P30 R29 B18 0 497 | - E25 G29 H29 Gg VO 461 - - N30 P32 C15 0 498 | - F24 G28 F31 H10 VO 462 [| - - N29 P31 D16 0 499 | - F23 E31 G30 B4 VO 463 | - - - - - 0 500 | - D25 E30 p32 E7 VO 464 | - - - - - 0 501 - - F29 E31 C5 vecio | - - [vecio*| vecio* | vecio* | vecio* 0 502 | - - F28 G29 D GND - | p22 | @np* | GND* | GND* | GND* 0 503 | - - - - - VO 465 | - K25 N28 N33 Gi9 0 504 [| - - - - - VO 466 | - L24 N31 P30 A17 GND - - - GND* | GND* | GND* VO 467 | - L23 M31 P29 Fis vecio | - - - | vecio* | vecio* - VO 468 | - J26 M29 M32 E17 0 505 | - - - - - VO 469 | - - - N31 B16 0 506 | - - - - - VO 470 | - - - N30 C13 VO (TCK)| 507 | P7 | E24 D31 C33 D4 VO 471 - - M28 L33 A15 vO (TDI) | 508 | Pe | C26 D30 F30 H8 VO 472 | - - M30 N29 D14 0 509 | P5 | 23 E29 D31 A3 vecio | - - - | vecio* | vecio* - 0 510 | - - - - F6 GND - - - GND* | GND* | GND* VCCINT | - P4 | D24 |VCCINT*|VCCINT*|VCCINT* VO 473 | P21 | J25 L30 M31 E15 VO (A17)| 511 | P38 | C25 C30 F29 C3 VO 474 | P20 | K24 L29 L32 G17 0,GCK1] 512 | P2 | D23 p29 B33 C1 VO 475 | - - - M30 B14 (A16) VO 476 |. : : 131 Cit GND - Pi | GND* | GND* | GND* | GND* vecio | - | P19 |vecio*| vecio* | vecio* | vccio* veclo | - A10 Al A4 Al3 VO 477 | Pigs | K23 K31 M29 D12 veclo | - Al? All A10 A31 VO (TMs)| 478 | P17 | H25 K30 J33 Alt veclo | - 7 | Aca | At Al6 A43 vecint | - | Pie | J24 [VCCINT*|VCCINT*|VCCINT* veclo | - 7 | Ac20 | A381 A22 B2 VO 470 | : : : E13 vecio | - - AC8 D1 A26 C7 0, 480 | Pi5 | J23 K28 L30 cg veclo | - 7 | AFIO | Dat A30 C19 FCLK1 vecio | - - | AFI7 Li B2 C25 GND - | Pia | @np* | GND* | GND* | GND* vecio | - - D7 L4 B13 C87 vecio | - - - | vecio* | vecio* - vecio | - - D13 L28 B19 F14 VO 481 - G26 J30 K31 H16 vecio | - - D19 L31 B32 F30 VO 482 [| - G25 H31 L29 B10 vecio | - - @23 | AAI C3 G3 VO 483 | P13 | H24 J29 H33 Gi5 vecio | - - H4 AA4 C31 G7 VO 484 | Pi2 | H23 J28 K30 AQ vecio | - - Ki AA28 C32 G37 VO 485 | - - - J31 D10 vecio | - - K26 | AAS1 D1 Gat VO 486 | - - - H32 BS vecio | - - N23 | AH11 D33 Nt 6-252 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40110XV Pinout Table (Continued) XC40110XV Pinout Table (Continued) PAD EPIC PAD EPIC NAME. | PAD# HQ240| BG352 | BG432 | BG560 | PG559 NAME | PAD# HQ240| BG352 | BG432 | BG560 | PG559 vcclo - - P4 AH21 E5 N43 GND - - A2 AQ A18 A39 vcclo - - U4 ALi H1 P6 GND - - A22 Al4 A20 B12 vcclo - - U26 AL11 K33 P38 GND - - A25 A18 A24 B32 vcclo - - We23 AL21 M1 W3 GND - - A26 A23 A29 E1 vcclo - - Y4 AL31 N32 w41 GND - - Ad A25 A832 E5 vcclo - - B2 c3 R2 AE3 GND - - A8 A29 Bi E39 vcclo - - B25 C29 T33 AE41 GND - - AB1 A30 B6 E43 vcclo - - AE2 AJ3 v1 AK6 GND - - AB26 Bi B9 F10 vcclo - - AE25 AJ29 W32 AK38 GND - - AE1 B2 B15 Fi6 vcclo - - - - AA2 AL1 GND - - AE26 B30 B23 F28 vcclo - - - - AB33 AL43 GND - - AF1 B31 B27 F34 vcclo - - - - AD1 AU3 GND - - AF13 C1 B31 H22 vcclo - - - - AF33 AU7 GND - - AF19 C31 c2 K6 vcclo - - - - AK1 AU37 GND - - AF2 D16 E1 K38 vcclo - - - - AK4 AU41 GND - - AF22 G1 F32 M2 vcclo - - - - AK33 AV14 GND - - AF25 G31 G2 M42 vcclo - - - - AL2 AV30 GND - - AF26 J1 G33 T6 vcclo - - - - AL3 BA7 GND - - AF5 J31 J32 T38 vcclo - - - - AL31 BA19 GND - - AF8 P1 K1 wi vcclo - - - - AM2 BA25 GND - - Bi P31 L2 W43 vcclo - - - - AM15 BA37 GND - - B26 T4 M33 AB8 vcclo - - - - AM21 BC1 GND - - E1 T28 P1 AB36 vcclo - - - - AM32 BC13 GND - - E26 v1 P33 AE1 vcclo - - - - AN4 BC31 GND - - H1 V31 R32 AE43 vcclo - - - - AN8 BC43 GND - - H26 ACI T1 AH6 vcclo - - - - AN12 - GND - - N1 AC31 V33 AH38 vcclo - - - - AN18 - GND - - P26 AE1 We AM2 vcclo - - - - AN24 - GND - - wi AE31 Y1 AM42 vcclo - - - - AN30 - GND - - W26 AH16 Y33 AP6 GND - - - AJ AB1 AP38 VCCINT - - - A10 E12 H12 GND - - - AJ31 AC32 AT22 VCCINT - - - AB2 AD2 H18 GND - - - AK1 AD33 AV10 VCCINT - - - AB30 AD32 H26 GND - - - AK2 AE2 AV16 VCCINT - - - AG28 AK31 H32 GND - - - AK30 AGI AV28 VCCINT - - - AH15 AM17 M8 GND - - - AK31 AG32 AV34 VCCINT - - - AH5 AK5 M36 GND - - - AL2 AH2 AW1 VCCINT - - - AJ10 AK11 V8 GND - - - AL3 AJ33 AW5 VCCINT - - - AK22 AN25 V36 GND - - - AL7 AL32 AW39 VCCINT - - - B23 C24 AF8 GND - - - ALY AM3 AW43 VCCINT - - - B4 D6 AF36 GND - - - AL14 AM11 BB12 VCCINT - - - C16 C17 AM8 GND - - - AL18 AM19 BB32 VCCINT - - - E28 E30 AM36 GND - - - AL23 AM25 BC5 VCCINT - - - K29 K32 AT12 GND - - - AL25 AM28 BC19 VCCINT - - - K3 J1 AT18 GND - - - AL29 AM33 BC25 VCCINT - - - R2 T3 AT26 GND - - - AL30 AM7 BC39 VCCINT - - - R29 U32 AT32 GND - - - - AN2 - GND - - - - AN5 - GND - - Al A2 A7 Ad GND - - - - AN10 - GND - - Al4 A3 Al2 A19 GND - - - - AN14 - GND - - A19 A7 Al4 A25 GND - - - - AN16 - February 1, 1999 (Version 1.0) 6-253XC4000XLA/XV Field Programmable Gate Arrays >: XILINX XC40110XV Pinout Table (Continued) PAD EPIC NAME. | PAD# HQ240| BG352 | BG432 | BG560 | PG559 GND AN20 GND AN22 GND AN27 NC - P204 c8 c8 Al NC - P219 A33 NC AC2 NC AN1 NC AN33 6-254 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40150XV Pinout Table (Continued) XC40150XV Pinout Table EPIC PAD NAME | pan ,|H@240| BG352 | BG432 | BG560 | PG559 PAD NAME oa Ha240| BG352 | BG432 | BG560 | PGS559 fe) 44 - - - D22 T4 GND - - - GND* | GND* | GND* Vcclo - | P2ao | vecio] vecio* | vccio | vccio* YOu yooior | vooIo VO, GCK8 (A15)| 1 Pe39 | C24 D28 E29 E3 7a z - - - /O (A14) 2 | pess | D202 C28 D30 F4 70 6 VO 3 | P237 | C23 B29 E28 J7 - - - - - VO 47 - - - C22 U5 VO 4 | pe3e | Bea D27 D29 D2 70 me = YD VO 5 | p235 | cee B28 C30 K8 - - - VO 49 - - D20 B22 U7 VO 6 | pesa | Det C27 D28 H6 70 ; VO 50 - - B21 D214 U3 7 5 VO 51 - A18 C20 cat Y2 VO 52 - D16 B20 B21 v4 VCclo - - - vecio* | vccio* - VO 53 - B17 A20 E20 V6 GND - - - GND* | GND* | GND* 70 5 VO 54 - C16 D19 A2t W5 1 0 GND - - GND* | GND* | GND* | GND* 70 7 vcclo - - |vecio*] vecio* | vecio | vecio* 70 3 /O (A11) 55 | Peet | Bie C19 D20 W7 /O (A10) 56 | P220 | at B19 C20 v4 vo 18 - - p26 Ast os /0 57 | Peis | Dis Ai9 B20 AAI VO 14 - - A28 E27 F2 VO 58 | P2i7 | C15 Bis E19 Y6 vo 6 - Bes Be7 ce8 He VO (A18 59 | Pete | B15 D18 D19 AB2 VO 16 - A24 C26 B30 at (A18) /O (A19) 60 | P2i5 | A15 C18 C19 Y8 VO 17 - A23 D25 D27 J5 10 7 VO 18 - D20 A27 C28 L7 70 = - - - - - vcclo - - |vecio*] vecio* | vecio | vccio* 70 3 - - - - - GND - - GND* | GND* GND* GND* 70 aa - - - - - /0 (A13) 19 | p233 | cet B26 E26 J3 Sno Snow GND PGND 0 (A12) 20 | p232 | Bee p24 B29 KA - - - vcclo - - - vecio* | vccio* - VO 21 | pest | Bet C25 B28 H2 70 xs VO 22 | P230 | c20 A26 D26 L5 - - - - - VO 66 - - - - - VO 23 - - B25 C27 Jt 70 a A AAS VO 24 - - D23 E25 M6 - - - VO 68 - - - D18 AA5 vo 2 - - - A28 Ke /0 69 BI7 E18 ACT VO 26 - - - A27 N7 - - VO 70 - - C17 C18 AAT VO 27 - - - - - 70 58 /O (AQ) 71 | Peta | c14 A17 Bis AB4 /O (A8) 72 | P2is | D14 D17 A17 AB6 vcclo - - |vecio*] vecio* | vecio | vccio* vcclo - | P2t2 | vcecio*| vecio* | vccio* | vccio* GND - - - GND* | GND* | GND* GND - | Pett | @np* | a@nD* | GND* | GND* VO 29 - - - D25 P38 VO (A7) 73 | Peto | Bi4 At6 D17 AC3 VO 30 - - - C26 L3 /O (A6) 74 | P209 | Ai3 B16 E17 AC5 VO 31 - - - E24 1 VCCINT - - - VCCINT* | VCCINT* | VCCINT* VO 32 - - - B26 M4 7 = ADD VO 33 | P229 | B20 C24 C25 P2 - - - - VO 76 - - A15 B17 AC7 VO 34 | P228 | aot B24 p24 N5 70 = S16 AD VO 35 - D18 C23 B25 Rt - - - VO 78 - - - D16 AD4 VO 36 - C19 D22 E23 N3 VO 79 - - - - - vcclo - - - vecio* | vccio* - 70 30 GND - | P227 | G@ND* | GND* | GND* | GND* VOuIO - - VOOIO YOOIO - VO 37 | p226 | Big A24 A25 R7 - - - - GND - - - GND* | GND* | GND* VO 38 - - - - P4 70 3 VCCINT - P225 | A20_ | VCCINT*| VCCINT* | VCCINT* 70 a - - - - - VO 39 | Pe24 | DI7 C22 D23 T2 70 35 - - - - - VO 40 | P223 ] cts B22 B24 T8 70 aa - - - - - vcclo - P222 | vecio*| vecio* | vecio* | vccio* 7 ana 35 5D08 313 a6 a6 ADS VO 41 - Bis A22 E22 R5 (A20) /O (A21) se | P207 | C13 C15 C16 AE5 vo - ad cai 028 RS VO 87 | P206 | At2 D15 A15 AF4 VO 43 - - - A23 Ut VO gs | P205 | B12 B14 C15 AG1 February 1, 1999 (Version 1.0) 6-255XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40150XV Pinout Table (Continued) XC40150XV Pinout Table (Continued) PAD NAME oa Ha240| BG352 | BG432 | Baseo | PGs59 PAD NAME oa Ha240| BG352 | BG432 | Baseo | Passo 1/0 (A5) g9 | P203 | Cte Ai3 D15 AD8 0 132 - C5 B5 Ba AT6 1/0 (AA) 90 | P202 | Diz C14 E15 AG3 V0 133 - - - - - VCCIO - - |vecio*| vecios | vecio* | vccio* V0 134 - - - - - GND - - GND* | GND* | GND* | GND* V0 135 - - - - - V0 91 - Ait B13 B14 AH4 V0 136 - - - - - V0 92 - Bit D14 C14 AE7 GND - - - GND* | GND* | GND* V0 93 - B10 Ai2 Di4 AH2 VCCIO - - - vocio* | VCCIO* - V0 94 - C11 C13 Ai3 AF6 V0 137 - - - - - V0 95 - - Bt2 E14 Ast V0 138 - - - - - V0 96 - - D13 C13 AGS V0 139 - - D C5 AP8 V0 97 - - - DI3 AJB V0 140 - - A4 E7 AR7 V0 98 - - - Bt2 AK4 V0 141 - - C5 A3 AY4 V0 99 - - - - - V0 j42 | Pise | a3 - - BB2 V0 400 - - - - - VGCINT - | P185 | DS | vCCINT*| VCCINT* | VCCINT* VCCIO - - - vecio* | vCCIo* - VO, GCK7 (A1)| 143 | P184 | C4 DS A2 AV6 GND - - - GND* | GND* | GND* vO (AO, ws) | 144 | P183 | B3 B3 DS AT8 V0 101 - - - C12 AG7 GND - | pts2 | @np* | G@ND* | GND* | GND* 0 102 - - - E13 AK2 0, TDO - | Prat | 4 C4 E6 BA3 V0 403 Dit C12 Ait AJ5 VCCIO - | P180 - voecio* | vccio* | vCcIO* 0 404 Ag Bit Di2 AL3 CCLK - | Piva | c3 D4 C4 BAS VCCIO - | p201 | vccio*| vecio* | vccio* | vccio* vo,qcke | 145 | Piva | E4 D3 D4 BB4 /0 405 | P200 | Bo D12 Btt AM4 (DOUT) 10 toe | Piso | G10 Ci Ci ANT VO (DO, DIN) | 146 | Pizz | D3 C2 E4 AY6 VCCINT - | P198 | Dio | VCCINT*| VCCINT* | VCCINT* vO 147 | Piv6 | C2 be FS BC3 10 i07 - - - - ALE V0 44g | P175 | E83 E4 B3 AW7 /0 jos | Pto7 | Bs B10 B10 AH8 vO 149 : F4 D1 D3 BB6 GND T piss | onp= | anp= 1 anp 1 GND* V0 150 - D2 E3 F4 AUS VCCIO - - - veclo | vccio* - vO 154 : : : : : /0 409 - C9 C10 Dit AJ7 vO 152 : : : : : /0 410 | Pi95 | De Bg C10 AP2 Veclo : : : Veclo* | VCCIO" : /0 411 | Pisa | a7 C9 AQ AN3 GND : : : GND" | GND" | GND* /0 112 | Pi93 | B7 D190 Ett AP4 vO 153 : : : : : /0 113 - - - ca ARI vO 154 : : : : : 10 ta - - - Dio ANS V0 155 - - E2 Ci AT10 10 115 - - - Ae AMe V0 156 - - F4 G5 AV8 10 16 - - - Be AKS V0 157 - Ci Et E3 AY8 GND - - - GND* | GND) GND* V0 158 - Di F3 D2 BC7 VCCIO - - |vecio*| vecio* | vccio* | vccio* vO 159 : : : : : VO 117 - - - - - ie) 160 7 7 7 7 7 10 i8 - - - - - vOURCK, | 161 | Pi74| G4 Fe G4 AWS 0 119 E10 AL7 RDY_/BUSY) - - - 0 (D1) 162 | P173 F3 G4 F3 BAQ V0 120 - - - C8 AT2 0 oy A 55 ARS VCCIO - - - voecio* | vccio* | vCcIO* - - GND - - - GND* GND* | GND* V0 422 - - B8 B7 AU /0 423 | Pig2 | Ds De AG AT4 vo 168 - - - - - V0 164 - - - - - V0 424 | Piot | AG B7 EQ AV2 /0 425 | Pi90 | Be C7 C7 AR5 vo 168 - - A Hs AUN V0 166 - - G3 E2 AY10 V0 426 | Pisa | C7 D8 D8 AN7 GND GND* | GND* | GND* | GND* vo 167 - - Ge re BBS - - VO 168 - - H4 H4 AW11 VCCIO - - |vecio*| vecios | vecio* | vccio* O 7H Ma tS A AWS V0 469 | Pi72 | E2 H3 G3 BCg : V0 170 | Pivi | Fe H2 5 AVI2 V0 128 - B5 B6 B5 AV4 0 (A3 429 | Pisa | ce D7 E8 BAT vo ii | Pi70 | G8 - A Avis (A3) V0 172 | Pies | G2 - Gt AT14 1/0, 430 | P1s7 | De AS C6 AUS (C81, A2) VCCIO - - - voecio* | vccio* | vCcIO* 0 iat | - B4 C6 D7 AY2 GND : : : GND" | GND" | GND" 6-256 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40150XV Pinout Table (Continued) XC40150XV Pinout Table (Continued) PAD NAME oa Ha240| BG352 | BG432 | Baseo | PGs59 PAD NAME oa Ha240| BG352 | BG432 | Baseo | Passo 0 73] , , 4 BATT VocIO - | piso} - | vocio* | vocio* | vocior 10 174) : : H3 AY12 10 at7 | P14a | Pt T2 ua | Awe3 10 17 | : : K5 BBIO /0 (D4) ate | Pi4a | Pe TH US AY24 10 176} : : He AW13 10 ato | : : : : 10 177 | Pies | FA Hi 3 BOT 10 220 | - : : : : 10 178 | Piev7 | JA J4 K4 AUIS 10 aor | : : U4 BC23 10 17} H3 3 Je BBI4 10 222 | - : : U2 BA27 10 10 | - He Je L5 ATI6 10 203 | Pi47 | P3 U3 v2 Au23 VocIO : : - | vecio* | vocio* : 10 2o4 | Pi46 | RI U4 v4 AV24 GND - | pies | GND* | GND* | GNo* | GND* VocIO : : - | vecio* | vocio* : 10 tei | Pies | Gt K4 K3 BATS GND : : : GND* | GND* | GND* 10 12 | : : : AYI4 10 205 | P145 | Re U2 V5 AY26 VCCINT - | piea | Ka | VOcINT*| VocINT* | VCCINT* 10 206 | P144 | RS U4 V3 BB24 0, FCLK4 | 183 | Pi63 | J3 Ke L4 BO15 10 207 | Ra V3 wi AW25 10 184 | Pie2 | ue KA Ke AW15 10 208 | TH v4 W3 BB26 vocio - | Piet |vocio*| vocio* | vecio* | vecio* 0 220 | . v2 wa AT24 10 15 | : : M5 BAIS 10 230 | - : we ws BaZa 0 186 | - . . L3 AUI7 0 ast | . . . . 10 187 | Pieo | KS (3 1 BBI6 10 232 | - : : : : /0 (D2) a8 | Piso | ut la M4 AY16 0 233 | . . . . GND : : : GND* | GND* | GND* 10 234 | - : : : : VocIO : : - | vecio* | vocio* : VocIO : - | vecio*| vocio* | vecio* | vecio* 10 tao | : M4 ma | AW17 GND - | p143 | GND* | GND* | GND* | GND* 10 too | - : Ma NS AVI8 10 235 | T2 W3 Y2 AY28 10 for | : : Ma BAI7 10 236 | U2 wa Y3 AU25 10 to2 | - : : N4 BOI7 10 237 | : : v4 AV26 10 toa | : : : : 10 236 | : : AAT BC27 10 toa | : : : : 10 230 | : : : : 10 tos | L4 Ma NB AUI9 10 240 | - : : : : 10 too | Ke Mt No BBIE 10 at | : wi Y5 AW27 10 to7 | - (3 Na PS AY18 10 242 | - : v4 AAS | BB28 10 to | (2 NB NA AW19 10 243 | T3 Y3 aA4 | BASH GND - | piss | GND* | GND* | GNo* | GND* 10 aa | T4 v4 AB | AY30 VocIO : - | vecio*| vocio* | vocio* | vocio* VocIO : : - | vecio* | vocio* | vecio* 10 too | : : : : GND : : : GND* | GND* | GND* 10 200 | - : : : : Oo eso) | 245 | Piao | vi Y2 ABs | Aw29 10 201 | - : : : : /0 (D8) 246 | Piai | ve AA2 AAS | BC29 10 202 | - : : : : 10 247 | : : aci | Aue7 10 203 | - : N2 P4 AV20 10 Cn : : AB4 | BASS 10 204 | - : Ni P3 AT20 VocIO - | p140 | vocio*| vocio* | vecio* | vecio* 0 205 | - 4 P4 Pe BB20 0 249 | P1390 | U3 AAS aca. | AY32 10 206 | - M4 P3 RS AY20 0, FCLK3 | 250 | Pi3e | U4 ABI ABs | AWS31 0 207 | P1s7 | M3 Pe R4 BC? VCCINT - | pia7 | we | vocint*|vocint | vocinT* 10 208 | P1se | M2 R3 R3 BA2t 10 251 | : : : BB3O GND : : : GND* | GND* | GND* 10 252 | Pise | V3 ABS aca | BASS VocIO : : - | vecio* | vocio* : GND - | pias | GND* | GND* | GND* | GND* 10 209 | P15 | M1 Ra Ri AW21 VocIO : : - | vecio* | vocio* : 10 ato | - : : T4 Aut 10 253 | v4 AB4 aD3 | AT28 10 am |. : : T5 BB22 10 254 | v4 Ace AE! | AU29 10 ate | - : : : AY22 10 255 | Pisa | Ye AD1 acs | BC33 10 aia | : : : : 10 256 | P1a3 | wa AC3 AES | AY34 10 ata | - : : : : 10 257 | : : aD4 | BB34 VCCINT - | Pisa | Na | VCCINT*| VCCINT* | VCCINT* 10 258 | : : AF1 | AW33 OURS) | 215 | P1s3 | Na Ri T2 AV22 10 259 | - : : Aro | AUS /0 (D3) at6 | p1s2 | Ne T3 U3 BA23 10 260 | - : : aps | AV32 GND - | Pit : GND* | GND* | GND* GND : : : GND* | GND* | GND* February 1, 1999 (Version 1.0) 6-257XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40150XV Pinout Table (Continued) XC40150XV Pinout Table (Continued) PAD NAME oa Ha240| BG352 | BG432 | Baseo | PGs59 PAD NAME oa Ha240| BG352 | BG432 | Baseo | Passo VCCIO : - | vecio*| vecios | vecio* | vecio* V0 305 | - ac7 | ALS AL6 | AR3O V0 zor | - : : : : V0 306 | - ape | AK6 Aus | AN37 V0 262 | - : : : : VCCIO : - | vecio| vecios | vecio* | vecio* V0 263 | : : Ace | AT30 GND : - | @np* | GND* | GND* | GND* V0 264 | - : : AE4 | AU33 V0 307 | Pit2 | Acs | AH8 ame | AT40 V0 265 | : ACA ars | AW35 V0 308 | Pii1 | Ace | Adv AN6 | AP40 V0 266 | - : AD2 AHA BC35 V0 309 | Pii0 | abv | Ale aks | AR43 V0 267 | Pise | wa AE2 AES | AY36 V0 310 | Piog | AE7 | AK7 AL7 | AN39 V0 268 | Pist | AAt AD3 aG3 | BB36 V0 ait | : AHS Aus | AP4e V0 269 | Piz0 | Aa2 | AD4 ara | Av36 V0 aie | - : AJB AN7 | AM38 1/0 (D6) 270 | Pie9 | 3 AFI At AU35 V0 aia | - : : Ale | AN43 GND : : : GND* | GND* | GND* V0 aia | - : : akg | AL37 VCCIO : : - | vecio* | vecio* | vecio V0 ais | - : : : : V0 at | ACt AF2 Ale | AT34 V0 aie | - : : : : V0 ae | - AB2 | AES ars | AW37 VCCIO : - | vecio| vecios | vecio* | vecio* V0 ama | : : : : GND : : : GND* | GND* | GND* V0 ava | : : : : V0 ai7 | : : ams | AK36 V0 275 | : : : : V0 aia | - : : Asio. | AR4 V0 276 | : : : : V0 aio | - : : Als | AL4t V0 a7 | : AE4 AH3 | BC37 V0 320 | - : : amo | AN41 V0 27a | : AGI aaa | Ay38 V0 321 | Pios | are | AKa | AKio | AK2 V0 279 | Pies | Aas | AGe Ake | BB38 V0 322 | Pioy | aca | Ads aN | AM4o V0 280 | Piey | Aad | AFS aus | BA4t V0 303 | - aps | AHto | Auit | AJ43 GND : : : GND* | GND* | GND* V0 304 | - AES | ALS ALio | AJ37 VCCIO : : - | vecio* | vecio* : VCCIO : : - | vecio* | vocio : V0 zat | - : : : : GND - | pioe | GND* | G@ND* | GND* | GND* V0 282 | - : : : : V0 325 | Pios | aF7 | AKo | AMto | AL39 V0 283 | ace | AF4 aas | ayaa V0 326 | - : : : AH36 V0 284 | - ABS | AHA AL BB40 VCCINT - [| Pioa | acio |vocint*| vCcINT* | VCCINT* V0 286 | Pi26 | ADI AH2 AH4 | AT36 V0 327 | Pio3 | ADs | AKio | ALIt | AH42 V0 286 | Pies | AB4 | aG3 AK3 | BA3O V0 328 | Pio2 | Aco | aLio | Avie | Ado v0,GcKs | 287 | Pi2ea | aca | aca Al4 | Av38 VCCIO - | Pto1 | vocio*| voecio* | vecio* | vecio* 0 (D7) 288 | Pi23 | ADe | Ale AHS | BC41 V0 320 | Pico | ADIO | Aditi | ANi1 | AK4o PROGRAM | - | Ptee | Ac4 | AH3 ami | BB42 V0 330 | poo | aro | Anta | aki2 | aqat VCCIO - | Piet | vocio*| vecios | vocio* | vecio* V0 sat | : : Alia | Aldi DONE - | Pi20 | aD3 | AH4 Als | Avae V0 332 | - : : AMi2 | AH4o GND - | pita | @Np* | @ND* | GND* | GND* GND : : : GND* | GND* | GND* v0,ack4 | 289 | Piia | acs | Ala Ala | Awat VCCIO : : - | vecio* | vocio : V0 290 | Pii7 | AD4 | AK3 Ase. | Avao V0 333 | : : : : VCCINT - | pite | AES | VCCINT* | VCCINT* | VCCINT* V0 aaa | : : : : V0 aot | - : : : Avae V0 335 | : : Asia | AG37 V0 292 | Piis | ADS | AKA ANS | AR37 V0 336 | - : : AKi3 | AG43 V0 293 | : Als AK | AP36 V0 aa7 | : aki1 | Aliza | AG39 V0 204 | : AH6 ALS | AT38 V0 338 | - : ali2 | AMt3 | AF38 V0 295 | : : : : V0 ago | - | Acit | akt2 | ANi3 | ArFae V0 296 | : : : : V0 340 | - | acio | alia | asta | Apae VCCIO : : - | vecio* | vecio* : V0 a4t | - | adit | Ania | aki4 | AFao GND : : : GND* | GND* | GND* V0 a42 | - | acit | auia | ALi4 | AES7 V0 297 | : : : : GND - | pgs | GND* | G@ND* | GND* | GND* V0 298 | : : : : VCCIO : - | vecio| vecios | vecio* | vecio* V0 299 | : : : : V0 343 | - | arti | akia | amta | AESo V0 300 | - : : : : V0 34a | - | Aci2 | alia | aNis | AD40 V0 zor | - ace | Al4 Al7 | AU39 V0 345 | pov | ADi2 | aKkia | Auts | Aca3 V0 302 | - AE4 | AKS ama | Au43 V0 346 | pos | Acie | AHi4 | AKi5 | AD38 V0 303 | Pii4 | ars | Ade ams | BA43 V0 347 | pos | arte | auia | ALis | Aca V0 304 | P1i3 | ara | AH AK? | AT42 V0 34s | poa | ADIs | aKis | Amie | AD36 6-258 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40150XV Pinout Table (Continued) XC40150XV Pinout Table (Continued) PAD NAME oa Ha240| BG352 | BG432 | Baseo | PGs59 PAD NAME oa Ha240| BG352 | BG432 | Baseo | Passo V0 a4o | : : : : V0 393 | p7s | ADi7 | Avot | Ales | N39 V0 350 | - : : : : V0 304 | pv | Aci7 | alee | Adee T36 V0 ast | : : : : VCCINT - | P77 | AEI9 | vocinT* | VCCINT* | VCCINT* V0 352 | - : : : : V0 305 | - : : : P42 GND : : : GND* | GND* | GND* V0 306 | pve | ADIs | AJe2 | akes | R37 VCCIO : : - | vecio* | vecio* : GND - | p75 | GND* | G@ND* | GND* | GND* V0 353 | : : : : VCCIO : : - | vecio* | vocio : V0 354 | : : : : V0 3o7 | - | Acia | akea | Alea Lat V0 355 | : : ALie | acae V0 308 | - | areo | Ades | ANoe 143 V0 356 | : : Asi6 | AC37 V0 390 | p74 | ac20 | AHe2 | Aes K40 V0 357 | : Allis | Akie | ABdo V0 400 | p73 | ADio | ale4 | Ales Kae V0 358 | : ALis | ANi7 | AB2 V0 aor | - : : AK24 [39 VCCINT - | ps3 | aci3 | vccint | VCCINT* | VCCINT* V0 4o2 | - : : aM26 | J43 V0 359 | : : : AB38 V0 403 | - : : aMe7 | M38 V0 360 | poe | acta | alie | ALi7 | Aaat V0 404 | - : : AJ24 P36 GND - | pot | @No* | @ND* | GND* | GND GND : : : GND* | GND* | GND* VCCIO - | ps0 |vocio*| vecio* | vecio* | vecio* VCCIO : - | vecio| vecios | vecio* | vecio* vont) | 361 | pss | AFi4 | AKkie | adi7 | AAgO V0 405 | - : : : : V0 362 | pas | Acta | Adie | AKi7 | AAS7 V0 406 | - : : : : V0 363 | - : ALi7 | AMia | Y4o V0 4o7 | - : : Ales | Nav V0 364 | - : AKi7 | Alta | 38 V0 408 | - : : akes | H42 V0 365 | : : AKi8 | AA43 V0 4oo | - : Ake4 | AN28 Jat V0 366 | - : : Asia | W39 V0 aio | - : AHe3 | AN2a | G43 V0 367 | - : : : : V0 ait | p72 | acia | auea | Ales H40 V0 368 | : : : : V0 ai2 | p71 | arei | akes | AL27 F42 VCCIO : : - | vecio* | vecio* : V0 413 | p7o | Acet | Ades | AKo6 39 GND : : : GND* | GND* | GND* V0 4i4 | pes | AD20 | AH24 | Ameo | Lav V0 360 | : : : : GND : - | @np* | GND* | GND* | GND* V0 370 | - : : : : VCCIO : - | vecio| vecios | vecio* | vecio* V0 at | : : : : V0 ais | - | area | ales | amso | cat V0 a2. : : : : V0 416 | - | ace2 | ako | Auoe F40 V0 373 | pay | ADi4 | Adi7 | aANig | vao V0 ai7 | - | Avet | Anes | Ales | ca3 V0 37a | pas | arts | AHi7 | ALia | Y36 V0 ais | - | acet | alev | ake7 | Gao V0 375 | pas | AEts | AKta | AKig | Udi V0 aio | - : alee | AL29 D42 V0 376 | paa4 | ADIs | aLig | Ameo | Yaa V0 420 | - : Ake7 | ANS1 H38 V0 a77 | - | acts | asia | Asta T40 V0 aot | - : : : : V0 ava | - | arte | Akio | Aleo | wav V0 422 | - : : : : VCCIO : - | vecio| vecios | vecio* | vecio* V0 423 | - : : : : GND - | pas | GND* | GND* | GND* | GND V0 424 | - : : : : V0 37a | - | acte | AHia | AKeo | v38 GND : : : GND* | GND* | GND* V0 380 | - | AEt17 | al2o | ANet U39 VCCIO : : - | vecio* | vecio* : V0 aet | - | Adie | aio | Aled v2 V0 425 | - : : : : V0 382 | - | Acie | AKeo | AJeo R41 V0 426 | - : : : : V0 383 | : Ania | AM22 | U43 voulpc) | 427 | Pes | AEe3 | Anes | Aue7 K36 V0 384. : Al20 | AKet P40 V0 428 | pev | AD22 | ales | AM31 J37 V0 385 | : : AN23 | 142 V0 429 | pes | area | Alev | AKes B42 V0 386 | - : : AL22 U37 V0 430 | pes | Ace2 | akes | ALSO D40 V0 387 | : : : : vO(HDc) | 431 | pea | abe3 | AHe7 | Akeo | cat V0 388 | : : : : 0,GcK3 | 432 | pes | Acea | Akeo | Aves F38 VCCIO : : - | vecio* | vecio* | vecio (M2) - | Pe2 | aces | Aves | AN32 | H36 GND : : : GND* | GND* | GND* VCCIO - | Pet |vocio*| vocio* | vocio* | vocio* V0 389 | : : Adet R39 (Mo) - | Peo | abea | anes | Adag C39 V0 300 | - : : aMe3 | N41 GND - | ps9 | GND* | G@ND* | GND* | GND* V0 aot | pae | arte | AKo1 | akee | R43 O (M1) - | pss | ABe3 | Ades | AK30 | 038 V0 392 | pai | acta | AH20 | AMea | Mao v0,acke | 433 | ps7 | acea | asso | AH2o | E37 VCCIO - | Pao |vocio*| vocio* | vocio* : V0 434 | ps6 | AD25 | AH30 | AJ30 B40 February 1, 1999 (Version 1.0) 6-259XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40150XV Pinout Table (Continued) XC40150XV Pinout Table (Continued) PAD NAME oa Ha240| BG352 | BG432 | Baseo | PGs59 PAD NAME oa Ha240| BG352 | BG432 | Baseo | Passo VCCINT - | P55 | AB24 | vCCINT* | VCCINT* | VCCINT* V0 47a | - Ted y30 | AAg0 B28 V0 435 | : : : H34 V0 479 | - : 31 AAS G25 V0 436 | p54 | Aao3s | AH3t | AH30 | G35 V0 480 | - : wee | AA32 | A27 V0 437 | - | Aces | aaea | ALS3 F36 V0 4st | - : : : : V0 43a | - | Ad26 | aaso | Aces | p36 V0 482 | - : : : : V0 430 | : : : : V0 483 | - : : 29 D26 V0 440 | - : : : : V0 44 | - : : AAs3 | B26 VCCIO : : - | vecio* | vecio* : V0 485 | - Tes | wes 30 E25 GND : : : GND* | GND* | GND* V0 486 | - Tes | wa0 31 Fo4 V0 441 | ps3 | Aces | Ares | AJ31 E35 GND - | ps7 | @ND* | G@ND* | GND* | GND* V0 442 | ps2 | vos | aaat | aK32 | aAdat VCCIO : - | vecio| vecios | vecio* | vecio* V0 443 | : area | aaso | G33 V0 487 | - : : : : V0 44a. - : aF30 | AH31 B38 V0 488 | - : : : : V0 445 | - : : : : V0 489 | - : : : : V0 446 | - : : : : V0 490 | - : : : : V0 447 | - : : : : V0 aot | - : w3t 32 Hod V0 44a | - : : : : V0 4o2 | - : V28 wee B24 V0 44a | - | aaoad | AEoe | AF29 D34 V0 493 | - Re3 | veg w30 De4 V0 450 | - | ABes | Arai | AJa2 E33 V0 4oa | - Rea | v30 wat A23 VCCIO : - | vecio*| vecio* | vecio* | vecio* V0 495 | p36 | R25 U29 W33 623 GND : - | @np* | GND* | GND* | GND* V0 496 | pas | Ree | U28 V30 E23 V0 451 | P51 | AAes | AE29 | AH32 F32 GND : : : GND* | GND* | GND* V0 452 | ps0 | Yea | AE30 | AF30 | Gat VCCIO : : - | vecio* | vocio : V0 453 | pag | vos | Ades | AGSt A37 V0 497 | p34 | Pod U30 v29 G23 V0 454 | pas | aaze | AD2a | AE2a | H30 V0 498 | p33 | P23 U31 Vv31 B22 V0 455 | - : aD30 | AH33 | B36 V0 aso | - : : v32 D22 V0 456 | - : ap3i_ | aq33 | 033 V0 500 | - : : U33 A241 V0 457 | - : : AE30 | C35 V0 sor | - : : : : V0 458 | - : : AF31 Da2 V0 502 | - : : : : V0 459 | - : : : : V0 503 | p32 | P25 Tog U30 Foo V0 460 | - : : : : V0 504 | pai | Nee | 130 U29 C24 VCCIO : - | vecio| vecios | vecio* | vecio* VCCIO - | p30 |vocio*| vocio* | vocio* | vocio* GND : : : GND* | GND* | GND* GND - | pea | @ND* | G@ND* | GND* | GND* V0 4e1 | - : : Ap2o | E31 V0 505 | pes | Nes | Tat U31 Et V0 462 | - : : AF32 | G29 V0 506 | - : : : D20 V0 463 | - : : AES A385 VCCINT - | p27 | Nea | vocint*| vCcINT* | VCCINT* V0 464 | - : : AD30 | H28 V0 so7 | - : : : : V0 465 | p47 | vo3 | Aces | AEs2 B34 V0 508 | - : : : : V0 466 | p46 | wea | Acea | aces | cat V0 509 | - : : T32 C17 V0 467 | - wes | Ac30 | AE33 | A33 V0 B10 | - : : T30 Get V0 468 | - vos | ABe8 | AD31 D30 V0 sit | pee | M26 | Ree T29 F20 VCCIO : : - | vecio* | vecio* : V0 512 | pes | Mes | R30 31 D18 GND - | p4s | GNo* | @ND* | GND* | GND VCCIO : : - | vecio* | vecio* : v0,FCLKe | 46a | pa4 | Ue3s | ABeo | acgo | ces GND : : : GND* | GND* | GND* V0 470 | - : : : C29 V0 513 | P24 | Med | R31 R33 F19 VCCINT - | p43 | ve4a_ | vccint | VccINT* | VCCINT* V0 514 | p23 | mes | Pes R31 B20 V0 471 | p42 | vos | ABSi | AB29 B30 V0 515 | - [26 P28 R30 H20 V0 472 | pai | Ue4a | Aaea | acat Go7 V0 516 | - [25 P30 R29 B18 VCCIO - | p40 |vocio*| vecio* | vocio* | vecio* V0 si7 | - : N30 P32 C15 V0 473 | : : aca3 | D28 V0 sia | - : N29 Pat Di6 V0 47a | : : AB30 | Aza V0 si9 | - : : : : V0 475 | p30 | vee | Aaso | ABS E27 V0 520 | - : : : : V0 476 | pas | 123 yon | AAzg F26 V0 sat | - : : : : GND : : : GND* | GND* | GND* V0 522 | - : : : : VCCIO : : - | vecio* | vecio* : VCCIO : - | vecio| vecios | vecio* | vecio* V0 477 | ues | veo | apse | cov GND - | p22 | @Np* | @ND* | GND* | GND* 6-260 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40150XV Pinout Table (Continued) XC40150XV Pinout Table (Continued) PAD NAME oa Ha240| BG352 | BG432 | Baseo | PGs59 PAD NAME oa Ha240| BG352 | BG432 | Baseo | Passo 0 523 | - K25 N28 N33 G19 0 568 | , , , , 10 524 | - [24 N31 P30 Ai7 GND : : : GND* | GND* | GND* VCCINT : : : : : : VocIO : : - | vecio* | vocio* : 10 525 | - (23 Mat P29 Fig 10 569 | - : : : : 10 526 | - J26 M29 a2 E17 10 570 | - : : : : 10 507 | - : : : : vo(rck) | 571 | Pv | cea | pat 033 D4 10 528 | - : : : : vob) | 572 | pe | cee | D30 F30 H8 10 520 | - : : NBt B16 10 573 | Ps | 23 E29 Dat a3 10 530 | - : : N30 O13 10 57a | : : : F6 10 sar | - : M28 (33 Ais VCCINT : P4 | Dea | VCcINT*| VCCINT* | VOCINT* 10 532 | - : M30 N29 D14 VO (A17) | 575 | P3 | ces | C30 F29 63 VocIO : : - | vecio* | vocio* : 0, GCK1 (A16)| 576 | P2 | Dea | p29 B33 or GND : : : GND* | GND* | GND* GND : Pi | GNb* | GNp* | GND* | GND* 10 533 | Poi | J25 [30 Mat E15 10 534 | P20 | Kod [29 (32 Gi7 VCCIO - - A10 Al Ad A13 0 535 | - . . M30 Bi4 vocio . . ai7 | Att Ato A3t 10 536 | - : : (31 on VocIO : - | acta | Aat Ai6 aaa vocio - | pia |vocio*| vocio* | vecio* | vecio* vocio . - | aceo | aat A22 Be 10 537 | Pte | Kea Kat M29 Di2 VocIO : : ace | Dit A26 C7 vo(rTMs) | 538 | Pi7 | Hes K30 J33 Ait vocio . - | aFio | Det A30 C19 VCCINT - | pie | ve4 | vocinT| vocINT* | VCCINT* VocIO : - | AFI7 1 Be 25 10 530 | - : : : E13 VocIO : : D7 L4 B13 037 0, FCLK1 | 540 | P15 | J23 K28 [30 C9 VocIO : : D13 (28 B19 Fi4 GND - | p14 | GND* | GND* | GND* | GND* VocIO : : Dis (31 B32 F30 VocIO : : - | vecio* | vocio* : VocIO : : Gea | AAT 63 a3 10 541 | - aoe | 30 Kat H16 VocIO : : H4 AAA 31 G7 10 542 | - aes | Hat [29 B10 VocIO : : KA aAze | C32 G37 10 543 | P13 | Hoa | Jag H33 G15 VocIO : : K26 | AASt Di Gai 10 544 | P12 | Ho3 | J28 K30 AS VocIO : : N23 | ANT D33 Ni 10 545 | - : : Jat Di0 VocIO : : Pa | AH21 ES N43 10 546 | - : : H32 BB VocIO : : U4 ALI Hi P6 10 547 | - : : K29 Et VocIO : : u26 | ALt K33 P38 10 548 | - : : H34 G13 VocIO : : we3 | AL2t Mt W3 GND : : : GND* | GND* | GND* VocIO : : ya | AL3t N32 wat VocIO : - | vecio*| vocio* | vocio* | vocio* VocIO : : Be 63 Re AES 10 s49 | P11 | Foo : 330 Fia VocIO : : B25 | C29 733. | AEA 10 550 | P10 | Fes : G32 H14 VocIO : : Ace | Ad3 Vi AK6 10 551 | po | Gea | H30 F33 tt VocIO : - | Aces | Aveo | wae | AK38 10 552 | ps | pee | G30 Jeg AT vocio . . . . AA2 AL 10 553 | - : H29 Gai EQ VocIO : : : : aBs3 | AL43 0 554 | - . H28 H30 B vocio . . . . ADt AU3 10 555 | - : Fat E33 D8 VocIO : : : : AF33 | AU7 0 556 | - . F30 E32 F8 vocio . . . . aki | Au37 10 557 | - : : : : VocIO : : : : aKa | Aud 10 558 | - : : : : VocIO : : : : Akasa | AVI4 GND : - | GND* | GND* | GND* | GND VocIO : : : : Ale | Av30 VocIO : - | vecio*| vocio* | vocio* | vocio* VocIO : : : : ALS BAT 10 550 | - E25 | Goo H29 Go VocIO : : : : als! | BATS 10 560 | - Foa | G28 F31 H10 VocIO : : : : ame | BA25 10 sor | - : : : : VocIO : : : : amis | BA37 10 562 | - : : : : VocIO : : : : amet | BC1 10 563 | - FO3 Est G30 B4 VocIO : : : : ama2 | BOTS 10 564 | - D25 E30 D32 E7 VocIO : : : : aN4_ | BC31 10 565 | - : Fog Est C5 VocIO : : : : aNs | BC43 10 566 | - : Fa G29 D VocIO : : : : AN12 : 10 567 | - : : : : VocIO : : : : AN18 : February 1, 1999 (Version 1.0) 6-261XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX XC40150XV Pinout Table (Continued) XC40150XV Pinout Table (Continued) PADNAME | @.),{H@240| BG352 | BG432 | BGS6O | PGss9 PADNAME | erp;,{H@240| BG352 | BG432 | BGS6O | PGS5S VCCIO - - - - AN24 - GND - - Et 728 Pt AB36 VCCIO - - - - AN30 - GND - - E26 al P33 AEt GND - - H1 V31 R32 AE43 VCCINT - - - A10 E12 H12 GND - - H26 ACt TA AH6 VCCINT - - - AB2 AD2 H18 GND - - N1 AC31 V33 AH38 VCCINT - - - AB30 | AD32 H26 GND - - P26 AEt we AM2 VCCINT - - - AG28 | AK31 H32 GND - - wi AES1 Y1 AM42 VCCINT - - - AH15 | AM17 M8 GND - - wee | AH16 33 AP6 VCCINT - - - AH5 AK5 M36 GND - - - At ABI AP38 VCCINT - - - AJ10 AKI 1 V8 GND - - - AJ31 Ac32 | AT22 VCCINT - - - AK22 | AN25 V36 GND - - - AKi AD33. | AVI VCCINT - - - B23 C24 AF8 GND - - - AK2 AE2 AVI6 VCCINT - - - B4 De AF36 GND - - - AK30 AGt AV28 VCCINT - - - C16 C17 AM8 GND - - - AK31 | AG32 | aAv34 VCCINT - - - E28 E30 AM36 GND - - - AL2 AH2 AW VCCINT - - - K29 K32 ATI2 GND - - - AL3 AJ33 AWS5 VCCINT - - - K3 J AT18 GND - - - AL7 AL32 | Aws39 VCCINT - - - R2 3 AT26 GND - - - ALQ AM3 | AW43 VCCINT - - - R29 U32 AT32 GND - - - AL14 | AMIt BB12 GND - - - ALig | aMig | BB32 GND - - Al A2 A7 AS GND - - - AL23 | AM25 BCS GND - - A14 A3 A12 A19 GND - - - AL25 | ames | BC1g9 GND - - A19 A7 A14 A25 GND - - - AL2g | aM33 | BC25 GND - - A2 AQ A18 A39 GND - - - AL30 AM7 BC3g GND - - A22 A14 A20 B12 GND - - - - AN2 - GND - - A25 A18 A24 B32 GND - - - - AN5 - GND - - A26 A23 A29 Et GND - - - - AN10 - GND - - AS A25 A32 E5 GND - - - - AN14 - GND - - AS A29 Bi E39 GND - - - - AN16 - GND - - ABI A30 Be E43 GND - - - - AN20 - GND - - AB26 Bt Bg F10 GND - - - - AN22 - GND - - AEt B2 B15 F16 GND - - - - AN27 - GND - - AE26 B30 B23 F28 GND - - AF 1 B31 B27 F34 NC - | P204] ce C8 Al - GND - - AF13 C1 B31 H22 NC - | Pats - - A33 - GND - - AF1g C31 C2 K6 NC - - - - AC2 - GND - - AF2 D16 Et K38 NC - - - - AN1 - GND - - AF22 Gi F32 M2 NC - - - - AN33 - GND - - AF25 | G31 G2 M42 12/21/98 ewe ff AEB | if se | Te *Note: Pads labelled GND*, VCCINT*, or VCCIO* are inter- GND - - AF5 J31 J32 T38 a GND - - AFB Py Kt wit nally bonded to the corresponding power plane within the GND : : BI P31 Ib was associated package. They have no direct connection to any GND ; ; B26 TA M33 ABS specific package pin. 6-262 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40200XV Pinout Table XC40200XV Pinout Table (Continued) 6 Pad Name bade BG432 BG560 PG559 Pad Name BG432 BG560 PG559 Pad # 0 46 B22 B24 T8 vcclo - VcCclo* VcCclo* VcCclo* vcclo . vcclo* vcclo* vcclo* VO, GCK8 (A15 1 D28 E29 E3 VO 47 A22 F290 R5 OQ (A)14) 2 C28 D30 F4 0 48 C24 C23 R3 0 3 Beg E28 J7 VO 49 . A23 Ut 0 4 D27 Deg D2 VO 50 . D22 T4 0 5 B28 C30 K8 VO 51 . . . 0 6 C27 D28 H6 VO 52 . . . 0 7 - - VO 53 . . . 0 8 - - - 0 54 - - - 0 9 - - - GND - GND* GND* GND* 0 10 - - - VCCIO - VCCIO* VCCIO* - VCCIO - VCCIO* VCCIO* - 0 55 - - - GND - GND* GND* GND* 0 56 - - - 0 14 - - - 0 57 - C22 US 0 12 - - - 0 58 - E24 v2 0 13 - - - 0 59 D20 B22 U7 0 14 - - - 0 60 Bet D21 U3 0 15 D26 A314 G5 0 64 C20 C21 Y2 0 16 A28 E27 F2 0 62 B20 B24 V4 0 17 B27 C29 H4 0 63 A20 E20 V6 0 18 C26 B30 Gi 0 64 Dig A21 W5 0 19 D25 D27 J5 GND - GND* GND* GND* 0 20 A27 C28 L7 VCCIO - VCCIO* VCCIO* VCCIO* VCCIO - VCCIO* VCCIO* VCCIO* V0 (A11) 65 C19 D20 W7 GND - GND* GND* GND* 10 (A10) 66 B19 C20 v4 1/0 (A13) 21 B26 E26 J3 0 67 Aig B20 AAI 1/0 (A12) 22 D24 B29 K4 0 68 B18 E19 Y6 0 23 C25 B28 H2 1/0 (A18) 69 D18 D19 AB2 0 24 A26 D26 L5 1/0 (A19) 70 C18 C19 Y8 0 25 B25 C27 Jt 0 71 - - - 0 26 D23 E25 M6 0 72 - - - 0 27 - A28 K2 0 73 - - - 0 28 - A27 N7 0 74 - - - 0 29 - - - GND - GND* GND* GND* 0 30 - - - VCCIO - VCCIO* VCCIO* - VCCIO - VCCIO* VCCIO* VCCIO* 0 75 - - - GND - GND* GND* GND* 0 76 - - - 0 31 - - - 0 77 - - - 0 32 - - - 0 78 - - - 0 33 - - - 0 79 - A19 AA3 0 34 - - - 0 80 - D18 AAS 0 35 - D25 P8 0 81 B17 E18 ACI 0 36 - C26 L3 0 82 C17 C18 AA7 0 37 - E24 uf 1/0 (A) 83 A17 B18 AB4 0 38 - B26 M4 1/0 (A8) 84 DI7 AI7 AB6 0 39 C24 C25 P2 VCCIO - VCCIO* VCCIO* VCCIO* 0 40 B24 p24 N5 GND - GND* GND* GND* 0 A C23 B25 RI 1/0 (A7) 85 A16 DI7 AC3 0 42 D22 E23 N3 1/0 (A6) 86 Bi6 E17 AC5 VCCIO - VCCIO* VCCIO* - VCCINT - C16 C17 VCCINT* GND - GND* GND* GND* 0 87 - - AD2 0 43 A24 A25 R7 0 88 A15 B17 AC7 0 44 - - P4 0 89 - B16 AF2 VCCINT - B23 C24 VCCINT* 0 90 - D16 AD4 0 45 C22 D23 T2 0 at - - - February 1, 1999 (Version 1.0) 6-263XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40200XV Pinout Table (Continued) XC40200XV Pinout Table (Continued) Pad Name bed g BG432 BG560 PG559 Pad Name bade BG432 BG560 PG559 V0 92 : : : V0 137 : : : V0 93 : : : V0 138 : : : V0 34 : : : GND : GND* GND* GND* VCCIO : vocio* | Vvccio* : VCCIO : vecioe | voecio* | vocio* GND : GND* GND* GND* V0 139 : : : V0 95 : : : V0 140 : : : V0 36 : : : V0 144 : F10 ALT V0 a7 : : : V0 142 : C8 AT2 V0 98 : : : V0 143 AS De ARS 70 (A20) 39 B15 E16 AD6 V0 144 Ba B7 AU 0 (A21) 100 C15 C16 AES V0 145 De AG AT4 V0 101 Dis At5 AF4 V0 146 B7 Eg Ave V0 102 Bi4 C15 AGI V0 147 C7 C7 ARS 1/0 (AS) 103 At3 DIS ADS V0 148 D8 D8 AN7 0 (AA) 104 C14 E15 AGS GND : GND* GND* GND* VCCIO : vecioe | vocio* | vocio* VCCIO : vecioe | vocio* | vocio* GND : GND* GND* GND* V0 149 AG AS AWS V0 105 Bi3 B14 AHA V0 150 B BS AV4 V0 106 D4 C14 AE7 1/0 (A3) 151 D7 E8 BAT V0 107 Ate D14 AH2 1/0, (CS1, A2) 152 AS C6 AUS V0 108 C13 At3 AFG V0 153 oc D7 Aye V0 109 Bia E14 AS V0 154 BS B4 AT6 V0 140 Di3 C13 AGS V0 155 : : : V0 114 : DIB Al3 V0 156 : : : V0 142 : B12 AK4 V0 157 : : : V0 113 : : : V0 158 : : : V0 114 : : : GND : GND* GND* GND* VCCIO : vocio* | Vvccio* : VCCIO : vocio* | Vvccio* : GND : GND* GND* GND* V0 159 : : : V0 115 : : : V0 160 : : : V0 116 : : : V0 161 : : : V0 147 : : : V0 162 : : : V0 118 : : : V0 163 D6 C5 APB V0 119 : C12 AG? V0 164 AA E7 ART V0 120 : E13 AK2 V0 165 C5 AB AY4 V0 124 Ct2 At Als V0 166 : : BB2 V0 122 Bit Di2 ALS 0, GCK7 (At) 167 DS A2 AVE VCCIO : vecioe | voecio* | vocio* 1/0 (AO, WS) 168 B3 DS ATS V0 123 Di2 Bit AM4 GND : GND* GND* GND* V0 124 ot Ct ANI 0, TDO : C4 E6 BAS VCCINT : A10 E12 VCGINT* VCCIO : vecioe | vocio* | vocio* V0 125 : : ALS CCLK : D4 C4 BAS VCCINT : : : : 0, GCK6 (DOUT) | 169 D3 D4 BB4 V0 126 Bio B10 AHS 1/0 (DO, DIN) 170 C2 E4 AY6 GND : GND* GND* GND* V0 171 D2 F5 BC3 VCCIO : VGCIO VCCIO* : V0 172 E4 B3 AW7 V0 127 C10 Dt Al? V0 173 D1 D3 BBE V0 128 Bo C10 AP2 V0 174 E3 FA AUS V0 129 Co Ao ANS V0 176 : : : V0 130 Dio E14 AP4 V0 177 : : : V0 131 : ee ARI V0 178 : : : V0 132 : D10 ANS VCCIO : vocio* | Vvccio* : V0 133 : AS AM6 GND : GND* GND* GND* V0 134 : Ba AK8 V0 179 : : : V0 135 : : : V0 180 : : : V0 136 : : : V0 181 Ea Ct ATO 6-264 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40200XV Pinout Table (Continued) XC40200XV Pinout Table (Continued) Pad Name bed g BG432 BG560 PG559 Pad Name bade BG432 BG560 PG559 0 182 FA G5 AVS 0 228 , , , 10 183 FY E3 AYS 10 229 Ma NB AUIS 10 184 F3 D2 BO7 10 230 Mt N2 BBIE 10 185 : : : 10 231 Na PS AY18 10 186 : : : 10 232 NB Ni AW19 0 (RCK,RDY_/BUSY)| 187 Fo G4 AWS GND : GND* GND* GND* /0 (D1) 188 G4 F3 BAS VoCIO : vecio* | voecio* | vocio* VoCIO : vecio* | voecio* | vocio* 10 233 : : : GND : GND* GND* GND* 10 234 : : : 10 189 : : : 10 235 : : : 10 190 : : : 10 236 : : : 10 tot : HS AUit 10 237 N2 P4 AV20 10 192 : E2 AY10 10 238 Ni P3 AT20 10 193 FA Fo BBS 10 239 P4 Pe BB20 10 194 a3 H4 AW11 10 240 P3 R5 AY20 0 195 G2 a3 BCS 0 241 Pe R4 BC2 10 196 Ha J5 AVI2 10 242 R3 R3 BA2t 0 197 H3 FA AUi3 GND . GND* GND* GND* 10 198 He Gt AT14 VoCIO : vecio* | VccIo* : VCCIO . vecioe | voecio* | vocio 0 243 R4 Ri AW21 GND : GND* GND* GND* 10 244 : T4 Auat 10 199 : : : 10 245 : TS BB22 10 200 : : : 10 246 : : AY22 10 201 : : : 10 247 : : : 10 202 : : : 10 248 : : : 10 203 : J4 BATT 10 249 : : : 10 204 : H3 AY12 10 250 : : : 10 205 : K5 BB10 VCCINT : Re T3 VCCINT* 10 206 : He AW13 /0 (RS) 251 Ri T2 AV22 10 207 HA 3 BOT /0 (D3) 252 T3 U3 BA23 10 208 J4 K4 AUIS GND : GND* GND* GND* 10 209 3 Je BB14 VoCIO : vecio* | voecio* | vocio* 10 210 Je L5 ATI6 10 253 T2 U4 AW23 VoCIO : vecio* | VccIo* : /0 (D4) 254 TH US AY24 GND : GND* GND* GND* 10 255 : : : 10 at K4 K3 BATS 10 256 : : : 10 212 : : AYI4 10 257 : : : VCCINT : K3 a VCCINT* 10 258 : : : 0, FCLK4 213 Ke L4 BOIS 10 259 : U4 Boas 10 214 KA Ke AW15 10 260 : U2 BA27 VCCIO . vecioe | voecio* | vocio 0 261 U3 v2 Au23 10 215 : : : 10 262 U4 v4 AV24 0 216 . . . VCCIO . vecio* | Vccio* . 10 217 : : : GND : GND* GND* GND* 10 218 : : : 10 263 U2 V5 AY26 10 219 : M5 BAIS 10 264 U4 V3 BB24 10 220 : (3 AUI7 10 265 V3 wi AW25 10 224 (3 1 BBI6 10 266 v4 W3 BB26 /0 (D2) 222 (2 M4 AY16 10 267 v2 wa AT24 GND : GND* GND* GND* 10 268 we ws BA2S VoCIO : vecio* | VccIo* : 10 269 : : : 10 203 M4 Ma AWI7 10 270 : : : 10 204 Ma N5 AV18 10 a7 : : : 10 225 : Ma BAI7 10 272 : : : 10 226 : Na BCI7 VoCIO : vecio* | voecio* | vocio* 10 227 : : : GND : GND* GND* GND* February 1, 1999 (Version 1.0) 6-265XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40200XV Pinout Table (Continued) XC40200XV Pinout Table (Continued) Pad Name bed g BG432 BG560 PG559 Pad Name bade BG432 BG560 PG559 V0 273 W3 Y2 AY28 V0 319 : : : V0 274 w4 3 AU25 V0 320 : : : V0 275 : YA AV26 V0 324 : : : V0 276 : AAI BC27 V0 322 : : : V0 277 : : : V0 323 AE4 AHS BC37 V0 278 : : : V0 324 AGI AG4 AY38 V0 279 wi Y5 AW27 V0 325 AG2 AK2 BB38 V0 280 Y4 AAS BB28 V0 326 AF3 Al3 BA4t V0 281 3 AAA BA3i GND : GND* GND* GND* V0 282 4 AB2 AY30 VCCIO : vocio* | Vvccio* : VCCIO : vecioe | voecio* | vocio* V0 327 : : : GND : GND* GND* GND* V0 328 : : : 0 (C80) 283 Y2 AB3 Awe9 V0 329 : : : 1/0 (DS) 284 AA2 AAS Boag V0 330 : : : V0 285 : ACt AU27 V0 334 AF4 AGS AY40 V0 286 : AB4 BA33 V0 332 AHA AL BB40 V0 287 : : : V0 333 AH2 AHA AT36 V0 288 : : : V0 334 AG3 AK3 BA39 V0 289 : : : 0, GCKS 336 AG4 Al4 AV38 V0 280 : : : /0 (D7) 336 Ade AHS BCA! VCCIO : vecioe | voecio* | vocio* PROGRAM : AHS AMI BB42 V0 291 AAS AC3 AY32 VCCIO : vecioe | voecio* | vocio* 0, FCLK3 292 ABI ABS AWS DONE : AHA Als AY42 VCCINT : AB2 AD2 VCCINT* GND : GND* GND* GND* V0 293 : : BB30 0, GCK4 337 Add AL4 AWA V0 294 AB3 ACA BA35 V0 338 AK3 Al6 AV40 GND : GND* GND* GND* VCCINT : AHS AKS VCCINT* VCCIO : vocio* | Vvccio* : V0 330 : : Av42 V0 295 AB4 AD3 AT28 V0 340 AK4 ANS AR37 V0 296 Ace AEt Au2g V0 341 AJ5 AK6 AP36 V0 297 ADI ACS BC33 V0 342 AH6 ALS AT38 V0 298 AC3 AES AY34 V0 343 : : : V0 299 : AD4 BB34 V0 344 : : : V0 300 : AFI AW33 V0 345 : : : V0 301 : AF2 AU31 V0 346 : : : V0 302 : ADS AV32 VCCIO : vocio* | Vvccio* : V0 303 : : : GND : GND* GND* GND* V0 304 : : : V0 347 : : : V0 305 : : : V0 348 : : : V0 306 : : : V0 349 : : : GND : GND* GND* GND* V0 350 : : : VCCIO : vecioe | voecio* | vocio* V0 361 AL4 Al? AU3a V0 307 : : : V0 352 AK5 AM4 AU43 V0 308 : : : V0 353 AJ6 AMS BA43 V0 309 : AG2 AT30 V0 354 AH7 AK7 AT42 V0 310 : AE4 AU33 V0 355 ALS AL6 AR3a V0 314 ACA AF3 AW35 V0 356 AK6 AJB AN37 V0 312 AD2 AHA BC35 VCCIO : vecioe | voecio* | vocio* V0 313 AE2 AES AY36 GND : GND* GND* GND* V0 314 AD3 AG3 BB36 V0 357 AH8 AM6 AT40 V0 315 AD4 AF4 AV36 V0 358 Ad? ANG AP40 1/0 (D6) 316 AFI At AU35 V0 359 AL6 AK8 AR43 GND : GND* GND* GND* V0 360 AK7 ALT AN39 VCCIO : vecioe | voecio* | vocio* V0 361 AHS Al9 AP42 V0 317 AF2 Ade AT34 V0 362 AB AN7 AM38 V0 318 AES AFS AW37 V0 363 : ALB AN43 6-266 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40200XV Pinout Table (Continued) XC40200XV Pinout Table (Continued) Pad Name bed g BG432 BG560 PG559 Pad Name bade BG432 BG560 PG559 V0 364 : AKS AL37 V0 410 : : : V0 365 : : : GND : GND* GND* GND* V0 366 : : : VCCIO : vocio* | Vvccio* : VCCIO : vecioe | voecio* | vocio* V0 at : : : GND : GND* GND* GND* V0 412 : : : V0 367 : : : V0 413 : : : V0 368 : : : V0 414 : : : V0 369 : : : V0 415 : ALi6 Acaa V0 370 : : : V0 416 : AM6 AC37 V0 371 : AMB AK36 V0 47 AJ15 AKi6 AB40 V0 372 : AJ10 ARA V0 418 ALi5 ANI7 AB42 V0 373 : ALS ALA VCCINT : AHi5 AMi7_ | VCCINT* V0 374 : AMS ANA1 V0 419 : : AB38 V0 375 AK8 AKA0 AK42 V0 420 ALi6 ALI7 AAAI V0 376 Als ANS AM40 GND : GND* GND* GND* V0 377 AHi0 AJ 43 VCCIO : vecioe | vocio* | vocio* V0 378 ALS ALio AJ37 70 (INIT) 424 AKi6 AM7 AA3a VCCIO : voecio* | VvccIo* : V0 422 AJ16 AKi7 AA37 GND : GND* GND* GND* V0 423 ALI7 AM18 40 V0 379 AKS AM10 AL39 V0 424 AKI7 ALi8 38 V0 380 : : AH36 V0 425 : AK18 AA43 VCCINT : AJ10 AKA VCCINT* V0 426 : AM8 we V0 381 AKA0 ALi AH42 V0 427 : : : V0 382 AL10 AJ12 AJ39 V0 428 : : : VCCIO : vecioe | voecio* | vocio* V0 429 : : : V0 383 Alt ANTI AK4o V0 430 : : : V0 384 AHi2 AK12 AGA VCCIO : vocio* | Vvccio* : V0 385 : ALi2 AlAs GND : GND* GND* GND* V0 386 : AM12 AH40 V0 431 : : : V0 387 : : : V0 432 : : : V0 388 : : : V0 433 : : : V0 389 : : : V0 434 : : : V0 380 : : : V0 436 AJ? ANiS v40 GND : GND* GND* GND* V0 436 AHI7 ALIS 36 VCCIO : vocio* | Vvccio* : V0 437 AK18 AK19 U4 V0 304 : : : V0 438 ALIS AM20 Y42 V0 392 : : : V0 439 AJ18 As19 T40 V0 393 : AJ13 AG37 V0 440 AK19 AL20 W237 V0 304 : AKi3 AG43 VCCIO : vecioe | voecio* | vocio* V0 395 AKA ALI3 AG39 GND : GND* GND* GND* V0 396 Al12 AM13 AF38 V0 444 AHi8 AK20 V38 V0 397 AK12 ANTS AF42 V0 442 AL20 AN24 U39 V0 398 ALt2 AJ14 AD42 V0 443 AJ19 AL2t ve V0 399 AHT3 AKI4 AF40 V0 444 AK20 AJ20 Rai V0 400 Al13 AL4 AE37 V0 445 AHiS AM22 U43 GND : GND* GND* GND* V0 446 AJ20 AK2t P40 VCCIO : vecioe | voecio* | vocio* VCCIO : : : : V0 401 AKi3 AM14 AE39 GND : : : : V0 402 ALIS ANi5 AD40 V0 447 : AN23 T42 V0 403 AKI4 AJ15 AC43 V0 448 : AL22 U37 V0 404 AH14 AK15 AD38 V0 449 : : : V0 405 Ali4 ALi5 ACA V0 450 : : : V0 406 AK15 AM16 AD36 VCCIO : vecioe | voecio* | vocio* V0 407 : : : GND : GND* GND* GND* V0 408 : : : V0 451 : : : V0 409 : : : V0 452 : : : February 1, 1999 (Version 1.0) 6-267XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40200XV Pinout Table (Continued) XC40200XV Pinout Table (Continued) Pad Name bed g BG432 BG560 PG559 Pad Name bade BG432 BG560 PG559 V0 453 : : : V0 498 : : : V0 454 : : : 0 /LDG) 499 AH26 Al27 K36 V0 455 : Adet R39 V0 500 AL28 AM31 J37 V0 456 : AM23 N41 V0 501 AJ27 AK28 B42 V0 457 Ake AK22 R43 V0 502 AK28 AL30 D40 V0 458 AH20 AM24 M40 0 (HDG) 503 AH27 AK2g Cat VCCIO : vocio* | Vvccio* : 0, GCK3 504 AK29 Al28 F38 V0 459 Alar AL23 N39 (M2) : AJ28 AN32 H36 V0 460 AL22 AJ22 T36 VCCIO : vecioe | voecio* | vocio* VCCINT : AK22 AN25 VCCINT* (MO) : AH28 AJ29 C39 V0 461 : : P42 GND : GND* GND* GND* V0 462 Al22 AK23 R37 O (M1) : AH2g AK30 D38 GND : GND* GND* GND* 0, GCK2 505 AJ30 AH2g E37 VCCIO : vocio* | Vvccio* : V0 506 AH30 AJ30 B40 V0 463 AK23 AL24 Lat VCCINT : AG28 AKI VCCINT* V0 464 Al23 AN26 143 V0 507 : : H34 V0 465 AH22 As23 K40 V0 508 AH31 AH30 G35 V0 466 Al24 AL25 Ka2 V0 509 AG29 AL33 F36 V0 467 : AK24 [39 V0 510 AG30 AG29 D36 V0 468 : AM26 43 V0 511 : : : V0 469 : AM27 M38 V0 512 : : : V0 470 : AJ24 P36 V0 513 : : : V0 471 : : : V0 514 : : : V0 472 : : : VCCIO : vocio* | Vvccio* : V0 473 : : : GND : GND* GND* GND* V0 474 : : : V0 515 AF28 Ast E35 GND : GND* GND* GND* V0 516 AGS AK32 ve VCCIO : vecioe | voecio* | vocio* V0 517 AF29 AG3O G33 V0 475 : : : V0 518 AF30 AH31 B38 V0 476 : : : V0 519 : : : V0 477 : AL26 N37 V0 520 : : : V0 478 : AK25 H42 V0 521 : : : V0 479 AK24 AN28 41 V0 522 : : : V0 480 AH23 AN29 G43 V0 523 AE28 AF29 D34 V0 481 Al24 AJ25 H40 V0 524 AFS1 AJ32 E33 V0 482 AK25 AL27 Fa2 VCCIO : vecioe | voecio* | vocio* VCCINT : : : : GND : GND* GND* GND* V0 483 Al25 AK26 J39 V0 525 AE29 AH32 F32 V0 484 AH24 AM29 137 V0 526 AE3O AF30 Gat GND : GND* GND* GND* V0 527 AD28 AGSt A37 VCCIO : vecioe | vocio* | vocio* V0 528 AD29 AE29 H30 V0 485 AL26 AM30 E41 V0 529 AD30 AH33 B36 V0 486 AK26 AJ26 F40 V0 530 AD31 AG33 633 V0 487 AH25 AL28 643 V0 531 : AE3O C35 V0 488 AL27 AK27 G39 V0 532 : AFS1 Da2 V0 489 AJ26 AL2g D42 V0 533 : : : V0 480 AK27 AN31 H38 V0 534 : : : V0 4914 : : : VCCIO : vecioe | voecio* | vocio* V0 492 : : : GND : GND* GND* GND* V0 493 : : : V0 536 : : : V0 494 : : : V0 536 : : : GND : GND* GND* GND* V0 537 : : : VCCIO : vocio* | Vvccio* : V0 538 : : : V0 495 : : : V0 539 : ADeg Est V0 496 : : : V0 540 : AFS32 Gea V0 497 : : : V0 BAT : AES A385 6-268 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40200XV Pinout Table (Continued) XC40200XV Pinout Table (Continued) Pad Name bed g BG432 BG560 PG559 Pad Name bade BG432 BG560 PG559 V0 542 : AD30 H28 V0 588 T30 U29 C21 V0 543 Ac28 AE32 B34 VCCIO : vecioe | voecio* | vocio* V0 544 Ace9 Ace9 C3t GND : GND* GND* GND* V0 545 AC30 AE33 A33 V0 589 31 U31 Et V0 546 AB28 AD31 D30 V0 580 : : D20 VCCIO : vocio* | Vvccio* : VCCINT : R29 U32 VCCINT* GND : GND* GND* GND* V0 591 : : : 0, FOLK2 547 AB29 AC30 E29 V0 592 : : : V0 548 : : C29 V0 593 : : : VCCINT : AB30 AD32 VCCINT* V0 594 : : : V0 549 ABST AB29 B30 V0 595 : T32 C17 V0 550 AA29 AC31 Go7 V0 596 : T30 Get VCCIO : vecioe | voecio* | vocio* V0 597 R28 Teg F20 V0 551 : : : V0 598 R30 T31 D18 V0 552 : : : VCCIO : vocio* | Vvccio* : V0 553 : : : GND : GND* GND* GND* V0 554 : : : V0 599 R31 R33 F19 V0 555 : AC33 D28 V0 600 Pag R31 B20 V0 556 : AB30 A29 V0 601 P28 R30 H20 V0 557 AAO ABS E27 V0 602 P30 R29 B18 V0 558 28 AA29 F26 V0 603 N30 P32 C15 GND : GND* GND* GND* V0 604 N29 Pat Di6 VCCIO : vocio* | Vvccio* : V0 605 : : : V0 559 29 AB32 C27 V0 606 : : : V0 560 30 AAO B28 V0 607 : : : V0 561 31 AAS G25 V0 608 : : : V0 562 wes AA32 A27 VCCIO : vecioe | voecio* | vocio* V0 563 : : : GND : GND* GND* GND* V0 564 : : : V0 609 N28 N33 Gig V0 565 : 29 D26 V0 610 N31 P30 AT V0 566 : AASB B26 V0 611 Mat Pag F18 V0 567 wee 30 E25 V0 612 Meg M32 E17 V0 568 w30 31 Fod V0 613 : : : GND : GND* GND* GND* V0 614 : : : VCCIO : vecioe | voecio* | vocio* V0 615 : N31 B16 V0 569 : : : V0 616 : N30 C13 V0 570 : : : V0 617 M28 133 At5 V0 571 : : : V0 618 M30 N29 D14 V0 572 : : : VCCIO : vocio* | Vvccio* : V0 573 wat 32 Hed GND : GND* GND* GND* V0 574 V28 wea B24 V0 619 L30 M31 E15 V0 575 v29 w30 Dea V0 620 Leg [32 Gi7 V0 576 V30 w3t A23 V0 624 : M30 B14 V0 577 Ue9 W33 C23 V0 622 : (31 Ct V0 578 U28 V30 E23 V0 623 : : : GND : GND* GND* GND* V0 624 : : : VCCIO : vocio* | Vvccio* : V0 625 : : : V0 579 U30 v29 G23 V0 626 : : : V0 580 U3t Vv31 B22 VCCIO : vecioe | voecio* | vocio* V0 581 : v32 D22 V0 627 Kat Meg Di2 V0 582 : U33 A241 0 (TMS) 628 K30 J33 At V0 583 : : : VCCINT : Kag K32 VCCINT* V0 584 : : : V0 629 : : E13 V0 585 : : : V0, FCLK1 630 K28 [30 ee V0 586 : : : GND : GND* GND* GND* V0 587 T29 U30 Foo VCCIO : vocio* | Vvccio* : February 1, 1999 (Version 1.0) 6-269XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40200XV Pinout Table (Continued) XC40200XV Pinout Table (Continued) Pad Name bed g BG432 BG560 PG559 Pad Name bade BG432 BG560 PG559 V0 631 J30 K31 H16 VCCIO : A31 A22 Ba V0 632 H31 Leg B10 VCCIO : Dt A26 C7 V0 633 Jeg H33 Gis VCCIO : D241 A30 C19 V0 634 J28 K30 Ao VCCIO : 4 Ba C25 V0 635 : J3t D10 VCCIO : \4 B13 C37 V0 636 : H32 Ba VCCIO : [28 B19 Fi4 V0 637 : Kag E14 VCCIO : (31 B32 F30 V0 638 : H31 G13 VCCIO : AAI C3 G3 V0 639 : : : VCCIO : AAA C3t G7 V0 640 : : : VCCIO : AA28 C32 G37 V0 641 : : : VCCIO : AAS D1 Gat V0 642 : : : VCCIO : AH D33 Ni GND : GND* GND* GND* VCCIO : AH? ES N43 VCCIO : vecioe | voecio* | vocio* VCCIO : AL Hy P6 V0 643 H30 J30 Fie VCCIO : ALi K33 P38 V0 644 G30 G32 H14 VCCIO : AL2t MA W3 V0 645 Hee F33 Git VCCIO : AL3t N32 wat V0 646 He8 Jeg AT VCCIO : C3 R2 AES V0 647 F34 Gat Eg VCCIO : C29 T33 AEA V0 648 F30 H30 B VCCIO : Au3 Vi AK6 V0 649 : E33 D8 VCCIO : AJ29 w232 AK38 V0 650 : E32 F8 VCCIO : : AA2 AL V0 651 : : : VCCIO : : AB33 AL43 V0 652 : : : VCCIO : : ADI AU3 GND : GND* GND* GND* VCCIO : : AF33 AUT VCCIO : vecioe | voecio* | vocio* VCCIO : : AKA AU37 V0 653 Gag H29 ag VCCIO : : AK4 AUAI V0 654 G28 F34 H10 VCCIO : : AK33 AVI4 V0 655 : : : VCCIO : : AL2 AV30 V0 656 : : : VCCIO : : ALS BAT V0 657 E31 G30 B4 VCCIO : : AL3t BA19 V0 658 E30 Da2 E7 VCCIO : : AM2 BA25 V0 659 F29 Est C5 VCCIO : : AM15 BA37 V0 660 F28 Gag D6 VCCIO : : AM21 BCT V0 661 : : : VCCIO : : AM32 BC13 V0 662 : : : VCCIO : : ANA BCs GND : GND* GND* GND* VCCIO : : ANS BC43 VCCIO : vocio* | Vvccio* : VCCIO : : ANi2 : V0 663 : : : VCCIO : : ANi8 : V0 664 : : : VCCIO : : AN24 : V0 665 : : : VCCIO : : AN30 : V0 666 : : : GND : : : : VCCINT - - - H12 VCCIO : : : : VCCINT : : : H18 0 (TCK) 667 Dat 633 D4 VCCINT : : : H26 70 (TDN) 668 D30 F30 H8 VCCINT : : : H32 V0 669 E29 DSi AB VCCINT : : : Ma V0 670 : : F6 VCCINT : : : M36 VCCINT : E28 E30 VCCINT* VCCINT : : : V8 0 (A17) 671 C30 F29 C3 VCCINT : : : V36 0, GCK1 (A16) 672 Deg B33 Ct VCCINT : : : AFB GND : GND* GND* GND* VCCINT : : : AF36 VCCINT : : : AMB VCCIO - At AA AIS VCCINT : : : AM36 VCCIO : At At0 A31 VCCINT : : : ATI2 VCCIO : A241 At6 Aas VCCINT : : : ATI8 6-270 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40200XV Pinout Table (Continued) XC40200XV Pinout Table (Continued) Pad Name bed g BG432 BG560 PG559 Pad Name bade BG432 BG560 PG559 VCCINT - - - AT26 GND - AJt ABI AP38 VCCINT - - - AT32 GND - AJ31 AC32 AT22 GND - AKt AD33 AV10 GND - A2 AZ AS GND - AK2 AE2 AV16 GND - A3 A12 A19 GND - AK30 AG1 AV28 GND - A7 A14 A25 GND - AK31 AG32 AV34 GND - AQ A18 A39 GND - AL2 AH2 AW1 GND - A14 A20 B12 GND - AL3 AJ33 AW5 GND - A18 A24 B32 GND - AL7 AL32 AW39 GND - A23 A29 Et GND - ALQ AM3 AW43 GND - A25 A32 E5 GND - AL14 AM11 BB12 GND - A29 Bt E39 GND - AL18 AM19 BB32 GND - A30 B E43 GND - AL23 AM25 BC5 GND - Bt BO F10 GND - AL25 AM28 BC19 GND - B2 B15 F16 GND - AL29 AM33 BC25 GND - B30 B23 F28 GND - AL30 AM7 BC39 GND - B3t B27 F34 GND - - AN2 - GND - Ct B31 H22 GND - - ANS - GND - C31 C2 K6 GND - - AN10 - GND - D16 Et K38 GND - - AN14 - GND - al F32 M2 GND - - AN16 - GND - G31 G2 M42 GND - - AN20 - GND - J G33 T GND - - AN22 - GND - J31 J32 138 GND - - AN27 - GND - Pt K1 wi GND - P3t L2 w43 NC - C8 At - GND - T4 M33 AB8 NC - - A33 - GND - T28 PA AB36 NC - - AC2 - GND - vi P33 AEt NC - - AN1 - GND - V31 R32 AE43 NC - - AN33 - GND - ACt T1 AH6 12/21/98 exe Acs vs aes *Note: Pads labelled GND*, VCCINT*, or VCCIO* are inter- GND - AEt we AM2 : me GND - AER v4 AMad nally bonded to the corresponding power plane within the GND - AHi6 153 APS associated package. They have no direct connection to any specific package pin. February 1, 1999 (Version 1.0) 6-271XC4000XLA/XV Field Programmable Gate Arrays 3: XILINX 6-272 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40250XV Pinout Table XC40250XV Pinout Table (Continued) XC40250XV Pinout Table Pad Name Peds BG432 BG560 PG559 Pad Name Ped BG432 BG560 PG559 GND : GND* GND" GND" 0 47 A24 A25 R7 VCCIO : vecioy | vecio* | vccio* 70 8 - - BA 0, GCK8 (A15) 1 D28 E29 E3 VOCINT - BD3 Opa VOCINT /0 (A14) 2 C28 D30 F4 70 n opp 583 75 vo 3 B29 E28 u7 0 50 B22 B24 T8 vO 4 bez bee be VCCIO - vecior | vccio* | vccio* vo 5 B28 30 K8 0 51 A22 E22 R5 vo 8 Cer bes H6 To) 52 C2 C23 R3 vO z : : : 0 53 - A23 ut vo 8 : : : 0 54 : p22 T4 vO 9 : : : /0 55 - - - vo 10 : : : 0 56 - - - VCCIO : vecior | vccio* : 70 57 - - - GND : GND* GND* GND* 70 58 - - - vO 1 : : : GND - GND* GND* GND* vO 12 : : : VCCIO - VCCIO* VCCIO* - vO 13 : : : /0 59 - - - vO 14 : : : /0 60 - - - vO 15 : : : /0 61 - - - vO 16 : : : /0 62 - - - 0 17 D26 A3t G5 70 53 - Goo UE 0 18 A28 E27 F2 70 5 - = ve vO 19 B27 Cea H4 V0 65 D20 B22 U7 vo 20 C26 B30 a 0 66 B21 Det U3 vO 24 D2s be? Jb V0 67 C20 C2 v2 vo 22 A27 C28 L? 0 68 B20 B21 V4 VCCIO : vecior | vecio* | vecio* 70 50 rr =50 V6 GND : GND* GND" GND" 0 70 Dig Aes W5 1/0 (A13) 23 B26 E26 3 SND - GND* GND* GND* VO (A12) 24 b24 B29 K4 VCCIO : veclo* vecio* | voecio vo 25 C25 B28 He 0 (A11) 71 C19 D20 W7 vo 26 A26 D26 Ls 1/0 (A10) 72 B19 C20 Y4 vO 27 Bes Cer a To) 73 At9 B20 AAI vo 28 b23 E26 M6 0 74 Bis E19 6 vo 29 : A28 Ke 70 (A18) 75 D18 D19 AB2 vo 30 : A27 N? /0 (A19) 76 C18 C19 8 vo 31 : : : 0 77 - - - vO 32 : : : /0 78 - - - vo 33 : : : 0 79 - - - vO 34 : : : /0 80 - - - VCCIO - vecior | vecio* | vccio* 70 31 - - - GND : GND* GND* GND* 70 3 - - - vO 38 : : : GND - GND* GND* GND* vO 36 : : : VCCIO - VCCIO* VCCIO* - vO 37 : : : /0 83 - - - vO 38 : : : /0 84 - - - 0 39 : D25 P8 70 35 - - - 0 40 : C26 13 70 36 - - - vo 44 : E24 U1 0 87 : AIS AA3 vO 42 : B26 M4 VO 88 - D18 AAS vo 43 C24 C25 Pe 0 89 Bi7 E18 ACI vo 44 Be4 bea N5 To) 90 Ci7 C18 AAT vo 45 C23 Bes Ri 1/0 (AQ) 94 AI7 Bis AB4 vo 46 bee E23 N3 70 (A8) 92 DI7 At7 ABG veclo : VCCIO" VOCIO" : VCCIO - VCCIO* vecio* | vccio* February 1, 1999 (Version 1.0) 6-273XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40250XV Pinout Table (Continued) XC40250XV Pinout Table (Continued) Pad Name Ped BG432 BG560 PG559 Pad Name Peds BG432 BG560 PG559 GND - GND* GND* GND* GND - GND* GND* GND* 0 (A7) 93 A16 D17 AC3 VccloO - vcclo VCCIO* - /0 (A6) 94 B16 E17 AC5 Vo 139 C10 Dit AJ7 VCCINT - C16 C17 VCCINT* V0 140 Bg C10 AP2 V0 95 - - AD2 V0 144 cg AQ AN3 V0 96 A15 B17 AC7 V0 142 Dio E14 AP4 V0 97 - B16 AF2 V0 143 - cg ARI V0 98 - D16 AD4 V0 144 - Dio AN5 V0 99 - - - V0 145 - AS AM6 V0 100 - - - V0 146 - B8 AK8 V0 101 - - - V0 147 - - - V0 102 - - - V0 148 - - - VccloO - VCCIO* VCCIO* - V0 149 - - - GND - GND* GND* GND* V0 150 - - - V0 103 - - - GND - GND* GND* GND* V0 104 - - - VccloO - VCCIO* VCCIO* VCCIO* V0 105 - - - V0 151 - - - V0 106 - - - V0 152 - - - V0 107 - - - V0 153 - - - V0 108 - - - V0 154 - - - /0 (A20) 109 B15 E16 AD6 V0 155 - E10 AL7 /0 (A21) 110 C15 C16 AE5 V0 156 - C8 AT2 V0 111 D15 A15 AF4 V0 157 AS De AR3 Vo 112 B14 C15 AGI Vo 158 B8 B7 AUt /0 (A5) 113 A13 D15 AD8 V0 159 De AG AT4 0 (A4) 114 C14 E15 AG3 Vo 160 B7 E9 AV2 VccloO - VCCIO* VCCIO* VCCIO* V0 161 C7 C7 ARS GND - GND* GND* GND* Vo 162 bs bs AN7 V0 115 B13 B14 AH4 GND - GND* GND* GND* V0 116 D14 C14 AE7 VccloO - VCCIO* VCCIO* VCCIO* V0 117 Ai2 D14 AH2 V0 163 AG AS AW3 V0 118 C13 A13 AF6 V0 164 B6 BS AV4 V0 119 B12 E14 Adt 1/0 (A3) 165 D7 E8 BAt V0 120 D13 C13 AGS /0,, (CS1, A2) 166 AS C6 AUS V0 121 - D13 AJ3 V0 167 C6 D7 AY2 V0 122 - B12 AK4 V0 168 BS B4 AT6 V0 123 - - - V0 169 - - - V0 124 - - - V0 170 - - - V0 125 - - - V0 171 - - - V0 126 - - - V0 172 - - - VccloO - VCCIO* VCCIO* - V0 173 - - - GND - GND* GND* GND* V0 174 - - - V0 127 - - - GND - GND* GND* GND* V0 128 - - - VccloO - VCCIO* VCCIO* - V0 129 - - - V0 175 - - - V0 130 - - - V0 176 - - - V0 131 - C12 AG7 V0 177 - - - V0 132 - E13 AK2 V0 178 - - - Vo 133 C12 Att AJ5 Vo 179 D C5 APS V0 134 B14 D12 AL3 V0 180 A4 E7 AR7 vcclo - VCClo* VCClO* VCCIO* Vo 181 C5 A3 AY4 V0 135 D12 B14 AM4 V0 182 - - BB2 V0 136 Cit Cit AN1 VCCINT - B4 D VCCINT* VCCINT - A10 E12 VCCINT* VO, GCK7 (A1) 183 DS A2 AV6 V0 137 - - AL5 /0 (AO, AWS) 184 B3 DS AT8 V0 138 B10 B10 AH8 GND - GND* GND* GND* 6-274 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40250XV Pinout Table (Continued) XC40250XV Pinout Table (Continued) Pad Name Ped BG432 BG560 PG559 Pad Name Peds BG432 BG560 PG559 0, TDO - C4 E6 BA3 GND - GND* GND* GND* VccloO - VCCIO* VCCIO* VCCIO* V0 231 K4 K3 BA13 CCLK - D4 C4 BAS Vo 232 - - AY14 /0,CK6 (DOUT) 185 D3 D4 BB4 VCCINT - K3 Jf VCCINT* 1/0 (DO, DIN) 186 C2 E4 AY6 VO, FCLK4 233 K2 L4 BC15 V0 187 be F5 BC3 V0 234 KA K2 AW15 V0 188 E4 B3 AW7 VccloO - VCCIO* VCCIO* VCCIO* V0 189 D1 D3 BB6 V0 235 - - - V0 190 E3 F4 Aug V0 236 - - - V0 191 - - - V0 237 - - - V0 192 - - - V0 238 - - - V0 193 - - - V0 239 - M5 BA15 V0 194 - - - V0 240 - 3 AUI7 VccloO - VCCIO* VCCIO* - V0 241 3 uy BB16 GND - GND* GND* GND* /0 (D2) 242 L2 M4 AY16 V0 195 - - - GND - GND* GND* GND* V0 196 - - - VccloO - VCCIO* VCCIO* - V0 197 - - - V0 243 M4 M3 AW17 V0 198 - - - V0 244 M3 N5 AV18 V0 199 E2 Ct AT10 V0 245 - M2 BAI7 V0 200 F4 G5 AV8 V0 246 - N4 BC17 V0 201 1 E3 AY8 V0 247 - - - V0 202 F3 be BC7 V0 248 - - - Vo 203 - - - Vo 249 - - - V0 204 - - - V0 250 - - - 0 (/RCK, RDY_/BUSY)| 205 F2 G4 Awa Vo 251 M2 N3 AU19 /0 (D1) 206 G4 F3 BAg V0 252 M1 N2 BB18 vcclo - VCClo* VCCIO* VCCIO* Vo 253 N4 P5 AY18 GND - GND* GND* GND* V0 254 N3 Ni AW19 V0 207 - - - GND - GND* GND* GND* V0 208 - - - VccloO - VCCIO* VCCIO* VCCIO* V0 209 - H5 AUt4 V0 255 - - - V0 210 - E2 AY10 V0 256 - - - V0 att Fi F2 BB8 V0 257 - - - V0 212 G3 H4 AW11 V0 258 - - - V0 213 G2 G3 BC9 V0 259 - - - V0 214 H4 J5 AV12 V0 260 - - - V0 215 H3 Fi AU13 V0 261 N2 P4 AV20 V0 216 H2 G1 AT14 V0 262 Ni P3 AT20 V0 217 - - - V0 263 P4 P2 BB20 V0 218 - - - V0 264 P3 R5 AY20 VccloO - VCCIO* VCCIO* VCCIO* V0 265 P2 R4 Bc2t GND - GND* GND* GND* V0 266 R3 R3 BA24 V0 219 - - - GND - GND* GND* GND* V0 220 - - - VccloO - VCCIO* VCCIO* - V0 221 - - - V0 267 R4 Ri Awe V0 222 - - - V0 268 - T4 AU24 V0 223 - J4 BA11 V0 269 - T5 BB22 Vo 224 - H3 AY12 Vo 270 - - AY22 V0 225 - K5 BB10 V0 271 - - - Vo 226 - H2 AW13 Vo 272 - - - V0 227 H1 J3 BCt1 V0 273 - - - V0 228 J4 K4 AU15 V0 274 - - - V0 229 J3 J2 BB14 VCCINT - R2 73 VCCINT* V0 230 J2 L5 AT16 /0 (/RS) 275 Ri T2 AV22 VccloO - VCCIO* VCCIO* - /0 (D3) 276 73 U3 BA23 February 1, 1999 (Version 1.0) 6-275XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40250XV Pinout Table (Continued) XC40250XV Pinout Table (Continued) Pad Name Ped BG432 BG560 PG559 Pad Name Peds BG432 BG560 PG559 GND - GND* GND* GND* GND - GND* GND* GND* VccloO - VCCIO* VCCIO* VCCIO* VccloO - VCCIO* VCCIO* - Vo 277 T2 U4 AW23 Vo 323 AB4 AD3 AT28 /0 (D4) 278 TI U5 AY24 V0 324 AC2 AE1 AU29 V0 279 - - - V0 325 ADI AC5 BC33 V0 280 - - - V0 326 AC3 AE3 AY34 V0 281 - - - V0 327 - AD4 BB34 V0 282 - - - V0 328 - AFI AW33 V0 283 - ud BC23 V0 329 - AF2 AU31 V0 284 - U2 BA27 V0 330 - AD5 AV32 V0 285 U3 v2 AU23 V0 331 - - - V0 286 U4 v4 Av24 V0 332 - - - VccloO - VCCIO* VCCIO* - V0 333 - - - GND - GND* GND* GND* V0 334 - - - V0 287 U2 V5 AY26 GND - GND* GND* GND* V0 288 ud V3 BB24 VccloO - VCCIO* VCCIO* VCCIO* V0 289 V3 wi AW25 V0 335 - - - V0 290 v4 W3 BB26 V0 336 - - - V0 291 v2 w4 AT24 V0 337 - - - V0 292 we W5 BAzg V0 338 - - - V0 293 - - - V0 339 - AG2 AT30 V0 204 - - - V0 340 - AE4 AU33 V0 295 - - - V0 341 AC4 AF3 AW35 Vo 296 - - - Vo 342 AD2 AH1 BC35 V0 297 - - - V0 343 AE2 AE5 AY36 Vo 298 - - - Vo 344 AD3 AG3 BB36 VccloO - VCCIO* VCCIO* VCCIO* V0 345 AD4 AF4 AV36 GND - GND* GND* GND* /0 (D6) 346 AFI AJt AU35 V0 299 W3 Y2 AY28 GND - GND* GND* GND* V0 300 w4 Y3 AU25 VccloO - VCCIO* VCCIO* VCCIO* V0 301 - Y4 AV26 V0 347 AF2 AJ2 AT34 V0 302 - AAt BC27 V0 348 AE3 AF5 AW37 V0 303 - - - V0 349 - - - V0 304 - - - V0 350 - - - V0 305 - - - V0 351 - - - V0 306 - - - V0 352 - - - V0 307 wi Y5 AW27 V0 353 AE4 AH3 BC37 V0 308 Y1 AA3 BB28 V0 354 AGI AG4 AY38 V0 309 Y3 AA4 BA31 V0 355 AG2 AK2 BB38 V0 310 Y4 AB2 AY30 V0 356 AF3 AJ3 BA41 VccloO - VCCIO* VCCIO* VCCIO* V0 357 - - - GND - GND* GND* GND* V0 358 - - - 0 (C80) 311 Y2 AB3 Aweg GND - GND* GND* GND* 1/0 (D5) 312 AA2 AAS BC29 VccloO - VCCIO* VCCIO* - V0 313 - ACI AU27 V0 359 - - - V0 314 - AB4 BA33 V0 360 - - - V0 315 - - - V0 361 - - - V0 316 - - - V0 362 - - - Vo 317 - - - Vo 363 AF4 AGS AY40 V0 318 - - - V0 364 AH1 ALt BB40 vcclo - VCClo* VCClO* VCCIO* Vo 365 AH2 AH4 AT36 V0 319 AA3 AC3 AY32 V0 366 AG3 AK3 BA39 VO, FCLK3 320 ABI AB5 AW31 VO, GCK5 367 AG4 AJ4 AV38 VCCINT - AB2 AD2 VCCINT* /0 (D7) 368 AJ2 AH5 BC41 V0 321 - - BB30 /PROGRAM - AH3 AM1 BB42 V0 322 AB3 AC4 BA35 VccloO - VCCIO* VCCIO* VCCIO* 6-276 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40250XV Pinout Table (Continued) XC40250XV Pinout Table (Continued) Pad Name Ped BG432 BG560 PG559 Pad Name Peds BG432 BG560 PG559 DONE - AH4 AUS AY42 GND - GND* GND* GND* GND - GND* GND* GND* V0 415 AK AM10 AL39 VO, GCK4 369 AJ4 AL4 AW41 Vo 416 - - AH36 V0 370 AK3 AJB AV40 VCCINT - AJ10 AK11 VCCINT* VCCINT - AH5 AK5 VCCINT* V0 417 AK10 AL11 AH42 V0 371 - - AV42 V0 418 AL10 AJ12 AJ39 V0 372 AK4 AN3 AR37 VccloO - VCCIO* VCCIO* VCCIO* V0 373 AUS AK6 AP36 V0 419 AJt1 AN14 AK40 V0 374 AH6 AL5 AT38 V0 420 AH12 AK12 AG41 V0 375 - - - V0 421 - AL12 AJ V0 376 - - - V0 422 - AM12 AH40 V0 377 - - - V0 423 - - - V0 378 - - - V0 424 - - - VccloO - VCCIO* VCCIO* - V0 425 - - - GND - GND* GND* GND* V0 426 - - - V0 379 - - - GND - GND* GND* GND* V0 380 - - - VccloO - VCCIO* VCCIO* - V0 381 - - - V0 427 - - - V0 382 - - - V0 428 - - - V0 383 - - - V0 429 - - - V0 384 - - - V0 430 - - - V0 385 AL4 AJ7 AU39 V0 431 - AJ13 AG37 V0 386 AK5 AM4 AU43 V0 432 - AK13 AG43 Vo 387 AJB AM5 BA43 Vo 433 AK11 AL13 AG39 V0 388 AH7 AK7 AT42 V0 434 AJ12 AM13 AF38 Vo 389 ALS AL6 AR39 Vo 435 AK12 AN13 AF42 V0 390 AK6 AJ8 AN37 V0 436 AL12 AJ14 AD42 vcclo - VCClo* VCClO* VCCIO* Vo 437 AH13 AK14 AF40 GND - GND* GND* GND* V0 438 AJ13 AL14 AE37 V0 391 AH8 AM6 AT40 GND - GND* GND* GND* V0 392 AJ7 AN6 AP40 VccloO - VCCIO* VCCIO* VCCIO* V0 393 AL6 AK8 AR43 V0 439 AK13 AM14 AE39 V0 304 AK7 AL7 AN39 V0 440 AL13 AN15 AD40 V0 395 AHg AJg AP42 V0 441 AK14 AJ15 AC43 V0 396 AJ8 AN7 AM38 V0 442 AH14 AK15 AD38 V0 397 - AL8 AN43 V0 443 AJ14 AL15 AC41 V0 398 - AK AL37 V0 444 AK15 AM16 AD36 V0 399 - - - V0 445 - - - V0 400 - - - V0 446 - - - V0 401 - - - V0 447 - - - V0 402 - - - V0 448 - - - VccloO - VCCIO* VCCIO* VCCIO* V0 449 - - - GND - GND* GND* GND* V0 450 - - - V0 403 - - - GND - GND* GND* GND* V0 404 - - - VccloO - VCCIO* VCCIO* - V0 405 - - - V0 451 - - - V0 406 - - - V0 452 - - - V0 407 - AM8 AK36 V0 453 - - - Vo 408 - AJ10 AR41 Vo 454 - - - V0 409 - ALQ AL41 V0 455 - AL16 AC39 Vo 410 - AMg AN44 Vo 456 - AJ16 AC37 V0 att AK8 AK10 AK42 V0 457 AJ15 AK16 AB40 V0 412 AJg ANQ AM40 V0 458 AL15 AN17 AB42 V0 413 AH10 AJt1 AJ43 VCCINT - AH15 AM17 VCCINT* V0 414 AL8 AL10 AJ37 V0 459 - - AB38 VccloO - VCCIO* VCCIO* - V0 460 AL16 AL17 AAA1 February 1, 1999 (Version 1.0) 6-277XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40250XV Pinout Table (Continued) XC40250XV Pinout Table (Continued) Pad Name Ped BG432 BG560 PG559 Pad Name Peds BG432 BG560 PG559 GND - GND* GND* GND* GND - GND* GND* GND* VccloO - VCCIO* VCCIO* VCCIO* VccloO - VCCIO* VCCIO* - 0 (NIT) 461 AK16 AJ17 AA39 Vo 507 AK23 AL24 L441 V0 462 AJ16 AK17 AA37 V0 508 AJ23 AN26 L43 V0 463 AL17 AM18 Y40 V0 509 AH22 AJ23 K40 V0 464 AK17 AL18 Y38 V0 510 AL24 AL25 K42 V0 465 - AK18 AA43 V0 511 - AK24 L39 V0 466 - AJ18 weg V0 512 - AM26 J43 V0 467 - - - V0 513 - AM27 M38 V0 468 - - - V0 514 - AJ24 P36 V0 469 - - - V0 515 - - - V0 470 - - - V0 516 - - - VccloO - VCCIO* VCCIO* - V0 517 - - - GND - GND* GND* GND* V0 518 - - - V0 471 - - - GND - GND* GND* GND* V0 472 - - - VccloO - VCCIO* VCCIO* VCCIO* V0 473 - - - V0 519 - - - V0 474 - - - V0 520 - - - V0 475 - - - V0 521 - - - V0 476 - - - V0 522 - - - V0 477 AJ17 AN19 v40 V0 523 - AL26 N37 V0 478 AH17 AL19 Y36 V0 524 - AK25 H42 V0 479 AK18 AK19 U4 V0 525 AK24 AN28 J41 Vo 480 AL19 AM20 Y42 Vo 526 AH23 AN29 G43 V0 481 AJ18 AJ19 T40 V0 527 AJ24 AJ25 H490 Vo 482 AKi9 AL20 w37 Vo 528 AK25 AL27 F42 VccloO - VCCIO* VCCIO* VCCIO* V0 529 AJ25 AK26 J39 GND - GND* GND* GND* Vo 530 AH24 AM29 L37 V0 483 AH18 AK20 V38 GND - GND* GND* GND* V0 484 AL20 AN24 U39 VccloO - VCCIO* VCCIO* VCCIO* V0 485 AJ19 AL21 v42 V0 531 AL26 AM30 E41 V0 486 AK20 AJ20 R41 V0 532 AK26 AJ26 F40 V0 487 AH19 AM22 U43 V0 533 AH25 AL28 C43 V0 488 AJ20 AK21 P40 V0 534 AL27 AK27 G39 V0 489 - AN23 T42 V0 535 AJ26 AL29 D42 V0 490 - AL22 U37 V0 536 AK27 AN31 H38 V0 491 - - - V0 537 - - - V0 492 - - - V0 538 - - - V0 493 - - - V0 539 - - - V0 494 - - - V0 540 - - - VccloO - VCCIO* VCCIO* VCCIO* V0 541 - - - GND - GND* GND* GND* V0 542 - - - V0 495 - - - GND - GND* GND* GND* V0 496 - - - VccloO - VCCIO* VCCIO* - V0 497 - - - V0 543 - - - V0 498 - - - V0 544 - - - V0 499 - AJ21 R39 V0 545 - - - V0 500 - AM23 N41 V0 546 - - - Vo 501 AK21 AK22 R43 0 (LDC) 547 AH26 AJ27 K36 V0 502 AH20 AM24 M40 V0 548 AL28 AM31 J37 vcclo - VCClo* VCClO* - Vo 549 AJ27 AK28 B42 V0 503 AJ21 AL23 N39 V0 550 AK28 AL30 D490 V0 504 AL22 AJ22 T36 0 (HDC) 551 AH27 AK29 C41 VCCINT - AK22 AN25 VCCINT* V0, GCK3 552 AK29 AJ28 F38 V0 505 - - P42 | (M2) - AJ28 AN32 H36 V0 506 AJ22 AK23 R37 VccloO - VCCIO* VCCIO* VCCIO* 6-278 February 1, 1999 (Version 1.0)$= XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40250XV Pinout Table (Continued) XC40250XV Pinout Table (Continued) Pad Name Ped BG432 BG560 PG559 Pad Name Peds BG432 BG560 PG559 | (MO) - AH28 AJ29 c39 VCClO - VCCIO* VCCIO* - GND - GND* GND* GND* GND - GND* GND* GND* O (M1) - AH29 AK30 D38 VO, FCLK2 599 AB29 AC30 E29 VO, GCK2 553 AJ30 AH29 E37 V0 600 - - C29 V0 554 AH30 AJ30 B40 VCCINT - AB30 AD32 VCCINT* VCCINT - AG28 AK31 VCCINT* V0 601 AB31 AB29 B30 V0 555 - - H34 V0 602 AA29 AC31 G27 V0 556 AH314 AH30 G35 VccloO - VCCIO* VCCIO* VCCIO* V0 557 AG29 AL33 F36 V0 603 - - - V0 558 AG30 AG29 D36 V0 604 - - - V0 559 - - - V0 605 - - - V0 560 - - - V0 606 - - - V0 561 - - - V0 607 - AC33 b28 V0 562 - - - V0 608 - AB30 A29 VccloO - VCCIO* VCCIO* - V0 609 AA30 AB31 E27 GND - GND* GND* GND* V0 610 Y28 AA29 F26 V0 563 AF28 AJ31 E35 GND - GND* GND* GND* V0 564 AG31 AK32 A4t VccloO - VCCIO* VCCIO* - V0 565 AF29 AG30 G33 V0 611 Y29 AB32 C27 V0 566 AF30 AH31 B38 V0 612 30 AA30 B28 V0 567 - - - V0 613 Y31 AA31 G25 V0 568 - - - V0 614 W28 AA32 A27 V0 569 - - - V0 615 - - - Vo 570 - - - Vo 616 - - - V0 571 - - - V0 617 - - - Vo 572 - - - Vo 618 - - - V0 573 AE28 AF29 D34 V0 619 - Y29 D26 Vo 574 AF31 AJ32 E33 Vo 620 - AA33 B26 VccloO - VCCIO* VCCIO* VCCIO* V0 621 wee 30 E25 GND - GND* GND* GND* V0 622 W30 Y31 F24 V0 575 AE29 AH32 F32 GND - GND* GND* GND* V0 576 AE30 AF30 G3t VccloO - VCCIO* VCCIO* VCCIO* V0 577 AD28 AG31 A37 V0 623 - - - V0 578 AD29 AE29 H30 V0 624 - - - V0 579 AD30 AH33 B36 V0 625 - - - V0 580 AD31 AG33 C33 V0 626 - - - V0 581 - AE30 C35 V0 627 - - - V0 582 - AF31 D32 V0 628 - - - V0 583 - - - V0 629 wet 32 H24 V0 584 - - - V0 630 V28 wee B24 V0 585 - - - V0 631 v29 W30 p24 V0 586 - - - V0 632 V30 wet A23 VccloO - VCCIO* VCCIO* VCCIO* V0 633 U29 w33 C23 GND - GND* GND* GND* V0 634 U28 V30 E23 V0 587 - - - GND - GND* GND* GND* V0 588 - - - VccloO - VCCIO* VCCIO* - V0 589 - - - V0 635 U30 v29 G23 V0 590 - - - V0 636 U3t v31 B22 Vo 591 - AD29 E34 Vo 637 - V32 bD22 V0 592 - AF32 G29 V0 638 - U33 A2t Vo 593 - AE31 A35 Vo 639 - - - V0 594 - AD30 H28 V0 640 - - - V0 595 AC28 AE32 B34 V0 641 - - - V0 596 AC29 AC29 C31 V0 642 - - - V0 597 AC30 AE33 A33 V0 643 T29 U30 F22 V0 598 AB28 AD31 D30 V0 644 T30 U29 ct February 1, 1999 (Version 1.0) 6-279XC4000XLA/XV Field Programmable Gate Arrays $< XILINX? XC40250XV Pinout Table (Continued) XC40250XV Pinout Table (Continued) Pad Name Ped BG432 BG560 PG559 Pad Name Peds BG432 BG560 PG559 VCClO - VCCIO* VCCIO* VCCIO* VO, FCLK1 690 K28 L30 cg GND - GND* GND* GND* GND - GND* GND* GND* Vo 645 T31 U3t E24 vcclo - VCClo* VCCIO* - V0 646 - - D20 V0 691 J30 K34 H16 VCCINT - R29 U32 VCCINT* V0 692 H31 L29 B10 V0 647 - - - V0 693 J29 H33 G15 V0 648 - - - V0 694 J28 K30 Ag V0 649 - - - V0 695 - J31 D190 V0 650 - - - V0 696 - H32 BS V0 651 - 732 C17 V0 697 - K29 E11 V0 652 - T30 Gat V0 698 - H31 G13 V0 653 R28 T29 F20 V0 699 - - - V0 654 R30 T31 Di8 V0 700 - - - VccloO - VCCIO* VCCIO* - V0 701 - - - GND - GND* GND* GND* V0 702 - - - V0 655 R31 R33 E19 GND - GND* GND* GND* V0 656 P29 R31 B20 VccloO - VCCIO* VCCIO* VCCIO* V0 657 P28 R30 H20 V0 703 - - - V0 658 P30 R29 B18 V0 704 - - - V0 659 N30 P32 C15 V0 705 H30 J30 F12 V0 660 N29 P34 D16 V0 706 G30 G32 H14 V0 661 - - - V0 707 H29 F33 Git V0 662 - - - V0 708 H28 J29 A7 Vo 663 - - - Vo 709 F31 G3t E9 V0 664 - - - V0 710 F30 H30 B6 Vo 665 - - - Vo 711 - E33 bs V0 666 - - - V0 712 - E32 F8 vcclo - VCClo* VCClO* VCCIO* Vo 713 - - - GND - GND* GND* GND* V0 714 - - - V0 667 N28 N33 Gig GND - GND* GND* GND* V0 668 N31 P30 Ai7 VccloO - VCCIO* VCCIO* VCCIO* V0 669 M31 P29 F418 V0 715 G29 H29 G9 V0 670 M29 M32 E17 V0 716 G28 F31 H10 V0 671 - - - V0 717 - - - V0 672 - - - V0 718 - - - V0 673 - - - V0 719 E31 G30 B4 V0 674 - - - V0 720 E30 D32 E7 V0 675 - N31 B16 V0 721 F29 E31 C5 V0 676 - N30 C13 V0 722 F28 G29 D V0 677 M28 L33 A15 V0 723 - - - V0 678 M30 N29 D14 V0 724 - - - VccloO - VCCIO* VCCIO* - V0 725 - - - GND - GND* GND* GND* V0 726 - - - V0 679 L30 M31 E15 GND - GND* GND* GND* V0 680 L29 [32 G17 VccloO - VCCIO* VCCIO* - V0 681 - M30 B14 V0 727 - - - V0 682 - L31 Cit V0 728 - - - V0 683 - - - V0 729 - - - Vo 684 - - - Vo 730 - - - V0 685 - - - 0 (TCK) 731 D31 C33 D4 Vo 686 - - - /0 (TDI) 732 D30 F30 H8 VccloO - VCCIO* VCCIO* VCCIO* V0 733 E29 D31 A3 V0 687 K34 M29 D12 V0 734 - - F6 /O (TMS) 688 K30 J33 Att VCCINT - E28 E30 VCCINT* VCCINT - K29 K32 VCCINT* 0 (A17) 735 C30 F29 C3 V0 689 - - E13 0, GCK1 (A16) 736 D29 B33 C1 6-280 February 1, 1999 (Version 1.0)3. XILINX XC4000XLA/XV Field Programmable Gate Arrays XC40250XV Pinout Table (Continued) XC40250XV Pinout Table (Continued) Pad Name oes BG432 BG560 PG559 Pad Name Peds BG432 BG560 PG559 GND : GND* GND* GND* VCCINT : : : AF36 VCCINT : : : AME VCCIO - At Ad A13 VCCINT : : : AM36 VCCIO : At At0 A31 VCCINT : : : ATI2 VCCIO : A241 At6 Aas VCCINT : : : ATIB VCCIO : A31 A22 Ba VCCINT : : : AT26 VCCIO : Dt A26 C7 VCCINT : : : ATS2 VCCIO : D241 A30 C19 VCCIO : 4 Ba C25 GND - A2 AT AS VCCIO : \4 B13 C37 GND : AB Ate A19 VCCIO : [28 B19 Fi4 GND : AT At4 A25 VCCIO : (31 B32 F30 GND : Ao At8 A39 VCCIO : AAI C3 G3 GND : At4 A20 Bia VCCIO : AAA C3t G7 GND : At8 Ad B32 VCCIO : AA28 C32 G37 GND : A23 A29 EH VCCIO : AAS D1 Gat GND : A25 A32 ES VCCIO : AH D33 Ni GND : A29 Bt E39 VCCIO : AH? ES N43 GND : A30 Be E43 VCCIO : AL Hy P6 GND : Bt Bg F10 VCCIO : ALi K33 P38 GND : Ba B15 F16 VCCIO : AL2t MA W3 GND : B30 B23 F28 VCCIO : AL3t N32 wat GND : Bat B27 F34 VCCIO : C3 Re AES GND : Ct Bat Hee VCCIO : C29 733 AEAI GND : Cat C2 K6 VCCIO : Al3 Vi AK6 GND : Di6 EH K38 VCCIO : AJ29 w32 AK38 GND : Gi F32 M2 VCCIO : : AA2 AL GND : Gat Ga M42 VCCIO : : AB33 AL43 GND : wt G33 T6 VCCIO : : ADI AUS GND : J31 J32 T38 VCCIO : : AF33 AUT GND : Py KA wi VCCIO : : AKA AU37 GND : Pat l2 w43 VCCIO : : AK4 AUAI GND : TA M33 ABS VCCIO : : AK33 AVI4 GND : T28 Py AB36 VCCIO : : AL2 AV30 GND : Vi P33 AEt VCCIO : : ALS BAT GND : Vv31 R32 AE43 VCCIO : : AL3t BATS GND : ACI TH AH6 VCCIO : : AM2 BA25 GND : AC31 V33 AH38 VCCIO : : AM15 BA37 GND : AEX we AM2 VCCIO : : AM21 BCT GND : AES1 v1 AM42 VCCIO : : AM32 BC13 GND : AHt6 33 APG VCCIO : : ANA BOs GND : AS ABI AP38 VCCIO : : ANS BC43 GND : Ast AC32 AT22 VCCIO : : ANi2 : GND : AKA AD33 AVI0 VCCIO : : ANi8 : GND : AK2 AE2 AVI6 VCCIO : : AN24 : GND : AK30 AGI AV28 VCCIO : : AN30 : GND : AK31 AG32 AV34 GND : AL2 AH2 AW! VCCINT - - - Ht2 GND : ALS A383 AWS VCCINT : : : H18 GND : ALT AL32 AW39 VCCINT : : : H26 GND : ALS AM3 AW43 VCCINT : : : H32 GND : AL4 AM11 BB12 VCCINT : : : Ma GND : ALi8 AM19 BB32 VCCINT : : : M36 GND : AL23 AM25 BCS VCCINT : : : V8 GND : AL25 AM28 BC19 VCCINT : : : V36 GND : AL2g AM33 BC25 VCCINT : : : AFB GND : AL30 AM7 BC39 February 1, 1999 (Version 1.0) 6-281XC4000XLA/XV Field Programmable Gate Arrays XC40250XV Pinout Table (Continued) Pad Name oes BG432 BG560 PG559 GND AN2 GND ANS GND AN10 GND AN14 GND ANi6 GND AN20 GND AN22 GND AN27 NG C8 Al NC A338 NC Ace NC ANt NC AN33 12/21/98 *Note: Pads labelled GND*, VCCINT*, or VCCIO are inter- nally bonded to the corresponding power plane within the associated package. They have no direct connection to any specific package pin. $< XILINX? 6-282 February 1, 1999 (Version 1.0)