WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 1 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
I/O8
I/O9
I/O10
A14
A16
A11
A0
A18
I/O0
I/O1
I/O2
RESET#
CS2#
GND
I/O11
A10
A9
A15
VCC
CS1#
A19
I/O3
I/O15
I/O14
I/O13
I/O12
OE#
A17
WE#
I/O7
I/O6
I/O5
I/O4
I/O24
I/O25
I/O26
A7
A12
A21
A13
A8
I/O16
I/O17
I/O18
VCC
CS4#
NC
I/O27
A4
A5
A6
A20
CS3#
GND
I/O19
I/O31
I/O30
I/O29
I/O28
A1
A2
A3
I/O23
I/O22
I/O21
I/O20
11 22 33 44 55 66
1 12 23 34 45 56
FIGURE 1 – PIN CONFIGURATION FOR
WF4M32-XH2X5
Top View
4Mx32 5V NOR FLASH MODULE
FEATURES
Access Times of 100, 120, 150ns
Packaging:
• 66 pin, PGA Type, 1.385" square, Hermetic Ceramic HIP
(Package 402).
• 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square
(Package 509) 4.57mm (0.180") height. Designed to fi t
JEDEC 68 lead 0.990CQFJ footprint (Fig. 3)
Sector Architecture
• 32 equal size sectors of 64KBytes per each 2Mx8 chip
• Any combination of sectors can be erased. Also supports
full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
Organized as 4Mx32
User confi gurable as 2x4Mx16 or 4x4Mx8 in HIP.
Commercial, Industrial, and Military Tem per a ture Ranges
5 Volt Read and Write. 5V ± 10% Sup ply.
Low Power CMOS
Data# Polling and Toggle Bit feature for detection of
program or erase cycle com ple tion.
Supports reading or programming data to a sector not being
erased.
RESET# pin resets internal state machine to the read
mode.
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation, Separate Power and Ground Planes to
improve noise immunity
* This product is subject to change without notice.
Note: For programming information refer to Flash Programming 16M5 Application Note.
BLOCK DIAGRAM
I/O0-7
CS1# CS2# CS3# CS4#
I/O8-15 I/O16-23 I/O24-31
OE#
A
0-20
A21
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2Mx 8
2M x 8
2M x 8
WE#
RESET#
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-21 Address Inputs
WE# Write Enable
CS1-4# Chip Select
OE# Output Enable
VCC Power Supply
VSS Ground
RESET# Reset
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 2 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
2M x 8
8
I/O0-7
CS1#
I/O8-15
CS2#
I/O16-23 I/O24-31
A0-20
OE#
WE#
RESET#
2M x 8
2M x 8
8
2M x 8
2M x 8
8
2M x 8
2M x 8
8
2M x 8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VCC
A11
A12
A13
A14
A15
A16
CS1#
OE#
CS2#
A17
NC
NC
NC
A18
A19
A20
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
RESET#
A0
A1
A2
A3
A4
A5
NC
GND
NC
WE#
A6
A7
A8
A9
A10
VCC
FIGURE 2 – PIN CONFIGURATION FOR WF4M32-XG2TX5
TOP VIEW
The White 68 lead G2T CQFP fi lls the same fi t and function
as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has
the TCE and lead inspection advantage of the CQFP form.
Block Diagram
Note: CS1#& CS2# are used as bank select
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-21 Address Inputs
WE# Write Enable
CS1-2# Chip Select
OE# Output Enable
VCC Power Supply
GND Ground
RESET# Reset
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 3 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
HIP = 66 pin, PGA Type, 1.385" square, Hermetic Ceramic HIP (Package 402).
G2T = 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square. Designed to fi t JEDEC 68
lead 0.990" CQFJ footprint (Fig. 3) (Package 509)
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Ratings Unit
Voltage on Any Pin Relative to VSS V
T-2.0 to +7.0 V
Power Dissipation PT8W
Storage Temperature TSTG -65 to +125 °C
Short Circuit Output Current IOS 100 mA
Endurance — write/erase cycles (Mil Temp) 100,000 min. cycles
Data Retention (Mil Temp) 20 years
RECOMMENDED DC OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 000V
Input High Voltage VIH 2.0 – VCC + 0.5 V
Input Low Voltage VIL -0.5 – +0.8 V
Operating Temperature (Mil.) TA -55 – +125 °C
Operating Temperature (Ind.) TA -40 – +85 °C
DC CHARACTERISTICS – CMOS COMPATIBLE
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter Symbol Conditions
HIP G2T G4T
Min Max Min Max Min Max Unit
Input Leakage Current ILI VCC = 5.5, VIN = GND to VCC 10 10 10 μA
Output Leakage Current ILOX32 VCC = 5.5, VIN = GND to VCC 10 10 10 μA
VCC Active Current for Read (1) ICC1 CS# = VIL, OE# = VIH, f = 5MHz 320 215 345 mA
VCC Active Current for Program or Erase (2) ICC2 CS# = VIL, OE# = VIH 420 295 445 mA
VCC Standby Current ICC3 VCC = 5.5, CS# = VIH,
f = 5MHz, RESET# = VIH
20 2.0 95 mA
Output Low Voltage VOL IOL = 12.0 mA, VCC = 4.5 0.45 0.45 0.45 V
Output High Voltage VOH IOH = -2.5 mA, VCC = 4.5 0.85 x
VCC
0.85 x
VCC
0.85 x
VCC
V
Low VCC Lock-Out Voltage VLKO 3.2 4.2 3.2 4.2 3.2 4.2 V
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent
component (@ 5MHz). The frequency component typically is less than 2mA/MHz, with OE# at
VIH.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions VIL = 0.3V, VIH = VCC - 0.3V
CAPACITANCE
TA = +25°C, VIN = OV, F = 1.0MHz
Parameter Symbol HIP (H2) CQFP (G2T) CQFP(G4T)
OE# capacitance COE 75 75 20
WE# capacitance CWE 75 75 20
CS# capacitance CCS 20 50 20
Data I/O capacitance CI/O 30 30 30
Address input capacitance CAD 75 75 20
This parameter is guaranteed by design but not tested.
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 4 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE# CONTROLLED
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter Symbol -100 -120 -150 UnitMin Max Min Max Min Max
Write Cycle Time tAVAV tWC 100 120 150 ns
Chip Select Setup Time tELWL tCS 000ns
Write Enable Pulse Width tWLWH tWP 45 50 50 ns
Address Setup Time tAVWL tAS 000ns
Data Setup Time tDVWH tDS 45 50 50 ns
Data Hold Time tWHDX tDH 000ns
Address Hold Time tWLAX tAH 45 50 50 ns
Write Enable Pulse Width High tWHWL tWPH 20 20 20 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 μs
Sector Erase (2) tWHWH2 15 15 15 sec
Read Recovery Time before Write tGH
W
L000μs
VCC Setup Time tVCS 50 50 50 μs
Chip Programming Time 44 44 44 sec
Chip Erase Time (3) 256 256 256 sec
Output Enable Hold Time (4) tOEH 10 10 10 ns
RESET# Pulse Width tRP 500 500 500 ns
NOTES:
1. Typical value for tWHWH1 is 7μs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
AC CHARACTERISTICS – READ-ONLY OPERATIONS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter Symbol -1000 -120 -150 UnitMin Max Min Max Min Max
Read Cycle Time TAVAV TRC 100 120 150 ns
Address Access Time TAVQV TACC 100 120 150 ns
Chip Select Access Time TELQV TCE 100 120 150 ns
Output Enable to Output Valid TGLQV TOE 40 50 55 ns
Chip Select High to Output High Z (1) TEHQZ TDF 20 30 35 ns
Output Enable High to Output High Z (1) TGHQZ TDF 20 30 35 ns
Output Hold from Addresses, CS# or OE# Change,
whichever is First
TAXQX TOH 000ns
RESET# Low to Read Mode (1) TREADY 20 20 20 μs
1. Guaranteed by design, not tested.
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 5 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
AC CHARACTERISTICS FOR G2T PACKAGE – WRITE/ERASE/PROGRAM OPERATIONS,
CS# CONTROLLED
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Parameter Symbol -100 -120 -150 UnitMin Max Min Max Min Max
Write Cycle Time tAVAV tWC 100 120 150 ns
Write Enable Setup Time tWLEL tWS 000ns
Chip Select Pulse Width tELEH tCP 45 50 50 ns
Address Setup Time tAVEL tAS 000ns
Data Setup Time tDVEH tDS 45 50 50 ns
Data Hold Time tEHDX tDH 000ns
Address Hold Time tELAX tAH 45 50 50 ns
Chip Select Pulse Width High tEHEL tCPH 20 20 20 ns
Duration of Byte Programming Operation (1) tWHWH1 300 300 300 μs
Sector Erase Time (2) tWHWH2 15 15 15 sec
Read Recovery Time tGHEL 000μs
Chip Programming Time 44 44 44 sec
Chip Erase Time (3) 256 256 256 sec
Output Enable Hold Time (4) tOEH 10 10 10 ns
NOTES:
1. Typical value for tWHWH1 is 7μs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 6 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
AC CHARACTERISTICS FOR H2 PACKAGE – WRITE/ERASE/PROGRAM OPERATIONS - WE# CONTROLLED
VCC = 5.0V, TA = -55°C, -55°C ≤ TA ≤ +125°C
Parameter Symbol -100 -120 -150 UnitMin Max Min Max Min Max
Write Cycle Time tAVAV tWC 100 120 150 ns
Chip Select Setup Time tELWL tCS 000ns
Write Enable Pulse Width tWLWH tWP 45 50 50 ns
Address Setup Time tAVWL tAS 000ns
Data Setup Time tDVWH tDS 45 50 50 ns
Data Hold Time tWHDX tDH 15 15 15 ns
Address Hold Time (1) tWLAX tAH 45 50 50 ns
Write Enable Pulse Width High (2) tWHWL tWPH 20 20 20 ns
Duration of Byte Programming Operation (3) tWHWH1 300 300 300 μs
Sector Erase (4) tWHWH2 15 15 15 sec
Read Recovery Time before Write tGH
W
L000μs
VCC Setup Time tVCS 50 50 50 μs
Chip Programming Time 44 44 44 sec
Chip Erase Time (5) 256 256 256 sec
Output Enable Hold Time (6) tOEH 10 10 10 ns
RESET# Pulse Width tRP 500 500 500 ns
NOTES:
1. A21 must be held constant until WE# or CS# go high, whichever occurs fi rst.
2. Guaranteed by design, but not tested.
3. Typical value for tWHWH1 is 7μs.
4. Typical value for tWHWH2 is 1sec.
5. Typical value for Chip Erase Time is 32sec.
6. For Toggle and Data Polling.
AC CHARACTERISTICS FOR H2 PACKAGE – READ-ONLY OPERATIONS
VCC = 5.0V, TA = -55°C, -55°C ≤ TA ≤ +125°C
Parameter Symbol -1000 -120 -150 UnitMin Max Min Max Min Max
Read Cycle Time TAVAV TRC 100 120 150 ns
Address Access Time TAVQV TACC 100 120 150 ns
Chip Select Access Time TELQV TCE 100 120 150 ns
Output Enable to Output Valid TGLQV TOE 50 50 55 ns
Chip Select High to Output High Z TEHQZ TDF 40 45 45 ns
Output Enable High to Output High Z TGHQZ TDF 40 45 45 ns
Output Hold from Addresses, CS# or OE# Change,
whichever is First
TAXQX TOH 000ns
RESET# Low to Read Mode TREADY 20 20 20 μs
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 7 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
AC CHARACTERISTICS FOR PACKAGE – WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Parameter Symbol -100 -120 -150 UnitMin Max Min Max Min Max
Write Cycle Time tAVAV tWC 100 120 150 ns
Write Enable Setup Time tWLEL tWS 000ns
Chip Select Pulse Width tELEH tCP 45 50 50 ns
Address Setup Time tAVEL tAS 000ns
Data Setup Time tDVEH tDS 45 50 50 ns
Data Hold Time tEHDX tDH 15 15 15 ns
Address Hold Time (1) tELAX tAH 45 50 50 ns
Chip Select Pulse Width High tEHEL tCPH 20 20 20 ns
Duration of Byte Programming Operation (2) tWHWH1 300 300 300 μs
Sector Erase Time (3) tWHWH2 15 15 15 sec
Read Recovery Time tGHEL 000μs
Chip Programming Time 44 44 44 sec
Chip Erase Time (4) 256 256 256 sec
Output Enable Hold Time (5) tOEH 10 10 10 ns
NOTES:
1. A21 must be held constant until WE# or CS# go high, whichever occurs fi rst.
2. Typical value for tWHWH1 is 7μs.
3. Typical value for tWHWH2 is 1sec.
4. Typical value for Chip Erase Time is 32sec.
5. For Toggle and Data Polling.
AC Test Conditions
Parameter Typ Unit
Input Pulse Levels
VIL = 0, VIH = 3.0
V
Input Rise and Fall 5 ns
Input and Output Reference Level 1.5 V
Output Timing Reference Level 1.5 V
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load cir cuit.
ATE tester includes jig capacitance.
Current Source
D.U.T.
C
EFF
= 50 pf
I
OL
I
OH
V
Z
≈ 1.5V
(Bipolar Supply)
Current Source
RESET#
t
RP
t
Ready
FIGURE 4 – AC TEST CIRCUIT
FIGURE 5 – RESET TIMING DIAGRAM
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 8 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
FIGURE 6 – AC WAVEFORMS FOR READ OPERATIONS
CS#
OE#
WE#
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 9 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
FIGURE 7 – WRITE/ERASE/PROGRAM OPERATION, WE# CONTROLLED
CS#
Data# Polling
OE#
D7#
WE#
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 10 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
CS#
OE#
WE#
FIGURE 8 – AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
NOTE:
1. SA is the sector address for Sector Erase.
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 11 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
FIGURE 9 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED
ALGORITHM OPERATIONS
tOE
tCE
tCH
tOH
D7# D7 =
Valid Data
High Z
D0-D6 = Invalid D0-D7
Valid Data
tDF
D7
D0-D6
tOEH
tWHWH 1 or 2
Data
CS#
OE#
WE#
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 12 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
Notes:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to each chip.
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
FIGURE 10 – ALTERNATE CS# CONTROLLED PROGRAMMING OPERATION TIMINGS
CS#
OE#
WE#
Data# Polling
D7#
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 13 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
PACKAGE 402 – 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 14 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
The White 68 lead G2T CQFP fi lls the same fi t and function as the
JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead
inspection advantage of the CQFP form.
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 15 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
ORDERING INFORMATION
MICROSEMI CORPORATION
FLASH
ORGANIZATION, 4M x 32
User confi gurable as 2x4M x 16 or 4x4M x 8 in HIP package
ACCESS TIME (ns)
PACKAGE TYPE:
H2 = Ceramic Hex In line Package, HIP (Package 402)
G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509)
DEVICE GRADE:
M = Military -55°C to +125°C
I = Industrial -40°C to +85°C
C = Commercial 0°C to +70°C
Q = MIL-STD-883
VPP PROGRAMMING VOLTAGE:
5 = 5 V
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
W F 4M32 - XXX X X 5 X
WF4M32-XXX5
August 2011 © 2011 Microsemi Corporation. All rights reserved. 16 Microsemi Corporation • (602) 437-1520 • www.whiteedc.com
Rev. 9 www.microsemi.com
Microsemi Corporation reserves the right to change products or specifi cations without notice.
Document Title
4Mx32 5V NOR FLASH MODULE
Revision History
Rev # History Release Date Status
Rev 7 Changes (Pg. 1, 2, 3, 6, 7, 13, 15)
7.1 Remove G4T package option, all references to G4T and "is under
devlopment, not qualifi ed or characterized"
7.2 Remove Fig 2: G4T pin confi guration
7.3 Remove preference to G4T on page 3
7.4 Remove reference to G4T on page 6
7.5 Remove reference to G4T on page 7
7.6 Remove package 502-G4T package
7.7 Add "Q" = MIL-STD-883 screened
7.8 Remove reference to G4T package
June 2009 Final
Rev 8 Changes (Pg. 1-16)
8.1 Change document layout from White Electronic Designs to Microsemi May 2011 Final
Rev 9 Changes (Pg. 1, 16)
9.1 Add "NOR" to headline August 2011 Final
