Single-Supply, Differential,
18-Bit ADC Driver
Data Sheet ADA4941-1
Rev. D Document Feedback
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FEATURES
Single-ended-to-differential converter
Excellent linearity
Distortion −110 dBc at 100 kHz for VO, dm = 2 V p-p
Low noise: 10.2 nV/√Hz, output-referred, G = 2
Extremely low power: 2.2 mA (3 V supply)
High input impedance: 24 MΩ
User-adjustable gain
High speed: 31 MHz, −3 dB bandwidth (G = +2)
Fast settling time: 300 ns to 0.005% for a 2 V step
Low offset: 0.8 mV maximum, output-referred, G = 2
Rail-to-rail output
Disable feature
Wide supply voltage range: 2.7 V to 12 V
Available in space-saving, 3 mm × 3 mm LFCSP
APPLICATIONS
Single-supply data acquisition systems
Instrumentation
Process control
Battery-power systems
Medical instrumentation
FUNCTIONAL BLOCK DIAGRAM
DIS
4
3
2
1
IN
OUT–OUT+
V+
REF
FB
V–
7
8
5
6
05704-001
Figure 1.
GENERAL DESCRIPTION
The ADA4941-1 is a low power, low noise differential driver for
analog-to-digital converters (ADCs) up to 18 bits in systems
that are sensitive to power. The ADA4941-1 is configured in an
easy-to-use, single-ended-to-differential configuration and
requires no external components for a gain of 2 configuration.
A resistive feedback network can be added to achieve gains greater
than 2. The ADA4941-1 provides essential benefits, such as low
distortion and high SNR that are required for driving high
resolution ADCs.
With a wide input voltage range (0 V to 3.9 V on a single 5 V
supply), rail-to-rail output, high input impedance, and a user-
adjustable gain, the ADA4941-1 is designed to drive single-supply
ADCs with differential inputs found in a variety of low power
applications, including battery-operated devices and single-
supply data acquisition systems.
The ADA4941-1 is ideal for driving the 16-bit and 18-bit
PulSAR® ADCs, such as the AD7687, AD7690, and AD7691.
The ADA4941-1 is manufactured on Analog Devices, Inc.,
proprietary, second-generation, eXtra fast complementary
bipolar (XFCB) process, which enables the amplifier to achieve
18-bit performance on low supply currents.
The ADA4941-1 is available in a small 8-lead LFCSP as well as a
standard 8-lead SOIC and is rated to work over the extended
industrial temperature range, −40°C to +125°C.
–
60
–140
0.1 101 1000
FREQUENCY (kHz)
DISTORTION (dBc)
100
V
O
= 2V p-p
V
O
= 6V p-p
05704-045
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
HD3
HD2 HD3
HD2
Figure 2. Distortion vs. Frequency at Various Output Amplitudes
ADA4941-1 Data Sheet
Rev. D | Page 2 of 23
TABLE OF CONTENTS
Features........................................................................................... 1
Applications ................................................................................... 1
Functional Block Diagram ............................................................ 1
General Description ...................................................................... 1
Revision History ............................................................................ 2
Specifications ................................................................................. 3
Absolute Maximum Ratings ......................................................... 6
Thermal Resistance ................................................................... 6
M a xim um Po we r D is sip a tio n ................................................... 6
ESD Ca utio n............................................................................... 6
Pin Configuration and Function Descriptions............................ 7
Typical Performance Characteristics............................................ 8
Theory of Operation.................................................................... 15
Basic Operation ....................................................................... 15
DC Error Calculations ............................................................ 16
Output Voltage Noise .............................................................. 17
Frequency Response vs. Closed-Loop Gain .......................... 19
Applications Information............................................................ 20
Overview .................................................................................. 20
Using the REF Pin.................................................................... 20
Internal Feedback Network Power Dissipation ..................... 20
Disable Feature......................................................................... 20
Adding a 3-Pole, Sallen-Key Filter.......................................... 21
Driving the AD7687 ADC ...................................................... 22
Gain of −2 Configuration........................................................ 22
Outline Dimensions .................................................................... 23
Ordering Guide........................................................................ 23
REVISION HISTORY
5/16—Rev. C to Re v. D
Change CP-8-2 to CP-8-13 ........................................ Throughout
Changes to Figure 4 ........................................................................7
Added Figure 5; Renumbered Sequentially ..................................7
Updated Outline Dimensions ......................................................23
Changes to Ordering Guide .........................................................23
8/11—Rev. B to R ev. C
Change to Gain Error Drift Unit, Table 1 .....................................3
Change to Gain Error Drift Unit, Table 2 .....................................4
Change to Gain Error Drift Unit, Table 3 .....................................5
8/10—R ev. A to R ev. B
Added Caption to Figure 1.............................................................1
Added Exposed Pad Notation to Figure 4 and Table 6 ................7
Added Exposed Pad Notation to Outline Dimensions ..............23
Changes to Ordering Guide .........................................................23
3/09—Rev. 0 to R ev. A
Change to Gain Error Drift Parameter, Table 1............................3
Change to Gain Error Drift Parameter, Table 2............................4
Change to Gain Error Drift Parameter, Table 3............................5
Updated Outline Dimensions ......................................................23
4/06—Revision 0: Initial Version
Data Sheet ADA4941-1
Rev. D | Page 3 of 23
SPECIFICATIONS
TA = 25°C, VS = 3 V, OUT+ connected to FB (G = 2), RL, dm = 1 kΩ, REF = 1.5 V, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VO = 0.1 V p-p 21 30 MHz
VO = 2.0 V p-p 4.6 6.5 MHz
Overdrive Recovery Time +Recover/−recovery 320/650 ns
Slew Rate VO = 2 V step 22 V/µs
Settling Time 0.005% VO = 2 V p-p step 300 ns
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion fC = 40 kHz, VO = 2 V p-p, HD2/HD3 −116/−112 dBc
fC = 100 kHz, VO = 2 V p-p, HD2/HD3 −101/−98 dBc
fC = 1 MHz, VO = 2 V p-p, HD2/HD3 −75/−71 dBc
RTO Voltage Noise f = 100 kHz 10.2 nV/√Hz
Input Current Noise f = 100 kHz 1.6 pA/√Hz
DC PERFORMANCE
Differential Output Offset Voltage 0.2 0.8 mV
Differential Input Offset Voltage Drift 1.0 µV/°C
Single-Ended Input Offset Voltage Amp A1 or Amp A2 0.1 0.4 mV
Single-Ended Input Offset Voltage Drift 0.3 µV/°C
Input Bias Current IN and REF 3 4.5 µA
Input Offset Current IN and REF 0.1 µA
Gain (+OUT − −OUT)/(IN − REF) 1.98 2.00 2.01 V/V
Gain Error −1 +1 %
Gain Error Drift 1 5 ppm/°C
INPUT CHARACTERISTICS
Input Resistance IN and REF 24 MΩ
Input Capacitance
IN and REF
1.4
pF
Input Common-Mode Voltage Range
0.2
1.9
V
Common-Mode Rejection Ratio (CMRR) CMRR = VOS, dm/VCM, VREF = VIN, VCM = 0.2 V to 1.9 V, G = 4 81 105 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Each single-ended output, G = 4 ±2.90 ±2.95 V
Output Current 25 mA
Capacitive Load Drive 20% overshoot, VO, dm = 200 mV p-p 20 pF
POWER SUPPLY
Operating Range 2.7 12 V
Quiescent Current 2.2 2.4 mA
Quiescent Current—Disable 10 16 µA
Power Supply Rejection Ratio (PSRR)
+PSRR
PSRR = VOS, dm/ΔVS, G = 4
86
100
dB
−PSRR 86 110 dB
DISABLE
DIS Input Voltage
Disabled, DIS = high ≥1.5 V
Enabled, DIS = low ≤1.0 V
DIS Input Current Disabled, DIS = high 5.5 8 µA
Enabled, DIS = low 4 6 µA
Turn-On Time 0.7 µs
Turn-Off Time 30 µs
ADA4941-1 Data Sheet
Rev. D | Page 4 of 23
TA = 25°C, VS = 5 V, OUT+ connected to FB (G = 2), RL, dm = 1 kΩ, REF = 2.5 V, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
VO = 0.1 V p-p
22
31
MHz
VO = 2.0 V p-p
4.9
7
MHz
Overdrive Recovery Time +Recover/−recovery 200/600 ns
Slew Rate VO = 2 V step 24.5 V/µs
Settling Time 0.005% VO = 6 V p-p step 610 ns
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion fC = 40 kHz, VO = 2 V p-p, HD2/HD3 −118/−119 dBc
fC = 100 kHz, VO = 2 V p-p, HD2/HD3 −110/−112 dBc
fC = 1 MHz, VO = 2 V p-p, HD2/HD3 −83/−73 dBc
RTO Voltage Noise f = 100 kHz 10.2 nV/√Hz
Input Current Noise f = 100 kHz 1.6 pA/√Hz
DC PERFORMANCE
Differential Output Offset Voltage
0.2
0.8
mV
Differential Input Offset Voltage Drift 1.0 µV/°C
Single-Ended Input Offset Voltage Amp A1 or Amp A2 0.1 0.4 mV
Single-Ended Input Offset Voltage Drift 0.3 µV/°C
Input Bias Current IN and REF 3 4.5 µA
Input Offset Current IN and REF 0.1 µA
Gain (+OUT − −OUT)/(IN − REF) 1.98 2 2.01 V/V
Gain Error −1 +1 %
Gain Error Drift 1 5 ppm/°C
INPUT CHARACTERISTICS
Input Resistance IN and REF 24 MΩ
Input Capacitance IN and REF 1.4 pF
Input Common-Mode Voltage Range 0.2 3.9 V
Common-Mode Rejection Ratio (CMRR)
CMRR = VOS, dm /VCM, VREF = VIN, VCM = 0.2 V to 3.9 V, G = 4
84
106
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Each single-ended output, G = 4 ±4.85 ±4.93 V
Output Current 25 mA
Capacitive Load Drive 20% overshoot, VO, dm = 200 mV p-p 20 pF
POWER SUPPLY
Operating Range 2.7 12 V
Quiescent Current 2.3 2.6 mA
Quiescent Current—Disable 12 20 µA
Power Supply Rejection Ratio (PSRR)
+PSRR PSRR = VOS, dm/ΔVS, G = 4 87 100 dB
−PSRR
87
110
dB
DISABLE
DIS Input Voltage
Disabled, DIS =
high ≥1.5 V
Enabled, DIS =
low ≤1.0 V
DIS Input Current
Disabled, DIS =
high 5.5 8 µA
Enabled, DIS = low 4 6 µA
Turn-On Time 0.7 µs
Turn-Off Time 30 µs
Data Sheet ADA4941-1
Rev. D | Page 5 of 23
TA = 25°C, VS = ±5 V, OUT+ connected to FB (G = 2), RL, dm = 1 kΩ, REF = 0 V, unless otherwise noted.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth
23
32
MHz
5.2
7.5
MHz
Overdrive Recovery Time +Recover/−recovery 200/650 ns
Slew Rate VO = 2 V step 26 V/µs
Settling Time 0.005% VO = 12 V p-p step 980 ns
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion fC = 40 kHz, VO = 2 V p-p, HD2/HD3 −118/−119 dBc
fC = 100 kHz, VO = 2 V p-p, HD2/HD3 −109/−112 dBc
fC = 1 MHz, VO = 2 V p-p, HD2/HD3 −84/−75 dBc
RTO Voltage Noise f = 100 kHz 10.2 nV/√Hz
Input Current Noise f = 100 kHz 1.6 pA/√Hz
DC PERFORMANCE
Differential Output Offset Voltage
0.2
0.8
mV
Differential Input Offset Voltage Drift 1.0 µV/°C
Single-Ended Input Offset Voltage Amp A1 or Amp A2 0.1 0.4 mV
Single-Ended Input Offset Voltage Drift 0.3 µV/°C
Input Bias Current IN and REF 3 4.5 µA
Input Offset Current IN and REF 0.1 µA
Gain (+OUT − −OUT)/(IN − REF) 1.98 2 2.01 V/V
Gain Error −1 +1 %
Gain Error Drift 1 5 ppm/°C
INPUT CHARACTERISTICS
Input Resistance IN and REF 24 MΩ
Input Capacitance IN and REF 1.4 pF
Input Common-Mode Voltage Range −4.8 +3.9 V
Common-Mode Rejection Ratio (CMRR)
OS, dm
CM
VCM = −4.8 V to +3.9 V, G = 4 85 105 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing Each single-ended output, G = 4 VS − 0.25 VS ± 0.14 V
Output Current 25 mA
Capacitive Load Drive 20% overshoot, VO, dm = 200 mV p-p 20 pF
POWER SUPPLY
Operating Range
2.7
12
V
Quiescent Current 2.5 2.7 mA
Quiescent Current—Disable 15 26 µA
Power Supply Rejection Ratio (PSRR)
+PSRR PSRR = VOS, dm/ΔVS, G = 4 87 100 dB
−PSRR 87 110 dB
DISABLE
DIS Input Voltage Disabled, DIS = high ≥ −3 V
Enabled, DIS = low ≤ −4 V
DIS Input Current Disabled, DIS = high 7 10 µA
Enabled, DIS = low 4 6 µA
Turn-On Time 0.7 µs
Turn-Off Time 30 µs
ADA4941-1 Data Sheet
Rev. D | Page 6 of 23
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 12 V
Power Dissipation See Figure 3
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
Junction Temperature 150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in the circuit board with its
exposed paddle soldered to a pad (if applicable) on the PCB
surface that is thermally connected to a copper plane, with zero
airflow.
Table 5. Thermal Resistance
Package Type θJA θJC Unit
8-Lead SOIC on 4-Layer Board 126 28 °C/W
8-Lead LFCSP with EP on 4-Layer Board 83 19 °C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4941-1
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4941-1. Exceeding a
junction temperature of 150°C for an extended period can
result in changes in the silicon devices potentially causing
failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The power dissipated due to the load
drive depends upon the particular application. For each output,
the power due to load drive is calculated by multiplying the load
current by the associated voltage drop across the device. The
power dissipated due to all of the loads is equal to the sum of
the power dissipation due to each individual load. RMS voltages
and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θJA. The exposed paddle on the underside of the
package must be soldered to a pad on the PCB surface that is
thermally connected to a copper plane to achieve the specified θJA.
Figure 3 shows the maximum safe power dissipation in the
packages vs. the ambient temperature for the 8-lead SOIC
(126°C/W) and for the 8-lead LFCSP (83°C/W) on a JEDEC
standard 4-layer board. The LFCSP must have its underside
paddle soldered to a pad that is thermally connected to a PCB
plane. θJA values are approximations.
2.5
0
–40 120
AMBI ENT T E M P E RATURE ( °C)
MAXIMUM POWER DISSIPATIO N (W)
2.0
1.5
1.0
0.5
–20 020 40 60 80 100
LFCSP
SOIC
05704-002
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Data Sheet ADA4941-1
Rev. D | Page 7 of 23
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05704-102
FB
REF
V+
OUT+
IN
DIS
V–
OUT–
A
DA4941-1
3
4
1
2
6
5
8
7
NOTES
1. THE EXPOSED PAD IS NOT ELECTRICALLY CONNECTED TO THE DEVICE.
IT IS TYPICALLY SOLDERED TO GROUND OR A POWER PLANE ON THE PCB
THAT IS THERMALLY CONDUCTIVE.
TOP VIEW
(Not to Scale)
Figure 4. 8-Lead LFCSP Pin Configuration
05704-101
FB
1
REF
2
V+
3
O
UT+
4
IN
8
DIS
7
V–
6
OUT–
5
A
DA4941-1
(Not to Scale)
TOP VIEW
Figure 5. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 FB Feedback Input.
2 REF Reference Input.
3 V+ Positive Power Supply.
4 OUT+ Noninverting Output.
5 OUT− Inverting Output.
6 V− Negative Power Supply.
7 DIS Disable.
8 IN Input.
EPAD (LFCSP Only) Exposed Paddle. The exposed pad is not electrically connected to the device. It is typically soldered to
ground or a power plane on the PCB that is thermally conductive.
ADA4941-1 Data Sheet
Rev. D | Page 8 of 23
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, VS = 5 V, RL, dm = 1 kΩ, REF = 2.5 V, DIS = low, OUT+ directly connected to FB (G = 2), TA = 25°C.
2
–16
–15
–14
–13
–12
1 1000
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
1
0
–1
–2
–3
–11
–4
–5
–6
–7
–8
–9
–10
10 100
V
O, dm
= 0.1V p-p
V
S
= +3V
V
S
= +5V
V
S
=±5V
05704-004
Figure 6. Small Signal Frequency Response for Various Power Supplies
2
–16
–15
–14
–13
–12
1 1000
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
1
0
–1
–2
–3
–11
–4
–5
–6
–7
–8
–9
–10
10 100
+25°C
–40°C
+85°C
V
O, dm
= 0.1V p-p
05704-005
Figure 7. Small Signal Frequency Response at Various Temperatures
2
–15
1 1000
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
10 100
R
L, dm
= 1kΩ
R
L, dm
= 5kΩ
R
L, dm
= 500Ω
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
V
O, dm
= 0.1V p-p
05704-006
Figure 8. Small Signal Frequency Response for Various Resistive Loads
2
–16
–15
–14
–13
–12
0.1 100
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
1
0
–1
–2
–3
–11
–4
–5
–6
–7
–8
–9
–10
110
V
S
= +3V
V
O, dm
= 2V p-p
V
S
= +5V
V
O, dm
= 6V p-p
V
S
=±5V
V
O, dm
= 12V p-p
05704-007
Figure 9. Large Signal Frequency Response for Various Power Supplies
2
–16
–15
–14
–13
–12
0.1 100
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
1
0
–1
–2
–3
–11
–4
–5
–6
–7
–8
–9
–10
110
+25°C
–40°C
+85°C
V
O, dm
= 6V p-p
05704-008
Figure 10. Large Signal Frequency Response at Various Temperatures
2
–16
0.1 10
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
R
L, dm
= 1kΩ
R
L, dm
= 5kΩ
R
L, dm
= 500Ω
V
O, dm
= 6V p-p
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
1
05704-009
Figure 11. Large Signal Frequency Response for Various Resistive Loads
Data Sheet ADA4941-1
Rev. D | Page 9 of 23
2
–16
–15
–14
–13
–12
1 100
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
1
0
–1
–2
–3
–11
–4
–5
–6
–7
–8
–9
–10
10
G = +4
G = +10
G = +2
G = –2
V
O, dm
= 0.1V p-p
05704-010
Figure 12. Small Signal Frequency Response for Various Gains
2
–16
–15
–14
–13
–12
1 10010 1000
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
1
0
–1
–2
–3
–11
–4
–5
–6
–7
–8
–9
–10
C
L
= 0pF
C
L
= 20pF
V
O, dm
= 0.1V p-p
05704-011
Figure 13. Small Signal Frequency Response for Various Capacitive Loads
2
–16
–15
–14
–13
–12
1 10 1000
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
1
0
–1
–2
–3
–11
–4
–5
–6
–7
–8
–9
–10
VREF = 0.05V p-p
V
S
= +5V
V
S
=±5V
V
S
= +3V
05704-012
Figure 14. REF Input Small Signal Frequency Response for Various Supplies
2
–16
–15
–14
–13
–12
1 10 1000
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
1
0
–1
–2
–3
–11
–4
–5
–6
–7
–8
–9
–10
100
G = +4
G = +10
G = +2
G = –2
V
O, dm
= 2V p-p
05704-013
Figure 15. Large Signal Frequency Response for Various Gains
2
–16
–15
–14
–13
–12
0.1 101 1000
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
1
0
–1
–2
–3
–11
–4
–5
–6
–7
–8
–9
–10
100
V
O, dm
= 2V p-p
V
O, dm
= 6V p-p
V
O, dm
= 0.1V p-p
05704-014
Figure 16. Frequency Response for Various Output Amplitudes
–
70
–140
0.1 101 1000
FREQUENCY (kHz)
DISTORTION (dBc)
100
05704-015
HD3
HD2
HD2
R
L
= 2kΩ
R
L
= 1kΩ
R
L
=500Ω
V
O, dm
= 2V p-p
VREF = MIDSUPPLY
–80
–90
–100
–110
–120
–130
Figure 17. Distortion vs. Frequency for Various Loads
ADA4941-1 Data Sheet
Rev. D | Page 10 of 23
–
65
–75
–85
–95
–105
–115
–125
–135
020
OUTPUT AMPLITUDE (V p-p)
DISTORTION (dBc)
05704-016
V
S
= +5V
f
= 10kHz
V
S
= ±5VV
S
= +3V
24681012141618
HD2
HD2
HD2
HD3
HD3
HD3
Figure 18. Distortion vs. Output Amplitude for Various Supplies (G = +2)
–
60
–140
0.1 101 1000
FREQUENCY (kHz)
DISTORTION (dBc)
100
05704-017
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
HD3
HD3
HD2
V
S
= +3V
V
S
= +5V
V
S
=±5V
HD2
V
O, dm
= 2V p-p
VREF = MIDSUPPLY
Figure 19. Distortion vs. Frequency for Various Supplies
–
60
–140
0.1 101 1000
FREQUENCY (kHz)
DISTORTION (dBc)
100
V
O
= 2V p-p
V
O
= 6V p-p
05704-045
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
HD3
HD2 HD3
HD2
Figure 20. Distortion vs. Frequency at Various Output Amplitudes
HD3
–
65
–145
020
OUTPUT AMPLITUDE (V p-p)
DISTORTION (dBc)
05704-019
DIFFERENTIAL G = –2
f
= 10kHz
24681012141618
–75
–85
–95
–105
–115
–125
–135
V
S
= +5V V
S
= ±5V
V
S
= +3V
HD2
HD3 HD3
Figure 21. Distortion vs. Output Amplitude for Various Supplies (G = −2)
–
70
–140
0.1 101 1000
FREQUENCY (kHz)
DISTORTION (dBc)
100
05704-020
HD3 HD3
HD3 G = –2
G = +2
G = +4
V
O, dm
= 2V p-p
VREF = MIDSUPPLY
–80
–90
–100
–110
–120
–130
HD2
HD2
Figure 22. Distortion vs. Frequency for Various Gains
0.12
–0.12
OUTPUT VOLTAGE (V)
50ns/DIV
V
OUT
= 200mV p-p
0.08
0.04
0
–0.04
–0.08
C
L
=0pF
C
L
= 20pF
05704-022
Figure 23. Small Signal Transient Response for Various Capacitive Loads
Data Sheet ADA4941-1
Rev. D | Page 11 of 23
0.12
–0.12
OUTPUT VOLTAGE (V)
50ns/DIV
VOUT = 200mV p-p
0.08
0.04
0
–0.04
–0.08
VS =+3V
VS = +5V OR VS = ±5V
05704-018
Figure 24. Small Signal Transient Response for Various Supplies
8
–8
AMPLITUDE (V)
V
S
=±5V
V
O, dm
= 12V p-p
V
O, dm
2 × V
IN
ERROR = 2 × V
IN
– V
O, dm
6
4
2
0
–2
–4
–6
2.4
–2.4
ERROR (mV) 1 DIV = 0.005%
1.8
1.2
0.6
0
–0.6
–1.2
–1.8
1µs/DIV
05704-023
Figure 25. Settling Time (0.005%), VS = ±5 V
12
–12
10
8
6
4
2
0
–2
–4
–6
–8
–10
OUTPUT VOLTAGE (V)
1µs/DIV
INPUT × 2
OUTPUT
05704-024
Figure 26. Input Overdrive Recovery, VS = ±5 V
8
–8
OUTPUT VOLTAGE (V)
200ns/DIV
V
S
= ±5V
V
O, dm
= 12V p-p
V
S
= ±2.5V
V
O, dm
=6V p-p
V
S
= ±1.5V
V
O, dm
=2V p-p
6
4
2
0
–2
–4
–6
05704-021
Figure 27. Large Signal Transient Response for Various Supplies
9
1
AMPLITUDE (V)
V
S
=+5V
V
O, dm
=6V p-p
V
O, dm
2 × V
IN
ERROR = 2 × V
IN
– V
O, dm
8
7
6
5
4
3
2
1.2
–1.2
ERROR (mV) 1 DIV = 0.005%
0.9
0.6
0.3
0
–0.3
–0.6
–0.9
1µs/DIV
05704-026
Figure 28. Settling Time (0.005%), VS = +5 V
8
–8
OUTPUT VOLTAGE (V)
1µs/DIV
6
4
2
0
–2
–4
–6
INPUT × 2
OUTPUT
05704-027
Figure 29. Input Overdrive Recovery, VS = +5 V
ADA4941-1 Data Sheet
Rev. D | Page 12 of 23
0
–110
0.001 1000
FREQUENCY (MHz)
PSRR (dB)
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.01 0.1 1 10 100
+PSRR
–PSRR
05704-028
Figure 30. Power Supply Rejection Ratio vs. Frequency
3.5
1.0
–40 120
TEMPERATURE (°C)
POWER SUPPLY CURRENT (mA)
V
S
=±5V
V
S
=+5V
V
PD
= V
S–
V
S
=+3V
3.0
2.5
2.0
1.5
–20 0 20 40 60 80 100
05704-029
Figure 31. Power Supply Current vs. Temperature
150
0
–40 120
TEMPERATURE (°C)
DIFFERENTIAL OUTPUT OFFSET (µV)
–20 0 20 40 60 80 100
05704-030
125
100
75
50
25
V
OS
_A1 10V
V
OS
_A2 = 3V
V
OS
_A1 = 3V
V
OS
_A2 = 5V
V
OS
_A1 = 5V
V
OS
_A2 = 10V
Figure 32. Differential Output Offset Voltage vs. Temperature
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
–40 120
TEMPERATURE (°C)
OUTPUT SATURATION VOLTAGE
WITH RESPECT TO RAIL (V)
–20 0 20 40 60 80 100
05704-031
±5V SUPPLIES, POSITIVE RAIL
+5V SUPPLIES, POSITIVE RAIL
±5V SUPPLIES, NEGATIVE RAIL
+5V SUPPLIES, NEGATIVE RAIL
+3V SUPPLIES, POSITIVE RAIL
+3V SUPPLIES, NEGATIVE RAIL
Figure 33. Output Saturation Voltage vs. Temperature
2.5
–0.5
0.6 2.0
DISABLE INPUT VOLTAGE WITH RESPECT TO V
S–
(V)
SUPPLY CURRENT (mA)
I
CC
@ V
S
=±5V
I
CC
@ V
S
=+5V
I
CC
@ V
S
=+3V
2.0
1.5
1.0
0.5
0
0.81.01.21.41.61.8
05704-032
Figure 34. Power Supply Current vs. Disable Voltage
140
0
–200
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
20
40
60
80
100
120
140
160
180
200
OFFSET VOLTAGE (µV)
FREQUENCY
120
100
80
60
40
20
V
OS
1
MEAN = –8µV
STD. DEV = 47µV
V
OS
2
MEAN = 11µV
STD. DEV = 20µV
NO. OF UNITS = 611
05704-033
Figure 35. Differential Output Offset Distribution
Data Sheet ADA4941-1
Rev. D | Page 13 of 23
100
1
1 100M
FREQUENCY (Hz)
DIFFERENTIAL OUTPUT VOLTAGE NOISE (nV/√Hz)
10
10 100 1k 10k 100k 1M 10M
05704-034
Figure 36. Differential Output Voltage Noise vs. Frequency
2.65
2.35
–40 125
TEMPERATURE (°C)
INPUT BIAS CURRENT (µA)
V
S
=±5V
V
S
=+5V
V
S
=+3V
2.60
2.55
2.50
2.45
2.40
–25 –10 5 20 35 50 65 80 95 110
05704-035
Figure 37. Input Bias Current vs. Temperature for Various Supplies
3.3
2.7
–40 120
TEMPERATURE (°C)
REFERENCE BIAS CURRENT (µA)
–20 0 20 40 60 80 100
05704-036
3.2
3.1
3.0
2.9
2.8
REFERENCE I
BIAS
=5V
REFERENCE I
BIAS
=3V
REFERENCE I
BIAS
=10V
Figure 38. REF Input Bias Current vs. Temperature
28
0
11M
FREQUENCY (Hz)
INPUT CURRENT NOISE (pA/√Hz)
26
24
22
20
18
16
14
12
10
8
6
4
2
10 100 1k 10k 100k
05704-037
Figure 39. Input Current Noise vs. Frequency
3.5
1.5
–0.5 10.0
INPUT VOLTAGE WITH RESPECT TO V
S– (V)
INPUT BIAS CURRENT (µA)
05704-038
3.0
2.5
2.0
00.51.01.52.02.53.03.54.04.55.05.56.06.57.07.58.08.59.09.5
VS =±5V
VS = +5VVS = +3V
Figure 40. Input Bias Current vs. Input Voltage
4.0
2.0
0 10.0
REFERENCE INPUT VOLTAGE WITH RESPECT TO V
S–
(V)
REFERENCE INPUT BIAS CURRENT (µA)
05704-039
3.5
3.0
2.5
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.07.5 8.08.5 9.0 9.5
V
S
=±5V
VREF = VIN
V
S
= +5VV
S
= +3V
Figure 41. REF Input Bias Current vs. REF Input Voltage
ADA4941-1 Data Sheet
Rev. D | Page 14 of 23
10
0
–40 120
TEMPERATURE (°C)
DISABLED SUPPLY CURRENT (µA)
–20 0 20 40 60 80 100
05704-040
8
6
4
2
G = 4
RF =1kΩ
RL = ∞
DIS = HIGH
VS =±5V
VS =+5V
VS =+3V
Figure 42. Disable Supply Current vs. Temperature for Various Supplies
500mV/DIV
40µs/DIV
V
PD
V
O, dm
05704-041
Figure 43. Disable Assert Time
–
40
–110
0.1 1000
FREQUENCY (MHz)
ISOLATION (dB)
–50
–60
–70
–80
–90
–100
1 10 100
VIN = 50mV p-p
05704-042
Figure 44. Disabled Input-to-Output Isolation vs. Frequency
14
0
010
DISABLE INPUT VOLTAGE WITH RESPECT TO V
S–
(V)
DISABLE INPUT CURRENT (µA)
12
10
8
6
4
2
123456789
V
S
=±5V
05704-043
Figure 45. Disable Input Current vs. Disable Input Voltage
500mV/DIV
40µs/DIV
V
PD
V
O, dm
05704-044
Figure 46. Disable Deassert Time
100
0.0001
0.001 100
FREQUENCY (MHz)
IMPEDANCE (Ω)
VOP
VON
10
1
0.1
0.01
0.001
0.01 0.1 1 10
05704-025
Figure 47. Single-Ended Output Impedance vs. Frequency
Data Sheet ADA4941-1
Rev. D | Page 15 of 23
THEORY OF OPERATION
The ADA4941-1 is a low power, single-ended input, differential
output amplifier optimized for driving high resolution ADCs.
Figure 48 illustrates how the ADA4941-1 is typically connected.
The amplifier is composed of an uncommitted amplifier, A1,
driving a precision inverter, A2. The negative input of A1 is
brought out to Pin 1 (FB), allowing for user-programmable
gain. The inverting op amp, A2, provides accurate inversion of
the output of A1, VOP, producing the output signal VON.
1kΩ
1kΩ
R
G
R
F
R
F
|| R
G
500Ω
A2
A1
REF
IN
VREF
2
8
4
5
FB
OUT+
+
–
VOP
1
OUT–
+
–
VON
VINVG
05704-052
Figure 48. Basic Connections (Power Supplies Not Shown)
The voltage applied to the REF pin appears as the output
common-mode voltage. Note that the voltage applied to the
REF pin does not affect the voltage at the OUT+ pin. Because of
this, a differential offset can exist between the outputs, while the
desired output common-mode voltage is present. For example,
when VOP = 3.5 V and VON = 1.5 V, the output common-
mode voltage is equal to 2.5 V, just as it is when both outputs
are at 2.5 V. In the first case, the differential voltage (or offset) is
2.0 V, and in the latter case, the differential voltage is 0 V. When
calculating output voltages, both differential and common-mode
voltages must be considered at the same time to avoid undesired
differential offsets.
BASIC OPERATION
In Figure 48, RG and RF form the external gain-setting network.
VG and VREF are externally applied voltages. VO, cm is defined
as the output common-mode voltage and VO, dm is defined as
the differential-mode output voltage. The following equations
can be derived from Figure 48:
G
F
G
F
R
R
VG
R
R
VINVOP 1 (1)
)(21 VREF
R
R
VG
R
R
VINVON
G
F
G
F
(2)
)(221)(2
,
VREF
R
R
VG
R
R
VINVONVOP
dmV
G
F
G
F
O
(3)
VREF
VONVOP
cmVO
2
, (4)
When RF = 0 and RG is removed, Equation 3 simplifies to the
following:
VO, dm = 2(VIN) − 2(VREF) (5)
1kΩ
1kΩ
4.99kΩ
1kΩ
825Ω500Ω
A2
A1
REF
IN
2
8
4
5
FB
+5V
–5V
V
S+
V
S–
OUT+
+
–
VOP
1
3
6
OUT–
+
–
VON
VIN
05704-053
Figure 49. Dual Supply, G = 2.4, Single-Ended-to-Differential Amplifier
Figure 49 shows an example of a dual-supply connection. In this
example, VG and VREF are set to 0 V, and the external RF and
RG network provides a noninverting gain of 1.2 in A1. This
example takes full advantage of the rail-to-rail output stage.
The gain equation is
VOP − VON = 2.4(VIN) (6)
The in-series, 825 Ω resistor combined with Pin 8 compensates
for the voltage error generated by the input offset current of A1.
The linear output range of both A1 and A2 extends to within
200 mV of each supply rail, which allows a peak-to-peak
differential output voltage of 19.2 V on ±5 V supplies.
1kΩ
1kΩ
500Ω
A2
A1
REF
IN
2
8
4
5
FB
+5V
V
S+
V
S–
OUT+
+
–
VOP
1
3
6
OUT–
+
–
VON
+2.5V
VIN
05704-054
Figure 50. Single +5V Supply, G=2 Single-Ended-to-Differential Amplifier
Figure 50 shows a single 5 V supply connection with A1 used as
a unity gain follower. The 2.5 V at the REF pin sets the output
common-mode voltage to 2.5 V. The transfer function is then
VOP − VON = 2(VIN) − 5 V (7)
ADA4941-1 Data Sheet
Rev. D | Page 16 of 23
In this case, the linear output voltage is limited by A1. On the
low end, the output of A1 starts to saturate and show degraded
linearity when VOP approaches 200 mV. On the high end, the
input of A1 becomes saturated and exhibits degraded linearity
when VIN moves beyond 4 V (within 1 V of VCC). This limits
the linear differential output voltage in the circuit shown in
Figure 50 to about 7.6 V p-p.
1kΩ
1kΩ
665Ω
1.02kΩ
402Ω500Ω
A2
A1
REF
IN
2
8
4
5
FB
+5V
V
S+
V
S–
OUT+
+
–
VOP
1
3
OUT–
+
–
VON
VIN +2.5V
6
05704-055
Figure 51. 5 V Supply, G = 5, Single-Ended-to-Differential Amplifier
Figure 51 shows a single 5 V supply connection for G = 5. The
RF and RG network sets the gain of A1 to 2.5, and the 2.5 V at
the REF input provides a centered 2.5 V output common-mode
voltage. The transfer function is then
VOP − VON = 5(VIN) − 5 V (8)
The output range limits of A1 and A2 limit the differential
output voltage of the circuit shown in Figure 51 to approximately
8.4 V p-p.
DC ERROR CALCULATIONS
1kΩ
1kΩ
R
G
R
F
R
S–
IN
I
BP–
A2
I
BN–
A2
V
OS–
A1 500Ω
A2
A1
REF
IN
2
8
4
5
FB
OUT+
+
–
VOP
1
OUT–
+
–
VON
V
OS–
A2
R
S–
REF
I
BP–
A1
I
BN–
A1
05704-056
Figure 52. DC Error Sources
Figure 52 shows the major contributions to the dc output
voltage error. For each output, the total error voltage can be
calculated using familiar op amp concepts. Equation 9 expresses
the dc voltage error present at the VOP output.

FBP
S
BP
OS
G
FR_A1I_INR_A1I_A1V
R
R
VOP_error
)())((1
(9)
When using data from the Specifications tables, it is often more
expedient to use input offset current in place of the individual
input bias currents when calculating errors. Input offset current
is defined as the magnitude of the difference between the two
input bias currents. Using this definition, each input bias
current can be expressed in terms of the average of the two
input bias currents, IB, and the input offset current, IOS, as
IBP, N = IB ± IOS/2. DC errors are minimized when RS = RF || RG. In
this case, Equation 9 is reduced to

)||()(1 G
F
S
F
OSOS
G
FRRRRI_A1V
R
R
VOP_error
Equation 10 expresses the dc voltage error present at the VON
output.
VON_error = −(VOP_error) + 2[VOS_A2 −
(IBP_A2)(RS_REF + 500)] + 1000(IBN_A2) (10)
The internal 500 Ω resistor is provided on-chip to minimize dc
errors due to the input offset current in A2. The minimum
error is achieved when RS_REF = 0 Ω. In this case, Equation 10
is reduced to
VON_error =
−(VOP_error) + 2[VOS_A2] + (IOS)1000 (RS_REF = 0 Ω)
The differential output voltage error VO_error, dm, is the
difference between VOP_error and VON_error:
VO_error, dm = VOP_error − VON_error (11)
The output offset voltage of each amplifier in the ADA4941-1
also includes the effects of finite common-mode rejection ratio
(CMRR), power supply rejection ratio (PSRR), and dc open-
loop gain (AVOL).
VOL
SCM
OSOS A
VOUT
PSRR
V
CMRR
V
_nomVV Δ
ΔΔ (12)
where:
VOS_nom is the nominal output offset voltage without including
the effects of CMRR, PSRR, and AVOL.
Δ indicates the change in conditions from nominal.
VCM is the input common-mode voltage (for A1, the voltage at
IN, and for A2, the voltage at REF).
VS is the power supply voltage.
VOUT is either op amp output.
Data Sheet ADA4941-1
Rev. D | Page 17 of 23
Table 7, Table 8, and Table 9 show typical error budgets for the
circuits shown in Figure 49, Figure 50, and Figure 51.
RF = 1.0 kΩ, RG = 4.99 kΩ, RS_IN = 825 Ω, RS_REF = 0 Ω
Table 7. Output Voltage Error Budget for G = 2.4 Amplifier
Shown in Figure 49
Error
Source
Typical
Value VOP_error VON_error VO_dm_error
VOS_A1 0.1 mV +0.12 mV −0.12 mV +0.24 mV
IBP_A1 3 μA +2.48 mV −2.48 mV −4.96 mV
IBN_A1 3 μA −2.48 mV +2.48 mV +4.96 mV
VOS_A2 0.1 mV 0 mV +0.2 mV +0.2 mV
Total VO_error, dm = 0.44 mV
RF = 0 Ω, RG = ∞, RS_IN = 0 Ω, RS_REF = 0 Ω
Table 8. Output Voltage Error Budget for Amplifier Shown
in Figure 50
Error
Source
Typical
Value VOP_error VON_error VO_dm_error
VOS_A1 0.1 mV +0.1 mV −0.1 mV +0.2 mV
IBP_A1 3 μA +2.48 mV −2.48 mV −4.96 mV
IBN_A1 3 μA −2.48 mV +2.48 mV +4.96 mV
VOS_A2 0.1 mV 0 mV +0.2 mV +0.2 mV
Total VO_error, dm = 0.4 mV
RF = 1.02 kΩ, RG = 665 Ω, RS_IN = 402 Ω, RS_REF = 0 Ω
Table 9. Output Voltage Error Budget for G = 5 Amplifier
Shown in Figure 51
Error
Source
Typical
Value VOP_error VON_error VO_dm_error
VOS_A1 0.1 mV +0.25 mV −0.25 mV +0.5 mV
IBP_A1 3 μA +1.21 mV −1.21 mV −2.4 mV
IBN_A1 3 μA −1.21 mV +1.21 mV +2.4 mV
VOS_A2 0.1 mV 0 mV +0.2 mV +0.2 mV
Total VO_error, dm = 0.7 mV
OUTPUT VOLTAGE NOISE
1kΩ
1kΩ
R
G
R
F
R
S
ip
–
A2
in
–
A2
vn
–
A1 500Ω
A2
A1
REF
IN
2
8
4
5
FB
OUT+
+
–
VOP
1
OUT–
+
–
VON
vn
–
A2
R
S–
REF
ip
–
A1
in
–
A1
05704-057
√4kT (1kΩ)
√4kT (1kΩ)
√4kT (500Ω)
√4kT (R
S–
REF)√4kTR
S
√4kTR
G
√4kTR
F
Figure 53. Noise Sources
Figure 53 shows the major contributors to the ADA4941-1
differential output voltage noise. The differential output noise
mean-square voltage equals the sum of twice the noise mean-
square voltage contributions from the noninverting channel
(A1), plus the noise mean-square voltage terms associated with
the inverting channel (A2).


2
2
2
2
2
2
2
2
_41
24242
_2)_(1
2)_(12
_,
nVONkTR
R
R
R
R
kTRkTR
RA1inRA1ip
R
R
A1vn
R
R
ndmV
S
G
F
G
F
G
F
F
S
G
F
G
F
O
(13)
where VON_n2 is calculated as

)(16(500)16(1000)8
)_(1000)_500)(_(4
4
22
22
_REFRkTkTkT
A2inREFRA2ip
vn_A2VON_n
S
S
(14)
where:
vn_A1 and vn_A2 are the input voltage noises of A1 and A2,
each equal to 2.1 nV/√Hz.
in_A1, in_A2, ip_A1, and ip_A2 are amplifier input current
noise terms, each equal to 1 pA/√Hz.
RS, RF, and RG are the external source, feedback, and gain
resistors, respectively.
kT is Boltzmann’s constant times absolute temperature, equal to
4.2 x 10-21 W-s at room temperature.
RS_REF is any source resistance at the REF pin.
When A1 is used as a unity gain follower, the output voltage
noise spectral density is at its minimum, 10 nV/√Hz. Higher
voltage gains have higher output voltage noise.
Table 10, Table 11, and Table 12 show the noise contributions
and output voltage noise for the circuits in Figure 49, Figure 50,
and Figure 51.
ADA4941-1 Data Sheet
Rev. D | Page 18 of 23
Table 10. Output Voltage Noise, G = 2.4 Differential Amplifier Shown in Figure 49
Noise Source Typical Value VOP Contribution (nV√Hz) VON Contribution (nV√Hz) VO, dm Contribution (nV√Hz)
vn_A1 2.1 nV/√Hz 2.5 2.5 5
ip_A1 1 pA/√Hz 1 1 2
in_A1 1 pA/√Hz 1 1 2
√4 kTRF 4 nV/√Hz 4 4 8
√4 kTRG 9 nV/√Hz 1.8 1.8 3.6
√4 kTRS 3.6 nV/√Hz 4.4 4.4 8.8
vn_inverter 9.2 nV/√Hz 0 9.2 9.2
√RS_REF 0 0 0 0
ip_A2 × RS_REF 0 0 0 0
Totals 6.8 11.4 16.5
RF = 1.0 kΩ, RG = 4.99 kΩ, RS = 825 Ω, RS_REF = 0 Ω.
vn_inverter = noise contributions from A2 and its associated internal 1 kΩ feedback resistors and 500 Ω offset current balancing resistor.
Table 11. Output Voltage Noise, G = 2 Differential Amplifier Shown in Figure 50
Noise Source Typical Value VOP Contribution (nV√Hz) VON Contribution (nV√Hz) VO, dm Contribution (nV√Hz)
vn_A1 2.1 nV/√Hz 2.1 2.1 4.2
ip_A1 0 0 0 0
in_A1 0 0 0 0
√4 kTRF 0 0 0 0
√4 kTRG 0 0 0 0
√4 kTRS 0 0 0 0
vn_inverter 9.2 nV/√Hz 0 9.2 9.2
√RS_REF 0 0 0 0
ip_A2 × RS_REF 0 0 0 0
Totals 2.1 9.4 10
RF = 0 Ω, RG = ∞, RS = 0 Ω, RS_REF = 0 Ω.
Table 12. Output Voltage Noise, G = 5 Differential Amplifier Shown in Figure 51
Noise Source Typical Value VOP Contribution (nV√Hz) VON Contribution (nV√Hz) VO, dm Contribution (nV√Hz)
vn_A1 2.1 nV/√Hz 5.25 5.25 10.5
ip_A1 1 pA/√Hz 1 1 2
in_A1 1 pA/√Hz 1 1 2
√4 kTRF 4 nV/√Hz 4 4 8
√4 kTRG 3.26 nV/√Hz 4.9 4.9 9.8
√4 kTRS 2.54 nV/√Hz 6.54 6.54 13.1
vn_inverter 9.2 nV/√Hz 0 9.2 9.2
√RS_REF 0 0 0 0
ip_A2 × RS_REF 0 0 0 0
Totals 10.7 14.1 23.1
RF = 1.02 kΩ, RG = 665 Ω, RS = 402 Ω, RS_REF = 0 Ω.
Data Sheet ADA4941-1
Rev. D | Page 19 of 23
FREQUENCY RESPONSE VS. CLOSED-LOOP GAIN
The operational amplifiers used in the ADA4941-1 are voltage
feedback with an open-loop frequency response that can be
approximated with the integrator response, as shown in Figure 54.
100
0
0.001 100
FREQUENCY (MHz)
OPEN-LOOP GAIN (dB)
05704-062
80
60
40
20
0.01 0.1 1 10
fcr = 50MHz
Figure 54. ADA4941-1 Op Amp Open-Loop Gain vs. Frequency
For each amplifier, the frequency response can be approximated
by the following equations:
fcr
f
R
RR
R
R
VIN_A1V
G
G
F
G
F
O
1
1
1 (15)
(Noninverting Response)
fcr
f
R
RR
R
R
VIN_A2V
G
G
F
G
F
O
1
1 (16)
(Inverting Response)
fCR is the gain-bandwidth frequency of the amplifier (where the
open-loop gain shown in Figure 54 equals 1). fCR for both
amplifiers is about 50 MHz.
The inverting amplifier A2 has a fixed feedback network. The
transfer function is approximately
MHz25
1
1
MHz50
2
1
1
2_ f
VOP
f
VINAVO(17)
The frequency response of A1 depends on the external feedback
network as indicated by Equation 15. The overall differential
output voltage is therefore
VO, dm = VOP − VON = VOP + VOP ×
MHz25
1
1
f (18)
MHz25
1
1
1
MHz50
1
1
1
f
f
R
RR
R
R
VIN, dmV
G
G
F
G
F
O
(19)
Multiplying the terms and neglecting negligible terms leads to
the following approximation:
MHz25
1
MHz50
1
2
1,
ff
R
RR
R
R
VINdmV
G
G
F
G
F
O
(20)
There are two poles in this transfer function, and the lower
frequency pole limits the bandwidth of the differential
amplifier. If VOP is shorted to IN− (A1 is a unity gain follower),
the 25 MHz closed-loop bandwidth of the inverting channel
limits the overall bandwidth. When A1 is operating with higher
noise gains, the bandwidth is limited by the closed-loop
bandwidth of A1, which is inversely proportional to the noise
gain (1 + RF/RG). For instance, if the external feedback network
provides a noise gain of 10, the bandwidth drops to 5 MHz.
ADA4941-1 Data Sheet
Rev. D | Page 20 of 23
APPLICATIONS INFORMATION
OVERVIEW
The ADA4941-1 is an adjustable-gain, single-ended-to-differential
voltage amplifier, optimized for driving high resolution ADCs.
Single-ended-to-differential gain is controlled by one feedback
network, comprised of two external resistors: RF and RG.
USING THE REF PIN
The REF pin sets the output base line in the inverting path and
is used as a reference for the input signal. In most applications,
the REF pin is set to the input signal midswing level, which in
many cases is also midsupply. For bipolar signals and dual power
supplies, REF is generally set to ground. In single-supply
applications, setting REF to the input signal midswing level
provides optimal output dynamic range performance with
minimum differential offset. Note that the REF input only
affects the inverting signal path or VON.
Most applications require a differential output signal with the
same dc common-mode level on each output. It is possible for
the signal measured across VOP and VON to have a common-
mode voltage that is of the desired level but not common to
both outputs. This type of signal is generally avoided because
it does not allow for optimal use of the output dynamic range of
the amplifier.
Defining VIN as the voltage applied to the input pin, the
equations that govern the two signal paths are given in
Equation 21 and Equation 22.
VOP = VIN (21)
VON = −VIN + 2 (REF) (22)
When the REF voltage is set to the midswing level of the input
signal, the two output signals fall directly on top of each other
with minimal offset. Setting the REF voltage elsewhere results
in an offset between the two outputs.
The best use of the REF pin can be further illustrated by
considering a single-supply case with a 10 V power supply and
an input signal that varies between 2 V and 7 V. This is a case
where the midswing level of the input signal is not at midsupply
but is at 4.5 V. Setting the REF input at 4.5 V and neglecting
offsets, Equation 21 and Equation 22 are used to calculate the
results. When the input signal is at its midpoint of 4.5 V, O U T +
is at 4.5 V, as is VON. This can be considered as a base line state
where the differential output voltage is 0. When the input increases
to 7 V, VOP tracks the input to 7 V, and VON decreases to 2 V.
This can be viewed as a positive peak signal where the differential
output voltage equals 5 V. When the input signal decreases to
2 V, VOP again tracks to 2 V, a n d VON increases to 7 V. This
can be viewed as a negative peak signal where the differential
output voltage equals −5 V. The resulting differential output
voltage is 10 V p-p.
The previous discussion reveals how the single-ended-to-
differential gain of 2 is achieved.
INTERNAL FEEDBACK NETWORK POWER
DISSIPATION
While traditional op amps do not have on-chip feedback
elements, the ADA4941-1 contains two on-chip, 1 kΩ resistors
that comprise an internal feedback loop. The power dissipated
in these resistors must be included in the overall power dissipation
calculations for the device. Under certain circumstances, the
power dissipated in these resistors could be comparable to the
quiescent dissipation of the device. For example, on ±5 V supplies
with the REF pin tied to ground and OUT− at +4 VDC, each
1 kΩ resistor carries 4 mA and dissipates 16 mW for a total of
32 mW. This is comparable to the quiescent power and must
therefore be included in the overall device power dissipation
calculations. For ac signals, rms analysis is required.
DISABLE FEATURE
The ADA4941-1 includes a disable feature that can be asserted
to minimize power consumption in a device that is not needed
at a particular time. When asserted, the disable feature does not
place the device output in a high impedance or tristate condition.
The disable feature is active high. See the Specifications tables
for the high and low level voltage specifications.
Data Sheet ADA4941-1
Rev. D | Page 21 of 23
ADDING A 3-POLE, SALLEN-KEY FILTER
The noninverting amplifier in the ADA4941-1 can be used as
the buffer amplifier of a Sallen-Key filter. A 3-pole, low-pass
filter can be designed to limit the signal bandwidth in front of
an ADC. The input signal first passes through the noninverting
stage where it is filtered. The filtered signal is then passed through
the inverting stage to obtain the complementary output.
Figure 55 illustrates a 3-pole, Sallen-Key, low-pass filter with a
−3 dB cutoff frequency of 100 kHz. The 1.69 kΩ resistor is
included to minimize dc errors due to the input offset current
in A1. The passive RC filters on the outputs are generally
required by the ADC converter that is being driven. The
frequency response of the filter is shown in Figure 56.
1kΩ
1kΩ
500Ω
A2
A1
REF
IN
2
8
4
2.7nF
5
FB
+5V
–5V560pF
V
S+
V
S–
OUT+
+
–
V
O, dm
1
3
OUT–
VIN
562Ω562Ω562Ω
1.69kΩ
33Ω
33Ω
6
05704-058
0.1µF
0.1µF
2.7nF
3.9nF
10nF
Figure 55. Sallen-Key, Low-Pass Filter with 100 kHz Cutoff Frequency
0
–100
10 100M
FREQUENCY (Hz)
V
O, dm
/VIN (dB)
05704-059
–10
–20
–30
–40
–50
–60
–70
–80
–90
100 1k 10k 100k 1M 10M
V
O, dm
= 3V p-p
Figure 56. Frequency Response of the Circuit Shown in Figure 55
ADA4941-1 Data Sheet
Rev. D | Page 22 of 23
DRIVING THE AD7687 ADC
The ADA4941-1 is an excellent driver for high resolution
ADCs, such as the AD7687, as shown in Figure 57. The Sallen-
Key, low-pass filter shown in Figure 55 is included in this
example but is not required. The circuit shown in Figure 57
accepts single-ended input signals that swing between 0 V and 3 V.
The ADR443 provides a stable, low noise, 3 V reference that is
buffered by one of the AD8032 amplifiers and applied to the
AD7687 REF input, providing a differential input full-scale level
of 6 V. The reference voltage is also divided by two and buffered
to supply the midsupply REF level of 1.5 V for the ADA4941-1.
GAIN OF −2 CONFIGURATION
The ADA4941-1 can be operated in a configuration referred to
as gain of −2. Clearly, a gain of −2 can be achieved by simply
swapping the outputs of a gain of +2 circuit, but the
configuration described here is different. The configuration is
referred to as having negative gain to emphasize that the input
amplifier, A1, is operated as an inverting amplifier instead of in
its usual noninverting mode. As implied in its name, the voltage
gain from VIN to VO, dm is −2 V/V. See Figure 58 for the gain
of −2 conguration on ±5 V supplies.
The gain of −2 configuration is most useful in applications that
have wide input swings because the input common-mode
voltages are held at constant levels. The signal size is therefore
constrained by the output swing limits. The gain of −2 has a low
input resistance that is equal to RG.
1kΩ
1kΩ
GND
500Ω
A2
A1
ADA4941-1
REF
IN
IN+
IN–
2
8
4
2.7nF
5
FB
+5
V
+5V
–5V560pF
V
S+
V
S–
OUT+
1
3
OUT–
V
IN
VIN
0V TO 3V
V
OUT
562Ω562Ω562Ω
1.69kΩ
33Ω
33Ω
6
05704-060
0.1µF
0.1µF
10µF
2.7nF
3.9nF
10nF
1/2
AD8032
ADR443
4
8
1
4
0.1µF
0.1µF
3
3
4
26
2
1/2
AD8032
AD7687
7
5
6
+5V
1kΩ
1kΩ
10µF
10µF 0.1µF 0.1µF
VDD
GND
5
REF
1
2
Figure 57. ADA4941-1 Driving the AD7687 ADC
1kΩ
1kΩ
R
F
1kΩ
R
G
1kΩ
500Ω
500ΩA2
A1
REF
IN
2
8
4
5
FB
+5V
–5V
V
S+
V
S–
OUT+
1
3
6
OUT–
VIN
05704-061
+
–
V
O, dm
Figure 58. Gain of −2 Configuration
Data Sheet ADA4941-1
Rev. D | Page 23 of 23
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 59. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.55
1.45
1.35
1.84
1.74
1.64
0.203 REF
0.05 MAX
0.02 NOM
0.50 BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229-WEED
12-07-2010-A
PIN1
INDICATOR
(R0.15)
Figure 60. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description
Package
Option
Ordering
Quantity Branding
ADA4941-1YRZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 98
ADA4941-1YRZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 2,500
ADA4941-1YRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8 1,000
ADA4941-1YCPZ-R2 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 250 H0C
ADA4941-1YCPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 5,000 H0C
ADA4941-1YCPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 1,500 H0C
ADA4941-1YCP-EBZ Evaluation Board
1 Z = RoHS Compliant Part.
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