Digital Step Attenuator 50 DC-2400 MHz 31.5 dB, 0.5 dB Step 6 Bit, Serial Control Interface, Dual Supply Voltage Product Features * Dual Supply Voltage: VDD=+3V, VSS=-3V * Immune to latch up * Excellent accuracy, 0.1 dB Typ * Serial control interface * Fast switching control frequency, 1 MHz typ. * Low Insertion Loss * High IP3, +52 dBm Typ * Very low DC power consumption * Excellent return loss, 20 dB Typ * Small size 4.0 x 4.0 mm DAT-31R5-SN+ + RoHS compliant in accordance with EU Directive (2002/95/EC) The +Suffix has been added in order to identify RoHS Compliance. See our web site for RoHS Compliance methodologies and qualifications. Typical Applications * Base Station Infrastructure * Portable Wireless * CATV & DBS * MMDS & Wireless LAN * Wireless Local Loop * UNII & Hiper LAN * Power amplifier distortion canceling loops General Description The DAT-31R5-SN+ is a 50 RF digital step attenuator that offers an attenuation range up to 31.5 dB in 0.5 dB steps. The control is a 6-bit serial interface, operating on dual supply voltage: VDD=+3V, VSS=-3V. The DAT-31R5-SN+ is produced using a unique CMOS process on silicon, offering the performance of GaAs, with the advantages of conventional CMOS devices. Simplified Schematic RF Input 16dB 4dB 8dB 1dB 2dB 0.5dB RF Out Digital Serial Control '. )''#$/&-')# . REV. D M114163 ')+"$()')%&*(**!'(("& '&$"&*"&""),"+*-*"+ DAT-31R5-SN+ 071024 Page 1 of 12 DAT-31R5-SN+ Digital Step Attenuator RF Electrical Specifications, DC-2400 MHz, TAMB=25C, VDD=+3V, VSS=-3V Parameter Freq. Range (GHz) Min. Typ. DC-1 -- 1-2.4 -- DC-1 -- Max. Units 0.03 0.1 dB 0.05 0.15 dB 0.02 0.1 dB Accuracy @ 0.5 dB Attenuation Setting Accuracy @ 1 dB Attenuation Setting Accuracy @ 2 dB Attenuation Setting Accuracy @ 4 dB Attenuation Setting Accuracy @ 8 dB Attenuation Setting 1-2.4 -- 0.05 0.15 dB DC-1 -- 0.05 0.15 dB 1-2.4 -- 0.15 0.25 dB DC-1 -- 0.07 0.2 dB 1-2.4 -- 0.15 0.25 dB DC-1 -- 0.03 0.2 dB 1-2.4 -- 0.15 0.25 dB DC-1 -- 0.1 0.3 dB 1-2.4 -- 0.15 0.3 dB DC-1 -- 1.3 1.9 dB 1-2.4 -- 1.6 2.4 dB Input IP3(note 2) (at Min. and Max. Attenuation) DC-2.4 -- +52 -- dBm Input Power @ 0.2dB Compression* (at Min. and Max. Attenuation) DC-2.4 -- +24 -- dBm DC-1 -- 1.2 1.5 -- 1-2.4 -- 1.2 1.5 -- Accuracy @ 16 dB Attenuation Setting Insertion Loss(note1) @ all attenuator set to 0dB VSWR Notes: 1. I. Loss values are de-embedded from test board Loss (test board's Insertion Loss: 0.10dB @100MHz, 0.35dB @1000MHz, 0.60dB @2400MHz, 0.75dB @4000MHz) 2. Input IP3 and 1dB compression degrades below 1 MHz DC Electrical Specifications Parameter Min. Typ. Max. Units VDD, Supply Voltage 2.7 3 3.3 V VSS, Supply Voltage -3.3 -3 -2.7 V -- -- 100 A Control Input Low -- -- 0.3xVDD V Control Input High 0.7xVDD -- -- V -- -- 1 A IDD (ISS), Supply Current Control Current Switching Specifications Parameter Min. Typ. Max. Units Switching Speed, 50% Control to 0.5dB of Attenuation Value -- 1.0 -- Sec Switching Control Frequency -- 1.0 -- MHz Absolute Maximum Ratings Parameter Ratings Operating Temperature -40C to 85C Storage Temperature -55C to 100C -0.3V Min., 4V Max. VDD -4V Min., 0.3V Max. VSS -0.3V Min., VDD+0.3V Max. Voltage on any input ESD, HBM 500V ESD, MM 100V Input Power +24dBm '. )''#$/&-')# . ')+"$()')%&*(**!'(("& '&$"&*"&""),"+*-*"+ Page 2 of 12 DAT-31R5-SN+ Digital Step Attenuator Pin Description Pin Configuration (Top View) Function Pin Number C16 1 Control for Attenuation bit, 16dB (Notes 3,4) RF in 2 RF in port (Note 1) Data 3 Serial Interface data input (Note 3) Clock 4 Serial Interface clock input LE 5 Latch Enable Input (Note 2) Not connected Clock 4 LE 5 VDD 9 Positive Supply Voltage GND 10 Ground connection GND 11 Ground connection VSS 12 Negative Supply Voltage VDD 13 Positive Supply Voltage RF out 14 RF out port (Note 1) C8 15 Control for attenuation bit, 8 dB (Note 4) C4 16 Control for attenuation bit, 4 dB (Note 4) C2 17 Control for attenuation bit, 2 dB (Note 4) GND 18 Ground Connection C1 19 Control for attenuation bit, 1 dB (Note 4) C0.5 20 Control for attenuation bit, 0.5 dB (Note 4) GND Paddle C0.5 C1 GND C2 C4 20 19 18 17 16 10 8 GND N/C 9 Not connected VDD 7 8 N/C 2x2mm Paddle ground N/C 3 Data 7 RFin 2 N/C Positive Supply Voltage 1 6 6 C16 VDD VDD Description 15 C8 14 RFout 13 VDD 12 VSS 11 GND Paddle ground (Note 5) Notes: 1. Both RF ports must be held at 0VDC or DC blocked with an external series capacitor. 2. Latch Enable (LE) has an internal 100K resistor to VDD. 3. Place a 10K resistor in series, as close to pin as possible to avoid freq. resonance. 4. Refer to Power-up Control Settings. 5. The exposed solder pad on the bottom of the package (See Pin configuration) must be grounded for proper device operation. '. )''#$/&-')# . ')+"$()')%&*(**!'(("& '&$"&*"&""),"+*-*"+ Page 3 of 12 DAT-31R5-SN+ Digital Step Attenuator Typical Performance Curves INSERTION LOSS (Ref) @ +25C, +85C, -45C 8 0.9 +85C +25C -45C 7 6 0.8 0.7 5 0.6 (dB) (dB) ATTENUATION (0.5dB) @ +25C, +85C, -45C 1 0.5 4 0.4 3 -45C +25C +85C 0.3 2 0.2 1 0.1 0 0 0 500 1000 1500 2000 2500 3000 3500 0 4000 500 1000 1500 ATTENUATION (1dB) @ +25C, +85C, -45C 1.5 2.4 1.3 2.3 1.2 2.2 1.1 2.1 (dB) 1.4 (dB) 2500 3000 3500 4000 ATTENUATION (2dB) @ +25C, +85C, -45C 2.5 1 2 1.9 0.9 -45C +25C +85C 0.8 0.7 -45C +25C +85C 1.8 1.7 1.6 0.6 1.5 0.5 0 500 1000 1500 2000 2500 3000 3500 0 4000 500 1000 1500 ATTENUATION (4dB) @ +25C, +85C, -45C 4.5 2000 2500 3000 3500 4000 Frequency (MHz) Frequency (MHz) ATTENUATION (8dB) @ +25C, +85C, -45C 9 4.4 8.8 4.3 8.6 4.2 8.4 4.1 8.2 (dB) (dB) 2000 Frequency (MHz) Frequency (MHz) 4 8 7.8 3.9 7.6 3.8 -45C +25C +85C 3.7 3.6 -45C +25C +85C 7.4 7.2 3.5 7 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 Frequency (MHz) 2000 2500 3000 3500 4000 Frequency (MHz) '. )''#$/&-')# . ')+"$()')%&*(**!'(("& '&$"&*"&""),"+*-*"+ Page 4 of 12 DAT-31R5-SN+ Digital Step Attenuator Typical Performance Curves ATTENUATION (16dB) @ +25C, +85C, -45C 17 ATTENUATION (31.5dB) @ +25C, +85C, -45C 32 16.8 31 16.6 -45C +25C +85C 16.4 -45C 30 +25C (dB) (dB) 16.2 16 +85C 29 15.8 28 15.6 15.4 27 15.2 26 15 0 500 1000 1500 2000 2500 3000 3500 0 4000 500 1000 1500 RETURN LOSS IN S11 (REF) @ +25C, +85C, -45C 50 2500 3000 3500 4000 RETURN LOSS OUT S22 (REF) @ +25C, +85C, -45C 50 -45C +25C +85C 40 -45C +25C +85C 40 30 (dB) (dB) 30 20 20 10 10 0 0 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 Frequency (MHz) 2000 2500 3000 3500 4000 Frequency (MHz) RETURN LOSS IN S11(Major Attenuation Steps) @ +25C 40 30 ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=16dB ATT=31.5dB 50 40 (dB) ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=16dB ATT=31.5dB 50 RETURN LOSS OUT S22 (Major Attenuation Steps) @+25C 60 60 (dB) 2000 Frequency (MHz) Frequency (MHz) 30 20 20 10 10 0 0 0 500 1000 1500 2000 2500 3000 3500 0 4000 500 1000 1500 2000 2500 3000 3500 4000 Frequency (MHz) Frequency (MHz) '. )''#$/&-')# . ')+"$()')%&*(**!'(("& '&$"&*"&""),"+*-*"+ Page 5 of 12 DAT-31R5-SN+ Digital Step Attenuator Typical Performance Curves IP-3 INPUT (Major Attenuation Steps) @ +25C 70 60 60 50 50 (dBm) 40 20 10 (dBm) ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=16dB ATT=31.5dB 30 IP-3 INPUT (Major Attenuation Steps) @ +85C 70 40 ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=16dB ATT=31.5dB 30 20 10 0 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 0 200 400 600 800 Frequency (MHz) Frequency (MHz) IP-3 INPUT (Major Attenuation Steps) @ -45C 70 1000 1200 1400 1600 1800 2000 2200 2400 COMPRESSION @INPUT POWER=+24dBm (+25C) 0.2 60 0 -0.2 40 ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=16dB ATT=31.5dB 30 20 10 ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=16dB ATT=31.5dB (dB) (dBm) 50 -0.4 -0.6 0 -0.8 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 0 200 400 600 800 Frequency (MHz) Frequency (MHz) COMPRESSION @INPUT POWER=+24dBm (+85C) 0.2 1000 1200 1400 1600 1800 2000 2200 2400 COMPRESSION @INPUT POWER=+24dBm (-45C) 0.2 0 0 -0.2 -0.2 -0.4 -0.6 ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=16dB ATT=31.5dB (dB) (dB) ATT=0dB ATT=0.5dB ATT=1dB ATT=2dB ATT=4dB ATT=8dB ATT=16dB ATT=31.5dB -0.4 -0.6 -0.8 -0.8 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 0 200 400 600 800 Frequency (MHz) 1000 1200 1400 1600 1800 2000 2200 2400 Frequency (MHz) '. )''#$/&-')# . ')+"$()')%&*(**!'(("& '&$"&*"&""),"+*-*"+ Page 6 of 12 DAT-31R5-SN+ Digital Step Attenuator Outline Drawing (DG983-1) PCB Land Pattern Suggested Layout, Tolerance to be within .002 Device Marking Pin 1 Index MCL 31R5 + Date Code Outline Dimensions (inch mm ) WT. GRAMS A B C D E F G H J K L M N P Q R .157 .157 .035 .008 .081 .081 .010 -- .022 .020 .166 .166 .070 .012 .026 .070 4.00 4.00 0.90 0.20 2.06 2.06 0.25 -- 0.56 0.50 4.22 4.22 1.78 0.31 0.66 1.78 .04 '. )''#$/&-')# . ')+"$()')%&*(**!'(("& '&$"&*"&""),"+*-*"+ Page 7 of 12 DAT-31R5-SN+ Digital Step Attenuator Suggested Layout for PCB Design (PL-181) The suggested Layout shows only the footprint area of the DAT, and the components located near this area (i.e.: R1-R7). For the complete Layout, see photo and schematic diagram on page 11 of 12. NOTES: 1. TRACE WIDTH IS SHOWN FOR FR4 WITH DIELECTRIC THICKNESS. .025" .002". COPPER: 1/2 OZ. EACH SIDE. FOR OTHER MATERIALS TRACE WIDTH MAY NEED TO BE MODIFIED. 2. 0603 SIZE CHIP FOOT PRINTS SHOWN FOR REFERENCE, VALUES OF RESISTORS WILL VARY BASED ON APPLICATION. 3. BOTTOM SIDE OF THE PCB IS CONTINUOUS GROUND PLANE. DENOTES PCB COPPER LAYOUT WITH SMOBC (SOLDER MASK OVER BARE COPPER) DENOTES COPPER LAND PATTERN FREE OF SOLDERMASK '. )''#$/&-')# . ')+"$()')%&*(**!'(("& '&$"&*"&""),"+*-*"+ Page 8 of 12 DAT-31R5-SN+ Digital Step Attenuator Simplified Schematic RF Input 16dB 8dB 4dB 2dB RF Out 0.5dB 1dB Digital Serial Control The DAT-31R5-SN+ serial interface consists of 6 control bits that select the desired attenuation state, as shown in Table 1: Truth Table Table 1. Truth Table Attenuation State C16 C8 C4 C2 C1 C0.5 Reference 0 0 0 0 0 0 0.5 (dB) 0 0 0 0 0 1 1 (dB) 0 0 0 0 1 0 2 (dB) 0 0 0 1 0 0 4 (dB) 0 0 1 0 0 0 8 (dB) 0 1 0 0 0 0 16 (dB) 1 0 0 0 0 0 31.5 (dB) 1 1 1 1 1 1 Note: Not all 64 possible combinations of C0.5 - C16 are shown in table The serial interface is a 6-bit serial in, parallel-out shift register buffered by a transparent latch. It is controlled by three CMOS-compatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The timing for this operation is defined by Figure 1 (Serial Interface Timing Diagram) and Table 2 (Serial Interface AC Characteristics). Table 2. Serial Interface AC Characteristics Figure 1: Serial Interface Timing Diagram Symbol fclk LE Clock Data MSB LSB tSDSUP tSDHLD tLESUP tLEPW Parameter Min. Max. Units 10 MHz Serial data clock frequency (Note 1) tclkH Serial clock HIGH time 30 ns tclkL Serial clock LOW time 30 ns tLESUP LE set-up time after last clock falling edge 10 ns tLEPW LE minimum pulse width 30 ns Serial data set-up time before clock rising edge 10 ns tSDSUP Serial data hold time 10 ns after clock falling edge Note 1. fclk verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10MHz to verify fclk specification. tSDHLD '. )''#$/&-')# . ')+"$()')%&*(**!'(("& '&$"&*"&""),"+*-*"+ Page 9 of 12 DAT-31R5-SN+ Digital Step Attenuator The DAT-31R5-SN+, uses a common 6-bit serial word format, as shown in Table 3: 6-Bit attenuator Serial Programming Register Map. The first bit, the MSB, corresponds to the 16 dB Step and the last bit, the LSB, corresponds to the 0.5 dB step. Table 3. 6-Bit attenuator Serial Programming Register Map B5 B4 B3 B2 B1 B0 C16 C8 C4 C2 C1 C0.5 MSB (first in) LSB (last in) Power-up Control Settings The DAT-31R5-SN+ always assumes a specifiable attenuation setting on power-up, allowing a known attenuation state to be established before an initial serial control word is provided. When the attenuator powers up, the six control bits are set to whatever data is present on the six data inputs (C0.5 to C16). This allows any one of the 64 attenuation settings to be specified as the power-up state. '. )''#$/&-')# . ')+"$()')%&*(**!'(("& '&$"&*"&""),"+*-*"+ Page 10 of 12 DAT-31R5-SN+ Digital Step Attenuator TB-342 Evaluation Board Schematic Diagram R4 R3 R2 20 RFin 19 18 C4 C2 GND C1 C0.5 R5 R1 17 R6 16 15 C16 1 2 RFin RFout DATA R7 R8 Connected to +VDD DAT 3 13 4 7 8 11 10 9 VDD C4 R11 VSS GND GND R10 6 VDD 5 LE C3 N/C Clock R9 N/C C2 12 VDD C1 RFout C8 14 C7 C5 3 2 4 5 N/C 3 N/C LE DC SUPPLY J2 2 Vss 1 5 GND DATA 4 LE N/C 3 GND 2 LE 13 CLOCK 12 +Vcc DATA 1 SERIAL CONTROL J1 11 CLK 10 CLOCK 9 14 DATA 8 R12 + R13 IC1 7 + C8 1 GND 4 VDD 5 GND 6 C6 Bill of Materials R1 - R12 Resistor 0603 10 KOhm +/- 1% R13 Resistor 0402 0 Ohm C1 - C5 & C8 NPO Capacitor 0603 100pF +/- 5% C6, C7 Tantalum Capacitor 100nF +/- 10% IC1 Hex inverting Schmitt trigger MM74HC14 TB-342 '. )''#$/&-')# . ')+"$()')%&*(**!'(("& '&$"&*"&""),"+*-*"+ Page 11 of 12 DAT-31R5-SN+ Digital Step Attenuator Tape and Reel Packaging Information Table T&R TR No. No. of Devices Designation Letter Reel Size 3000 T 13 inch T-005 multiples of 10, less than full reel of 3K PR 13 inch multiples of 10, on tape only E not applicable Tape Width Pitch 12 mm 8 mm Unit Orientation Tape Cavity Direction of Feed Ordering Information Model No. Description DAT-31R5-SN+ Serial Interface, Dual Voltage (Negative and Positive) TB-342 Test Board Only Packaging Designation Letter (See Table T&R) Quantity Min. No. of Units Price $ Ea. E 10 $3.80 Not Applicable 1 $79.95 How to Order Example: 3000 pieces of DAT-31R5-SN+ 3K DAT-31R5-SN+ Quantity T&R=T Model No. T&R designation letter (see Table T&R) '. )''#$/&-')# . ')+"$()')%&*(**!'(("& '&$"&*"&""),"+*-*"+ Page 12 of 12