PRELIMINARY CY2SSTU32864 1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register Features * * * * * * Operating frequency: DC to 500 MHz Supports DDRII SDRAM Two operations modes: 25 bit (1:1) and 14 bit (1:2) 1.8V operation Fully JEDEC-compliant 96-ball VFBGA Functional Description All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. The CY2SSTU32864 operates from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 = 1 and C1 = 0 is not allowed and either it does or it doesn't defaults to the C0 = C1 = 0 state. The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS# and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RESET input has priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is not desired, the CSR# input can be hardwired to ground, in which case the set-up time requirement for DCS# would be the same as for the other D data inputs. The device supports low-power standby operation. When the reset input (RESET#) is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET# is low, all registers are reset and all outputs are forced low. The LVCMOS RESET# and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the low state during power-up. In the DDR-II RDIMM application, RESET# is specified to be completely asynchronous with respect to CK and CK#. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. Pin Configuration Block Diagram Cypress Semiconductor Corporation Document #: 38-07576 Rev. *A * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised May 4, 2004 PRELIMINARY CY2SSTU32864 Pin Definition Pin Number (C0=0, C1=0) Pin Name Pin Number (C0=0, C1=1) Pin Number (C0=1, C1=1) Description GND B3, B4, D3, D4, F3, F4, B3, B4, D3, D4, F3, B3, B4, D3, D4, F3, Ground H3, H4, K3, K4, M3, M4, F4, H3, H4, K3, K4, F4, H3, H4, K3, K4, M3, M4, P3, P4 M3, M4, P3, P4 P3, P4 VDD A4, C3, C4, E3, E4, G3, A4, C3, C4, E3, G4, J3, J4, L3, L4, N3, E4, G3, G4, J3, J4, L3, L4, N3, N4, R3, N4, R3, R4, T4 R4, T4 A4, C3, C4, E3, Power Supply Voltage E4, G3, G4, J3, J4, L3, L4, N3, N4, R3, R4, T4 VREF A3, T3 A3, T3 A3, T3 Input Reference Voltage ZOH J5 J5 J5 Reserved ZOL J6 J6 J6 Reserved CK H1 H1 H1 Positive Master Clock CK# J1 J1 J1 Negative Master Clock C0 G6 G6 G6 Configuration control input C1 G5 G5 G5 Configuration control input RESET# G2 G2 G2 Asynchronous reset - resets registers and disables Vref data and clock differential input receivers CSR# J2 J2 J2 Chip Select - Disables D1-D24 when both CSR# and DCS# are High (VDD) DCS# H2 H2 H2 Chip Select - Disables D1-D24 when both CSR# and DCS# are High (VDD) A1 Data input - clocked in on the crossing points of CK and CK# B1, C1 Data input - clocked in on the crossing points of CK and CK# D1 Data input - clocked in on the crossing points of CK and CK# D1 D2-3 B1, C1 B1, C1 D4 D5, 6, 8, 9, 10 E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 Data input - clocked in on the crossing points of CK and CK# D11 N1 N1 D12, 13 P1, R1 P1, R1 D14 T1 T1 D15-25 B2, C2, E2, F2, K2, L2, M2, N2, P2, R2, T2 DODT D1 D1 N1 The outputs of this register bit will not be suspended by the DCS# and CSR# Control DCKE A1 A1 T1 The outputs of this register bit will not be suspended by the DCS# and CSR# Control A5 Data Outputs that are suspended by the DCS# and CSR# control B5, C5 Data Outputs that are suspended by the DCS# and CSR# control D5 Data Outputs that are suspended by the DCS# and CSR# control B5, C5 P1, R1 Data input - clocked in on the crossing points of CK and CK# Data input - clocked in on the crossing points of CK and CK# Data input - clocked in on the crossing points of CK and CK# Q1A Q2A-3A Data input - clocked in on the crossing points of CK and CK# B5, C5 Q4A Q5A, 6A, 8A, E5, F5, K5, L5, M5 9A, 10A E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 Data Outputs that are suspended by the DCS# and CSR# control Q11A N5 N5 Document #: 38-07576 Rev. *A Page 2 of 9 PRELIMINARY CY2SSTU32864 Pin Definition (Continued) Q12A, Q13A P5, R5 P5, R5 Q14A T5 T5 Data Outputs that are suspended by the DCS# and CSR# control Q1B Q2B-3B P5, R5 B6, C6 Q4B A6 Data Outputs that are suspended by the DCS# and CSR# control B6, C6 Data Outputs that are suspended by the DCS# and CSR# control D6 Data Outputs that are suspended by the DCS# and CSR# control Q5B, 6B, 8B, 9B, 10B, E6, F6, K6, L6, M6 E6, F6, K6, L6, M6 Data Outputs that are suspended by the DCS# and CSR# control Q11B N6 Q12B, 13B P6, R6 Q14B T6 Q15-25 B6, C6, E6, F6, K6, L6, M6, N6, P6, R6, T6 QCSA# H5 QCSB# QODTA D5 QODTB QCKEA A5 QCKEB NC Data Outputs that are suspended by the DCS# and CSR# control P6, R6 Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control H5 H5 Data outputs that will not be suspended by the DCS# and CSR# control H6 H6 Data outputs that will not be suspended by the DCS# and CSR# control D5 N5 Data outputs that will not be suspended by the DCS# and CSR# control D6 N6 Data outputs that will not be suspended by the DCS# and CSR# control A5 T5 Data outputs that will not be suspended by the DCS# and CSR# control A6 T6 Data outputs that will not be suspended by the DCS# and CSR# control No Connect Pins A2, B2, C2, D2, A2, A6, D2, D6, G1, H6 A2, B2, C2, D2, E2, F2, G1, K2, L2, E2, F2, G1, K2, L2, M2, N2, P2, R2, T2 M2, N2, P2, R2, T2 Table 1. Flip Flop Function Table RESET# H H H H H H H H H H H H L Inputs CK DCS# CSR# L L L L L L L or H L H L H L H L or H H L H L H L L or H H H H H H H L or H X or Floating X or Floating X or Floating Document #: 38-07576 Rev. *A CK# L or H L or H L or H L or H X or Floating Dn, DODT, DCKE L H X L H X L H X L H X X or Floating Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs QCS# QODT, QCKE L L L H Q0 Q0 L L L H Q0 Q0 H L H H Q0 Q0 H L H H Q0 Q0 L L Page 3 of 9 PRELIMINARY CY2SSTU32864 Recommended Operating Conditions Parameter Description Condition Min. Max. Unit TA (Ind.) Ambient Operating Temp -40 85 C TA (Com.) Ambient Operating Temp 0 70 C VDD Operating Voltage 1.7 1.9 V Min. Max. Unit -0.5 VDD + 0.5 V -0.5 VDD + 0.5 V -65 150 C -0.5 2.5 V -50 50 mA Absolute Maximum Conditions Parameter VIN [1] Description Condition Input Voltage Range[2,3] [2,3] VOUT Output Voltage Range TS Storage Temperature VCC Supply Voltage Range IIK Input Clamp Current Vo < 0 or Vo > VDD IOK Output Clamp Current Vo < 0 or Vo > VDD - 50 50 mA IO Continuous Output Current Vo = 0 to VDD - 50 50 mA -100 100 mA Min. Max. Unit 0.675 1.125 V Continuous Current through VDD/GND DC Electrical Specifications Parameter Description Conditions VIX Input Differential Crossing Voltage CK, CK# IDD Static Standby Power Supply Current RESET# = GND, IO = 0, VDD = 1.9V 100 A Static Operating Power Supply Current RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0, VDD = 1.9V 40 mA IDDD RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, Power Supply Current Dynamic Operating Clock CK# switching 50% duty cycle, Only VDD = 1.8V 28 (typical) A/MHz Dynamic Operating per each Data Input RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:1 configuration 18 (typical) A/MHz RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:2 configuration 36 (typical) A/MHz Low Power Active Mode, CLK only RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, CS Enabled 27 (typical) A/MHz Low Power Active Mode per each Data Input RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:1 configuration, CS Enabled 2 (typical) A/MHz RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:2 configuration; CS Enabled 2 (typical) A/MHz VID Input Differential Voltage VREF Voltage Reference CK, CK# 600 - mV 0.49*VDD 0.51*VDD V VTT Terminating Voltage VREF-40mV VREF+40mV V Notes: 1. Stresses beyond those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. These are stresses ratings only and functional operation of the device at these or any other conditions beyond those indicated under " Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 2.5V (max.) Document #: 38-07576 Rev. *A Page 4 of 9 PRELIMINARY CY2SSTU32864 DC Electrical Specifications (Continued) Parameter Description Conditions VI Input Voltage II Input Current VI = VDD or GND VIL AC Input Low Voltage Data Inputs VIH Min. Max. Unit 0 VDD V -5 5 A - VREF-250mV V DC Input Low Voltage Data Inputs - VREF-125mV V AC Input High Voltage Data Inputs VREF+250mV - V VREF+125mV - V - 0.2 V - 0.5 V VDD-0.2 - V DC Input High Voltage Data Inputs VOL Output Low Voltage IOL = 100uA, VCC = 1.7V to 1.9V VOH Output High Voltage IOH = -100 uA, VCC = 1.7V to 1.9V 1.2 - V IOH Output High Current - -8 mA IOL Output Low Current - 8 mA IOL = 6mA, VCC = 1.7V IOH = -6 mA, VCC = 1.7V AC Electrical Specifications Parameter SLR Description Conditions Min. Max. Unit Slew Rate Rising dv/dt_r (20 to 80%) 1 4 V/ns Slew Rate Falling dv/dt_f (20 to 80%) 1 4 V/ns - 1 V/ns VI = VREF 250mV 2.5 3.5 pF 3 pF dv/dt Delta between Rising/Falling Rates CIN Ci (Data) Ci (CK and CK#) VIX = 0.9V, VID = 600mV Ci (RESET#) VI = VDD or VDD 2 2.5 pF AC Timing Specifications Parameter FCLK Description Conditions Clock Frequency TW CK,CK# H or L Min. Max. Unit - 500 MHz 1 - ns TACT[4,5] TINACT[4,5] Differential Input Active time - 10 ns Differential Input Inactive time - 15 ns TSU Set up Time DCS# before crossing CK,CK#, CSR = H, CK going high 0.7 - ns DCS# before crossing CK,CK#, CSR = L, CK going high 0.5 - ns CSR, ODT, CKE and data before crossing CK,CK#, CK going high 0.5 - ns DCS#, CSRT#, ODT, CKE and data after crossing CK,CK#, CK going high 0.5 - ns TH Hold Time TPDM Propagation Delay without switching From CK, CK# to Q 2.15 (typical) ns TPDMS Propagation Delay with switching From CK, CK# to Q simultaneous switching 2.35 (typical) ns TrPLH Propagation Delay from Low to High RESET# to Q 3 ns TrPHL Propagation Delay from High to Low RESET# Start to Q Low 3 ns Notes: 4. Data and VREF inputs must be low a minimum time of TACT max, after RESET# is taken high. 5. Data, VREF and clock inputs must be held at valid levels (not floating) a minimum time of TINACT max after RESET# is taken low. Document #: 38-07576 Rev. *A Page 5 of 9 PRELIMINARY CY2SSTU32864 Figure 1. Test Load for Timing Measurements #1 Figure 2. Voltage and Current Inputs Active and Inactive Times Figure 3. Pulse Duration Document #: 38-07576 Rev. *A Page 6 of 9 PRELIMINARY CY2SSTU32864 Figure 4. Set up and Hold Times Figure 5. Propagation Delay Figure 6. Propagation Delay after RESET# Document #: 38-07576 Rev. *A Page 7 of 9 PRELIMINARY CY2SSTU32864 Ordering Information Part Number Package Type Product Flow CY2SSTU32864BVXC 96-pin VFBGA Commercial, 0 to 70C CY2SSTU32864BVXCT 96-pin VFBGA- Tape and Reel Commercial, 0 to 70C CY2SSTU32864BVXI 96-pin VFBGA Industrial, -40 to 85C CY2SSTU32864BVXIT 96-pin VFBGA- Tape and Reel Industrial, -40 to 85C Package Drawing and Dimensions 96 FBGA (5.5 x 13.5 x 1.4 mm) BA96A O0.05 M C O0.25 M C A B O0.500.05(96X) BOTTOM VIEW TOP VIEW A1 CORNER A1 CORNER 1 2 3 4 5 6 6 5 4 3 A B C C D 6.00 E E F G H H J K 12.00 F G 13.500.10 13.500.10 1 B D J K L L M N N 0.80 M P P R R T T A 2.00 A 0.80 5.500.10 B 4.00 0.15 C 0.400.05 0.530.05 0.25 C 2 A B 5.500.10 0.15(4X) 1.20 MAX 0.26 SEATING PLANE C Document #: 38-07576 Rev. *A REFERENCE JEDEC MO-205 PKG. WEIGHT: 0.23 gms 51-85202-*A Page 8 of 9 (c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. PRELIMINARY CY2SSTU32864 Document History Page Document Title: CY2SSTU32864 1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register Document #: 38-07576 Rev. *A Rev. ECN No. Issue Date Orig. of Change ** 129199 09/09/03 RGL New Data Sheet *A 224102 See ECN RGL Added more information to complete the DS Document #: 38-07576 Rev. *A Description of Change Page 9 of 9