PRELIMINARY
1.8V, 25-bit (1:1) or 14-bit (1:2)
JEDEC-Compliant Data Register
CY2SSTU32864
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-07576 Rev. *A Revised May 4, 2004
Features
• Operating frequency: DC to 500 MHz
• Supports DDRII SDRAM
• Two operations modes: 25 bit (1:1) and 14 bit (1:2)
• 1.8V operation
• Fully JEDEC-compliant
• 96-ball VFBGA
Functional Description
All clock and data inputs are compatible with the JEDEC
standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized to
drive the DDR-II DIMM load. The CY2SSTU32864 operates
from a differential clock (CK and CK#). Data are registered at
the crossing of CK going high, and CK# going low.
The C0 input controls the pinout configuration of the 1:2 pinout
from A configuration (when low) to B configuration (when
high). The C1 input controls the pinout configuration from
25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 = 1 and
C1 = 0 is not allowed and either it does or it doesn’t defaults to
the C0 = C1 = 0 state.
The device monitors both DCS# and CSR# inputs and will gate
the Qn outputs from changing states when both DCS# and
CSR# inputs are high. If either DCS# or CSR# input is low, the
Qn outputs will function normally. The RESET input has priority
over the DCS# and CSR# control and will force the outputs
low. If the DCS#-control functionality is not desired, the CSR#
input can be hardwired to ground, in which case the set-up
time requirement for DCS# would be the same as for the other
D data inputs.
The device supports low-power standby operation. When the
reset input (RESET#) is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference
voltage (VREF) inputs are allowed. In addition, when RESET#
is low, all registers are reset and all outputs are forced low. The
LVCMOS RESET# and Cn inputs must always be held at a
valid logic high or low level. To ensure defined outputs from the
register before a stable clock has been supplied, RESET#
must be held in the low state during power-up.
In the DDR-II RDIMM application, RESET# is specified to be
completely asynchronous with respect to CK and CK#.
Therefore, no timing relationship can be guaranteed between
the two. When entering reset, the register will be cleared and
the outputs will be driven low quickly, relative to the time to
disable the differential input receivers. However, when coming
out of reset, the register will become active quickly, relative to
the time to enable the differential input receivers.
Block Diagram Pin Configuration
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CY2SSTU32864
Document #: 38-07576 Rev. *A Page 2 of 9
Pin Definition
Pin Name
Pin Number
(C0=0, C1=0)
Pin Number
(C0=0, C1=1)
Pin Number
(C0=1, C1=1) Description
GND B3, B4, D3, D4, F3, F4,
H3, H4, K3, K4, M3, M4,
P3, P4
B3, B4, D3, D4, F3,
F4, H3, H4, K3, K4,
M3, M4, P3, P4
B3, B4, D3, D4, F3,
F4, H3, H4, K3, K4,
M3, M4, P3, P4
Ground
VDD A4, C3, C4, E3, E4, G3,
G4, J3, J4, L3, L4, N3,
N4, R3, R4, T4
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
Power Supply Voltage
VREF A3, T3 A3, T3 A3, T3 Input Reference Voltage
ZOHJ5 J5J5Reserved
ZOLJ6 J6J6Reserved
CK H1 H1 H1 Positive Master Clock
CK# J1 J1 J1 Negative Master Clock
C0 G6 G6 G6 Configuration control input
C1 G5 G5 G5 Configuration control input
RESET# G2 G2 G2 Asynchronous reset – resets registers and
disables Vref data and clock differential input
receivers
CSR# J2 J2 J2 Chip Select – Disables D1-D24 when both CSR#
and DCS# are High (VDD)
DCS# H2 H2 H2 Chip Select – Disables D1-D24 when both CSR#
and DCS# are High (VDD)
D1 A1 Data input – clocked in on the crossing points of
CK and CK#
D2-3 B1, C1 B1, C1 B1, C1 Data input – clocked in on the crossing points of
CK and CK#
D4 D1 Data input – clocked in on the crossing points of
CK and CK#
D5, 6, 8, 9,
10
E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 Data input – clocked in on the crossing points of
CK and CK#
D11 N1 N1 Data input – clocked in on the crossing points of
CK and CK#
D12, 13 P1, R1 P1, R1 P1, R1 Data input – clocked in on the crossing points of
CK and CK#
D14 T1 T1 Data input – clocked in on the crossing points of
CK and CK#
D15-25 B2, C2, E2, F2, K2, L2,
M2, N2, P2, R2, T2
Data input – clocked in on the crossing points of
CK and CK#
DODT D1 D1 N1 The outputs of this register bit will not be
suspended by the DCS# and CSR# Control
DCKE A1 A1 T1 The outputs of this register bit will not be
suspended by the DCS# and CSR# Control
Q1A A5 Data Outputs that are suspended by the DCS#
and CSR# control
Q2A-3A B5, C5 B5, C5 B5, C5 Data Outputs that are suspended by the DCS#
and CSR# control
Q4A D5 Data Outputs that are suspended by the DCS#
and CSR# control
Q5A, 6A, 8A,
9A, 10A
E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 Data Outputs that are suspended by the DCS#
and CSR# control
Q11A N5 N5
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Q12A, Q13A P5, R5 P5, R5 P5, R5
Q14A T5 T5 Data Outputs that are suspended by the DCS#
and CSR# control
Q1B A6 Data Outputs that are suspended by the DCS#
and CSR# control
Q2B-3B B6, C6 B6, C6 Data Outputs that are suspended by the DCS#
and CSR# control
Q4B D6 Data Outputs that are suspended by the DCS#
and CSR# control
Q5B, 6B, 8B,
9B, 10B,
E6, F6, K6, L6, M6 E6, F6, K6, L6, M6 Data Outputs that are suspended by the DCS#
and CSR# control
Q11B N6 Data Outputs that are suspended by the DCS#
and CSR# control
Q12B, 13B P6, R6 P6, R6 Data Outputs that are suspended by the DCS#
and CSR# control
Q14B T6 Data Outputs that are suspended by the DCS#
and CSR# control
Q15-25 B6, C6, E6, F6, K6, L6,
M6, N6, P6, R6, T6
Data Outputs that are suspended by the DCS#
and CSR# control
QCSA# H5 H5 H5 Data outputs that will not be suspended by the
DCS# and CSR# control
QCSB# H6 H6 Data outputs that will not be suspended by the
DCS# and CSR# control
QODTA D5 D5 N5 Data outputs that will not be suspended by the
DCS# and CSR# control
QODTB D6 N6 Data outputs that will not be suspended by the
DCS# and CSR# control
QCKEA A5 A5 T5 Data outputs that will not be suspended by the
DCS# and CSR# control
QCKEB A6 T6 Data outputs that will not be suspended by the
DCS# and CSR# control
NC A2, A6, D2, D6, G1, H6 A2, B2, C2, D2,
E2, F2, G1, K2, L2,
M2, N2, P2, R2, T2
A2, B2, C2, D2,
E2, F2, G1, K2, L2,
M2, N2, P2, R2, T2
No Connect Pins
Pin Definition (Continued)
Table 1. Flip Flop Function Table
Inputs Outputs
RESET# DCS# CSR# CK CK# Dn, DODT, DCKE Qn QCS# QODT, QCKE
HL L L LLL
HL L H HLH
H L L L or H L or H X Q0 Q0 Q0
HL H L LLL
HL H H HLH
H L H L or H L or H X Q0 Q0 Q0
HH L L LHL
HH L H HHH
H H L L or H L or H X Q0 Q0 Q0
HH H L Q0HL
HH H H Q0HH
H H H L or H L or H X Q0 Q0 Q0
L X or Floating X or Floating X or Floating X or Floating X or Floating L L L
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Document #: 38-07576 Rev. *A Page 4 of 9
Recommended Operating Conditions
Parameter Description Condition Min. Max. Unit
TA (Ind.) Ambient Operating Temp –40 85 C
TA (Com.) Ambient Operating Temp 0 70 C
VDD Operating Voltage 1.7 1.9 V
Absolute Maximum Conditions [1]
Parameter Description Condition Min. Max. Unit
VIN Input Voltage Range[2,3] –0.5 VDD + 0.5 V
VOUT Output Voltage Range[2,3] –0.5 VDD + 0.5 V
TSStorage Temperature –65 150 C
VCC Supply Voltage Range –0.5 2.5 V
IIK Input Clamp Current Vo < 0 or Vo > VDD –50 50 mA
IOK Output Clamp Current Vo < 0 or Vo > VDD – 50 50 mA
IOContinuous Output Current Vo = 0 to VDD – 50 50 mA
Continuous Current through VDD/GND –100 100 mA
DC Electrical Specifications
Parameter Description Conditions Min. Max. Unit
VIX Input Differential Crossing
Voltage CK, CK#
0.675 1.125 V
IDD Static Standby Power
Supply Current
RESET# = GND, IO = 0, VDD = 1.9V 100 µA
Static Operating Power
Supply Current
RESET# = VDD, VI = VIH(AC) or VIL(AC), IO =
0, VDD = 1.9V
40 mA
IDDD Power Supply Current
Dynamic Operating Clock
Only
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V
28 (typical) µA/MHz
Dynamic Operating per
each Data Input
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V, 1 IO switching 1:1 configuration
18 (typical) µA/MHz
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V, 1 IO switching 1:2 configuration
36 (typical) µA/MHz
Low Power Active Mode,
CLK only
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V, CS Enabled
27 (typical) µA/MHz
Low Power Active Mode
per each Data Input
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V, 1 IO switching 1:1 configuration,
CS Enabled
2 (typical) µA/MHz
RESET# = VDD, VI = VIH(AC) or VIL(AC), CK,
CK# switching 50% duty cycle,
VDD = 1.8V, 1 IO switching 1:2 configuration;
CS Enabled
2 (typical) µA/MHz
VID Input Differential Voltage CK, CK# 600 – mV
VREF Voltage Reference 0.49*VDD 0.51*VDD V
VTT Terminating Voltage VREF–40mV VREF+40mV V
Notes:
1. Stresses beyond those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. These are stresses ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “ Recommended Operating Conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 2.5V (max.)
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VIInput Voltage 0 VDD V
IIInput Current VI = VDD or GND –5 5 µA
VIL AC Input Low Voltage Data Inputs – VREF–250mV V
DC Input Low Voltage Data Inputs – VREF–125mV V
VIH AC Input High Voltage Data Inputs VREF+250mV – V
DC Input High Voltage Data Inputs VREF+125mV – V
VOL Output Low Voltage IOL = 100uA, VCC = 1.7V to 1.9V – 0.2 V
IOL = 6mA, VCC = 1.7V – 0.5 V
VOH Output High Voltage IOH = -100 uA, VCC = 1.7V to 1.9V VDD–0.2 – V
IOH = -6 mA, VCC = 1.7V 1.2 – V
IOH Output High Current – –8 mA
IOL Output Low Current – 8 mA
AC Electrical Specifications
Parameter Description Conditions Min. Max. Unit
SLR Slew Rate Rising dv/dt_r (20 to 80%) 1 4 V/ns
Slew Rate Falling dv/dt_f (20 to 80%) 1 4 V/ns
dv/dt ∆Delta between Rising/Falling Rates – 1 V/ns
CIN Ci (Data) VI = VREF ± 250mV 2.5 3.5 pF
Ci (CK and CK#) VIX = 0.9V, VID = 600mV 2 3 pF
Ci (RESET#) VI = VDD or VDD 2.5 pF
DC Electrical Specifications (Continued)
Parameter Description Conditions Min. Max. Unit
AC Timing Specifications
Parameter Description Conditions Min. Max. Unit
FCLK Clock Frequency – 500 MHz
TWCK,CK# H or L 1 – ns
TACT[4,5] Differential Input Active time – 10 ns
TINACT[4,5] Differential Input Inactive time – 15 ns
TSU Set up Time DCS# before crossing
CK,CK#, CSR = H, CK going
high
0.7 – ns
DCS# before crossing
CK,CK#, CSR = L, CK going
high
0.5 – ns
CSR, ODT, CKE and data
before crossing CK,CK#, CK
going high
0.5 – ns
THHold Time DCS#, CSRT#, ODT, CKE and
data after crossing CK,CK#,
CK going high
0.5 – ns
TPDM Propagation Delay without switching From CK, CK# to Q 2.15 (typical) ns
TPDMS Propagation Delay with switching From CK, CK# to Q -
simultaneous switching
2.35 (typical) ns
TrPLH Propagation Delay from Low to High RESET# to Q 3 ns
TrPHL Propagation Delay from High to Low RESET# Start to Q Low 3 ns
Notes:
4. Data and VREF inputs must be low a minimum time of TACT max, after RESET# is taken high.
5. Data, VREF and clock inputs must be held at valid levels (not floating) a minimum time of TINACT max after RESET# is taken low.
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CY2SSTU32864
Document #: 38-07576 Rev. *A Page 6 of 9
Figure 1. Test Load for Timing Measurements #1
Figure 2. Voltage and Current Inputs Active and Inactive Times
Figure 3. Pulse Duration
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Document #: 38-07576 Rev. *A Page 7 of 9
Figure 4. Set up and Hold Times
Figure 5. Propagation Delay
Figure 6. Propagation Delay after RESET#
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Document #: 38-07576 Rev. *A Page 8 of 9
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress.
Package Drawing and Dimensions
Ordering Information
Part Number Package Type Product Flow
CY2SSTU32864BVXC 96-pin VFBGA Commercial, 0° to 70°C
CY2SSTU32864BVXCT 96-pin VFBGA– Tape and Reel Commercial, 0° to 70°C
CY2SSTU32864BVXI 96-pin VFBGA Industrial, –40° to 85°C
CY2SSTU32864BVXIT 96-pin VFBGA– Tape and Reel Industrial, –40° to 85°C
A
1
A1 CORNER
0.80
0.80
Ø0.50±0.05(96X)
Ø0.25 M C A B
Ø0.05 M C
B
A
0.15(4X)
0.40±0.05
1.20 MAX
C
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
A1 CORNER
TOP VIEW BOTTOM VIEW
234
4.00
12.00
B
C
D
E
F
65
465231
5.50±0.10
13.50±0.10
A
B
2.00
6.00
G
H
0.26
L
R
N
T
P
M
J
K
M
T
R
N
P
C
G
E
K
L
J
H
F
D
A
B
REFERENCE JEDEC MO-205
PKG. WEIGHT: 0.23 gms
13.50±0.10
5.50±0.10
96 FBGA (5.5 x 13.5 x 1.4 mm) BA96A
51-85202-*A
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CY2SSTU32864
Document #: 38-07576 Rev. *A Page 9 of 9
Document History Page
Document Title: CY2SSTU32864 1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register
Document #: 38-07576 Rev. *A
Rev. ECN No.
Issue
Date
Orig. of
Change Description of Change
** 129199 09/09/03 RGL New Data Sheet
*A 224102 See ECN RGL Added more information to complete the DS
