General Description
The MAX9670/MAX9671 dual SCART matrices route
audio and video signals between a set-top box
decoder chip and two external SCART connectors
under I2C control. Operating from a 3.3V supply and a
12V supply, the MAX9670/MAX9671 consume 66mW
during quiescent operation and 300mW during average
operation when driving typical signals into typical
loads. Video input detection, video load detection, and
a 2.8mW standby mode facilitate the design of intelli-
gent, low-power set-top boxes.
The MAX9670/MAX9671 audio section contains a
buffered crosspoint to route audio inputs to audio out-
puts and programmable volume control from -62dB to
0dB in 2dB steps. The DirectDrive®output amplifiers
create a 2VRMS full-scale audio signal biased around
ground, eliminating the need for bulky output capaci-
tors and reducing click-and-pop noise. The zero-cross
detection circuitry also further reduces clicks and pops
by enabling audio sources to switch only during a zero-
crossing. The MAX9671 offers TV left and right audio
inputs.
The MAX9670/MAX9671 video section contains a
buffered crosspoint to route video inputs to video out-
puts. The standard-definition video signals from the set-
top box decoder chip are lowpass filtered to remove
out-of-band artifacts.
The MAX9670/MAX9671 also support slow-switching
and fast-switching signals. An interrupt signal from the
MAX9670/MAX9671 informs the microcontroller when
the system status has changed.
Applications
Set-Top Boxes
TVs
DVD Players
Features
o66mW Quiescent Power Consumption
o2.8mW Standby Mode Consumption
oProgrammable Audio Gain Control of -62dB to
0dB (TV Audio Outputs)
oClickless, Popless, DirectDrive Audio
oVideo Input and Video Load Detection
oVideo Reconstruction Filter with 10MHz Passband
and 52dB Attenuation at 27MHz
o3.3V and 12V Supply Voltages
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
________________________________________________________________
Maxim Integrated Products
1
19-4653; Rev 2; 12/10
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Ordering Information
PART TEMP RANGE PIN-
PACKAGE
TV R+L
AUDIO
INPUTS
MAX9670CTL+ 0°C to +70°C 40 TQFN-EP* No
MAX9671CTH+ 0°C to +70°C 44 TQFN-EP* Yes
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
DirectDrive is a registered trademark of Maxim Integrated
Products, Inc.
Typical Application Circuit appears at end of data sheet.
I2C INTERFACE
REGISTERS AND
ACTIVITY
MONITOR
VIDEO FILTERS AND
CROSSPOINT
AUDIO CROSSPOINT
WITH DIRECTDRIVE
OUTPUTS, VOLUME
CONTROL
SLOW SWITCHING
FAST SWITCHING
CHARGE PUMP
V12 VAUD
VVID
12V 3.3V3.3V
EP GNDVID
µC
VIDEO
ENCODER
STEREO
AUDIO
DAC
I2C
INTERRUPT
OUTPUT
RGB, Y/C, CVBS
SINGLE-ENDED R/L
STEREO AUDIO
RGB, Y/C, CVBS
CVBS
L/R AUDIO
(MAX9671 ONLY)
SLOW SWITCHING
Y/C, CVBS
RGB, Y/C, CVBS
L/R AUDIO
SLOW SWITCHING
STB CHIP
TV
SCART
VCR
SCART
FAST SWITCHING
FAST SWITCHING
L/R AUDIO
(MAX9670 ONLY)
MAX9670/MAX9671
System Block Diagram
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at
TA= +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VVID to GNDVID........................................................-0.3V to +4V
V12 to EP.................................................................-0.3V to +14V
VAUD to EP ...............................................................-0.3V to +4V
EP to GNDVID .......................................................-0.1V to +0.1V
All Video Inputs, VCRIN_FS to GNDVID...................-0.3V to +4V
All Audio Inputs to EP .......................................-1V to (VEP + 1V)
SDA, SCL, DEV_ADDR, INT to GNDVID ..................-0.3V to +4V
TV_SS, VCR_SS to EP .................................-0.3V to (V12 + 0.3V)
Current
All Video/Audio Inputs ...................................................±20mA
C1P, C1N, CPVSS .........................................................±50mA
Output Short-Circuit Current Duration
Video and Fast-Switching Outputs to VVID,
GNDVID.................................................................Continuous
Audio Outputs to VAUD, EP .....................................Continuous
TV_SS, VCR_SS to V12, EP......................................Continuous
Continuous Power Dissipation (TA= +70°C)
40-Pin TQFN-EP (derate 26.3mW/°C above +70°C) ...2105.3mW
44-Pin TQFN-EP (derate 26.3mW/°C above +70°C)...2222.2mW
Junction-to-Case Thermal Resistance (θJC) (Note 1)
40/44-pin TQFN-EP .........................................................1°C/W
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)
40/44-pin TQFN-EP .......................................................27°C/W
Operating Temperature Range...............................0°C to +70°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Video Supply Voltage Range VVID Inferred from video PSRR test at 3V and
3.6V 3 3.3 3.6 V
Audio Supply Voltage Range VAUD Inferred from audio PSRR test at 3V and
3.6V 3 3.3 3.6 V
V12 Supply Voltage Range V12 Inferred from slow-switching levels 11.4 12 12.6 V
Normal operation; all video output
amplifiers are enabled and muted (Note 3) 16 30 mA
Standby mode, slow switch inputs low 1500
VVID Quiescent Supply Current IVID_Q
Shutdown 35 µA
Normal operation (Note 3) 3.2 6 mA
VAUD Quiescent Supply Current IAUD_Q Shutdown 35 µA
Slow-switching output
set to low-level 0.3 100
Normal operation
(Note 3) Slow-switching output
set to medium-level 475
µA
V12 Quiescent Supply Current I12_Q
Shutdown, TA = +25°C 10 µA
VIDEO CHARACTERISTICS
DC-COUPLED INPUT
VVID = 3V 1.15
VVID = 3.135V 1.15Input Voltage Range VIN
RL = 75Ω to
GNDVID or 150Ω
to VVID/2; inferred
from gain test VVID = 3.3V 1.3
VP-P
Input Current IIN VIN = 0.3V, TA = +25°C 1 2 µA
Input Resistance RIN 300 kΩ
Note 1: Package thermal resistance were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AC-COUPLED INPUT
Sync-Tip Clamp Level VCLP Sync-tip clamp -13 -4 +6 mV
Sync Crush
S ync- ti p cl am p ; p er centag e r ed ucti on i n
sync p ul se ( 0.3V
P - P
) ; g uar anteed b y i np ut
cl am p i ng cur r ent m easur em ent, TA
= + 25° C
2%
Input Clamping Current Sync-tip clamp, VIN = 0.3V, TA = +25°C 1 2 µA
Maximum Input Source
Resistance
Input sync-tip circuit must be stable even if
the source resistance is as high as 300Ω300 Ω
Bias circuit 0.57 0.6 0.63
Input Voltage High-impedance input circuit 0.3 x
VVID
0.36 x
VVID
V
Bias circuit 10
Input Resistance High-impedance input circuit 222 kΩ
DC CHARACTERISTICS
DC Voltage Gain AVGuaranteed by output voltage swing 1.95 2 2.05 V/V
DC Gain Mismatch Among R, G,
and B Outputs
Guaranteed by output voltage swing of
TV_R/C_OUT, TV_G_OUT, and TV_B_OUT;
first input signal set is VCR_R/C_IN,
VCR_G_IN, and VCR_B_IN; second signal
set is ENC_R/C_IN, ENC_G_IN, and
ENC_B_IN
-2 +2 %
Sync-tip clamp (VIN = VCLP) 0.1 0.30 0.51
Output Level Bias circuit 1.3 1.5 1.78 V
Sync-tip clamp, measured at output,
VVID = 3V, VIN = VCLP to (VCLP +1.15V),
RL = 150Ω to VVID/2, RL = 75Ω to GNDVID
2.3
Measured at output, VVID = 3.135V, VIN =
VCLP to (VCLP + 1.15V), RL = 150Ω to
VVID/2, RL = 75Ω to GNDVID
2.243 2.3 2.358
Bias circuit, measured at output, VVID = 3V,
VIN = (VBIAS - 0.575V) to (VBIAS + 0.575V),
RL = 150Ω to VVID/2, RL = 75Ω to GNDVID
2.3
Output Voltage Swing
Measured at output, VVID = 3.135V,
VIN = (VBIAS - 0.575V) to (VBIAS + 0.575V),
RL = 150Ω to VVID/2, RL = 75Ω to GNDVID
2.243 2.3 2.358
VP-P
Output Short-Circuit Current 100 mA
Output Resistance ROUT 0.5 Ω
Output Leakage Current Output disabled (load detection not active) 170 µA
Power-Supply Rejection Ratio 3V ≤ VVID ≤ 3.6V 35 dB
ELECTRICAL CHARACTERISTICS (continued)
(V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at
TA= +25°C.) (Note 2)
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at
TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AC CHARACTERISTICS
Filter Passband Flatness VOUT = 2VP-P, f = 100kHz to 5.5MHz -1 dB
f = 9.5MHz 3
f = 27MHz 40
Filter Attenuation
VOUT = 2VP-P,
attenuation is
referred to 100kHz f = 54MHz 55
dB
Slew Rate VOUT = 2VP-P, no filter in video path 60 V/µs
Settling Time VOUT = 2VP-P, settle to 0.1% (Note 4) 400 ns
Differential Gain DG 5-step modulated staircase, f = 4.43MHz 0.15 %
Differential Phase DP 5-step modulated staircase, f = 4.43MHz 0.5 Degrees
2T Pulse-to-Bar K Rating
2T = 200ns, bar time is 18µs, the beginning
2.5% and the ending 2.5% of the bar time is
ignored
0.3 K%
2T Pulse Response 2T = 200ns 0.2 K%
2T Bar Response
2T = 200ns, bar time is 18µs, the beginning
2.5% and the ending 2.5% of the bar time is
ignored
0.2 K%
Nonlinearity 5-step staircase 0.1 %
Group Delay Distortion 100kHz ≤ f ≤ 5MHz, outputs are 2VP-P 11 ns
Glitch Impulse Caused by
Charge-Pump Switching Measured at outputs 100 pV-s
Peak Signal to RMS Noise 100kHz ≤ f ≤ 5MHz 70 dB
Power-Supply Rejection Ratio f = 100kHz, 100mVP-P 47 dB
Output Impedance f = 5MHz 2 Ω
Video Crosstalk f = 4.43MHz -80 dB
Reverse Isolation
VCR SCART inputs to encoder inputs,
full-power mode with VCR being looped
through to TV, f = 4.43MHz
92 dB
Pulldown Resistance Enable VCR_R/C_OUT pulldown through
I2C interface 4.4 7.5 Ω
AUDIO CHARACTERISTICS
Voltage Gain VIN = -0.707V to +0.707V 3.95 4 4.05 V/V
Gain Mismatch VIN = -0.707V to +0.707V -1.5 +1.5 %
Flatness f = 20Hz to 20kHz, 0.25VRMS input 0.006 dB
Frequency Bandwidth 0.25VRMS input, frequency where output is
-3dB referenced to 1kHz 230 kHz
Capacitive Drive No sustained oscillations; 75Ω series
resistor on output 300 pF
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at
TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Resistance VIN = -0.707V to +0.707V 10 MΩ
Input Bias Current VIN = 0, TA = +25°C 500 nA
Input Signal Amplitude f = 1kHz, THD < 1% 0.5 VRMS
Output DC Level No input signal, VIN grounded -4 +4 mV
DC 75 100
Power-Supply Rejection Ratio f = 1kHz 90 dB
Signal-to-Noise Ratio f = 1kHz, 0.25VRMS input, 20Hz to 20kHz 96 dB
RL = 3.33kΩ, f = 1kHz, 0.25VRMS input 0.002
Total Harmonic Distortion Plus
Noise RL = 3.33kΩ, f = 1kHz, 0.5VRMS input 0.001 %
Output Impedance f = 1kHz 0.4 Ω
Volume Control Attenuation Step Programmable gain to TV SCART volume
control from -62dB to 0 2dB
Volume Control Minimum
Attenuation 0dB
Volume Control Maximum
Attenuation 62 dB
Mute Suppression f = 1kHz, 0.25VRMS input 110 dB
Audio Crosstalk f = 1kHz, 0.25VRMS input 100 dB
VIDEO-TO-AUDIO INTERACTION
Crosstalk Video input: f = 15kHz, 1VP-P signal
Audio input: f = 15kHz, 0.5VRMS signal 92 dB
CHARGE PUMP
Switching Frequency 570 kHz
FAST SWITCHING
Input Low 0.4 V
Input High Level 1V
Input Current TA = +25°C 10 µA
Output Low Voltage IOL = 0.5mA 0.1 V
Output High Voltage IOH = 0.5mA VVID -
0.1 V
Output Resistance 7Ω
Rise Time 143Ω to GNDVID 12 ns
Fall Time 143Ω to GNDVID 10 ns
SLOW SWITCHING
Input Low Voltage 2V
Input Medium Voltage 4.5 7 V
Input High Voltage 9.5 V
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at
TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Current 70 100 µA
Output Low Voltage 10kΩ to EP, 11.4V ≤ V12 ≤ 12.6V 1.5 V
Output Medium Voltage 10kΩ to EP, 11.4V ≤ V12 ≤ 12.6V 5 6.5 V
Output High Voltage 10kΩ to EP, 11.4V ≤ V12 ≤ 12.6V 10 V
DIGITAL INTERFACE
Input High Voltage VIH 0.7 x
VVID V
Input Low Voltage VIL 0.3 x
VVID V
Input Hysteresis VHYS 0.06 x
VVID V
Input Leakage Current IIH, IIL TA = +25°C -1 +1 µA
Input Capacitance 6pF
Input Current
0.1VVID < SDA < 3.3V,
0.1VVID < SCL < 3.3V
I/O pins of fast-mode devices must not
obstruct the SDA and SCL lines if V+ is
switched off, TA = +25°C
-10 +10 µA
Output Low Voltage SDA VOL ISINK = 6mA 0.4 V
Serial-Clock Frequency fSCL 0 400 kHz
Bus Free Time Between a STOP
and a START Condition tBUF 1.3 µs
Hold Time, (Repeated) START
Condition tHD
,
STA 0.6 µs
Low Period of the SCL Clock tLOW 1.3 µs
High Period of the SCL Clock tHIGH 0.6 µs
Setup Time for a Repeated
START Condition tSU
,
STA 0.6 µs
Data Hold Time tHD
,
DAT (Note 5) 0 0.9 µs
Data Setup Time tHD
,
DAT 100 ns
Fall Time of SDA Transmitting tF
ISINK ≤ 6mA, CB = total capacitance of one
bus line in pF, tR and tF measured between
0.3VVID and 0.7VVID
100 ns
Setup Time for STOP Condition tSU
,
STO 0.6 µs
Pulse Width of Spike Suppressed tSP Input filters on the SDA and SCL inputs
suppress noise spikes less than 50ns 050ns
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA= 0°C to +70°C, unless otherwise noted. Typical values are at
TA= +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OTHER DIGITAL I/O
DEV_ADDR Low Level 0.3 x
VVID V
DEV_ADDR High Level 0.7 x
VVID V
DEV_ADDR Input Current TA = +25°C -1 +1 µA
Interrupt Output Low Voltage IOL = 0.5mA 0.1 V
Interrupt Output Leakage Current INT high impedance, TA = +25°C 10 µA
Note 2: All devices are 100% production tested at TA= +25°C. Specifications over temperature limits are guaranteed by design.
Note 3: Normal operation mode is full power with input video and load detection active.
Note 4: The settling time is measured from the 50% of the input swing to the 0.1% of the final value of the output.
Note 5: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge
the undefined region of SCL’s falling edge.
Typical Operating Characteristics
(VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150Ωto GNDVID, audio load is 10kΩto EP, TA= +25°C, unless
otherwise noted.)
SMALL-SIGNAL GAIN
vs. FREQUENCY
MAX9670 toc01
FREQUENCY (Hz)
GAIN (dB)
100M10M1M
-50
-40
-30
-20
-10
0
10
-60
100k 1G
NO FILTER
VOUT = 100mVP-P
FILTER
SMALL-SIGNAL GAIN FLATNESS
vs. FREQUENCY
MAX9670 toc02
FREQUENCY (Hz)
GAIN (dB)
10M
-7
-6
-5
-4
-3
-2
-1
0
1
2
-8
1M 100M
NO FILTER
VOUT = 100mVP-P
FILTER
LARGE-SIGNAL GAIN
vs. FREQUENCY
MAX9670 toc03
FREQUENCY (Hz)
GAIN (dB)
100M10M1M
-50
-40
-30
-20
-10
0
10
-60
100k 1G
NO FILTER
VOUT = 2VP-P
FILTER
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
8 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150Ωto GNDVID, audio load is 10kΩto EP, TA= +25°C, unless
otherwise noted.)
LARGE-SIGNAL GAIN FLATNESS
vs. FREQUENCY
MAX9670 toc04
FREQUENCY (Hz)
GAIN (dB)
10M
-7
-6
-5
-4
-3
-2
-1
0
1
2
-8
1M 100M
NO FILTER
FILTER
VIDEO CROSSTALK
vs. FREQUENCY
MAX9670 toc05
FREQUENCY (Hz)
DELAY (ns)
10M1M
-100
-80
-60
-40
-20
0
-120
100k 100M
VOUT = 100mVP-P
ALL HOSTILE
GROUP DELAY
vs. FREQUENCY
MAX9670 toc06
FREQUENCY (Hz)
DELAY (ns)
10M1M
20
40
60
80
100
120
140
0
100k 100M
VOUT = 2VP-P
FILTER
NO FILTER
VIDEO POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
MAX9670 toc07
FREQUENCY (Hz)
PSRR (dB)
10M1M
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
-50
100k 100M
FILTER
NO FILTER
VIDEO VOLTAGE GAIN
vs. TEMPERATURE
MAX9670 toc08
TEMPERATURE (°C)
VOLTAGE GAIN (V/V)
5025
1.97
1.98
1.99
2.00
2.01
2.02
2.03
2.04
1.96
075
VIDEO OUTPUT VOLTAGE
vs. INPUT VOLTAGE
MAX9670 toc09
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.20.80.4
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
01.6
DIFFERENTIAL GAIN AND PHASE
MAX9670 toc10
DIFFERENTIAL PHASE (deg)
1023
45
0.4
0.6
0.2
0
-0.2
-0.4
-0.6
DIFFERENTIAL GAIN (%)
0.2
0.3
0.1
0
-0.1
-0.2
-0.3
1023
45
DIFFERENTIAL GAIN AND PHASE
MAX9670 toc11
DIFFERENTIAL PHASE (deg)
1023
45
0.4
0.6
0.2
0
-0.2
-0.4
-0.6
DIFFERENTIAL GAIN (%)
0.2
0.3
0.1
0
-0.1
-0.2
-0.3
1023
4580ns/div
2T WITH FILTER
VIDEO INPUT
200mV/div
VIDEO OUTPUT
500mV/div
MAX9670 toc12
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
_______________________________________________________________________________________ 9
Typical Operating Characteristics (continued)
(VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150Ωto GNDVID, audio load is 10kΩto EP, TA= +25°C, unless
otherwise noted.)
80ns/div
2T NO FILTER
VIDEO INPUT
200mV/div
VIDEO OUTPUT
500mV/div
MAX9670 toc13
1µs/div
12.5T WITH FILTER
VIDEO INPUT
200mV/div
VIDEO OUTPUT
500mV/div
MAX9670 toc14
1µs/div
12.5T NO FILTER
VIDEO INPUT
200mV/div
VIDEO OUTPUT
500mV/div
MAX9670 toc15
10µs/div
NTC7 WITH FILTER
VIDEO INPUT
500mV/div
VIDEO OUTPUT
1V/div
MAX9670 toc16
10µs/div
NTC7 NO FILTER
VIDEO INPUT
500mV/div
VIDEO OUTPUT
1V/div
MAX9670 toc17
2ms/div
FIELD SQUARE WAVE
VIDEO INPUT
500mV/div
VIDEO OUTPUT
1V/div
MAX9670 toc18
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150Ωto GNDVID, audio load is 10kΩto EP, TA= +25°C, unless
otherwise noted.)
VIDEO INPUT SYNC-TIP CLAMP VOLTAGE
vs. TEMPERATURE
MAX9670 toc19
TEMPERATURE (°C)
INPUT CLAMP VOLTAGE (mV)
5025
-5
-4
-3
-2
-1
0
1
2
-6
075
VIDEO INPUT BIAS VOLTAGE
vs. TEMPERATURE
MAX9670 toc20
TEMPERATURE (°C)
INPUT BIAS VOLTAGE (mV)
5025
585
590
595
600
605
610
615
620
580
075
VIDEO INPUT SYNC-TIP CLAMP CURRENT
vs. TEMPERATURE
MAX9670 toc21
TEMPERATURE (°C)
INPUT CLAMP CURRENT (mA)
5025
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
0.6
075
0
2
1
4
3
7
6
5
8
0 1.00.5 1.5 2.0 2.5 3.0 3.5
VIDEO INPUT SYNC-TIP CLAMP CURRENT
vs. INPUT VOLTAGE
MAX9670 toc22
INPUT VOLTAGE (V)
INPUT CLAMP CURRENT (µA)
VIDEO OUTPUT BIAS VOLTAGE
vs. TEMPERATURE
MAX9670 toc23
TEMPERATURE (°C)
OUTPUT BIAS VOLTAGE (V)
5025
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.50
1.42
075
AUDIO LARGE-SIGNAL GAIN
vs. FREQUENCY
MAX9670 toc24
FREQUENCY (Hz)
GAIN (dB)
100k10k1k100
-15
-10
-5
0
5
10
-20
10 1M
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________
11
0
10
5
20
15
25
30
0255075
VVID QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
MAX9670 toc28
TEMPERATURE (°C)
CURRENT (mA)
0
1
3
2
4
5
VAUD QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
MAX9670 toc29
TEMPERATURE (°C)
CURRENT (mA)
0255075
V12 QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
MAX9670 toc30
TEMPERATURE (°C)
CURRENT (nA)
5025
100
200
300
400
500
600
700
800
0
075
Typical Operating Characteristics (continued)
(VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150Ωto GNDVID, audio load is 10kΩto EP, TA= +25°C, unless
otherwise noted.)
AUDIO CROSSTALK
vs. FREQUENCY
MAX9670 toc25
FREQUENCY (Hz)
CROSSTALK (dB)
10k1k100
-100
-80
-60
-40
-20
0
-120
10 100k
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
MAX9670 toc26
FREQUENCY (Hz)
THD+N (%)
10k1k100
0.001
0.01
0.1
0.0001
10 100k
TVIN TO
VCROUT
VIN = 0.25VRMS
TVIN TO
TVOUT
VAUD POWER-SUPPLY REJECTION RATIO
(INPUT REFERRED) vs. FREQUENCY
MAX9670 toc27
FREQUENCY (Hz)
PSRR (dB)
10k1k100
-100
-80
-60
-40
-20
0
-120
10 100k
VAUD = 3.3V + 100mVP-P
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
12 ______________________________________________________________________________________
Pin Description
PIN
MAX9670 MAX9671 NAME FUNCTION
1 1 SDA Bidirectional I2C Data I/O. Output is open drain and tolerates up to 3.6V.
2 2 SCL I2C Clock Input
3 3 DEV_ADDR Device Address Set Input. Connect to GNDVID, VVID, SDA or SCL. See Table 3.
44 INT
Interrupt Output. This is an open-drain output that pulls down to GNDVID to
indicate a change in the VCR slow switching or fast switching input, the activity
status of the composite video inputs, or the load status of the composite video
outputs.
55 V
AUD Audio Supply. Connect to a 3.3V supply. Bypass with a 10µF aluminum
electrolytic capacitor and a 0.47µF ceramic capacitor to EP.
6 6 C1P Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.47µF capacitor
from C1P to C1N.
7 7 C1N Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.47µF capacitor
from C1P to C1N.
8 8 CPVSS C har g e- P um p N eg ati ve P ow er S up p l y. Byp ass w i th a 1µF cer am i c cap aci tor to E P .
9 9 ENC_INL Encoder Left-Channel Audio Input
10 10 ENC_INR Encoder Right-Channel Audio Input
— 11 TV_INL TV SCART Left-Channel Audio Input
— 12 TV_INR TV SCART Right-Channel Audio Input
11 13 VCR_INL VCR SCART Left-Channel Audio Input
12 14 VCR_INR VCR SCART Right-Channel Audio Input
13 15 TV_OUTL TV SCART Left-Channel Audio Output
14 16 VCR_OUTL VCR SCART Left-Channel Audio Output
15 17 VCR_OUTR VCR SCART Right-Channel Audio Output
16 18 TV_OUTR TV SCART Right-Channel Audio Output
17 19 TV_SS TV SCART Bidirectional Slow-Switch Signal
18 20 V12 +12V Supply for the Slow Switching Circuit. Bypass with a 10µF + 0.47µF ceramic
capacitor to EP.
19 21 VCR_SS VCR SCART Bidirectional Slow-Switch Signal
20 22 TVOUT_FS TV SCART Fast-Switching Logic Output
— 23, 44 N.C. No Connection. Leave unconnected.
21 24 VCRIN_FS VCR SCART Fast-Switching Logic Input
22 25 ENC_B_IN Encoder Blue Video Input
23 26 ENC_G_IN Encoder Green Video Input
24 27 VCR_B_IN VCR SCART Blue Video Input
25 28 VCR_G_IN VCR SCART Green Video Input
26 29 TV_B_OUT TV SCART Blue Video Output
27 30 TV_G_OUT TV SCART Green Video Output
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 13
Detailed Description
The MAX9670/MAX9671 represents Maxim’s third gen-
eration of SCART audio/video (A/V) switches. Under I2C
control, these devices route audio, video, and control
information between the set-top box decoder chip and
two SCART connectors. The audio signals are left audio
and right audio. The video signals are composite video
with blanking and sync (CVBS) and component video
(red, green, blue). S-video (Y/C) can be transported
across the SCART interface if CVBS is reassigned to
luma (Y) and red is reassigned to chroma (C). Support
for S-video is optional. The slow-switch signal and the
fast-switch signal carry control information. The slow-
switch signal is a 12V, three-level signal that indicates
whether the picture aspect ratio is 4:3 or 16:9 or causes
the television to use an internal A/V source such as an
antenna. The fast-switch signal indicates whether the
television should display CVBS or RGB signals.
CVBS, left audio, and right audio are full duplex. All the
other signals are half duplex. Therefore, one device on
the link must be designated as the transmitter, and the
other device must be designated as the receiver.
The low power consumption and the advanced monitor-
ing functions of the MAX9670/MAX9671 enable the cre-
ation of lower power set-top boxes, televisions, and
DVD players. Unlike competing SCART ICs, the audio
and video circuits of the MAX9670/MAX9671 operate
entirely from 3.3V rather than from 5V and 12V. Only the
slow-switch circuit of the MAX9670/MAX9671 requires a
12V supply. The MAX9670/MAX9671 also have circuits
that detect activity on the CVBS inputs, loads on the
CVBS outputs, and the level of the slow-switch signals.
The INT signal informs the microcontroller if there are
any changes so that the microcontroller can intelli-
gently decide whether to power up or power down
the equipment.
In addition, the MAX9670/MAX9671 have DirectDrive
audio circuitry to eliminate click-and-pop noise. With
DirectDrive, the DC bias of the audio line outputs is
always at ground, no matter whether the MAX9670/
MAX9671 are being powered up or powered down.
Conventional audio line output drivers that operate from a
single supply require series AC-coupling capacitors.
During power-up, the DC bias on the AC-coupling capac-
itor moves from ground to a positive voltage, and during
power-down, the opposite occurs. The changing DC bias
usually causes an audible transient.
Pin Description (continued)
PIN
MAX9670 MAX9671 NAME FUNCTION
28 31 GNDVID Video Ground
29 32 VCR_R/C_IN VCR SCART Red/Chroma Video Input
30 33 VVID
Video and Digital Supply. Connect to a 3.3V supply. Bypass with parallel 1µF and
0.1µF ceramic capacitors to GNDVID. VVID also serves as a digital supply for the
I2C interface.
31 34 ENC_C_IN Encoder Chroma Video Input
32 35 ENC_R/C_IN Encoder Red/Chroma Video Input
33 36 TV_R/C_OUT TV SCART Red/Chroma Video Output
34 37 VCR_R/C_OUT VCR SCART Red/Chroma Video Output
35 38 VCR_Y/CVBS_OUT VCR SCART Luma/Composite Video Output
36 39 TV_Y/CVBS_OUT TV SCART Luma/Composite Video Output
37 40 VCR_Y/CVBS_IN VCR SCART Luma/Composite Video Input
38 41 TV_Y/CVBS_IN TV SCART Luma/Composite Video Input
39 42 ENC_Y_IN Encoder Luma Video Input
40 43 ENC_Y/CVBS_IN Encoder Luma/Composite Video Input
—— EP
Exposed Pad. The exposed pad is the internal ground for the audio amplifiers and
charge pump. A low-impedance connection between ground and EP is required
for proper isolation.
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
14 ______________________________________________________________________________________
Audio Section
The MAX9670 audio circuit is essentially a stereo,
2-by-2, nonblocking, audio crosspoint with output dri-
vers. The encoder (stereo audio DAC) and the VCR are
the two input sources, and the two outputs go to the TV
SCART connector and the VCR SCART connector. See
Figure 1. The MAX9671 audio circuit is similar to that of
the MAX9670 except that it is a stereo, 3-by-2,
nonblocking audio crosspoint with TV as the third input
source.
The integrated charge pump inverts the +3.3V supply
to create a -3.3V supply. The audio circuit operates
from bipolar supplies so the audio signal is always
biased to ground.
ENC_INL
VCR_INL
x4
ZCD
(0.5VRMS FULL-SCALE INPUT) (2VRMS FULL-SCALE OUTPUT)
(2VRMS FULL-SCALE OUTPUT)
TV_OUTL
TV_OUTR
MUTE
VAUD
C1P
EP
C1N
CPVSS
CHARGE
PUMP
SCL
SDA REGISTER
CONTROL
DEV_ADDR
MUTE
MUTE
MUTE
MUTE
VCR_OUTL
VCR_OUTR
*TV_INL
ENC_INR
VCR_INR
*TV_INR
x4
x4
VOLUME
CONTROL
0dB TO -62dB
VOLUME
CONTROL
0dB TO -62dB
*MAX9671 ONLY.
MUTE
MAX9670/MAX9671
x4
Figure 1. MAX9670/MAX9671 Audio Section Functional Diagram
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 15
Clickless Switching
The TV audio channel incorporates a zero-crossing
detect (ZCD) circuit that minimizes click noise due to
abrupt signal level changes that occur when switching
between audio signals at an arbitrary moment.
To implement the zero-crossing function when switch-
ing audio signals, set the ZCD bit high (Audio Control
register 00h, bit 6). Then set the mute bit high (Audio
Control register 00h, bit 0). Next, wait for a sufficient
period of time for the audio signal to cross zero. This
period is a function of the audio signal path’s low-fre-
quency 3dB corner (fL3dB). Thus, if fL3dB = 20Hz, the
time period to wait for a zero-crossing detect is 1/20Hz
or 50ms.
After the wait period, select a new audio source for the
TV audio channel by writing to bits 1 and 0 of TV Audio
Control register (01h). Finally, clear mute (Audio Control
register, 00h, bit 0), but leave ZCD (Audio Control reg-
ister 00h, bit 6) high. The MAX9670/MAX9671 switches
the signal out of mute at the next zero crossing. See
Tables 12 and 13.
Audio Outputs
The MAX9670/MAX9671 audio output amplifiers feature
Maxim’s DirectDrive architecture, thereby eliminating
the need for output-coupling capacitors required by
conventional single-supply audio line drivers. An inter-
nal charge pump inverts the positive supply (VAUD),
creating a negative supply (CPVSS). The audio output
amplifiers operate from these bipolar supplies with their
outputs biased about audio ground (Figure 2). The ben-
efit of this audio ground bias is that the amplifier out-
puts do not have a DC component. The DC-blocking
capacitors required with conventional audio line drivers
are unnecessary, conserving board space, reducing
system cost, and improving frequency response.
Conventional single-supply audio line drivers have their
outputs biased about a nominal DC voltage (typically
half the supply) for maximum dynamic range. Large
coupling capacitors are needed to block this DC bias.
Clicks and pops are created when the coupling capaci-
tors are charged during power-up and discharged dur-
ing power-down.
The MAX9670/MAX9671 features a low-noise charge
pump that requires only two small ceramic capacitors.
The 580kHz switching frequency is well beyond the
audio range and does not interfere with audio signals.
The switch drivers feature a controlled switching speed
that minimizes noise generated by turn-on and turn-off
transients.
The SCART standard specifies 2VRMS as the full-scale
for audio signals. As the audio circuits process
0.5VRMS full-scale audio signals internal to the
MAX9670/MAX9671, the gain-of-4 output amplifiers
restore the audio signals to a full-scale of 2VRMS.
To select which audio input source is routed to the TV
SCART connector, write to bits 1 and 0 of the TV Audio
Control register (01h). To select which audio input
source is routed to the VCR SCART connector, write to
bits 3 and 2 of the TV Audio Control register (01h). The
power-on default is for the TV and VCR audio outputs to
be muted (the inputs of the output amplifiers are con-
nected to audio ground). See Tables 10 and 13.
Volume Control
Volume control is programmable from -62dB to 0dB in
2dB steps through I2C interface. The block consists of
a resistive ladder network to generate 31 2dB volume
control steps, a unity gain buffer to isolate the input
from the resistive ladder, switches (MPLx and MNLx)
that select 1 of 32 nodes on the resistive ladder, and
logic to decode the the I2C volume control value. See
Table 12.
+VDD
-VDD
GND VOUT
CONVENTIONAL DRIVER-BIASING SCHEME
DirectDrive BIASING SCHEME
VDD/2
VDD
VDD
GND
2VDD
Figure 2. Conventional Driver Output Waveform vs. MAX9670/
MAX9671 Output Waveform.
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
16 ______________________________________________________________________________________
Video Section
The video circuit routes different video formats between
the set-top box decoder, the TV SCART connector, and
the VCR SCART connector. It also routes slow-switch
and fast-switch control information. See Figure 3.
MAX9670/MAX9671
AV = 2V/V
TV_Y/CVBS_IN
MUTE
TV_Y/CVBS_OUT
LOAD SENSE
AV = 2V/V VCR_Y/CVBS_OUT
LOAD SENSE
CLAMP
VCR_Y/CVBS_IN CLAMP
ENC_Y/CVBS_IN CLAMP
ENC_Y_IN CLAMP
ACTIVITY DETECT
ACTIVITY DETECT
ACTIVITY DETECT
ACTIVITY DETECT
LPF
LPF
AV = 2V/V
MUTE
TV_R/C_OUT
AV = 2V/V VCR_R/C_OUT
VCR_R/C_IN CLAMP/BIAS
ENC_R/C_IN CLAMP/BIAS
ENC_C_IN CLAMP/BIAS
LPF
LPF
AV = 2V/V
MUTE
TV_G_OUT
VCR_G_IN CLAMP
ENC_G_IN CLAMP LPF
AV = 2V/V
MUTE
TV_B_OUT
VCR_B_IN CLAMP
ENC_B_IN CLAMP LPF
AV = 1V/V
VCRIN_FS
0.7V
VVID
GNDVID
TVOUT_FS
TO I2C
AV = 1V/V
V12
+6V
EP
TV_SS
x1
TO I2C
AV = 1V/V
V12
+6V
EP
VCR_SS
x1
Figure 3. MAX9670/MAX9671 Video Section Function Diagram
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 17
Video Inputs
Whether the incoming video signal is AC-coupled or
DC-coupled into the MAX9670/MAX9671 depends
upon the origin, format, and voltage range of the video
signal. Table 1 below shows the recommended con-
nections. Always AC-couple an external video signal
through a 0.1µF capacitor because its voltage is not
well defined (see the
Typical Application Circuit
). For
example, the video transmitter circuit might have a dif-
ferent ground than the video receiver, thereby level
shifting the DC bias. 60Hz power line hum might cause
the video signal to change DC bias slowly.
Internal video signals that are between 0 and 1V can be
DC-coupled. Most video DACs generate video signals
between 0 and 1V because the video DAC sources cur-
rent into a ground-referenced resistor. For the minority
of video DACs that generate video signals between
2.3V and 3.3V because the video DAC sinks current
from a VVID-referenced resistor, AC-couple the video
signal to the MAX9670/MAX9671.
The MAX9670/MAX9671 restore the DC level of incom-
ing, AC-coupled video signals with either transparent
sync-tip clamps or bias circuits. When using an AC-
coupled input, the transparent sync-tip clamp automati-
cally clamps the input signal minimum to ground,
preventing it from going lower. A small current of 1µA
pulls down on the input to prevent an AC-coupled sig-
nal from drifting outside the input range of the part. Use
sync-tip clamps with CVBS, RGB, and luma signals.
The transparent sync-tip clamp is transparent when the
incoming video signal is DC-coupled and at or above
ground. Under such conditions, the clamp never acti-
vates. Therefore, the outputs of video DACs that gener-
ate signals between 0 and 1V can be directly
connected to the MAX9670/MAX9671 inputs.
The bias circuit accepts AC-coupled chroma, which is
a subcarrier with the color information modulated onto
it. The bias voltage of the bias circuits is around
600mV.
ENC_R/C_IN and VCR_R/C_IN can receive either a red
video signal or a chroma video signal. Set the input con-
figuration by writing to bits 7 and 3 of the VCR Video
Input Control register (08h). See Tables 10 and 16.
The MAX9670/MAX9671 also have video input detec-
tion. When activated, activity detect circuits check if
sync is present on incoming CVBS and luma (Y) sig-
nals. If so, then there is a valid video signal. Read bits
0, 2, 4, and 5 of the Video Activity Status register (0Fh)
to determine the status of the CVBS and luma (Y)
inputs. See Table 21.
In high-impedance mode, the inputs to the MAX9670/
MAX9671 do not distort the video signal in case the out-
puts of the video DAC are also connected to another
video circuit such as a high-definition video filter amplifi-
er. See the
SCART Set-Top Box with Analog HD Outputs
section. The inputs in high-impedance mode are biased
at VVID/3, which is sufficiently above ground so that the
ESD diodes never forward biases as the video signal
changes. The input resistance is 222kΩ, which presents
negligible loading on the video current DAC.
Video Reconstruction Filter
The video DAC outputs of the set-top box decoder chip
need to be lowpass-filtered to reject the out-of-band
noise. The MAX9670/MAX9671 integrate sixth-order,
Butterworth filters. The filter passband (±1dB) is typical-
ly 5.5MHz, and the attenuation at 27MHz is 52dB. The
filters are suited for standard-definition video.
Video Outputs
The video output amplifiers can both source and sink
load current, allowing output loads to be DC- or AC-
coupled. The amplifier output stage needs around
300mV of headroom from either supply rail. For video
signals with a sync pulse, the sync tip is typically at
300mV, as shown in Figure 4. For a chroma signal, the
blank level is typically at 1.5V, as shown in Figure 5.
If the supply voltage is greater than 3.135V (5% below
a 3.3V supply), each amplifier can drive two DC-cou-
pled video loads to ground. If the supply is less than
3.135V, each amplifier can drive only one DC-coupled
or AC-coupled video load.
The SCART standard allows for video signals to have a
superimposed DC component within 0 and 2V.
Therefore, most video signals are DC-coupled at the
output. In the unlikely event that the video signal needs
to be AC-coupled, the coupling capacitors should be
220µF or greater to keep the highpass filter formed by
the 37.5Ωequivalent resistance of the video transmis-
sion line to a corner frequency of 4.8Hz or below to keep
it well below the 25Hz frame rate of the PAL standard.
The CVBS outputs have load sense circuits. If enabled,
each load sense circuit checks for a load eight times
per second by connecting an internal 15kΩpullup
resistor to the output for 1ms. If the output is pulled up,
no load is present. If the output stays low, a load is con-
nected. Read bits 1 and 3 of the Video Activity Status
register (0Fh) to determine load status. See Table 21.
The selection of video sources that are sent to the TV
SCART connector are controlled by bits 0 to 4 of the TV
Video Input Control register (06h) while the selection of
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
18 ______________________________________________________________________________________
video sources that are sent to the VCR SCART connec-
tor are controlled by bits 0 to 2 of the VCR Video Input
Control register (08h). See Tables 10, 14, and 16. The
video outputs can be enabled or disabled by bits 2
through 7 of the Output Enable register (0Dh). See
Table 18.
Slow Switching
The MAX9670/MAX9671 support the IEC 933-1,
Amendment 1, three-level slow switching that selects
the aspect ratio for the display (TV). Under I2C control,
the MAX9670/MAX9671 set the slow-switching output
voltage level. Table 2 shows the valid input levels of the
slow-switching signal and the corresponding operating
modes of the display device.
Two bidirectional ports are available for slow-switching
signals for the TV and VCR. The slow-switching input
status is continuously read and stored in the Status reg-
ister (0Eh). The slow-switching outputs can be set to a
logic level or high impedance by writing to the TV Video
Output Control register (07h) and the VCR Video Output
Control register (09h). When enabled, INT becomes
active low if the voltage level changes on TV_SS or
VCR_SS. See Tables 10, 15, 17, and 20.
Fast Switching
The fast-switching signal was originally used to switch
between CVBS and RGB signals on a pixel-by-pixel
basis so that on-screen display (OSD) information
could be inserted. Since modern set-top box decoder
chips have integrated OSD circuitry, there is no need to
create OSD information using the older technique. Now,
the fast-switching signal is just used to switch between
CVBS and RGB signal sources.
Set the source of the fast-switching signal by writing to
bits 4 and 3 of the TV Video Output Control register
(07h). The fast-switching signal to the TV SCART con-
nector can be enabled or disabled by bit 1 of the Output
Enable register (0Dh). See Tables 10, 15, and 18.
I
2
C Serial Interface
The MAX9670/MAX9671 feature an I2C/SMBus™-com-
patible, 2-wire serial interface consisting of a serial-data
line (SDA) and a serial-clock line (SCL). SDA and SCL
facilitate communication between the MAX9670/
MAX9671 and the master at clock rates up to 400kHz.
Figure 6 shows the 2-wire interface timing diagram. The
master generates SCL and initiates data transfer on the
bus. A master device writes data to the MAX9670/
MAX9671 by transmitting a START (S) condition, the
proper slave address with the R/Wbit set to 0, followed
by the register address and then the data word. Each
transmit sequence is framed by a START and a STOP
(P) condition. Each word transmitted to the
MAX9670/MAX9671 is 8 bits long and is followed by an
acknowledge clock pulse. A master reads from the
MAX9670/MAX9671 by transmitting the slave address
with the R/Wbit set to 0, the register address of the reg-
ister to be read, a REPEATED START (Sr) condition, the
slave address with the R/Wbit set to 1, followed by a
series of SCL pulses. The MAX9670/MAX9671 transmit
data on SDA in sync with the master-generated SCL
pulses. The master acknowledges receipt of each byte
of data. Each read sequence is framed by a START or
MAX9670 fig04
20µs/div
INPUT
500mV/div
OUTPUT
500mV/div
Figure 4. MAX9670/MAX9671 Video Output with CVBS Signal,
Multiburst Video Test Signal Shown
MAX9670 fig05
10µs/div
INPUT
200mV/div
OUTPUT
200mV/div
Figure 5. MAX9670/MAX9671 Video Output with Chroma (C)
Signal, Multiburst Video Test Signal Shown
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 19
REPEATED START condition, an acknowledge or a not
acknowledge, and a STOP condition. SDA operates as
both an input and an open-drain output. A pullup resis-
tor, typically greater than 500Ω, is required on the SDA
bus. SCL operates as only an input. A pullup resistor,
typically greater than 500Ω, is required on SCL if there
are multiple masters on the bus, or if the master in a
single-master system has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the
MAX9670/MAX9671 from high-voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the
START and STOP
Conditions
section). SDA and SCL idle high when the
I2C bus is not busy.
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 7). A
START condition from the master signals the beginning
of a transmission to the MAX9670/MAX9671. The mas-
ter terminates transmission, and frees the bus, by issu-
ing a STOP condition. The bus remains active if a
REPEATED START condition is generated instead of a
STOP condition.
Early STOP Conditions
The MAX9670/MAX9671 recognize a STOP condition at
any point during data transmission except if the STOP
condition occurs in the same high pulse as a START
condition. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Slave Address
The slave address is defined as the 7 most significant
bits (MSBs) followed by the read/write (R/W) bit. Set the
R/Wbit to 1 to configure the MAX9670/MAX9671 to
read mode. Set the R/Wbit to 0 to configure the
MAX9670/MAX9671 to write mode. The slave address
is always the first byte of information sent to the
MAX9670/MAX9671 after a START or a REPEATED
START condition. The MAX9670/MAX9671 slave
address is configurable with DEV_ADDR. Table 3
shows the possible slave addresses for the
MAX9670/MAX9671.
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START CONDITION
START
CONDITION
tHD, STA
tSU, STA tHD, STA tSP
tBUF
tSU, STO
tLOW
tSU, DAT
tHD, DAT
tHIGH
tRtF
Figure 6. I
2
C Serial-Interface Timing Diagram
SCL
SDA
SSrP
Figure 7. START, STOP, and REPEATED START Conditions
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
20 ______________________________________________________________________________________
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9670/MAX9671 use to handshake receipt of each
byte of data when in write mode (see Figure 8). The
MAX9670/MAX9671 pull down SDA during the entire
master-generated ninth clock pulse if the previous byte
is successfully received. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master may retry
communication. The master pulls down SDA during the
ninth clock cycle to acknowledge receipt of data when
the MAX9670/MAX9671 are in read mode. An acknowl-
edge is sent by the master after each read byte to allow
data transfer to continue. A not acknowledge is sent
when the master reads the final byte of data from the
MAX9670/MAX9671, followed by a STOP condition.
Write Data Format
A write to the MAX9670/MAX9671 consists of transmit-
ting a START condition, the slave address with the R/W
bit set to 0, one data byte to configure the internal reg-
ister address pointer, one or more data bytes, and a
STOP condition. Figure 9 illustrates the proper frame
format for writing one byte of data to the
MAX9670/MAX9671. Figure 10 illustrates the frame for-
mat for writing n bytes of data to the MAX9670/
MAX9671.
The slave address with the R/Wbit set to 0 indicates
that the master intends to write data to the MAX9670/
MAX9671. The MAX9670/MAX9671 acknowledge
receipt of the address byte during the master-generat-
ed ninth SCL pulse.
The second byte transmitted from the master config-
ures the MAX9670/MAX9671’s internal register address
pointer. The pointer tells the MAX9670/MAX9671 where
to write the next byte of data. An acknowledge pulse is
sent by the MAX9670/MAX9671 upon receipt of the
address pointer data.
1
SCL
START
CONDITION
SDA
289
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
Figure 8. Acknowledge
A
0SLAVE ADDRESS REGISTER ADDRESS DATA BYTE
ACKNOWLEDGE FROM MAX9670/MAX9671
R/W 1 BYTE
ACKNOWLEDGE FROM MAX9670/MAX9671
ACKNOWLEDGE FROM MAX9670/MAX9671
B1 B0B3 B2B5 B4B7 B6
S AA P
Figure 9. Writing a Byte of Data to the MAX9670/MAX9671
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9670/MAX9671
ACKNOWLEDGE FROM
MAX9670/MAX9671
B1 B0B3 B2B5 B4B7 B6
AA0
ACKNOWLEDGE FROM MAX9670/MAX9671
R/W
SA
1 BYTE
ACKNOWLEDGE FROM
MAX9670/MAX9671
B1 B0B3 B2B5 B4B7 B6
P
A
SLAVE ADDRESS REGISTER ADDRESS DATA BYTE 1 DATA BYTE n
Figure 10. Writing n Bytes of Data to the MAX9670/MAX9671
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 21
The third byte sent to the MAX9670/MAX9671 contains
the data that is written to the chosen register. An
acknowledge pulse from the MAX9670/MAX9671 sig-
nals receipt of the data byte. The address pointer
autoincrements to the next register address after each
received data byte. This autoincrement feature allows a
master to write to sequential register address locations
within one continuous frame. The master signals the
end of transmission by issuing a STOP condition.
Read Data Format
The master presets the address pointer by first sending
the MAX9670/MAX9671’s slave address with the R/W
bit set to 0 followed by the register address after a
START condition. The MAX9670/MAX9671 acknowl-
edges receipt of its slave address and the register
address by pulling SDA low during the ninth SCL clock
pulse. A REPEATED START condition is then sent fol-
lowed by the slave address with the R/Wbit set to 1.
The MAX9670/MAX9671 transmits the contents of the
specified register. Transmitted data is valid on the ris-
ing edge of the master-generated serial clock (SCL).
The address pointer autoincrements after each read
data byte. This autoincrement feature allows all regis-
ters to be read sequentially within one continuous
frame. A STOP condition can be issued after any num-
ber of read data bytes. If a STOP condition is issued
followed by another read operation, the first data byte
to be read is from the register address location set by
the previous transaction and not 00h and subsequent
reads autoincrement the address pointer until the next
STOP condition. Attempting to read from register
addresses higher than 10h results in repeated reads
from a dummy register containing FFh data. The master
acknowledges receipt of each read byte during the
acknowledge clock pulse. The master must acknowl-
edge all correctly received bytes except the last byte.
The final byte must be followed by a not acknowledge
from the master and then a STOP condition. Figures 11
and 12 illustrate the frame format for reading data from
the MAX9670/MAX9671.
Interrupt Output
When interrupt is enabled in modes 1 and 2, INT, which
is an open-drain output, pulls low under the following
conditions: slow-switch signals change value, CVBS
input signals are detected or disappear, and CVBS out-
put loads are added or removed.
When interrupt is enabled in mode 3, INT pulls low only
when the slow-switch signal changes value.
Enable INT by writing a 1 into bit 4 of register 01h. See
Table 13.
The interrupt can be cleared by reading register 0Eh
and 0Fh.
Applications Information
Audio Inputs
The maximum full-scale audio signal that can be
applied to the audio inputs is 0.5VRMS biased at
ground. The recommended application circuit to atten-
uate and bias an incoming audio signal is shown in
Figure 13.
ACKNOWLEDGE FROM
MAX9670/MAX9671
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM
MAX9670/MAX9671
NOT ACKNOWLEDGE FROM MASTER
AA PA
0
ACKNOWLEDGE FROM
MAX9670/MAX9671
R/W
SA
R/WREPEATED START
Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE
Figure 11. Reading One Indexed Byte of Data from the MAX9670/MAX9671
ACKNOWLEDGE FROM
MAX9670/MAX9671
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM
MAX9670/MAX9671
AA AP
0
ACKNOWLEDGE FROM
MAX9670/MAX9671
R/W
SA
R/W
REPEATED START
Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE
NOT ACKNOWLEDGE FROM MASTER
Figure 12. Reading n Bytes of Indexed Data from the MAX9670/MAX9671
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
22 ______________________________________________________________________________________
The audio path has a gain of 4V/V so that the full scale
of the audio output signal is 2VRMS. If less than 2VRMS,
full scale is desired at the audio outputs, and the full
scale of the audio input signal should be proportionate-
ly decreased below 0.5VRMS.
Operating Modes
The MAX9670/MAX9671 has four operating modes,
which can be set by writing to bits 6 and 7 of register
10h. See Table 19.
Shutdown
All circuitry is shutdown in the MAX9670/MAX9671
except for the I2C interface, which is designed with sta-
tic CMOS logic. Except for register 10h, which sets the
operating mode, the values in all of the other I2C regis-
ters are preserved while entering, during, and leaving
shutdown mode.
Standby Mode
In standby mode, the MAX9670/MAX9671 monitor the
slow-switch signals and decide whether to loop through
the audio/video signals. If the VCR slow switch input
has activity (6V or 12V at the input), the audio/video sig-
nals are looped through from the VCR SCART to the TV
SCART. If the TV slow-switch input has activity, the
audio/video signals are looped through from the TV
SCART to the VCR SCART. If neither the VCR slow-
switch input nor the TV slow switch input show activity,
i.e., both inputs are at ground, no signals are looped
through. If both the VCR slow-switch input and the TV
slow-switch input have activity, the MAX9670/MAX9671
considers this condition to be illegal and does not loop
through any signals.
A finite state machine (Figure 14) controls the operation
of the MAX9670/MAX9671. State 0 is always the initial
state when the MAX9670/MAX9671 enter standby
mode. Table 4 shows the values of the I2C registers in
state 0. The state machine sets the other I2C registers
to the correct values to loop through the audio/video
signals in states 1 and 2 (see Tables 5 and 6). When
the MAX9670/MAX9671 leaves standby mode, the val-
ues in all of the I2C registers except register 10h are
preserved so that the operation is not disturbed. For
example, if in standby mode, the MAX9670 is looping
through the audio/video signals from VCR SCART to TV
SCART, and if the microcontroller changes the operat-
ing mode from standby mode to full-power mode, the
audio/video signals continue to be looped through dur-
ing and after the mode change. The user does not
experience any disruption in audio or video service.
The microcontroller can be turned off in standby mode
because the MAX9670/MAX9671 operate autonomous-
ly. Upon power-up, the default operating mode is
standby mode.
Full-Power Mode with Video Input Detection
and Video Load Detection
In this mode, the MAX9670/MAX9671 are fully on. If
interrupt is enabled, INT goes active low whenever the
slow-switch signal changes; a CVBS signal appears or
disappears; or a CVBS load appears or disappears.
The microcontroller can decide whether to change the
routing configuration or operating mode of the
MAX9670/MAX9671.
Full-Power Mode Without Video Input Detection
and Video Load Detection
This mode is similar to the above mode except that
video input detection and video load detection are not
active. If interrupt is enabled, INT goes active low only
when the slow-switch signal changes.
Power Consumption
The quiescent power consumption and average power
consumption of the MAX9670/MAX9671 are very low
because of 3.3V operation and low-power circuit design.
Quiescent power consumption is defined when the
MAX9670/MAX9671 are operating without loads and
without any audio or video signals. Table 7 shows the
quiescent power consumption in all 4 operating modes.
Average power consumption is defined when the MAX9670/
MAX9671 drives typical signals into typical loads. Table 8
shows the average power consumption in full-power
mode and Table 9 shows the input and output conditions.
MAX9670
1µF6.65kΩ
*R1 VALUES
DAC = CS4334/5/8/9: R1 = 4.53kΩ, 1%
DAC = PCM1742: R1 = 5.57kΩ, 1%
R1*
ENC_INL
1µF6.65kΩ
R1*
ENC_INR
STEREO
AUDIO
DACS
Figure 13. Application circuit to connect audio source to audio
inputs. The 1µF capacitor connected to the ground-referenced
resistors biases the audio signal at ground. The resistors atten-
uate the audio signal.
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 23
S-Video
The MAX9670/MAX9671 support S-video from the set-
top box to the TV, set-top box to the VCR, and VCR to
the set-top box. S-video was not included in the original
SCART specifications but was added afterwards. As a
consequence, the luma (Y) signal of S-video shares the
same SCART pin as the CVBS signal. Likewise, the
chroma (C) signal shares the same SCART pin as the
red signal. The pins that can carry both CVBS and luma
have Y/CVBS in their names, and the pins that can
carry red and chroma have R/C in their names.
Now, the Y/CVBS signals are full duplex while the R/C
signals are half duplex. Therefore, S-video is limited to
being half duplex. The MAX9670/MAX9671 have to
transmit a chroma signal and receive a chroma signal
TV_SS NOT ACTIVE
VCR_SS NOT ACTIVE
TV_SS ACTIVE
VCR_SS ACTIVE
TV_SS NOT ACTIVE
VCR_SS ACTIVE
TV_SS ACTIVE
VCR_SS NOT ACTIVE
TV_SS NOT ACTIVE
VCR_SS ACTIVE
TV_SS ACTIVE
VCR_SS NOT ACTIVE
TV_SS NOT ACTIVE
VCR_SS ACTIVE
TV_SS NOT ACTIVE
VCR_SS NOT ACTIVE
TV_SS NOT ACTIVE
VCR_SS NOT ACTIVE
TV_SS ACTIVE
VCR_SS NOT ACTIVE
STATE 0
SEARCH
AUDIO: INACTIVE
VIDEO: INACTIVE
SLOW SWITCH: LISTENING FOR ACTIVITY
FAST SWITCH: INACTIVE
STATE 1
TV-TO-VCR
AUDIO: TV TO VCR
VIDEO: TV TO VCR
SLOW SWITCH: TV TO VCR
FAST SWITCH: NOT APPLICABLE
STATE 2
VCR-TO-TV
AUDIO: VCR TO TV
VIDEO: VCR TO TV
SLOW SWITCH: VCR TO TV
FAST SWITCH: VCR TO TV
TV_SS ACTIVE
VCR_SS ACTIVE
TV_SS ACTIVE
VCR_SS ACTIVE
Figure 14. Standby mode finite state machine. TV_SS is active when either 6V or 12V are present. VCR_SS is active when either 6V
or 12V are present.
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
24 ______________________________________________________________________________________
on the same SCART pin, but not at the same time. The
75Ωresistor connected to VCR_R/C_OUT must act as a
back termination resistor when the MAX9670/MAX9671
is transmitting chroma signal and as an input termina-
tion resistor when it is receiving a chroma signal. Figure
15 shows how the MAX9670/MAX9671 transmits a
chroma signal to the VCR SCART connector while
Figure 16 shows how the MAX9670/MAX9671 receives
a chroma from the VCR SCART connector.
Write a 0 into bit 2 of register 09h to open the pulldown
switch at VCR_R/C_OUT. To close the pulldown switch,
write a 0 into bit 6 of register 0Dh to turn off the output
amplifier, and then write a 1 into bit 2 of register 09h.
See Tables 17 and 18.
Figure 15. Gain-of-2 amplifier on VCR_R/C_OUT outputs chroma signal to VCR SCART connector. Notice that the pulldown switch on
VCR_R/C_OUT is open.
VCR
SCART
TV
SCART
AV = 2V/V TV_R/C_OUT
AV = 2V/V VCR_R/C_OUT
VCR_R/C_IN BIAS
ENC_R/C_IN BIAS
ENC_C_IN BIAS
LPF
LPF
ON
MAX9670/MAX9671
75Ω
75Ω
0.1µF
Figure 16. VCR_R/C_IN receives chroma signal from VCR SCART connector. Notice that the pulldown switch on VCR_R/C_OUT is
closed and that the gain-of-2 amplifier is off. The chroma signal from VCR SCART is looped through to the TV SCART in the above
configuration.
VCR
SCART
TV
SCART
AV = 2V/V TV_R/C_OUT
AV = 2V/V VCR_R/C_OUT
VCR_R/C_IN BIAS
ENC_R/C_IN BIAS
ENC_C_IN BIAS
LPF
LPF
OFF
MAX9670/MAX9671
75Ω
75Ω
0.1µF
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 25
Interfacing to an RF Modulator
If the set-top box modulates CVBS and mono audio
onto an RF carrier (for example, channel 3), a simple
application circuit can provide the needed signals (see
Figure 17). 10kΩresistor summer circuit between
TV_OUTR and TV_OUTL creates the mono audio sig-
nal. The resistor-divider to ground on TV_Y/CVBS_OUT
creates a video signal with normal amplitude. The
unique feature of the MAX9670/MAX9671 that facilitates
this application circuit is that the audio and video out-
put amplifiers of the MAX9670/MAX9671 can drive mul-
tiple loads if VAUD and VVID are both greater than
3.135V.
Unconnected-Chassis Discharge
Protection and ESD
Some set-top boxes are not connected to earth ground.
As a result, the chassis can charge up to 500V. When a
SCART cable is connected to the SCART connector,
the charged chassis can discharge through a signal
pin. The equivalent circuit is a 2200pF capacitor
charged to 311V connected through less than 0.1Ωto a
signal pin. The MAX9670/MAX9671 are soldered on the
PCB when it experiences such a discharge. Therefore,
the current spike flows through both external and inter-
nal ESD protection devices and is absorbed by the
supply bypass capacitors, which have high capaci-
tance and low ESR.
To better protect the MAX9670/MAX9671 against
excess voltages during the cable discharge condition
or ESD events, add series resistors to all inputs and
outputs to the SCART connector if series resistors are
not already present in the application circuit. Also, add
external ESD protection diodes (for example, BAV99)
on all inputs and outputs to the SCART connector.
SCART Set-Top Box
with Analog HD Outputs
In set-top boxes with SCART connectors and cinch
connectors for high-definition YPbPr outputs, a triple-
video DAC usually outputs either standard-definition
RGB signals that are routed to the MAX9670/MAX9671
or high-definition YPbPr signals that are routed through
a high-definition filter amplifier like the MAX9653 (see
Figure 19). The set-top box devices have a limited num-
ber of video DACs, and hence, one bank of triple-video
DACs switches video format depending upon whether
standard-definition RGB or high-definition YPbPr sig-
nals are required.
When RGB signals are desired, the high-definition filter
amplifier should be turned off so that the RGB signals
do not appear on the YPbPr connectors. The
MAX9653/MAX9654 are well-suited for this application
because their video inputs are in high-impedance
mode when in shutdown.
Figure 17. Application Circuit to Connect CVBS and Mono Audio from TV SCART to RF Modulator
TV
SCART
MAX9670/MAX9671
TV_OUTR
TV_OUTL
10kΩ
10kΩ
MONO AUDIO
TV_Y/CVBS_OUT
75Ω OR GREATER
75Ω OR GREATER
75Ω
RF
MODULATOR
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
26 ______________________________________________________________________________________
Figure 18. Application Circuit to Connect Series Resistors and External ESD Protection Diodes at MAX9670/MAX9671 Outputs
EP
GNDVID
MICRO-
CONTROLLER
STB CHIP
VCR
SCART
TV
SCART
75Ω
TV_OUTR
TV_OUTL
TV_SS
TV_B_OUT
TV_G_OUT
TV_R/C_OUT
TVOUT_FS
TV_Y/CVBS_OUT
TV_Y/CVBS_IN
VCR_OUTR
VCR_INR
VCR_OUTL
VCR_INL
VCR_SS
VCR_B_IN
VCR_G_IN
VCR_R/C_IN
VCR_R/C_OUT
VCRIN_FS
VCR_Y/CVBS_OUT
VCR_Y/CVBS_IN
C1NC1P CPVSS
+3.3 V
SDA
SCL
INT
DEV_ADDR
ENC_Y/CVBS_IN
ENC_R/C_IN
ENC_G_IN
ENC_B_IN
ENC_Y_IN
ENC_C_IN
ENC_INL
ENC_INR
VIDEO ENCODER
STEREO
AUDIO DACS
*R1 VALUES
DAC = CS4334/5/8/9: R1 = 4.53kΩ ±1%
DAC = PCM1742: R1 = 5.57kΩ ±1%
1µF
1µF
75Ω
75Ω
V12 VAUD
VAUD
CPVSS
VVID
12V 3.3V
0.1µF
TV_INL
(MAX9671 ONLY)
TV_INR
(MAX9671 ONLY)
MAX9670
MAX9671
0.1µF
3.3V
0.1µF
1µF
1µF
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
R1*
6.65kΩ
1µF
75Ω
0.1µF
75Ω
0.1µF
75Ω
0.1µF
75Ω
75Ω
75Ω
0.1µF
0.1µF
R1*
6.65kΩ
1µF
2.55kΩ
7.68kΩ
2.55kΩ
7.68kΩ
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
1µF
2.55kΩ
7.68kΩ
75Ω
75Ω
75Ω
75Ω
VAUD
CPVSS
VAUD
CPVSS
VAUD
CPVSS
V12
EP
VVID
GNDVID
VVID
GNDVID
V12
EP
VAUD
CPVSS
VAUD
CPVSS
VVID
GNDVID
VVID
GNDVID
VVID
GNDVID
VVID
GNDVID
VVID
GNDVID
VVID
GNDVID
VVID
GNDVID
VVID
GNDVID
75Ω
VVID
GNDVID
VAUD
CPVSS
1µF
2.55kΩ
7.68kΩ
VAUD
CPVSS
VVID
GNDVID
VVID
GNDVID
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 27
Similarly, when YPbPr signals are desired, ENC_R/C_IN,
ENC_G_IN, and ENC_B_IN of the MAX9670/MAX9671
should be set to high-impedance mode by setting bit 4 in
register 08h to high if those video inputs are AC-coupled.
The high-impedance mode has higher priority whether
ENC_R/C_IN is in sync-tip clamp or bias circuit mode
(set by bit 3 in register 08h). If ENC_R/C_IN, ENC_G_IN,
and ENC_B_IN are DC-coupled, the inputs should be left
in sync-tip clamp mode. The RGB outputs of the
MAX9670/MAX9671 should be muted or shut down.
In either case, the inactive device should not distort the
video signals generated by the DACs.
Power-Supply Bypassing
The MAX9670/MAX9671 feature single 3.3V and 12V
supply operation and require no negative supply. The
12V supply V12 is for the SCART switching function. For
V12, place a 0.1µF bypass capacitor as close as possi-
ble. Connect all VAUD pins together to 3.3V and bypass
with a 10µF electrolytic capacitor in parallel with a
0.1µF ceramic capacitor to audio ground. Bypass each
VVID to video ground with a 0.1µF ceramic capacitor.
Using a Digital Supply
The MAX9670/MAX9671 are designed to operate from
noisy digital supplies. The high PSRR (49dB at 100kHz)
allows the MAX9670/MAX9671 to reject the noise from
the digital power supplies (see the
Typical Operating
Characteristics
). If the digital power supply is very noisy
and stripes appear on the television screen, increase
the supply bypass capacitance. An additional, smaller
capacitor in parallel with the main bypass capacitor
can reduce digital supply noise because the smaller
capacitor has lower equivalent series resistance (ESR)
and equivalent series inductance (ESL).
Layout and Grounding
For optimal performance, use controlled-impedance
traces for video signal paths and place input termina-
tion resistors and output back-termination resistors
close to the MAX9670/MAX9671. Avoid routing video
traces parallel to high-speed data lines.
The MAX9670/MAX9671 provide separate ground con-
nections for video and audio supplies. For best perfor-
mance, use separate ground planes for each of the
ground returns and connect all ground planes together
at a single point. See the MAX9670/MAX9671 evalua-
tion kit for a proven circuit board layout example.
If the MAX9670/MAX9671 are mounted using flow sol-
dering or wave soldering, the ground via(s) for the EP
pad should have a finished hole size of at least 14mils
to insure adequate wicking of soldering onto the
exposed pad. If the MAX9670/MAX9671 are mounted
using solder mask technique, the via requirement does
not apply. In either case, a good connection between
the exposed pad and ground is required to minimize
noise from coupling onto the outputs.
Figure 19. Triple DAC is connected to both a MAX9670/MAX9671 and a MAX9653/MAX9654 high-definition video-filter amplifier. (A)
The MAX9670/MAX9671 are transmitting standard-definition RGB signals while the MAX9653/MAX9654 are in shutdown mode. (B)
The MAX9670/MAX9671 are not transmitting RGB signals, but the MAX9653/MAX9654 are transmitting high-definition YPbPr signals.
DAC
DAC
DAC
SET-TOP BOX
CHIP
ENC_R/C_IN
ENC_G_IN
ENC_B_IN
75Ω
75Ω
75Ω
TV_R/C_OUT
TV_G_OUT
TV_B_OUT
MAX9653
MAX9654
SCART
CONNECTOR
OFF
YPbPr OUTPUTS
(A)
75Ω
75Ω
75Ω
YOUT
PBOUT
PROUT
YIN
PBIN
PRIN
SHDN
DAC
3.3V
3.3V
3.3V
DAC
DAC
SET-TOP BOX
CHIP
ENC_R/C_IN
ENC_G_IN
ENC_B_IN
MAX9670/MAX9671MAX9670/MAX9671 75Ω
75Ω
75Ω
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
TV_R/C_OUT
TV_G_OUT
TV_B_OUT
MAX9653
MAX9654
3.3V
3.3V
3.3V
3.3V
SCART
CONNECTOR
INPUTS SET TO HIGH IMPEDANCEINPUTS SET TO SYNC-TIP CLAMP
ON
YPbPr OUTPUTS
(B)
75Ω
75Ω
75Ω
YOUT
PBOUT
PROUT
YIN
PBIN
PRIN
SHDN
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
28 ______________________________________________________________________________________
VIDEO ORIGIN FORMAT VOLTAGE RANGE COUPLING INPUT CIRCUIT CONFIGURATION
External CVBS Unknown AC Transparent sync-tip clamp
External RGB Unknown AC Transparent sync-tip clamp
External Y Unknown AC Transparent sync-tip clamp
External C Unknown AC Bias circuit
Internal CVBS 0 to 1V DC Transparent sync-tip clamp
Internal RGB 0 to 1V DC Transparent sync-tip clamp
Internal Y/C 0 to 1V DC Transparent sync-tip clamp
Internal YPbPr 0 to 1V DC Transparent sync-tip clamp
Internal CVBS 2.3V to 3.3V AC Transparent sync-tip clamp
Internal RGB 2.3V to 3.3V AC Transparent sync-tip clamp
Internal Y 2.3V to 3.3V AC Transparent sync-tip clamp
Internal C 2.3V to 3.3V AC Bias circuit
Table 1. Recommended Coupling for Incoming Video Signals and Input Circuit
Configuration*
*
Use a 0.1µF capacitor to AC-couple a video signal into the MAX9670/MAX9671.
SLOW-SWITCHING
SIGNAL VOLTAGE
(V)
MODE
0 to 2
Display device uses an internal
source such as a built-in tuner to
provide a video signal.
4.5 to 7.0
Display device uses a video signal
from the SCART connector and sets
the display to 16:9 aspect ratio.
9.5 to 12.6
Display device uses a signal from the
SCART connector and sets the
display to 4:3 aspect ratio.
Table 2. Slow-Switching Modes
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 29
DEV_ADDR B7 B6 B5 B4 B3 B2 B1 B0 WRITE ADDRESS
(hex)
READ ADDRESS
(hex)
GNDVID 1 0 01010 R/W94h 95h
VVID 1001011 R/W96h 97h
SCL 1001100 R/W98h 99h
SDA 1001101 R/W9Ah 9Bh
Table 3. Slave Address
REGISTER ADDRESS
(hexadecimal) VALUE (binary)
00h uuuu uuuu
01h uuuu 1111
06h uuuu uuuu
07h uuuu uu10
08h uuuu uuuu
09h uuuu u010
0Dh 0000 000u
Table 4. I2C Register Values in State 0*
REGISTER ADDRESS
(hexadecimal) VALUE (binary)
00h uuuu uuu0
01h uuuu 1011
06h uuuu uuuu
07h uuu0 0u10
08h uuuu u011
09h uuuu u0MM
0Dh 1100 001u
Table 5. I2C Register Values in State 1*
REGISTER ADDRESS
(hexadecimal) VALUE (binary)
00h uuuu uuu0
01h uuuu 1101
06h uuu0 1010
07h uuu0 0uNN
08h uuuu uuuu
09h uuuu u110
0Dh 0011 111u
Table 6. I2C Register Values in State 2*
*
u indicates that the bit is unchanged from its previous state.
*
u indicates that the bit is unchanged from its previous state;
MM = Register 0Eh (bit 1, bit 0)
*
u indicates that the bit is unchanged from its previous state;
NN = Register 0Eh (bit 3, bit 2)
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
30 ______________________________________________________________________________________
OPERATING MODE POWER CONSUMPTION
(mW)
Shutdown 0.13
Standby mode with no video
activity (i.e., TV slow-switch and
VCR slow-switch inputs are at
ground). Standby mode is the
power-on default.
2.83
Full-power mode with input video
detection and video load
detection active.
66
Full-power mode without input
video detection and video load
detection active.
65
Table 7. Quiescent Power Consumption
OPERATING MODE POWER CONSUMPTION
(mW)
Full-power mode with input video
detection and video load
detection active.
300
Full-power mode without input
video detection and video load
detection active.
300
Table 8. Average Power Consumption
PIN (MAX9670) NAME TYPE SIGNAL LOAD
5V
AUD Supply 3.3V N/A
9 ENC_INL Input 0.25VRMS, 1kHz N/A
10 ENC_INR Input 0.25VRMS, 1kHz N/A
11 VCR_INL Input None N/A
12 VCR_INR Input None N/A
13 TV_OUTL Output 1VRMS, 1kHz 10kΩ to ground
14 VCR_OUTL Output 1VRMS, 1kHz 10kΩ to ground
15 VCR_OUTR Output 1VRMS, 1kHz 10kΩ to ground
16 TV_OUTR Output 1VRMS, 1kHz 10kΩ to ground
17 TV_SS Output 12V 10kΩ to ground
18 V12 Supply 12V N/A
19 VCR_SS Input 0 N/A
20 TVOUT_FS Output 3.3V 150Ω to ground
21 VCRIN_FS Input 0 N/A
22 ENC_B_IN Input 50% flat field N/A
23 ENC_G_IN Input 50% flat field N/A
24 VCR_B_IN Input None N/A
25 VCR_G_IN Input None N/A
26 TV_B_OUT Output 50% flat field 150Ω to ground
27 TV_G_OUT Output 50% flat field 150Ω to ground
28 GNDVID Supply 0 N/A
29 VCR_R/C_IN Input None N/A
30 VVID Supply 3.3V N/A
Table 9. Conditions for Average Power Consumption Measurement
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 31
PIN (MAX9670) NAME TYPE SIGNAL LOAD
31 ENC_C_IN Input None N/A
32 ENC_R/C_IN Input 50% flat field N/A
33 TV_R/C_OUT Output 50% flat field 150Ω to ground
34 VCR_R/C_OUT Output 50% flat field 150Ω to ground
35 VCR_Y/CVBS_OUT Output 50% flat field 150Ω to ground
36 TV_Y/CVBS_OUT Output 50% flat field 150Ω to ground
37 VCR_Y/CVBS_IN Input None N/A
38 TV_Y/CVBS_IN Input None N/A
39 ENC_Y_IN Input None N/A
40 ENC_Y/CVBS_IN Input 50% flat field N/A
Table 9. Conditions for Average Power Consumption Measurement (continued)
REGISTER
ADDRESS (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
00h Not used TV ZCD TV volume control TV audio
output mute
01h Not used Interrupt
enable VCR audio selection TV audio selection
02h Not used
03h Not used
04h Not used
05h Not used
06h Not used TV G and B video switch TV video switch
07h Not used Set TV fast switching Not used Set TV slow switching
08h VCR_R/C_IN
clamp Not used
ENC R/G/B
high-
impedance
bias
ENC_R/C_IN
clamp VCR video switch
09h Not used VCR_R/C_OUT
ground
Set VCR slow
switching
0Ah Not used
0Bh Not used
0Ch Not used
0Dh
VCR_Y/
CVBS_OUT
enable
VCR_R/
C_OUT
enable
TV_R/
C_OUT
enable
TV_G_OUT
enable
TV_B_OUT
enable
TV_Y/
CVBS_OUT
enable
TVOUT_FS
enable Not used
10h Operating mode Not used
Table 10. Data Format for Write Mode
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
32 ______________________________________________________________________________________
REGISTER
ADDRESS (hex) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0Eh Not used Power-on
reset Not used VCR slow-switch input
status
TV slow switch input
status
0Fh Not used
ENC_Y_IN
input video
detection
ENC_Y/
CVBS_IN
input video
detection
VCR CVBS
output load
VCR CVBS
input video
detection
TV CVBS
output load
TV CVBS
input video
detection
Table 11. Data Format for Read Mode
BIT
DESCRIPTION 76543210 COMMENTS
0Off
TV Audio Mute 1 On (power-on default)
0 0 0 0 0 0dB gain (power-on default)
0 0 0 0 1 -2dB gain
0 0 0 1 0 -4dB gain
0 0 0 1 1 -6dB gain
0 0 1 0 0 -8dB gain
0 0 1 0 1 -10dB gain
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
. . .
1 1 1 1 0 -60dB gain
TV Volume Control
1 1 1 1 1 -62dB gain
0Off
TV Zero-Crossing Detector 1 On (power-on default)
Table 12. Register 00h: Audio Control
BIT
DESCRIPTION 76543210 COMMENTS
0 0 Encoder audio
0 1 VCR audio
1 0 TV audio (MAX9671 only)
Input Source for TV Audio
1 1 Mute (power-on default)
0 0 Encoder audio
0 1 VCR audio
1 0 TV audio (MAX9671 only)
Input Source for VCR Audio
1 1 Mute (power-on default)
0 Disabled (power-on default)
Interrupt Enable 1 Enabled
Table 13. Register 01h: TV Audio
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 33
BIT
DESCRIPTION 76543210 COMMENTS
TV_Y/CVBS_OUT TV_R/C_OUT
0 0 0 ENC_Y/CVBS_IN ENC_R/C_IN
0 0 1 ENC_Y_IN ENC_C_IN
0 1 0 VCR_Y/CVBS_IN VCR_R/C_IN
0 1 1 TV_Y/CVBS_IN Mute
1 0 0 Not used Not used
1 0 1 Mute Mute
1 1 0 Mute Mute
Input Sources for TV Video
111Mute (power-on
default)
Mute (power-on
default)
TV_G_OUT TV_B_OUT
0 0 ENC_G_IN ENC_B_IN
0 1 VCR_G_IN VCR_B_IN
1 0 Mute Mute
Input Sources for TV_G_OUT and TV_B_OUT
11 Mute (power-on
default)
Mute (power-on
default)
Table 14. Register 06h: TV Video Input Control
BIT
DESCRIPTION 76543210 COMMENTS
0 0 Low (< 2V) internal source
01
Medium (4.5V to 7V); external SCART
source with 16:9 aspect ratio
1 0 High impedance (power-on default)
Set TV Slow Switching
11
High (> 9.5V); external SCART source
with 4:3 aspect ratio
0 0 GNDVID (power-on default)
0 1 Not used
1 0 Same level as VCRIN_FS
Set TV Fast Switching
11 V
VID
Table 15. Register 07h: TV Video Output Control
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
34 ______________________________________________________________________________________
BIT
DESCRIPTION 76543210 COMMENTS
VCR_Y/CVBS_OUT VCR_R/C_OUT
0 0 0 ENC_Y/CVBS_IN ENC_R/C_IN
0 0 1 ENC_Y_IN ENC_C_IN
0 1 0 VCR_Y/CVBS_IN VCR_R/C_IN
0 1 1 TV_Y/CVBS_IN Mute
1 0 0 Not used Not used
1 0 1 Mute Mute
1 1 0 Mute Mute
Input Sources for VCR Video
111
Mute (power-on
default)
Mute (power-on
default)
0DC restore clamp active at input
(power-on default)
ENC_R/C_IN Clamp/Bias
1 Chrominance bias applied at input
0High-impedance bias off
(power-on default)
ENC R/C, G, and B inputs high-impedance
bias (in HD application)
1
Biases the R/C, G, and B inputs to high
impedance (overwrites the ENC_R/C_IN
clamp and bias bit)
0DC restore clamp active at input
(power-on default)
VCR_R/C_IN Clamp/Bias
1 Chrominance bias applied at input
Table 16. Register 08h: ENC and VCR Video Input/Output Control
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 35
BIT
DESCRIPTION 76543210 COMMENTS
0 0 Low (< 2V) internal source
01
Medium (4.5V to 7V); external SCART
source with 16:9 aspect ratio
1 0 High impedance (power-on default)
Set VCR Slow Switching
11
High (> 9.5V); external SCART source
with 4:3 aspect ratio
0
Normal operation; pulldown on
VCR_R/C_OUT is off (power-on
default)
VCR_R/C_OUT Ground
1
Ground; pulldown on VCR_R/C_OUT
is on; the output amplifier driving
VCR_R/C_OUT is off
Table 17. Register 09h: VCR Video Output Control
BIT
DESCRIPTION 76543210 COMMENTS
0 Off (power-on default)
TVOUT_FS Enable 1On
0 Off (power-on default)
TV_Y/CVBS_OUT Enable 1On
0 Off (power-on default)
TV_B_OUT Enable 1On
0 Off (power-on default)
TV_G_OUT Enable 1On
0 Off (power-on default)
TV_R/C_OUT Enable 1On
0 Off (power-on default)
VCR_R/C_OUT Enable 1On
0 Off (power-on default)
VCR_Y/CVBS_OUT Enable 1On
Table 18. Register 0Dh: Output Enable
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
36 ______________________________________________________________________________________
BIT
DESCRIPTION 76543210 COMMENTS
0 0 Shutdown
01
Standby mode (power-on default).
Input video detection circuits are
active. Audio circuitry is off unless
video is detected. Once slow switch
is detected, the signal paths between
the VCR and TV SCART are
connected.
10
Full-power mode with input video
detection and video-load detection
active.
Operating Mode
11
Full-power mode without input video
detection and video-load detection
active.
Table 19. Register 10h: Operating Modes
BIT
DESCRIPTION 76543210 COMMENTS
0 0 0 to 2V; internal source
01
4.5V to 7V; external source with 16:9
aspect ratio
1 0 Not used
TV Slow-Switching Input Status
11
9.5V to 12.6V; external source with
4:3 aspect ratio
0 0 0 to 2V; internal source
01 4.5V to 7V; external source with 16:9
aspect ratio
1 0 Not used
VCR Slow-Switching Input Status
11 9.5V to 12.6V; external source with
4:3 aspect ratio
0VVID is too low for digital logic to
operate
Power-On Reset
1VVID is high enough for digital logic to
operate
Table 20. Register 0Eh: Status
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 37
BIT
DESCRIPTION 76543210 COMMENTS
0 No video detected.
TV CVBS Input Video Detection 1 Video detected.
0 No video detected.
TV CVBS Output Load 1 Video detected.
0 No video detected.
VCR CVBS Input Video Detection 1 Video detected.
0 No load connected.
VCR CVBS Output Load 1 Load connected.
0 No video detected.
ENC_Y/CVBS_IN Input Video Detection 1 Video detected.
0 No video detected.
ENC_Y_IN Input Video Detection 1 Video detected.
Table 21. Register 0Fh: Video Activity Status
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
38 ______________________________________________________________________________________
EP
GNDVID
MICRO-
CONTROLLER
STB CHIP
VCR
SCART
TV
SCART
75Ω
TV_OUTR
TV_OUTL
TV_SS
TV_B_OUT
TV_G_OUT
TV_R/C_OUT
TVOUT_FS
TV_Y/CVBS_OUT
TV_Y/CVBS_IN
VCR_OUTR
VCR_INR
VCR_OUTL
VCR_INL
VCR_SS
VCR_B_IN
VCR_G_IN
VCR_R/C_IN
VCR_R/C_OUT
VCRIN_FS
VCR_Y/CVBS_OUT
VCR_Y/CVBS_IN
C1NC1P CPVSS
+3.3 V
SDA
SCL
INT
DEV_ADDR
ENC_Y/CVBS_IN
ENC_R/C_IN
ENC_G_IN
ENC_B_IN
ENC_Y_IN
ENC_C_IN
ENC_INL
ENC_INR
VIDEO ENCODER
STEREO
AUDIO DACS
*R1 VALUES
DAC = CS4334/5/8/9: R1 = 4.53kΩ ±1%
DAC = PCM1742: R1 = 5.57kΩ ±1%
1µF
1µF
75Ω
V12 VAUD
VVID
12V 3.3V
0.1µF
TV_INL
(MAX9671 ONLY)
TV_INR
(MAX9671 ONLY)
MAX9670
MAX9671
0.1µF
3.3V
0.1µF
75Ω
75Ω
75Ω
75Ω
75Ω
R1*
6.65kΩ
1µF
75Ω
0.1µF
1µF
75Ω
0.1µF
75Ω
0.1µF
75Ω
75Ω
0.1µF
0.1µF
R1*
6.65kΩ
1µF
2.55kΩ
7.68kΩ
2.55kΩ
7.68kΩ
2.55kΩ
7.68kΩ
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
75Ω
1µF
2.55kΩ
7.68kΩ
75Ω
75Ω
Typical Application Circuit
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 39
MAX9670 MAX9671
40 TQFN
TOP VIEW
35
36
34
33
12
11
13
SCL
INT
VAUD
C1P
C1N
14
SDA
TV_G_OUT
VCR_G_IN
VCR_B_IN
GNDVID
VCR_R/C_IN
VVID
ENC_G_IN
ENC_B_IN
1 2
VCR_R/C_OUT
4567
27282930 26 24 23 22
VCR _Y/CVBS_OUT
TV_Y/CVBS_OUT
V12
TV_SS
TV_OUTR
VCR_OUTR
DEV_ADDR
TV_B_OUT
3
25
37
VCR_Y/CVBS_IN VCR_OUTL
38
39
40
TV_Y/CVBS_IN
ENC_Y_IN
ENC_Y/CVBS_IN
TV_OUTL
VCR_INR
VCR_INL
TV_R/C_OUT
32
15
VCR_SS
ENC_R/C_IN
31
16
17
18
19
20 TVOUT_FS
CPVSS
ENC_INL
ENC_INR VCRIN_FS
8910
21
ENC_C_IN
*EP = EXPOSED PAD *EP = EXPOSED PAD
DEV_ADDR
INT
VAUD
C1P
C1N
CPVSS
ENC_INL
ENC_INR
TV_INL
SCL
SDA 1
2
3
4
5
6
7
8
9
10
11
TV_R/C_OUT
VCR_R/C_OUT
VCR_Y/CVBS_OUT
TV _Y/CVBS_OUT
VCR_Y/CVBS_IN
TV_Y/CVBS_IN
ENC_Y_IN
ENC_Y/CVBS_IN
N.C.
ENC_R/C_IN
ENC_C_IN 34
35
36
37
38
39
40
41
42
43
44
V12
TV_SS
TV_OUTR
VCR_OUTR
VCR_OUTL
TV_OUTL
VCR_INR
VCR_INL
TV_INR
VCR_SS
TVOUT_FS
22
21
20
19
18
17
16
15
14
13
12
GNDVID
TV_G_OUT
TV_B_OUT
VCR_G_IN
VCR_B_IN
ENC_G_IN
ENC_B_IN
VCRIN_FS
N.C.
VCR_R/C_IN
VVID
33
32
31
30
29
28
27
26
25
24
23
44 TQFN
TOP VIEW
*EP
*EP
Pin Configurations
Chip Information
PROCESS: BiCMOS
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
40 ______________________________________________________________________________________
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
40 TQFN T4066+3 21-0141 90-0054
44 TQFN T4477+2 21-0144 90-0127
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 41
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
42 ______________________________________________________________________________________
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
______________________________________________________________________________________ 43
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
MAX9670/MAX9671
Low-Power Audio/Video Switch with Audio
Volume Control for Dual SCART Connectors
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
44
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 7/09 Initial release —
1 3/10
Added θJA and θJC information in the Absolute Maximum Ratings section,
adjusted Note references, updated power consumption Figures, and made
various corrections
1–8, 17, 20, 21, 22,
24–29, 33, 35, 36, 37
2 12/10 Updated Table 14 33
