19-4653; Rev 2; 12/10 KIT ATION EVALU E L B A IL AVA Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors The MAX9670/MAX9671 dual SCART matrices route audio and video signals between a set-top box decoder chip and two external SCART connectors under I2C control. Operating from a 3.3V supply and a 12V supply, the MAX9670/MAX9671 consume 66mW during quiescent operation and 300mW during average operation when driving typical signals into typical loads. Video input detection, video load detection, and a 2.8mW standby mode facilitate the design of intelligent, low-power set-top boxes. The MAX9670/MAX9671 audio section contains a buffered crosspoint to route audio inputs to audio outputs and programmable volume control from -62dB to 0dB in 2dB steps. The DirectDrive(R) output amplifiers create a 2VRMS full-scale audio signal biased around ground, eliminating the need for bulky output capacitors and reducing click-and-pop noise. The zero-cross detection circuitry also further reduces clicks and pops by enabling audio sources to switch only during a zerocrossing. The MAX9671 offers TV left and right audio inputs. The MAX9670/MAX9671 video section contains a buffered crosspoint to route video inputs to video outputs. The standard-definition video signals from the settop box decoder chip are lowpass filtered to remove out-of-band artifacts. The MAX9670/MAX9671 also support slow-switching and fast-switching signals. An interrupt signal from the MAX9670/MAX9671 informs the microcontroller when the system status has changed. Applications Features o 66mW Quiescent Power Consumption o 2.8mW Standby Mode Consumption o Programmable Audio Gain Control of -62dB to 0dB (TV Audio Outputs) o Clickless, Popless, DirectDrive Audio o Video Input and Video Load Detection o Video Reconstruction Filter with 10MHz Passband and 52dB Attenuation at 27MHz o 3.3V and 12V Supply Voltages Ordering Information PART TEMP RANGE MAX9670CTL+ 0C to +70C 40 TQFN-EP* MAX9671CTH+ 0C to +70C 44 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. TV R+L AUDIO INPUTS No Yes *EP = Exposed pad. System Block Diagram V12 12V STB CHIP VVID 3.3V VAUD 3.3V MAX9670/MAX9671 RGB, Y/C, CVBS I2C Set-Top Boxes C TVs PINPACKAGE I2C INTERFACE REGISTERS AND ACTIVITY MONITOR INTERRUPT OUTPUT DVD Players CVBS L/R AUDIO (MAX9671 ONLY) L/R AUDIO (MAX9670 ONLY) TV SCART SLOW SWITCHING VIDEO ENCODER STEREO AUDIO DAC RGB, Y/C, CVBS SINGLE-ENDED R/L STEREO AUDIO VIDEO FILTERS AND CROSSPOINT FAST SWITCHING AUDIO CROSSPOINT WITH DIRECTDRIVE OUTPUTS, VOLUME CONTROL RGB, Y/C, CVBS Y/C, CVBS L/R AUDIO VCR SCART SLOW SWITCHING SLOW SWITCHING FAST SWITCHING FAST SWITCHING Typical Application Circuit appears at end of data sheet. CHARGE PUMP DirectDrive is a registered trademark of Maxim Integrated Products, Inc. EP GNDVID ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX9670/MAX9671 General Description MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors ABSOLUTE MAXIMUM RATINGS VVID to GNDVID........................................................-0.3V to +4V Audio Outputs to VAUD, EP .....................................Continuous V12 to EP.................................................................-0.3V to +14V TV_SS, VCR_SS to V12, EP......................................Continuous VAUD to EP ...............................................................-0.3V to +4V Continuous Power Dissipation (TA = +70C) EP to GNDVID .......................................................-0.1V to +0.1V 40-Pin TQFN-EP (derate 26.3mW/C above +70C) ...2105.3mW All Video Inputs, VCRIN_FS to GNDVID...................-0.3V to +4V 44-Pin TQFN-EP (derate 26.3mW/C above +70C)...2222.2mW All Audio Inputs to EP .......................................-1V to (VEP + 1V) Junction-to-Case Thermal Resistance (JC) (Note 1) SDA, SCL, DEV_ADDR, INT to GNDVID ..................-0.3V to +4V 40/44-pin TQFN-EP .........................................................1C/W TV_SS, VCR_SS to EP .................................-0.3V to (V12 + 0.3V) Junction-to-Ambient Thermal Resistance (JA) (Note 1) Current 40/44-pin TQFN-EP .......................................................27C/W All Video/Audio Inputs ...................................................20mA Operating Temperature Range...............................0C to +70C C1P, C1N, CPVSS .........................................................50mA Junction Temperature ......................................................+150C Output Short-Circuit Current Duration Storage Temperature Range .............................-65C to +150C Video and Fast-Switching Outputs to VVID, Lead Temperature (soldering, 10s) .................................+300C GNDVID.................................................................Continuous Soldering Temperature (reflow) .......................................+260C Note 1: Package thermal resistance were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Video Supply Voltage Range VVID Inferred from video PSRR test at 3V and 3.6V 3 3.3 3.6 V Audio Supply Voltage Range VAUD Inferred from audio PSRR test at 3V and 3.6V 3 3.3 3.6 V 11.4 12 12.6 V 16 30 mA V12 Supply Voltage Range V12 Inferred from slow-switching levels Normal operation; all video output amplifiers are enabled and muted (Note 3) VVID Quiescent Supply Current IVID_Q Standby mode, slow switch inputs low 1500 Shutdown VAUD Quiescent Supply Current V12 Quiescent Supply Current IAUD_Q I12_Q 35 Normal operation (Note 3) 3.2 Shutdown Normal operation (Note 3) Slow-switching output set to low-level 0.3 A 6 mA 35 A 100 A Slow-switching output set to medium-level 475 Shutdown, TA = +25C 10 A 1.15 VP-P 2 A VIDEO CHARACTERISTICS DC-COUPLED INPUT VVID = 3V Input Voltage Range VIN RL = 75 to GNDVID or 150 to VVID/2; inferred from gain test Input Current IIN VIN = 0.3V, TA = +25C Input Resistance RIN 2 1.15 VVID = 3.135V VVID = 3.3V 1.3 1 300 _______________________________________________________________________________________ k Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS -13 -4 +6 mV 2 % 2 A AC-COUPLED INPUT Sync-Tip Clamp Level VCLP Sync-tip clamp Sync Crush Sync-tip clamp; percentage reduction in sync pulse (0.3VP-P); guaranteed by input clamping current measurement, TA = +25C Input Clamping Current Sync-tip clamp, VIN = 0.3V, TA = +25C Maximum Input Source Resistance Input sync-tip circuit must be stable even if the source resistance is as high as 300 Input Voltage Input Resistance 1 300 Bias circuit 0.57 High-impedance input circuit 0.3 x VVID 0.6 0.63 0.36 x VVID Bias circuit 10 High-impedance input circuit 222 V k DC CHARACTERISTICS DC Voltage Gain AV DC Gain Mismatch Among R, G, and B Outputs Output Level Guaranteed by output voltage swing Guaranteed by output voltage swing of TV_R/C_OUT, TV_G_OUT, and TV_B_OUT; first input signal set is VCR_R/C_IN, VCR_G_IN, and VCR_B_IN; second signal set is ENC_R/C_IN, ENC_G_IN, and ENC_B_IN Sync-tip clamp (VIN = VCLP) 1.95 0.1 0.30 0.51 Bias circuit 1.3 1.5 1.78 -2 Sync-tip clamp, measured at output, VVID = 3V, VIN = VCLP to (VCLP +1.15V), RL = 150 to VVID/2, RL = 75 to GNDVID Measured at output, VVID = 3.135V, VIN = VCLP to (VCLP + 1.15V), RL = 150 to VVID/2, RL = 75 to GNDVID 2 2.05 V/V +2 % 2.3 2.243 2.3 2.358 VP-P Output Voltage Swing Bias circuit, measured at output, VVID = 3V, VIN = (VBIAS - 0.575V) to (VBIAS + 0.575V), RL = 150 to VVID/2, RL = 75 to GNDVID Measured at output, VVID = 3.135V, VIN = (VBIAS - 0.575V) to (VBIAS + 0.575V), RL = 150 to VVID/2, RL = 75 to GNDVID 2.3 2.243 Output Short-Circuit Current Output Resistance V 2.3 2.358 100 ROUT mA 0.5 Output Leakage Current Output disabled (load detection not active) Power-Supply Rejection Ratio 3V VVID 3.6V 170 35 A dB _______________________________________________________________________________________ 3 MAX9670/MAX9671 ELECTRICAL CHARACTERISTICS (continued) MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors ELECTRICAL CHARACTERISTICS (continued) (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS AC CHARACTERISTICS Filter Passband Flatness VOUT = 2VP-P, f = 100kHz to 5.5MHz VOUT = 2VP-P, attenuation is referred to 100kHz Filter Attenuation -1 f = 9.5MHz 3 f = 27MHz 40 f = 54MHz 55 dB dB Slew Rate VOUT = 2VP-P, no filter in video path 60 V/s Settling Time VOUT = 2VP-P, settle to 0.1% (Note 4) 400 ns Differential Gain DG 5-step modulated staircase, f = 4.43MHz 0.15 % Differential Phase DP 5-step modulated staircase, f = 4.43MHz 0.5 Degrees 2T Pulse-to-Bar K Rating 2T = 200ns, bar time is 18s, the beginning 2.5% and the ending 2.5% of the bar time is ignored 0.3 K% 2T Pulse Response 2T = 200ns 0.2 K% 2T Bar Response 2T = 200ns, bar time is 18s, the beginning 2.5% and the ending 2.5% of the bar time is ignored 0.2 K% Nonlinearity Group Delay Distortion 5-step staircase 100kHz f 5MHz, outputs are 2VP-P 0.1 11 % ns Glitch Impulse Caused by Charge-Pump Switching Measured at outputs 100 pV-s Peak Signal to RMS Noise 100kHz f 5MHz 70 dB Power-Supply Rejection Ratio f = 100kHz, 100mVP-P 47 dB Output Impedance f = 5MHz 2 Video Crosstalk f = 4.43MHz -80 dB Reverse Isolation VCR SCART inputs to encoder inputs, full-power mode with VCR being looped through to TV, f = 4.43MHz 92 dB Pulldown Resistance Enable VCR_R/C_OUT pulldown through I2C interface 4.4 7.5 4 4.05 V/V AUDIO CHARACTERISTICS Voltage Gain VIN = -0.707V to +0.707V 3.95 Gain Mismatch VIN = -0.707V to +0.707V -1.5 Flatness f = 20Hz to 20kHz, 0.25VRMS input Frequency Bandwidth Capacitive Drive 4 +1.5 % 0.006 dB 0.25VRMS input, frequency where output is -3dB referenced to 1kHz 230 kHz No sustained oscillations; 75 series resistor on output 300 pF _______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS Input Resistance VIN = -0.707V to +0.707V Input Bias Current VIN = 0, TA = +25C MIN MAX 10 f = 1kHz, THD < 1% Output DC Level No input signal, VIN grounded -4 DC 75 0.5 100 90 Signal-to-Noise Ratio f = 1kHz, 0.25VRMS input, 20Hz to 20kHz 96 Total Harmonic Distortion Plus Noise RL = 3.33k, f = 1kHz, 0.25VRMS input 0.002 RL = 3.33k, f = 1kHz, 0.5VRMS input 0.001 Output Impedance f = 1kHz Volume Control Attenuation Step Programmable gain to TV SCART volume control from -62dB to 0 nA VRMS +4 f = 1kHz UNITS M 500 Input Signal Amplitude Power-Supply Rejection Ratio TYP mV dB dB % 0.4 2 dB Volume Control Minimum Attenuation 0 dB Volume Control Maximum Attenuation 62 dB Mute Suppression f = 1kHz, 0.25VRMS input 110 dB Audio Crosstalk f = 1kHz, 0.25VRMS input 100 dB Video input: f = 15kHz, 1VP-P signal Audio input: f = 15kHz, 0.5VRMS signal 92 dB 570 kHz VIDEO-TO-AUDIO INTERACTION Crosstalk CHARGE PUMP Switching Frequency FAST SWITCHING Input Low Input High Level 0.4 V 1 V Input Current TA = +25C 10 A Output Low Voltage IOL = 0.5mA 0.1 V Output High Voltage IOH = 0.5mA VVID 0.1 Output Resistance V 7 Rise Time 143 to GNDVID 12 ns Fall Time 143 to GNDVID 10 ns SLOW SWITCHING Input Low Voltage Input Medium Voltage 4.5 Input High Voltage 9.5 2 V 7 V V _______________________________________________________________________________________ 5 MAX9670/MAX9671 ELECTRICAL CHARACTERISTICS (continued) MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors ELECTRICAL CHARACTERISTICS (continued) (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN Input Current TYP MAX UNITS 70 100 A 1.5 V 6.5 V 10k to EP, 11.4V V12 12.6V Output Low Voltage Output Medium Voltage 10k to EP, 11.4V V12 12.6V 5 Output High Voltage 10k to EP, 11.4V V12 12.6V 10 V 0.7 x VVID V DIGITAL INTERFACE Input High Voltage VIH Input Low Voltage VIL Input Hysteresis VHYS Input Leakage Current IIH, IIL 0.3 x VVID 0.06 x VVID TA = +25C -1 Input Capacitance V +1 6 Input Current 0.1VVID < SDA < 3.3V, 0.1VVID < SCL < 3.3V I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V+ is switched off, TA = +25C ISINK = 6mA -10 V A pF +10 A 0.4 V 400 kHz Output Low Voltage SDA VOL Serial-Clock Frequency fSCL 0 Bus Free Time Between a STOP and a START Condition tBUF 1.3 s tHD, STA 0.6 s Low Period of the SCL Clock tLOW 1.3 s High Period of the SCL Clock Hold Time, (Repeated) START Condition tHIGH 0.6 s Setup Time for a Repeated START Condition tSU, STA 0.6 s Data Hold Time tHD, DAT Data Setup Time tHD, DAT Fall Time of SDA Transmitting Setup Time for STOP Condition Pulse Width of Spike Suppressed 6 tF (Note 5) ISINK 6mA, CB = total capacitance of one bus line in pF, tR and tF measured between 0.3VVID and 0.7VVID tSU, STO tSP 0 0.9 100 ns 100 ns 0.6 Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns s 0 _______________________________________________________________________________________ s 50 ns Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.3 x VVID V OTHER DIGITAL I/O DEV_ADDR Low Level 0.7 x VVID DEV_ADDR High Level V DEV_ADDR Input Current TA = +25C Interrupt Output Low Voltage IOL = 0.5mA 0.1 V Interrupt Output Leakage Current INT high impedance, TA = +25C 10 A Note 2: Note 3: Note 4: Note 5: -1 +1 A All devices are 100% production tested at TA = +25C. Specifications over temperature limits are guaranteed by design. Normal operation mode is full power with input video and load detection active. The settling time is measured from the 50% of the input swing to the 0.1% of the final value of the output. A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL's falling edge. Typical Operating Characteristics (VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150 to GNDVID, audio load is 10k to EP, TA = +25C, unless otherwise noted.) 0 -1 NO FILTER GAIN (dB) GAIN (dB) -10 VOUT = 100mVP-P 1 -20 FILTER -30 VOUT = 2VP-P 0 -10 NO FILTER -2 -3 FILTER -4 -5 -40 10 MAX9670 toc03 0 2 NO FILTER GAIN (dB) VOUT = 100mVP-P MAX9670 toc01 10 LARGE-SIGNAL GAIN vs. FREQUENCY SMALL-SIGNAL GAIN FLATNESS vs. FREQUENCY MAX9670 toc02 SMALL-SIGNAL GAIN vs. FREQUENCY -20 FILTER -30 -40 -6 -50 -50 -7 -8 -60 100k 1M 10M FREQUENCY (Hz) 100M 1G -60 1M 10M FREQUENCY (Hz) 100M 100k 1M 10M 100M 1G FREQUENCY (Hz) _______________________________________________________________________________________ 7 MAX9670/MAX9671 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150 to GNDVID, audio load is 10k to EP, TA = +25C, unless otherwise noted.) NO FILTER -20 -1 140 VOUT = 2VP-P 120 100 -2 -3 -4 FILTER -60 DELAY (ns) -40 DELAY (ns) ALL HOSTILE -80 -5 -6 -120 10M 100M 1M 100k 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) VIDEO POWER-SUPPLY REJECTION RATIO vs. FREQUENCY VIDEO VOLTAGE GAIN vs. TEMPERATURE VIDEO OUTPUT VOLTAGE vs. INPUT VOLTAGE VOLTAGE GAIN (V/V) -15 FILTER -20 -25 -30 NO FILTER -35 2.03 2.02 3.0 OUTPUT VOLTAGE (V) -5 -10 3.5 MAX9670 toc08 2.04 MAX9670 toc07 0 PSRR (dB) NO FILTER 0 1M 100k 100M 10M 60 20 -7 1M FILTER 40 -100 -8 80 2.01 2.00 1.99 1.98 MAX9670 toc09 GAIN (dB) VOUT = 100mVP-P MAX9670 toc06 1 MAX9670 toc05 0 MAX9670 toc04 2 0 GROUP DELAY vs. FREQUENCY VIDEO CROSSTALK vs. FREQUENCY LARGE-SIGNAL GAIN FLATNESS vs. FREQUENCY 2.5 2.0 1.5 1.0 -40 0.5 1.97 -45 1.96 -50 100k 1M 10M 0 25 0 100M 8 0 1 1 2 2 3 3 4 4 5 5 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 75 0 0.4 0.8 INPUT VOLTAGE (V) DIFFERENTIAL GAIN AND PHASE 2T WITH FILTER 1.2 1.6 MAX9670 toc12 MAX9670 toc11 DIFFERENTIAL GAIN (%) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 DIFFERENTIAL PHASE (deg) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 MAX9670 toc10 DIFFERENTIAL GAIN (%) DIFFERENTIAL GAIN AND PHASE 50 TEMPERATURE (C) FREQUENCY (Hz) DIFFERENTIAL PHASE (deg) MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors VIDEO INPUT 200mV/div 0 1 2 3 4 5 VIDEO OUTPUT 500mV/div 0 1 2 3 4 5 80ns/div _______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors 2T NO FILTER 12.5T WITH FILTER MAX9670 toc13 MAX9670 toc14 VIDEO INPUT 200mV/div VIDEO INPUT 200mV/div VIDEO OUTPUT 500mV/div VIDEO OUTPUT 500mV/div 80ns/div 1s/div 12.5T NO FILTER NTC7 WITH FILTER MAX9670 toc15 MAX9670 toc16 VIDEO INPUT 200mV/div VIDEO INPUT 500mV/div VIDEO OUTPUT 500mV/div VIDEO OUTPUT 1V/div 1s/div 10s/div NTC7 NO FILTER FIELD SQUARE WAVE MAX9670 toc17 10s/div MAX9670 toc18 VIDEO INPUT 500mV/div VIDEO INPUT 500mV/div VIDEO OUTPUT 1V/div VIDEO OUTPUT 1V/div 2ms/div _______________________________________________________________________________________ 9 MAX9670/MAX9671 Typical Operating Characteristics (continued) (VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150 to GNDVID, audio load is 10k to EP, TA = +25C, unless otherwise noted.) Typical Operating Characteristics (continued) (VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150 to GNDVID, audio load is 10k to EP, TA = +25C, unless otherwise noted.) VIDEO INPUT SYNC-TIP CLAMP VOLTAGE vs. TEMPERATURE 0 -1 -2 -3 -4 615 -5 605 600 595 590 580 0 25 50 75 25 0 50 75 TEMPERATURE (C) TEMPERATURE (C) VIDEO INPUT SYNC-TIP CLAMP CURRENT vs. TEMPERATURE VIDEO INPUT SYNC-TIP CLAMP CURRENT vs. INPUT VOLTAGE 1.2 1.1 1.0 0.9 0.8 MAX9670 toc22 1.3 8 7 INPUT CLAMP CURRENT (A) MAX9670 toc21 1.4 6 5 4 3 2 1 0.7 0 0.6 0 25 50 0 75 0.5 1.0 1.5 2.0 2.5 3.0 TEMPERATURE (C) INPUT VOLTAGE (V) VIDEO OUTPUT BIAS VOLTAGE vs. TEMPERATURE AUDIO LARGE-SIGNAL GAIN vs. FREQUENCY 10 MAX9670 toc23 1.50 1.49 3.5 MAX9670 toc24 INPUT CLAMP CURRENT (mA) 610 585 -6 5 1.48 0 GAIN (dB) 1.47 1.46 1.45 -5 -10 1.44 -15 1.43 1.42 -20 0 25 50 TEMPERATURE (C) 10 MAX9670 toc20 620 INPUT BIAS VOLTAGE (mV) 1 INPUT CLAMP VOLTAGE (mV) VIDEO INPUT BIAS VOLTAGE vs. TEMPERATURE MAX9670 toc19 2 OUTPUT BIAS VOLTAGE (V) MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors 75 10 100 1k 10k 100k 1M FREQUENCY (Hz) ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors AUDIO CROSSTALK vs. FREQUENCY -20 VIN = 0.25VRMS -40 0.01 THD+N (%) CROSSTALK (dB) 0.1 MAX9670 toc25 0 MAX9670 toc26 TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY -60 -80 TVIN TO TVOUT TVIN TO VCROUT 0.001 -100 -120 0.0001 10 100 1k 10k 100k 1k 10k VAUD POWER-SUPPLY REJECTION RATIO (INPUT REFERRED) vs. FREQUENCY VVID QUIESCENT SUPPLY CURRENT vs. TEMPERATURE -20 25 CURRENT (mA) -40 -60 100k MAX9670 toc28 30 MAX9670 toc27 VAUD = 3.3V + 100mVP-P 20 15 -80 10 -100 5 0 -120 100 1k 10k 0 100k 25 50 FREQUENCY (Hz) TEMPERATURE (C) VAUD QUIESCENT SUPPLY CURRENT vs. TEMPERATURE V12 QUIESCENT SUPPLY CURRENT vs. TEMPERATURE 800 MAX9670 toc29 5 4 75 MAX9670 toc30 10 700 600 CURRENT (nA) CURRENT (mA) 100 FREQUENCY (Hz) 0 PSRR (dB) 10 FREQUENCY (Hz) 3 2 500 400 300 200 1 100 0 0 0 25 50 TEMPERATURE (C) 75 0 25 50 75 TEMPERATURE (C) ______________________________________________________________________________________ 11 MAX9670/MAX9671 Typical Operating Characteristics (continued) (VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150 to GNDVID, audio load is 10k to EP, TA = +25C, unless otherwise noted.) MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Pin Description PIN NAME FUNCTION MAX9670 MAX9671 1 1 SDA Bidirectional I2C Data I/O. Output is open drain and tolerates up to 3.6V. 2 2 SCL I2C Clock Input 3 3 DEV_ADDR Device Address Set Input. Connect to GNDVID, VVID, SDA or SCL. See Table 3. Interrupt Output. This is an open-drain output that pulls down to GNDVID to indicate a change in the VCR slow switching or fast switching input, the activity status of the composite video inputs, or the load status of the composite video outputs. 12 4 4 INT 5 5 VAUD Audio Supply. Connect to a 3.3V supply. Bypass with a 10F aluminum electrolytic capacitor and a 0.47F ceramic capacitor to EP. 6 6 C1P Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.47F capacitor from C1P to C1N. 7 7 C1N Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.47F capacitor from C1P to C1N. 8 8 CPVSS Charge-Pump Negative Power Supply. Bypass with a 1F ceramic capacitor to EP. 9 9 ENC_INL Encoder Left-Channel Audio Input 10 10 ENC_INR Encoder Right-Channel Audio Input -- 11 TV_INL TV SCART Left-Channel Audio Input -- 12 TV_INR TV SCART Right-Channel Audio Input 11 13 VCR_INL VCR SCART Left-Channel Audio Input 12 14 VCR_INR VCR SCART Right-Channel Audio Input 13 15 TV_OUTL TV SCART Left-Channel Audio Output 14 16 VCR_OUTL VCR SCART Left-Channel Audio Output 15 17 VCR_OUTR VCR SCART Right-Channel Audio Output 16 18 TV_OUTR 17 19 TV_SS 18 20 V12 19 21 VCR_SS 20 22 TVOUT_FS -- 23, 44 N.C. 21 24 VCRIN_FS VCR SCART Fast-Switching Logic Input 22 25 ENC_B_IN Encoder Blue Video Input 23 26 ENC_G_IN Encoder Green Video Input 24 27 VCR_B_IN VCR SCART Blue Video Input 25 28 VCR_G_IN VCR SCART Green Video Input 26 29 TV_B_OUT TV SCART Blue Video Output 27 30 TV_G_OUT TV SCART Green Video Output TV SCART Right-Channel Audio Output TV SCART Bidirectional Slow-Switch Signal +12V Supply for the Slow Switching Circuit. Bypass with a 10F + 0.47F ceramic capacitor to EP. VCR SCART Bidirectional Slow-Switch Signal TV SCART Fast-Switching Logic Output No Connection. Leave unconnected. ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors PIN NAME FUNCTION MAX9670 MAX9671 28 31 GNDVID 29 32 VCR_R/C_IN 30 33 VVID 31 34 ENC_C_IN 32 35 ENC_R/C_IN Encoder Red/Chroma Video Input 33 36 TV_R/C_OUT TV SCART Red/Chroma Video Output 34 37 35 38 36 39 TV_Y/CVBS_OUT 37 40 VCR_Y/CVBS_IN 38 41 TV_Y/CVBS_IN 39 42 ENC_Y_IN 40 43 ENC_Y/CVBS_IN -- -- EP VCR_R/C_OUT Video Ground VCR SCART Red/Chroma Video Input Video and Digital Supply. Connect to a 3.3V supply. Bypass with parallel 1F and 0.1F ceramic capacitors to GNDVID. VVID also serves as a digital supply for the I2C interface. Encoder Chroma Video Input VCR SCART Red/Chroma Video Output VCR_Y/CVBS_OUT VCR SCART Luma/Composite Video Output TV SCART Luma/Composite Video Output VCR SCART Luma/Composite Video Input TV SCART Luma/Composite Video Input Encoder Luma Video Input Encoder Luma/Composite Video Input Exposed Pad. The exposed pad is the internal ground for the audio amplifiers and charge pump. A low-impedance connection between ground and EP is required for proper isolation. Detailed Description The MAX9670/MAX9671 represents Maxim's third generation of SCART audio/video (A/V) switches. Under I2C control, these devices route audio, video, and control information between the set-top box decoder chip and two SCART connectors. The audio signals are left audio and right audio. The video signals are composite video with blanking and sync (CVBS) and component video (red, green, blue). S-video (Y/C) can be transported across the SCART interface if CVBS is reassigned to luma (Y) and red is reassigned to chroma (C). Support for S-video is optional. The slow-switch signal and the fast-switch signal carry control information. The slowswitch signal is a 12V, three-level signal that indicates whether the picture aspect ratio is 4:3 or 16:9 or causes the television to use an internal A/V source such as an antenna. The fast-switch signal indicates whether the television should display CVBS or RGB signals. CVBS, left audio, and right audio are full duplex. All the other signals are half duplex. Therefore, one device on the link must be designated as the transmitter, and the other device must be designated as the receiver. ation of lower power set-top boxes, televisions, and DVD players. Unlike competing SCART ICs, the audio and video circuits of the MAX9670/MAX9671 operate entirely from 3.3V rather than from 5V and 12V. Only the slow-switch circuit of the MAX9670/MAX9671 requires a 12V supply. The MAX9670/MAX9671 also have circuits that detect activity on the CVBS inputs, loads on the CVBS outputs, and the level of the slow-switch signals. The INT signal informs the microcontroller if there are any changes so that the microcontroller can intelligently decide whether to power up or power down the equipment. In addition, the MAX9670/MAX9671 have DirectDrive audio circuitry to eliminate click-and-pop noise. With DirectDrive, the DC bias of the audio line outputs is always at ground, no matter whether the MAX9670/ MAX9671 are being powered up or powered down. Conventional audio line output drivers that operate from a single supply require series AC-coupling capacitors. During power-up, the DC bias on the AC-coupling capacitor moves from ground to a positive voltage, and during power-down, the opposite occurs. The changing DC bias usually causes an audible transient. The low power consumption and the advanced monitoring functions of the MAX9670/MAX9671 enable the cre______________________________________________________________________________________ 13 MAX9670/MAX9671 Pin Description (continued) MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors ZCD MUTE ENC_INL MUTE VCR_INL VOLUME CONTROL 0dB TO -62dB (0.5VRMS FULL-SCALE INPUT) MUTE VOLUME CONTROL 0dB TO -62dB *TV_INL x4 TV_OUTL (2VRMS FULL-SCALE OUTPUT) x4 TV_OUTR x4 VCR_OUTL MUTE MUTE ENC_INR (2VRMS FULL-SCALE OUTPUT) VCR_INR x4 VCR_OUTR MUTE *TV_INR SCL REGISTER CONTROL SDA DEV_ADDR VAUD C1P CHARGE PUMP EP C1N CPVSS MAX9670/MAX9671 *MAX9671 ONLY. Figure 1. MAX9670/MAX9671 Audio Section Functional Diagram Audio Section The MAX9670 audio circuit is essentially a stereo, 2-by-2, nonblocking, audio crosspoint with output drivers. The encoder (stereo audio DAC) and the VCR are the two input sources, and the two outputs go to the TV SCART connector and the VCR SCART connector. See Figure 1. The MAX9671 audio circuit is similar to that of the MAX9670 except that it is a stereo, 3-by-2, 14 nonblocking audio crosspoint with TV as the third input source. The integrated charge pump inverts the +3.3V supply to create a -3.3V supply. The audio circuit operates from bipolar supplies so the audio signal is always biased to ground. ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors VDD VDD/2 GND CONVENTIONAL DRIVER-BIASING SCHEME +VDD GND VOUT 2VDD -VDD DirectDrive BIASING SCHEME Figure 2. Conventional Driver Output Waveform vs. MAX9670/ MAX9671 Output Waveform. Clickless Switching The TV audio channel incorporates a zero-crossing detect (ZCD) circuit that minimizes click noise due to abrupt signal level changes that occur when switching between audio signals at an arbitrary moment. To implement the zero-crossing function when switching audio signals, set the ZCD bit high (Audio Control register 00h, bit 6). Then set the mute bit high (Audio Control register 00h, bit 0). Next, wait for a sufficient period of time for the audio signal to cross zero. This period is a function of the audio signal path's low-frequency 3dB corner (fL3dB). Thus, if fL3dB = 20Hz, the time period to wait for a zero-crossing detect is 1/20Hz or 50ms. After the wait period, select a new audio source for the TV audio channel by writing to bits 1 and 0 of TV Audio Control register (01h). Finally, clear mute (Audio Control register, 00h, bit 0), but leave ZCD (Audio Control register 00h, bit 6) high. The MAX9670/MAX9671 switches the signal out of mute at the next zero crossing. See Tables 12 and 13. Conventional single-supply audio line drivers have their outputs biased about a nominal DC voltage (typically half the supply) for maximum dynamic range. Large coupling capacitors are needed to block this DC bias. Clicks and pops are created when the coupling capacitors are charged during power-up and discharged during power-down. The MAX9670/MAX9671 features a low-noise charge pump that requires only two small ceramic capacitors. The 580kHz switching frequency is well beyond the audio range and does not interfere with audio signals. The switch drivers feature a controlled switching speed that minimizes noise generated by turn-on and turn-off transients. The SCART standard specifies 2VRMS as the full-scale for audio signals. As the audio circuits process 0.5V RMS full-scale audio signals internal to the MAX9670/MAX9671, the gain-of-4 output amplifiers restore the audio signals to a full-scale of 2VRMS. To select which audio input source is routed to the TV SCART connector, write to bits 1 and 0 of the TV Audio Control register (01h). To select which audio input source is routed to the VCR SCART connector, write to bits 3 and 2 of the TV Audio Control register (01h). The power-on default is for the TV and VCR audio outputs to be muted (the inputs of the output amplifiers are connected to audio ground). See Tables 10 and 13. Volume Control Volume control is programmable from -62dB to 0dB in 2dB steps through I2C interface. The block consists of a resistive ladder network to generate 31 2dB volume control steps, a unity gain buffer to isolate the input from the resistive ladder, switches (MPLx and MNLx) that select 1 of 32 nodes on the resistive ladder, and logic to decode the the I2C volume control value. See Table 12. ______________________________________________________________________________________ 15 MAX9670/MAX9671 VDD Audio Outputs The MAX9670/MAX9671 audio output amplifiers feature Maxim's DirectDrive architecture, thereby eliminating the need for output-coupling capacitors required by conventional single-supply audio line drivers. An internal charge pump inverts the positive supply (VAUD), creating a negative supply (CPVSS). The audio output amplifiers operate from these bipolar supplies with their outputs biased about audio ground (Figure 2). The benefit of this audio ground bias is that the amplifier outputs do not have a DC component. The DC-blocking capacitors required with conventional audio line drivers are unnecessary, conserving board space, reducing system cost, and improving frequency response. MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors ACTIVITY DETECT ACTIVITY DETECT ACTIVITY DETECT MAX9670/MAX9671 ACTIVITY DETECT TV_Y/CVBS_IN CLAMP VCR_Y/CVBS_IN CLAMP ENC_Y/CVBS_IN CLAMP ENC_Y_IN CLAMP LOAD SENSE TV_Y/CVBS_OUT AV = 2V/V LPF LPF MUTE LOAD SENSE VCR_R/C_IN CLAMP/BIAS ENC_R/C_IN CLAMP/BIAS LPF ENC_C_IN CLAMP/BIAS LPF AV = 2V/V VCR_Y/CVBS_OUT AV = 2V/V TV_R/C_OUT AV = 2V/V VCR_R/C_OUT AV = 2V/V TV_G_OUT AV = 2V/V TV_B_OUT AV = 1V/V TVOUT_FS AV = 1V/V TV_SS AV = 1V/V VCR_SS MUTE VCR_G_IN CLAMP ENC_G_IN CLAMP LPF MUTE VCR_B_IN CLAMP ENC_B_IN CLAMP LPF MUTE VVID GNDVID VCRIN_FS 0.7V V12 +6V EP TO I2C x1 V12 +6V EP TO I2C x1 Figure 3. MAX9670/MAX9671 Video Section Function Diagram Video Section The video circuit routes different video formats between the set-top box decoder, the TV SCART connector, and 16 the VCR SCART connector. It also routes slow-switch and fast-switch control information. See Figure 3. ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors The transparent sync-tip clamp is transparent when the incoming video signal is DC-coupled and at or above ground. Under such conditions, the clamp never activates. Therefore, the outputs of video DACs that generate signals between 0 and 1V can be directly connected to the MAX9670/MAX9671 inputs. The bias circuit accepts AC-coupled chroma, which is a subcarrier with the color information modulated onto it. The bias voltage of the bias circuits is around 600mV. ENC_R/C_IN and VCR_R/C_IN can receive either a red video signal or a chroma video signal. Set the input configuration by writing to bits 7 and 3 of the VCR Video Input Control register (08h). See Tables 10 and 16. The MAX9670/MAX9671 also have video input detection. When activated, activity detect circuits check if sync is present on incoming CVBS and luma (Y) signals. If so, then there is a valid video signal. Read bits 0, 2, 4, and 5 of the Video Activity Status register (0Fh) to determine the status of the CVBS and luma (Y) inputs. See Table 21. In high-impedance mode, the inputs to the MAX9670/ MAX9671 do not distort the video signal in case the outputs of the video DAC are also connected to another video circuit such as a high-definition video filter amplifier. See the SCART Set-Top Box with Analog HD Outputs section. The inputs in high-impedance mode are biased at VVID/3, which is sufficiently above ground so that the ESD diodes never forward biases as the video signal changes. The input resistance is 222k, which presents negligible loading on the video current DAC. Video Reconstruction Filter The video DAC outputs of the set-top box decoder chip need to be lowpass-filtered to reject the out-of-band noise. The MAX9670/MAX9671 integrate sixth-order, Butterworth filters. The filter passband (1dB) is typically 5.5MHz, and the attenuation at 27MHz is 52dB. The filters are suited for standard-definition video. Video Outputs The video output amplifiers can both source and sink load current, allowing output loads to be DC- or ACcoupled. The amplifier output stage needs around 300mV of headroom from either supply rail. For video signals with a sync pulse, the sync tip is typically at 300mV, as shown in Figure 4. For a chroma signal, the blank level is typically at 1.5V, as shown in Figure 5. If the supply voltage is greater than 3.135V (5% below a 3.3V supply), each amplifier can drive two DC-coupled video loads to ground. If the supply is less than 3.135V, each amplifier can drive only one DC-coupled or AC-coupled video load. The SCART standard allows for video signals to have a superimposed DC component within 0 and 2V. Therefore, most video signals are DC-coupled at the output. In the unlikely event that the video signal needs to be AC-coupled, the coupling capacitors should be 220F or greater to keep the highpass filter formed by the 37.5 equivalent resistance of the video transmission line to a corner frequency of 4.8Hz or below to keep it well below the 25Hz frame rate of the PAL standard. The CVBS outputs have load sense circuits. If enabled, each load sense circuit checks for a load eight times per second by connecting an internal 15k pullup resistor to the output for 1ms. If the output is pulled up, no load is present. If the output stays low, a load is connected. Read bits 1 and 3 of the Video Activity Status register (0Fh) to determine load status. See Table 21. The selection of video sources that are sent to the TV SCART connector are controlled by bits 0 to 4 of the TV Video Input Control register (06h) while the selection of ______________________________________________________________________________________ 17 MAX9670/MAX9671 Video Inputs Whether the incoming video signal is AC-coupled or DC-coupled into the MAX9670/MAX9671 depends upon the origin, format, and voltage range of the video signal. Table 1 below shows the recommended connections. Always AC-couple an external video signal through a 0.1F capacitor because its voltage is not well defined (see the Typical Application Circuit ). For example, the video transmitter circuit might have a different ground than the video receiver, thereby level shifting the DC bias. 60Hz power line hum might cause the video signal to change DC bias slowly. Internal video signals that are between 0 and 1V can be DC-coupled. Most video DACs generate video signals between 0 and 1V because the video DAC sources current into a ground-referenced resistor. For the minority of video DACs that generate video signals between 2.3V and 3.3V because the video DAC sinks current from a VVID-referenced resistor, AC-couple the video signal to the MAX9670/MAX9671. The MAX9670/MAX9671 restore the DC level of incoming, AC-coupled video signals with either transparent sync-tip clamps or bias circuits. When using an ACcoupled input, the transparent sync-tip clamp automatically clamps the input signal minimum to ground, preventing it from going lower. A small current of 1A pulls down on the input to prevent an AC-coupled signal from drifting outside the input range of the part. Use sync-tip clamps with CVBS, RGB, and luma signals. MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors video sources that are sent to the VCR SCART connector are controlled by bits 0 to 2 of the VCR Video Input Control register (08h). See Tables 10, 14, and 16. The video outputs can be enabled or disabled by bits 2 through 7 of the Output Enable register (0Dh). See Table 18. Slow Switching The MAX9670/MAX9671 support the IEC 933-1, Amendment 1, three-level slow switching that selects the aspect ratio for the display (TV). Under I2C control, the MAX9670/MAX9671 set the slow-switching output voltage level. Table 2 shows the valid input levels of the slow-switching signal and the corresponding operating modes of the display device. Two bidirectional ports are available for slow-switching signals for the TV and VCR. The slow-switching input status is continuously read and stored in the Status register (0Eh). The slow-switching outputs can be set to a logic level or high impedance by writing to the TV Video Output Control register (07h) and the VCR Video Output Control register (09h). When enabled, INT becomes active low if the voltage level changes on TV_SS or VCR_SS. See Tables 10, 15, 17, and 20. Fast Switching The fast-switching signal was originally used to switch between CVBS and RGB signals on a pixel-by-pixel basis so that on-screen display (OSD) information could be inserted. Since modern set-top box decoder chips have integrated OSD circuitry, there is no need to create OSD information using the older technique. Now, the fast-switching signal is just used to switch between CVBS and RGB signal sources. Set the source of the fast-switching signal by writing to bits 4 and 3 of the TV Video Output Control register (07h). The fast-switching signal to the TV SCART connector can be enabled or disabled by bit 1 of the Output Enable register (0Dh). See Tables 10, 15, and 18. I2C Serial Interface The MAX9670/MAX9671 feature an I2C/SMBusTM-compatible, 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9670/ MAX9671 and the master at clock rates up to 400kHz. Figure 6 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. A master device writes data to the MAX9670/ MAX9671 by transmitting a START (S) condition, the proper slave address with the R/W bit set to 0, followed by the register address and then the data word. Each transmit sequence is framed by a START and a STOP (P) condition. Each word transmitted to the MAX9670/MAX9671 is 8 bits long and is followed by an acknowledge clock pulse. A master reads from the MAX9670/MAX9671 by transmitting the slave address with the R/W bit set to 0, the register address of the register to be read, a REPEATED START (Sr) condition, the slave address with the R/W bit set to 1, followed by a series of SCL pulses. The MAX9670/MAX9671 transmit data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or MAX9670 fig05 MAX9670 fig04 INPUT 200mV/div INPUT 500mV/div OUTPUT 500mV/div 20s/div Figure 4. MAX9670/MAX9671 Video Output with CVBS Signal, Multiburst Video Test Signal Shown 18 OUTPUT 200mV/div 10s/div Figure 5. MAX9670/MAX9671 Video Output with Chroma (C) Signal, Multiburst Video Test Signal Shown ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 SDA tBUF tSU, STA tSU, DAT tHD, STA tHD, DAT tLOW tSP tSU, STO SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 6. I2C Serial-Interface Timing Diagram REPEATED START condition, an acknowledge or a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500, is required on the SDA bus. SCL operates as only an input. A pullup resistor, typically greater than 500, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9670/MAX9671 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-tohigh transition on SDA while SCL is high (Figure 7). A START condition from the master signals the beginning of a transmission to the MAX9670/MAX9671. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. S Sr P SCL SDA Figure 7. START, STOP, and REPEATED START Conditions Early STOP Conditions The MAX9670/MAX9671 recognize a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The slave address is defined as the 7 most significant bits (MSBs) followed by the read/write (R/W) bit. Set the R/W bit to 1 to configure the MAX9670/MAX9671 to read mode. Set the R/W bit to 0 to configure the MAX9670/MAX9671 to write mode. The slave address is always the first byte of information sent to the MAX9670/MAX9671 after a START or a REPEATED START condition. The MAX9670/MAX9671 slave address is configurable with DEV_ADDR. Table 3 shows the possible slave addresses for the MAX9670/MAX9671. ______________________________________________________________________________________ 19 MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9670/MAX9671 use to handshake receipt of each byte of data when in write mode (see Figure 8). The MAX9670/MAX9671 pull down SDA during the entire master-generated ninth clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the ninth clock cycle to acknowledge receipt of data when Write Data Format A write to the MAX9670/MAX9671 consists of transmitting a START condition, the slave address with the R/W bit set to 0, one data byte to configure the internal register address pointer, one or more data bytes, and a STOP condition. Figure 9 illustrates the proper frame format for writing one byte of data to the MAX9670/MAX9671. Figure 10 illustrates the frame format for writing n bytes of data to the MAX9670/ MAX9671. CLOCK PULSE FOR ACKNOWLEDGMENT START CONDITION SCL the MAX9670/MAX9671 are in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9670/MAX9671, followed by a STOP condition. 1 2 8 The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9670/ MAX9671. The MAX9670/MAX9671 acknowledge receipt of the address byte during the master-generated ninth SCL pulse. The second byte transmitted from the master configures the MAX9670/MAX9671's internal register address pointer. The pointer tells the MAX9670/MAX9671 where to write the next byte of data. An acknowledge pulse is sent by the MAX9670/MAX9671 upon receipt of the address pointer data. 9 NOT ACKNOWLEDGE SDA ACKNOWLEDGE Figure 8. Acknowledge ACKNOWLEDGE FROM MAX9670/MAX9671 B7 ACKNOWLEDGE FROM MAX9670/MAX9671 SLAVE ADDRESS S 0 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9670/MAX9671 A REGISTER ADDRESS A DATA BYTE A R/W P 1 BYTE Figure 9. Writing a Byte of Data to the MAX9670/MAX9671 ACKNOWLEDGE FROM MAX9670/MAX9671 ACKNOWLEDGE FROM MAX9670/MAX9671 ACKNOWLEDGE FROM MAX9670/MAX9671 ACKNOWLEDGE FROM MAX9670/MAX9671 S SLAVE ADDRESS 0 A REGISTER ADDRESS R/W B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 A DATA BYTE 1 A 1 BYTE DATA BYTE n 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 10. Writing n Bytes of Data to the MAX9670/MAX9671 20 ______________________________________________________________________________________ A P Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors S SLAVE ADDRESS 0 A REGISTER ADDRESS R/W NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX9670/MAX9671 ACKNOWLEDGE FROM MAX9670/MAX9671 A Sr SLAVE ADDRESS REPEATED START 1 R/W A DATA BYTE A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 11. Reading One Indexed Byte of Data from the MAX9670/MAX9671 S SLAVE ADDRESS 0 R/W ACKNOWLEDGE FROM MAX9670/MAX9671 ACKNOWLEDGE FROM MAX9670/MAX9671 ACKNOWLEDGE FROM MAX9670/MAX9671 A REGISTER ADDRESS A Sr SLAVE ADDRESS REPEATED START NOT ACKNOWLEDGE FROM MASTER 1 R/W A DATA BYTE A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 12. Reading n Bytes of Indexed Data from the MAX9670/MAX9671 The third byte sent to the MAX9670/MAX9671 contains the data that is written to the chosen register. An acknowledge pulse from the MAX9670/MAX9671 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential register address locations within one continuous frame. The master signals the end of transmission by issuing a STOP condition. Read Data Format The master presets the address pointer by first sending the MAX9670/MAX9671's slave address with the R/W bit set to 0 followed by the register address after a START condition. The MAX9670/MAX9671 acknowledges receipt of its slave address and the register address by pulling SDA low during the ninth SCL clock pulse. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9670/MAX9671 transmits the contents of the specified register. Transmitted data is valid on the rising edge of the master-generated serial clock (SCL). The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from the register address location set by the previous transaction and not 00h and subsequent reads autoincrement the address pointer until the next STOP condition. Attempting to read from register addresses higher than 10h results in repeated reads from a dummy register containing FFh data. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figures 11 and 12 illustrate the frame format for reading data from the MAX9670/MAX9671. Interrupt Output When interrupt is enabled in modes 1 and 2, INT, which is an open-drain output, pulls low under the following conditions: slow-switch signals change value, CVBS input signals are detected or disappear, and CVBS output loads are added or removed. When interrupt is enabled in mode 3, INT pulls low only when the slow-switch signal changes value. Enable INT by writing a 1 into bit 4 of register 01h. See Table 13. The interrupt can be cleared by reading register 0Eh and 0Fh. Applications Information Audio Inputs The maximum full-scale audio signal that can be applied to the audio inputs is 0.5V RMS biased at ground. The recommended application circuit to attenuate and bias an incoming audio signal is shown in Figure 13. ______________________________________________________________________________________ 21 MAX9670/MAX9671 ACKNOWLEDGE FROM MAX9670/MAX9671 MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors STEREO AUDIO DACS 1F MAX9670 6.65k ENC_INL R1* 1F 6.65k ENC_INR R1* *R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53k, 1% DAC = PCM1742: R1 = 5.57k, 1% Figure 13. Application circuit to connect audio source to audio inputs. The 1F capacitor connected to the ground-referenced resistors biases the audio signal at ground. The resistors attenuate the audio signal. The audio path has a gain of 4V/V so that the full scale of the audio output signal is 2VRMS. If less than 2VRMS, full scale is desired at the audio outputs, and the full scale of the audio input signal should be proportionately decreased below 0.5VRMS. Operating Modes The MAX9670/MAX9671 has four operating modes, which can be set by writing to bits 6 and 7 of register 10h. See Table 19. Shutdown All circuitry is shutdown in the MAX9670/MAX9671 except for the I2C interface, which is designed with static CMOS logic. Except for register 10h, which sets the operating mode, the values in all of the other I2C registers are preserved while entering, during, and leaving shutdown mode. Standby Mode In standby mode, the MAX9670/MAX9671 monitor the slow-switch signals and decide whether to loop through the audio/video signals. If the VCR slow switch input has activity (6V or 12V at the input), the audio/video signals are looped through from the VCR SCART to the TV SCART. If the TV slow-switch input has activity, the audio/video signals are looped through from the TV SCART to the VCR SCART. If neither the VCR slowswitch input nor the TV slow switch input show activity, i.e., both inputs are at ground, no signals are looped through. If both the VCR slow-switch input and the TV slow-switch input have activity, the MAX9670/MAX9671 22 considers this condition to be illegal and does not loop through any signals. A finite state machine (Figure 14) controls the operation of the MAX9670/MAX9671. State 0 is always the initial state when the MAX9670/MAX9671 enter standby mode. Table 4 shows the values of the I2C registers in state 0. The state machine sets the other I2C registers to the correct values to loop through the audio/video signals in states 1 and 2 (see Tables 5 and 6). When the MAX9670/MAX9671 leaves standby mode, the values in all of the I2C registers except register 10h are preserved so that the operation is not disturbed. For example, if in standby mode, the MAX9670 is looping through the audio/video signals from VCR SCART to TV SCART, and if the microcontroller changes the operating mode from standby mode to full-power mode, the audio/video signals continue to be looped through during and after the mode change. The user does not experience any disruption in audio or video service. The microcontroller can be turned off in standby mode because the MAX9670/MAX9671 operate autonomously. Upon power-up, the default operating mode is standby mode. Full-Power Mode with Video Input Detection and Video Load Detection In this mode, the MAX9670/MAX9671 are fully on. If interrupt is enabled, INT goes active low whenever the slow-switch signal changes; a CVBS signal appears or disappears; or a CVBS load appears or disappears. The microcontroller can decide whether to change the routing configuration or operating mode of the MAX9670/MAX9671. Full-Power Mode Without Video Input Detection and Video Load Detection This mode is similar to the above mode except that video input detection and video load detection are not active. If interrupt is enabled, INT goes active low only when the slow-switch signal changes. Power Consumption The quiescent power consumption and average power consumption of the MAX9670/MAX9671 are very low because of 3.3V operation and low-power circuit design. Quiescent power consumption is defined when the MAX9670/MAX9671 are operating without loads and without any audio or video signals. Table 7 shows the quiescent power consumption in all 4 operating modes. Average power consumption is defined when the MAX9670/ MAX9671 drives typical signals into typical loads. Table 8 shows the average power consumption in full-power mode and Table 9 shows the input and output conditions. ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 TV_SS ACTIVE VCR_SS ACTIVE TV_SS NOT ACTIVE VCR_SS NOT ACTIVE STATE 0 SEARCH AUDIO: INACTIVE VIDEO: INACTIVE SLOW SWITCH: LISTENING FOR ACTIVITY FAST SWITCH: INACTIVE TV_SS ACTIVE VCR_SS NOT ACTIVE TV_SS NOT ACTIVE VCR_SS ACTIVE TV_SS NOT ACTIVE VCR_SS NOT ACTIVE TV_SS NOT ACTIVE VCR_SS NOT ACTIVE TV_SS ACTIVE VCR_SS NOT ACTIVE TV_SS NOT ACTIVE VCR_SS ACTIVE STATE 1 TV-TO-VCR STATE 2 VCR-TO-TV AUDIO: TV TO VCR VIDEO: TV TO VCR SLOW SWITCH: TV TO VCR FAST SWITCH: NOT APPLICABLE AUDIO: VCR TO TV VIDEO: VCR TO TV SLOW SWITCH: VCR TO TV FAST SWITCH: VCR TO TV TV_SS ACTIVE VCR_SS ACTIVE TV_SS ACTIVE VCR_SS ACTIVE TV_SS NOT ACTIVE VCR_SS ACTIVE TV_SS ACTIVE VCR_SS NOT ACTIVE Figure 14. Standby mode finite state machine. TV_SS is active when either 6V or 12V are present. VCR_SS is active when either 6V or 12V are present. S-Video The MAX9670/MAX9671 support S-video from the settop box to the TV, set-top box to the VCR, and VCR to the set-top box. S-video was not included in the original SCART specifications but was added afterwards. As a consequence, the luma (Y) signal of S-video shares the same SCART pin as the CVBS signal. Likewise, the chroma (C) signal shares the same SCART pin as the red signal. The pins that can carry both CVBS and luma have Y/CVBS in their names, and the pins that can carry red and chroma have R/C in their names. Now, the Y/CVBS signals are full duplex while the R/C signals are half duplex. Therefore, S-video is limited to being half duplex. The MAX9670/MAX9671 have to transmit a chroma signal and receive a chroma signal ______________________________________________________________________________________ 23 MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors 0.1F VCR_R/C_IN ENC_R/C_IN ENC_C_IN BIAS AV = 2V/V BIAS LPF BIAS LPF AV = 2V/V TV_R/C_OUT 75 VCR_R/C_OUT 75 MAX9670/MAX9671 TV SCART VCR SCART ON Figure 15. Gain-of-2 amplifier on VCR_R/C_OUT outputs chroma signal to VCR SCART connector. Notice that the pulldown switch on VCR_R/C_OUT is open. 0.1F VCR_R/C_IN ENC_R/C_IN ENC_C_IN BIAS AV = 2V/V BIAS LPF BIAS LPF AV = 2V/V TV_R/C_OUT 75 VCR_R/C_OUT 75 MAX9670/MAX9671 TV SCART VCR SCART OFF Figure 16. VCR_R/C_IN receives chroma signal from VCR SCART connector. Notice that the pulldown switch on VCR_R/C_OUT is closed and that the gain-of-2 amplifier is off. The chroma signal from VCR SCART is looped through to the TV SCART in the above configuration. on the same SCART pin, but not at the same time. The 75 resistor connected to VCR_R/C_OUT must act as a back termination resistor when the MAX9670/MAX9671 is transmitting chroma signal and as an input termination resistor when it is receiving a chroma signal. Figure 15 shows how the MAX9670/MAX9671 transmits a chroma signal to the VCR SCART connector while Figure 16 shows how the MAX9670/MAX9671 receives a chroma from the VCR SCART connector. 24 Write a 0 into bit 2 of register 09h to open the pulldown switch at VCR_R/C_OUT. To close the pulldown switch, write a 0 into bit 6 of register 0Dh to turn off the output amplifier, and then write a 1 into bit 2 of register 09h. See Tables 17 and 18. ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 TV_OUTR 10k MAX9670/MAX9671 MONO AUDIO 10k TV_OUTL 75 TV SCART TV_Y/CVBS_OUT 75 OR GREATER 75 OR GREATER RF MODULATOR Figure 17. Application Circuit to Connect CVBS and Mono Audio from TV SCART to RF Modulator Interfacing to an RF Modulator If the set-top box modulates CVBS and mono audio onto an RF carrier (for example, channel 3), a simple application circuit can provide the needed signals (see Figure 17). 10k resistor summer circuit between TV_OUTR and TV_OUTL creates the mono audio signal. The resistor-divider to ground on TV_Y/CVBS_OUT creates a video signal with normal amplitude. The unique feature of the MAX9670/MAX9671 that facilitates this application circuit is that the audio and video output amplifiers of the MAX9670/MAX9671 can drive multiple loads if V AUD and V VID are both greater than 3.135V. Unconnected-Chassis Discharge Protection and ESD Some set-top boxes are not connected to earth ground. As a result, the chassis can charge up to 500V. When a SCART cable is connected to the SCART connector, the charged chassis can discharge through a signal pin. The equivalent circuit is a 2200pF capacitor charged to 311V connected through less than 0.1 to a signal pin. The MAX9670/MAX9671 are soldered on the PCB when it experiences such a discharge. Therefore, the current spike flows through both external and internal ESD protection devices and is absorbed by the supply bypass capacitors, which have high capacitance and low ESR. To better protect the MAX9670/MAX9671 against excess voltages during the cable discharge condition or ESD events, add series resistors to all inputs and outputs to the SCART connector if series resistors are not already present in the application circuit. Also, add external ESD protection diodes (for example, BAV99) on all inputs and outputs to the SCART connector. SCART Set-Top Box with Analog HD Outputs In set-top boxes with SCART connectors and cinch connectors for high-definition YPbPr outputs, a triplevideo DAC usually outputs either standard-definition RGB signals that are routed to the MAX9670/MAX9671 or high-definition YPbPr signals that are routed through a high-definition filter amplifier like the MAX9653 (see Figure 19). The set-top box devices have a limited number of video DACs, and hence, one bank of triple-video DACs switches video format depending upon whether standard-definition RGB or high-definition YPbPr signals are required. When RGB signals are desired, the high-definition filter amplifier should be turned off so that the RGB signals do not appear on the YPbPr connectors. The MAX9653/MAX9654 are well-suited for this application because their video inputs are in high-impedance mode when in shutdown. ______________________________________________________________________________________ 25 MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors 12V 3.3V 0.1F V12 3.3V 0.1F VVID 0.1F VAUD VAUD TV_INL (MAX9671 ONLY) +3.3 V TV_INR (MAX9671 ONLY) STB CHIP VAUD CPVSS 2.55k 7.68k 1F CPVSS VAUD 2.55k 75 SDA MICROCONTROLLER 1F 7.68k TV_OUTR VAUD SCL 75 INT CPVSS TV_OUTL V12 DEV_ADDR 75 CPVSS TV_SS VVID 75 75 75 75 75 75 75 GNDVID VVID TVOUT_FS 75 75 VVID 75 TV_Y/CVBS_IN ENC_Y_IN GNDVID TV_Y/CVBS_OUT ENC_B_IN 75 GNDVID VVID TV_R/C_OUT ENC_G_IN 75 GNDVID VVID TV_G_OUT ENC_R/C_IN 75 VVID 75 ENC_Y/CVBS_IN 75 TV SCART EP TV_B_OUT VIDEO ENCODER 0.1F 75 MAX9670 MAX9671 75 VAUD GNDVID 75 GNDVID ENC_C_IN GNDVID 75 VCR_OUTR 75 VAUD 7.68k CPVSS 1F VCR_INR STEREO AUDIO DACS 1F CPVSS 2.55k 75 6.65k VCR_OUTL ENC_INL VAUD 7.68k CPVSS 1F VCR_INL R1* 1F VAUD CPVSS 2.55k 75 6.65k V12 VCR SCART VCR_SS ENC_INR VVID 0.1F 75 R1* EP VCR_B_IN 75 GNDVID VVID 0.1F 75 VCR_G_IN 75 75 VVID GNDVID 0.1F VCR_R/C_IN VVID GNDVID VCR_R/C_OUT *R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53k 1% DAC = PCM1742: R1 = 5.57k 1% VVID 75 GNDVID VCRIN_FS VVID 75 GNDVID VCR_Y/CVBS_OUT 75 VVID GNDVID 0.1F C1P EP VCR_Y/CVBS_IN C1N CPVSS 75 1F GNDVID 75 1F Figure 18. Application Circuit to Connect Series Resistors and External ESD Protection Diodes at MAX9670/MAX9671 Outputs 26 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors ENC_R/C_IN 0.1F 3.3V TV_G_OUT ENC_G_IN SET-TOP BOX CHIP 75 0.1F SCART CONNECTOR 3.3V 75 TV_G_OUT ENC_G_IN 0.1F SET-TOP BOX CHIP TV_B_OUT ENC_B_IN 75 ENC_R/C_IN TV_R/C_OUT 75 0.1F MAX9670/MAX9671 0.1F 75 TV_R/C_OUT TV_B_OUT ENC_B_IN INPUTS SET TO SYNC-TIP CLAMP SCART CONNECTOR 75 INPUTS SET TO HIGH IMPEDANCE DAC DAC 3.3V 3.3V DAC DAC 3.3V 3.3V DAC DAC MAX9653 MAX9654 YIN YOUT PBIN PBOUT 75 YIN YOUT PBIN PBOUT PRIN PROUT 0.1F 75 YPbPr OUTPUTS 75 PRIN MAX9653 MAX9654 0.1F 75 PROUT ON OFF (A) YPbPr OUTPUTS 75 SHDN 3.3V SHDN 75 0.1F (B) Figure 19. Triple DAC is connected to both a MAX9670/MAX9671 and a MAX9653/MAX9654 high-definition video-filter amplifier. (A) The MAX9670/MAX9671 are transmitting standard-definition RGB signals while the MAX9653/MAX9654 are in shutdown mode. (B) The MAX9670/MAX9671 are not transmitting RGB signals, but the MAX9653/MAX9654 are transmitting high-definition YPbPr signals. Similarly, when YPbPr signals are desired, ENC_R/C_IN, ENC_G_IN, and ENC_B_IN of the MAX9670/MAX9671 should be set to high-impedance mode by setting bit 4 in register 08h to high if those video inputs are AC-coupled. The high-impedance mode has higher priority whether ENC_R/C_IN is in sync-tip clamp or bias circuit mode (set by bit 3 in register 08h). If ENC_R/C_IN, ENC_G_IN, and ENC_B_IN are DC-coupled, the inputs should be left in sync-tip clamp mode. The RGB outputs of the MAX9670/MAX9671 should be muted or shut down. In either case, the inactive device should not distort the video signals generated by the DACs. Power-Supply Bypassing The MAX9670/MAX9671 feature single 3.3V and 12V supply operation and require no negative supply. The 12V supply V12 is for the SCART switching function. For V12, place a 0.1F bypass capacitor as close as possible. Connect all VAUD pins together to 3.3V and bypass with a 10F electrolytic capacitor in parallel with a 0.1F ceramic capacitor to audio ground. Bypass each VVID to video ground with a 0.1F ceramic capacitor. Using a Digital Supply The MAX9670/MAX9671 are designed to operate from noisy digital supplies. The high PSRR (49dB at 100kHz) allows the MAX9670/MAX9671 to reject the noise from the digital power supplies (see the Typical Operating Characteristics). If the digital power supply is very noisy and stripes appear on the television screen, increase the supply bypass capacitance. An additional, smaller capacitor in parallel with the main bypass capacitor can reduce digital supply noise because the smaller capacitor has lower equivalent series resistance (ESR) and equivalent series inductance (ESL). Layout and Grounding For optimal performance, use controlled-impedance traces for video signal paths and place input termination resistors and output back-termination resistors close to the MAX9670/MAX9671. Avoid routing video traces parallel to high-speed data lines. The MAX9670/MAX9671 provide separate ground connections for video and audio supplies. For best performance, use separate ground planes for each of the ground returns and connect all ground planes together at a single point. See the MAX9670/MAX9671 evaluation kit for a proven circuit board layout example. If the MAX9670/MAX9671 are mounted using flow soldering or wave soldering, the ground via(s) for the EP pad should have a finished hole size of at least 14mils to insure adequate wicking of soldering onto the exposed pad. If the MAX9670/MAX9671 are mounted using solder mask technique, the via requirement does not apply. In either case, a good connection between the exposed pad and ground is required to minimize noise from coupling onto the outputs. ______________________________________________________________________________________ 27 MAX9670/MAX9671 MAX9670/MAX9671 0.1F MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Table 1. Recommended Coupling for Incoming Video Signals and Input Circuit Configuration* VIDEO ORIGIN FORMAT VOLTAGE RANGE COUPLING INPUT CIRCUIT CONFIGURATION External External CVBS Unknown AC Transparent sync-tip clamp RGB Unknown AC External Transparent sync-tip clamp Y Unknown AC Transparent sync-tip clamp External C Unknown AC Bias circuit Internal CVBS 0 to 1V DC Transparent sync-tip clamp Internal RGB 0 to 1V DC Transparent sync-tip clamp Internal Y/C 0 to 1V DC Transparent sync-tip clamp Internal YPbPr 0 to 1V DC Transparent sync-tip clamp Internal CVBS 2.3V to 3.3V AC Transparent sync-tip clamp Internal RGB 2.3V to 3.3V AC Transparent sync-tip clamp Internal Y 2.3V to 3.3V AC Transparent sync-tip clamp Internal C 2.3V to 3.3V AC Bias circuit *Use a 0.1F capacitor to AC-couple a video signal into the MAX9670/MAX9671. Table 2. Slow-Switching Modes SLOW-SWITCHING SIGNAL VOLTAGE (V) 0 to 2 28 MODE Display device uses an internal source such as a built-in tuner to provide a video signal. 4.5 to 7.0 Display device uses a video signal from the SCART connector and sets the display to 16:9 aspect ratio. 9.5 to 12.6 Display device uses a signal from the SCART connector and sets the display to 4:3 aspect ratio. ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Table 3. Slave Address DEV_ADDR B7 B6 B5 B4 B3 B2 B1 B0 GNDVID VVID SCL SDA 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 R/W R/W R/W R/W Table 4. I2C Register Values in State 0* WRITE ADDRESS (hex) 94h 96h 98h 9Ah READ ADDRESS (hex) 95h 97h 99h 9Bh Table 5. I2C Register Values in State 1* VALUE (binary) REGISTER ADDRESS (hexadecimal) VALUE (binary) 00h uuuu uuuu 00h uuuu uuu0 01h uuuu 1111 01h uuuu 1011 06h uuuu uuuu 06h uuuu uuuu 07h uuuu uu10 07h uuu0 0u10 08h uuuu uuuu 08h uuuu u011 09h uuuu u010 09h uuuu u0MM 0Dh 0000 000u 0Dh 1100 001u REGISTER ADDRESS (hexadecimal) *u indicates that the bit is unchanged from its previous state. *u indicates that the bit is unchanged from its previous state; MM = Register 0Eh (bit 1, bit 0) Table 6. I2C Register Values in State 2* REGISTER ADDRESS (hexadecimal) VALUE (binary) 00h uuuu uuu0 01h uuuu 1101 06h uuu0 1010 07h uuu0 0uNN 08h uuuu uuuu 09h uuuu u110 0Dh 0011 111u *u indicates that the bit is unchanged from its previous state; NN = Register 0Eh (bit 3, bit 2) ______________________________________________________________________________________ 29 MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Table 7. Quiescent Power Consumption OPERATING MODE Table 8. Average Power Consumption POWER CONSUMPTION (mW) Shutdown 0.13 Standby mode with no video activity (i.e., TV slow-switch and VCR slow-switch inputs are at ground). Standby mode is the power-on default. 2.83 Full-power mode with input video detection and video load detection active. 66 Full-power mode without input video detection and video load detection active. 65 OPERATING MODE POWER CONSUMPTION (mW) Full-power mode with input video detection and video load detection active. 300 Full-power mode without input video detection and video load detection active. 300 Table 9. Conditions for Average Power Consumption Measurement PIN (MAX9670) 30 NAME TYPE SIGNAL LOAD 5 VAUD 9 ENC_INL Supply 3.3V N/A Input 0.25VRMS, 1kHz 10 N/A ENC_INR Input 0.25VRMS, 1kHz N/A 11 VCR_INL Input None N/A 12 VCR_INR Input None N/A 13 TV_OUTL Output 1VRMS, 1kHz 10k to ground 14 VCR_OUTL Output 1VRMS, 1kHz 10k to ground 15 VCR_OUTR Output 1VRMS, 1kHz 10k to ground 16 TV_OUTR Output 1VRMS, 1kHz 10k to ground 17 TV_SS Output 12V 10k to ground 18 V12 Supply 12V N/A 19 VCR_SS Input 0 N/A 20 TVOUT_FS Output 3.3V 150 to ground 21 VCRIN_FS Input 0 N/A 22 ENC_B_IN Input 50% flat field N/A 23 ENC_G_IN Input 50% flat field N/A 24 VCR_B_IN Input None N/A 25 VCR_G_IN Input None N/A 26 TV_B_OUT Output 50% flat field 150 to ground 27 TV_G_OUT Output 50% flat field 150 to ground 28 GNDVID Supply 0 N/A 29 VCR_R/C_IN Input None N/A 30 VVID Supply 3.3V N/A ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Table 9. Conditions for Average Power Consumption Measurement (continued) PIN (MAX9670) NAME TYPE SIGNAL LOAD 31 ENC_C_IN Input None N/A 32 ENC_R/C_IN Input 50% flat field N/A 33 TV_R/C_OUT Output 50% flat field 150 to ground 34 VCR_R/C_OUT Output 50% flat field 150 to ground 35 VCR_Y/CVBS_OUT Output 50% flat field 150 to ground 36 TV_Y/CVBS_OUT Output 50% flat field 150 to ground 37 VCR_Y/CVBS_IN Input None N/A 38 TV_Y/CVBS_IN Input None N/A 39 ENC_Y_IN Input None N/A 40 ENC_Y/CVBS_IN Input 50% flat field N/A Table 10. Data Format for Write Mode REGISTER ADDRESS (hex) BIT 7 BIT 6 00h Not used TV ZCD 01h Not used 02h 03h 04h 05h 06h 07h Not used Not used 08h VCR_R/C_IN clamp BIT 5 Not used 0Ah 0Bh 0Ch 0Dh 10h VCR_Y/ VCR_R/ CVBS_OUT C_OUT enable enable Operating mode BIT 3 TV volume control Not used 09h BIT 4 TV_R/ C_OUT enable BIT 2 BIT 1 BIT 0 TV audio output mute Interrupt VCR audio selection TV audio selection enable Not used Not used Not used Not used TV G and B video switch TV video switch Set TV fast switching Not used Set TV slow switching ENC R/G/B ENC_R/C_IN highVCR video switch clamp impedance bias VCR_R/C_OUT Set VCR slow ground switching Not used Not used Not used TV_Y/ TV_G_OUT TV_B_OUT TVOUT_FS Not used CVBS_OUT enable enable enable enable Not used ______________________________________________________________________________________ 31 MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Table 11. Data Format for Read Mode REGISTER ADDRESS (hex) BIT 7 BIT 6 0Eh Not used Power-on reset 0Fh BIT 5 BIT 4 BIT 3 Not used BIT 1 VCR slow-switch input status Not used ENC_Y/ CVBS_IN input video detection ENC_Y_IN input video detection BIT 2 TV slow switch input status VCR CVBS input video detection VCR CVBS output load BIT 0 TV CVBS output load TV CVBS input video detection Table 12. Register 00h: Audio Control DESCRIPTION BIT 7 6 5 4 3 2 1 0 TV Audio Mute 1 On (power-on default) 0 0dB gain (power-on default) 0 0 0 0 1 -2dB gain 0 0 0 1 0 -4dB gain 0 0 0 1 1 -6dB gain 0 0 1 0 0 -8dB gain 0 0 1 0 1 -10dB gain ... ... 0 ... 0 ... 0 ... 0 ... ... ... TV Zero-Crossing Detector Off ... TV Volume Control COMMENTS 0 1 1 1 1 0 -60dB gain 1 1 1 1 1 -62dB gain 0 Off 1 On (power-on default) Table 13. Register 01h: TV Audio DESCRIPTION BIT 7 6 5 4 3 2 Input Source for TV Audio Input Source for VCR Audio Interrupt Enable 32 COMMENTS 1 0 0 0 0 1 VCR audio 1 0 TV audio (MAX9671 only) 1 1 Encoder audio Mute (power-on default) 0 0 Encoder audio 0 1 VCR audio 1 0 TV audio (MAX9671 only) 1 1 Mute (power-on default) 0 Disabled (power-on default) 1 Enabled ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors DESCRIPTION BIT 7 6 5 4 3 Input Sources for TV Video Input Sources for TV_G_OUT and TV_B_OUT 2 1 0 0 0 0 COMMENTS TV_Y/CVBS_OUT TV_R/C_OUT ENC_Y/CVBS_IN ENC_R/C_IN 0 0 1 ENC_Y_IN ENC_C_IN 0 1 0 VCR_Y/CVBS_IN VCR_R/C_IN 0 1 1 TV_Y/CVBS_IN Mute 1 0 0 Not used Not used 1 0 1 Mute Mute 1 1 0 Mute Mute 1 1 1 Mute (power-on default) Mute (power-on default) TV_G_OUT TV_B_OUT 0 0 ENC_G_IN ENC_B_IN 0 1 VCR_G_IN VCR_B_IN 1 0 Mute Mute 1 1 Mute (power-on default) Mute (power-on default) Table 15. Register 07h: TV Video Output Control DESCRIPTION BIT 7 6 5 4 3 Set TV Slow Switching 0 Set TV Fast Switching 0 2 COMMENTS 1 0 0 0 Low (< 2V) internal source 0 1 Medium (4.5V to 7V); external SCART source with 16:9 aspect ratio 1 0 High impedance (power-on default) 1 1 High (> 9.5V); external SCART source with 4:3 aspect ratio GNDVID (power-on default) 0 1 Not used 1 0 Same level as VCRIN_FS 1 1 VVID ______________________________________________________________________________________ 33 MAX9670/MAX9671 Table 14. Register 06h: TV Video Input Control MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Table 16. Register 08h: ENC and VCR Video Input/Output Control DESCRIPTION BIT 7 6 5 4 3 Input Sources for VCR Video ENC_R/C_IN Clamp/Bias 34 1 0 0 0 0 0 0 1 ENC_Y_IN ENC_C_IN 0 1 0 VCR_Y/CVBS_IN VCR_R/C_IN 0 1 1 TV_Y/CVBS_IN Mute 1 0 0 Not used Not used 1 0 1 Mute Mute 1 1 0 Mute Mute 1 1 1 VCR_Y/CVBS_OUT VCR_R/C_OUT ENC_Y/CVBS_IN ENC_R/C_IN Mute (power-on default) Mute (power-on default) 0 DC restore clamp active at input (power-on default) 1 Chrominance bias applied at input 0 High-impedance bias off (power-on default) 1 Biases the R/C, G, and B inputs to high impedance (overwrites the ENC_R/C_IN clamp and bias bit) ENC R/C, G, and B inputs high-impedance bias (in HD application) VCR_R/C_IN Clamp/Bias COMMENTS 2 0 DC restore clamp active at input (power-on default) 1 Chrominance bias applied at input ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors DESCRIPTION BIT 7 6 5 4 3 2 Set VCR Slow Switching COMMENTS 1 0 0 0 Low (< 2V) internal source 0 1 Medium (4.5V to 7V); external SCART source with 16:9 aspect ratio 1 0 High impedance (power-on default) 1 1 High (> 9.5V); external SCART source with 4:3 aspect ratio 0 Normal operation; pulldown on VCR_R/C_OUT is off (power-on default) 1 Ground; pulldown on VCR_R/C_OUT is on; the output amplifier driving VCR_R/C_OUT is off VCR_R/C_OUT Ground Table 18. Register 0Dh: Output Enable DESCRIPTION BIT 7 6 5 4 3 2 TVOUT_FS Enable 0 TV_Y/CVBS_OUT Enable 1 TV_B_OUT Enable 0 TV_G_OUT Enable 1 0 TV_R/C_OUT Enable 1 VCR_R/C_OUT Enable VCR_Y/CVBS_OUT Enable 1 COMMENTS 0 0 Off (power-on default) 1 On Off (power-on default) On 0 Off (power-on default) 1 On Off (power-on default) On Off (power-on default) On 0 Off (power-on default) 1 On 0 Off (power-on default) 1 On ______________________________________________________________________________________ 35 MAX9670/MAX9671 Table 17. Register 09h: VCR Video Output Control MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Table 19. Register 10h: Operating Modes DESCRIPTION BIT 5 4 3 2 1 COMMENTS 7 6 0 0 0 Shutdown 0 1 Standby mode (power-on default). Input video detection circuits are active. Audio circuitry is off unless video is detected. Once slow switch is detected, the signal paths between the VCR and TV SCART are connected. 1 0 Full-power mode with input video detection and video-load detection active. 1 1 Full-power mode without input video detection and video-load detection active. 7 6 Operating Mode Table 20. Register 0Eh: Status DESCRIPTION BIT 5 4 3 2 TV Slow-Switching Input Status VCR Slow-Switching Input Status COMMENTS 1 0 0 0 0 to 2V; internal source 0 1 4.5V to 7V; external source with 16:9 aspect ratio 1 0 Not used 1 1 9.5V to 12.6V; external source with 4:3 aspect ratio 0 0 0 to 2V; internal source 0 1 4.5V to 7V; external source with 16:9 aspect ratio 1 0 Not used 1 1 9.5V to 12.6V; external source with 4:3 aspect ratio 0 VVID is too low for digital logic to operate 1 VVID is high enough for digital logic to operate Power-On Reset 36 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Table 21. Register 0Fh: Video Activity Status DESCRIPTION BIT 7 6 5 4 3 2 1 TV CVBS Input Video Detection TV CVBS Output Load 0 VCR CVBS Input Video Detection 1 VCR CVBS Output Load 0 ENC_Y/CVBS_IN Input Video Detection ENC_Y_IN Input Video Detection 1 0 COMMENTS 0 No video detected. 1 Video detected. 0 No video detected. 1 Video detected. No video detected. Video detected. 0 No load connected. 1 Load connected. No video detected. Video detected. 0 No video detected. 1 Video detected. ______________________________________________________________________________________ 37 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors MAX9670/MAX9671 Typical Application Circuit 12V 3.3V 3.3V 0.1F V12 0.1F VVID 0.1F VAUD 7.68k TV_INL (MAX9671 ONLY) +3.3 V 2.55k 7.68k TV_INR (MAX9671 ONLY) STB CHIP 2.55k SDA MICROCONTROLLER TV_OUTR 75 SCL TV_OUTL INT 75 DEV_ADDR TV_SS 75 TV_B_OUT VIDEO ENCODER TV SCART 75 TV_G_OUT ENC_Y/CVBS_IN 75 TV_R/C_OUT 75 75 ENC_R/C_IN TVOUT_FS 75 75 ENC_G_IN TV_Y/CVBS_OUT 0.1F 75 75 TV_Y/CVBS_IN ENC_B_IN 75 75 ENC_Y_IN 75 MAX9670 MAX9671 GNDVID VCR_OUTR ENC_C_IN 75 7.68k 75 1F VCR_INR 2.55k STEREO AUDIO DACS VCR_OUTL 1F 75 7.68k 6.65k ENC_INL 1F VCR_INL 2.55k R1* VCR_SS 1F 0.1F 6.65k 75 VCR_B_IN ENC_INR VCR SCART 75 0.1F R1* VCR_G_IN 75 0.1F VCR_R/C_IN VCR_R/C_OUT 75 VCRIN_FS 75 *R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53k 1% DAC = PCM1742: R1 = 5.57k 1% VCR_Y/CVBS_OUT 0.1F C1P EP 75 VCR_Y/CVBS_IN C1N CPVSS 1F 75 1F 38 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors VVID VCR_R/C_IN GNDVID TV_G_OUT TV_B_OUT VCR_G_IN VCR_B_IN ENC_G_IN ENC_B_IN VCRIN_FS N.C. 33 32 31 30 29 28 27 26 25 24 23 VCRIN_FS ENC_B_IN VCR_B_IN ENC_G_IN TV_B_OUT VCR_G_IN TV_G_OUT GNDVID VCR_R/C_IN VVID TOP VIEW TOP VIEW 30 29 28 27 26 25 24 23 22 21 20 TVOUT_FS ENC_C_IN 31 ENC_C_IN 34 22 TVOUT_FS ENC_R/C_IN 35 21 VCR_SS TV_R/C_OUT 36 20 V12 VCR_R/C_OUT 37 19 TV_SS VCR_Y/CVBS_OUT 38 18 TV_OUTR TV _Y/CVBS_OUT 39 17 VCR_OUTR VCR_Y/CVBS_IN 40 16 VCR_OUTL TV_Y/CVBS_IN 41 15 TV_OUTL 13 TV_OUTL ENC_Y_IN 42 14 VCR_INR ENC_Y_IN 39 12 VCR_INR ENC_Y/CVBS_IN 43 13 VCR_INL ENC_Y/CVBS_IN 40 11 VCR_INL N.C. 44 12 TV_INR *EP = EXPOSED PAD 2 3 4 DEV_ADDR INT 11 1 40 TQFN TV_INL 10 10 9 SCL 8 SDA INT 7 ENC_INL DEV_ADDR 6 *EP ENC_INR SCL 5 C1N 4 CPVSS 3 C1P 2 VAUD 1 SDA *EP ENC_INR TV_Y/CVBS_IN 38 9 14 VCR_OUTL VCR_Y/CVBS_IN 37 MAX9671 ENC_INL 15 VCR_OUTR 8 TV_Y/CVBS_OUT 36 CPVSS MAX9670 7 16 TV_OUTR VCR _Y/CVBS_OUT 35 C1N 17 TV_SS VCR_R/C_OUT 34 6 18 V12 C1P TV_R/C_OUT 33 5 19 VCR_SS VAUD ENC_R/C_IN 32 44 TQFN *EP = EXPOSED PAD Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 39 MAX9670/MAX9671 Pin Configurations MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 40 PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 40 TQFN T4066+3 21-0141 90-0054 44 TQFN T4477+2 21-0144 90-0127 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. ______________________________________________________________________________________ 41 MAX9670/MAX9671 Package Information (continued) MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Package Information (continued) For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 42 ______________________________________________________________________________________ Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. ______________________________________________________________________________________ 43 MAX9670/MAX9671 Package Information (continued) MAX9670/MAX9671 Low-Power Audio/Video Switch with Audio Volume Control for Dual SCART Connectors Revision History REVISION NUMBER REVISION DATE 0 7/09 Initial release 1 3/10 Added JA and JC information in the Absolute Maximum Ratings section, adjusted Note references, updated power consumption Figures, and made various corrections 2 12/10 Updated Table 14 DESCRIPTION PAGES CHANGED -- 1-8, 17, 20, 21, 22, 24-29, 33, 35, 36, 37 33 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 44 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.