$< XILINX XC5200L Field Programmable Gate Arrays June 1, 1996 (Version 1.0) Advance Product Specification Features High-density family of Field-Programmable Gate Arrays (FPGAs) JEDEC-compliant 3.3 V version of XC5200 FPGA family Design- and process-optimized for low cost - 0.5-um three-layer metal (TLM) process * SRAM-based, in-system reprogrammable architecture * Flexible architecture with abundant routing resources - VersaBlock logic module - VersaRing I/O interface Dedicated cell-feedthrough path - Hierarchical interconnect structure - Extensive registers/latches - Dedicated carry logic for arithmetic functions - Cascade chain for wide input functions - Dedicated IEEE 1149.1 boundary-scan logic - Internal 3-state bussing capability - Four global low-skew clock or signal distribution nets - Output slew-rate control - 4-mA sink current per output Configured by loading binary file - Unlimited reprogrammability - Seven programming modes, including high-speed Express mode * 100% factory tested * 100% architecture, pin-out and bit-stream compatible with XC5200 families * 100% footprint compatibility for common packages 5V tolerant inputs Fully supported by XACTstep Development System Includes complete support for XACT-Performance, X-BLOX, Unified Libraries, Relationaily Placed Macros (RPMs), XDelay, and XChecker - Wide selection of PC and workstation platforms - Interfaces to more than 100 third-party CAE tools Description The XC5200L Field-Programmablie Gate Array Family is engineered to deliver the lowest cost of any FPGA family. By optimizing the new XC5200L architecture for three-layer metal technology and 0.5-um CMOS SRAM process, dra- matic advances have been made in silicon efficiency. These advances position the XC5200L family as a cost- effective, high-volume alternative to gate arrays. Building on experiences gained with three previous suc- cessful SRAM FPGA families, the XC5200L family brings a robust feature set to high-density programmable logic design. The VersaBlock logic module, the VersaRing I/O interface, and a rich hierarchy of interconnect resources combine to enhance design flexibility and reduce time-to- market. Complete support for the XC5200L family is delivered through the familiar XACT step software environment. The XC5200L family is fully supported on popular workstation and PC platforms. Popular design entry methods are fully supported, including ABEL, schematic capture, and syn- thesis. Designers utilizing logic synthesis can use their existing Synopsys, Viewlogic, Mentor, and Exemplar tools to design with the XC5200L devices. Table 1: Initial XC5200L Field-Programmable Gate Array Family Members Device XC5202L XC5206L XC5215L Max Logic Gates 3,000 10,000 23,000 Typical Gate Range 2,000 - 3,000 6,000 - 10,000 : 15,000 - 23,000 VersaBlock Array 8x8 14x14 22 x 22 Number of CLBs 64 196 484 Number of Flip-Flops 256 784 1,936 Number of I/Os 84 148 : 244 TBUFs per Horizontal Longline 400 : 16 24 June 1, 1996 (Version 1.0) 4- 249XC5200L Field Programmable Gate Arrays XC5200L Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC5200L Operating Conditions Symbol Description Min Max | Units Voc Supply voltage relative to GND Commercial: T)j=0C to 85C junction 3.0 3.6 Vv Vig High-level input voltageCMOS configuration 2.0 5.0 Vv Vin Low-level input voltageCMOS configuration oo ~ -0.3 0.8 Vv Tw [Input signal transition time a - 250 | ns XC5200L DC Characteristics Over Operating Conditions Symbol | ~~" Description Min Max | Units Vou High-level output voltage @ |g, =-4 MA, Veg min 2.4 Vv Vo. ~~ |Low-level output voltage @ IL. = 4 mA, Ve, max (Note 1) oo 0.4 Vv leco ~~ Quiescent FPGA supply current(Note2) ~ N/A mA | Nh _ Leakage current : -10 +10 pA Cy ~~ |Input capacitance (sample tested) pe 15 pF ban Pad pull-up (when selected) @ V,, = OV (sample tested) | 0.02 | 0.25 mA Notes: 1. With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins. 2. With no output current loads, all package pins at Vcc or GND, either TTL or CMOS inputs, and the FPGA configured with a MakeBits tie option. XC5200L Absolute Maximum Ratings Symbol | Description Units Voc Supply voltage relative to GND -0.5 to +7.0 Vv Von Input voltage with respect to GND 0.5 to Veg +0.5 Vv Vig Voltage applied to 3-state output -0.5 to Veg +0.5 Vv Tstaq Storage temperature (ambient) , -65 to +150 C Tso. Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 oS C T, Junction temperature in plastic packages +125 C Junction temperature in ceramic packages +150 ore Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 4- 250 June 1, 1996 (Version 1.0)