Supertex inc.
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV5308B
Features
►Processed with HVCMOS® technology
►Low power level shifting
►Source/sink current minimum 20mA
►Shift register speed 8.0MHz
►Latched data outputs
►CMOS compatible inputs
►Forward and reverse shifting options
►Diode to VPP allows efcient power recovery
General Description
The HV5308B is a low voltage serial to high voltage parallel
converter with push-pull outputs. This device has been designed
for use as a driver for AC-electroluminescent displays. It can also
be used in any application requiring multiple output high voltage
current sourcing and sinking capabilities, such as driving plasma
panels, vacuum uorescent, or large matrix LCD displays.
The HV5308B consists of a 32-bit shift register, 32 latches, and
control logic to enable outputs. Q1 is connected to the rst stage
of the shift register through the Output Enable logic. Data is shifted
through the shift register on the low to high transition of the clock.
When viewed from the top of the package, the HV5308B shifts
in the clockwise direction. A data output buffer is provided for
cascading devices. This output reects the current status of the
last bit of the shift register (32). Operation of the shift register is
not affected by the LE (latch enable) or the OE (output enable)
inputs. Transfer of data from the shift register to the latch occurs
when the LE input is high. The data in the latch is retained when
LE is low.
Typical Application Circuit
32-Channel Serial to Parallel Converter
With High Voltage Push-Pull Outputs
DATA
INPUT
CLK
LE
OE
HV
OUT
1
Micro
Processor
Supertex HV5308B
Display
Panel
Columns
Row
Driver
HV
OUT
32
Data Input for cascading the next HV5308B
DATA
OUT
Low Voltage High Voltage
Shift Register
Latches
Output Contr.
Level
Translators
&
Push-Pull
Output
Buffers
VPP
VDD
2
HV5308B
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Ordering Information
Device
Package Options
44-Lead
Quad Cerpac
.650x.650in body
.190in height (max)
.050in pitch
44-Lead PQFP
10.00x10.00mm body
2.35mm height (max)
0.80mm pitch
44-Lead PLCC
.653x.653in body
.180in height (max)
.050in pitch
HV5308B HV5308DJ-B* HV5308PG-B-G HV5308PJ-B-G
-G indicates package is RoHS compliant (‘Green’).
* Hi-Rel process ow available.
Absolute Maximum Ratings
Supply voltage, VDD -0.5V to +16V
Supply voltage, VPP -0.5V to +90V
Logic input levels -0.5V to VDD +0.5V
Ground current11.5A
Continuous total power dissipation2
Plastic
Ceramic
1200mW
1500mW
Operating temperature range
Plastic
Ceramic
-40OC to +85OC
-55OC to +125OC
Storage temperature range -65OC to +150OC
Parameter Value
Pin Congurations
Notes:
1. Duty cycle is limited by the total power dissipated in the package.
2. For operation above 25°C ambient derate linearly to maximum
operating temperature at 20mW/°C for plastic and at 15mW/°C for
ceramic.
1 44
6 40
1
44
Product Marking
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability. All voltages are referenced to device ground.
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW
HV5308PG-B
LLLLLLLLL
CCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
A = Assembler ID
C = Country of Origin*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW AAA
HV5308PJ-B
LLLLLLLLLL
CCCCCCCCCCC
44-Lead PQFP (PG)
(top view)
44-Lead PLCC (PJ)
(top view)
44-Lead PQFP
(PG)
44-Lead PLCC
(PJ)
1 44
6 40
44-Lead Quad Cerpac (DJ)
(top view)
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
*May be part of top marking
Top Marking
Bottom Marking
YYWW
HV5308DJ-B
LLLLLLLLLL
CCCCCCCCCCC
AAA
44-Lead Quad Cerpac
(DJ)
Packages may or may not include the following marks: Si or
3
HV5308B
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Sym Parameter Min Max Units Conditions
Electrical Characteristics (VPP = 60V, VDD = 12V, TA = 25°C)
DC Characteristics
IPP VPP supply current - 0.5 mA HVOUTPUTS high to low
IDDQ IDD supply current (quiescent) - 100 µA All inputs = VDD or GND
IDD IDD supply current (operating) - 15 mA VDD = VDD max, fCLK = 8.0MHz
VOH (data) Shift register output voltage 10.5 - V IO = -100µA
VOL (data) Shift register output voltage - 1.0 V IO = 100µA
IIH Current leakage, any input - 1.0 µA VIN = VDD
IIL Current leakage, any input - -1.0 µA VIN = 0
VOC HV output clamp diode voltage - -1.5 V IOL = -100mA
VOH HV output when sourcing 52 - V IOH = -20mA, -40 to 85°C
VOL HV output when sinking - 8.0 V IOL = 20mA, -40 to 85°C
VOH HV output when sourcing 52 - V IOH = -15mA, -55 to 125°C
VOL HV output when sinking - 8.0 V IOL = 15mA, -55 to 125°C
Power-Up Sequence
Power-up sequence should be the following:
1. Connect ground
2. Apply VDD
3. Set all inputs (Data, CLK, LE, etc.) to a known state
4. Apply VPP
5. The VPP should not fall below VDD or oat during operation.
Power-down sequence should be the reverse of the above.
Sym Parameter Min Max Units
Recommended Operating Conditions (over -40°C to 85°C for plastic and -55°C to 125°C for ceramic)
VDD Logic voltage supply 10.8 13.2 V
VPP High voltage supply 8.0 80 V
VIH Input high voltage VDD - 2.0 VDD V
VIL Input low voltage 0 2.0 V
fCLK Clock frequency 0 8.0 MHz
4
HV5308B
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Switching Waveforms
LE
HVOUT
w/ S/R LOW
Data Valid
50%
DATA
IN
CLK
DATA
OUT
tSU tH
tWL tWH
50%
50%
tDLH
tDHL
50%
tWLE
tDLE tSLE
50% 50%
tON
10%
90%
90%
10%
tOFF
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
VIH
VIL
VOH
VOL
VOH
VOL
50%
50% 50% 50%
HVOUT
w/ S/R HIGH
AC Characteristics
Sym Parameter Min Max Units Conditions
fCLK Clock frequency - 8.0 MHz ---
tWL or tWH Clock width, HIGH or LOW 62 - ns ---
tSU Setup time before CLK rises 25 - ns ---
tHHold time after CLK rises 10 - ns ---
tDLH (Data) Data output delay after L to H CLK - 110 ns CL = 15pF
tDHL (Data) Data output delay after H to L CLK - 110 ns CL = 15pF
tDLE LE delay after L to H CLK 50 - ns ---
tWLE Width of LE pulse 50 - ns ---
tSLE LE setup time before L to H CLK 50 - ns ---
tON Delay from LE to HVOUT, L to H - 500 ns ---
tOFF Delay from LE to HVOUT, H to L - 500 ns ---
5
HV5308B
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Functional Block Diagram
VPP
LE
OE
HV
OUT
2
•
•
•
28 Additional
Outputs
•
•
•
HV
OUT
31
HV
OUT
1
HV
OUT
32
DATA
INPUT
CLK
DATA
OUT
32 bit
Static
Register
32 bit
Latches
DATA IN LE OE HV OUT
X X L All HVOUT = LOW
X L H Previous latched data
H H H H
L H H L
Function Tables
DATA IN CLK* DATA OUT
H H
L L
X No No change
Note:
* = LOW - to - HIGH transition
H = High
L = Low
X = Don’t Care
Input and Output Equivalent Circuits
VDD
DATA
INPUT
GND
VPP
GND
HV
OUT
Logic Inputs
GND
DATA OUT
Logic Data Output High Voltage Outputs
VDD
6
HV5308B
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Pin # Function Description
1 HVOUT22
High voltage outputs.
High voltage push-pull outputs, which, depending on controlling low voltage data,
can drive loads either to GND, or to VPP rail levels.
2 HVOUT21
3 HVOUT20
4 HVOUT19
5 HVOUT18
6 HVOUT17
7 HVOUT16
8 HVOUT15
9 HVOUT14
10 HVOUT13
11 HVOUT12
12 HVOUT11
13 HVOUT10
14 HVOUT9
15 HVOUT8
16 HVOUT7
17 HVOUT6
18 HVOUT5
19 HVOUT4
20 HVOUT3
21 HVOUT2
22 HVOUT1
23 DATA OUT
Serial data output.
Data output for cascading to the data input of the next device.
24
N/C No connect.25
26
27 CLK
Data shift register clock
Input are shifted into the shift register on the positive edge of the clock.
28 GND Logic and high voltage ground
29 VPP High voltage power rail.
30 VDD Low voltage logic power rail.
44-Lead PQFP Pin Assignment (PG)
7
HV5308B
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Pin # Function Description
31 LE
Latch enable input.
When LE is HIGH, shift register data is transferred into a data latch. When LE is
LOW, data is latched, and new data can be clocked into the shift register.
32 DATA IN
Serial data input.
Data needs to be present before each rising edge of the clock.
33 OE
Output enable input.
When OE is LOW, all HV outputs are forced into a LOW state, regardless of data in
each channel. When OE is HIGH, all HV outputs reect data latched.
34 N/C No connect.
35 HVOUT32
High voltage outputs.
High voltage push-pull outputs, which, depending on controlling low voltage data,
can drive loads either to GND, or to VPP rail levels.
36 HVOUT31
37 HVOUT30
38 HVOUT29
39 HVOUT28
40 HVOUT27
41 HVOUT26
42 HVOUT25
43 HVOUT24
44 HVOUT23
44-Lead PQFP Pin Assignment (PG)
8
HV5308B
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
44-Lead Quad Cerpac/PLCC Pin Assignment (DJ/PJ)
Pin # Function Description
1 HVOUT17
High voltage outputs.
High voltage push-pull outputs, which, depending on controlling low voltage data,
can drive loads either to GND, or to VPP rail levels.
2 HVOUT16
3 HVOUT15
4 HVOUT14
5 HVOUT13
6 HVOUT12
7 HVOUT11
8 HVOUT10
9 HVOUT9
10 HVOUT8
11 HVOUT7
12 HVOUT6
13 HVOUT5
14 HVOUT4
15 HVOUT3
16 HVOUT2
17 HVOUT1
18 DATA OUT
Serial data output.
Data output for cascading to the data input of the next device.
19
N/C No connect.20
21
22 CLK
Data shift register clock
Input are shifted into the shift register on the positive edge of the clock.
23 GND Logic and high voltage ground
24 VPP High voltage power rail.
25 VDD Low voltage logic power rail.
26 LE
Latch enable input.
When LE is HIGH, shift register data is transferred into a data latch. When LE is
LOW, data is latched, and new data can be clocked into the shift register.
27 DATA IN
Serial data input.
Data needs to be present before each rising edge of the clock.
9
HV5308B
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Pin # Function Description
28 OE
Output enable input.
When OE is LOW, all HV outputs are forced into a LOW state, regardless of data
in each channel. When OE is HIGH, all HV outputs reect data latched.
29 N/C No connect.
30 HVOUT32
High voltage outputs.
High voltage push-pull outputs, which, depending on controlling low voltage data,
can drive loads either to GND, or to VPP rail levels.
31 HVOUT31
32 HVOUT30
33 HVOUT29
34 HVOUT28
35 HVOUT27
36 HVOUT26
37 HVOUT25
38 HVOUT24
39 HVOUT23
40 HVOUT22
41 HVOUT21
42 HVOUT20
43 HVOUT19
44 HVOUT18
44-Lead Quad Cerpac/PLCC Pin Assignment (DJ/PJ)
10
HV5308B
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
44-Lead Quad Cerpac Package Outline (DJ)
.650x.650in body, .190in height (max), .050in pitch
.150 MAX
.040 x 45O
1
.075 MAX
640
D
D1
E1 E
Top View
View B
AA2
A1
Seating
Plane
e
b
Note 1
(Index Area)
.035 x 45O
0.25 max
3 Places
.025 MIN
View B
44
b1
Horizontal Side View
Vertical Side View
Symbol A A1 A2 b b1 D D1 E E1 e
Dimension
(inches)
MIN .155 .090 .060
REF
.017 .026 .685 .630 .685 .630 .050
BSC
NOM .172 .100 .019 .029 .690 .650 .690 .650
MAX .190 .120 .021 .032 .695 .665 .695 .665
JEDEC Registration MO-087, Variation AB, Issue B, August, 1991.
Drawings not to scale.
Supertex Doc. #: DSPD-44CERPACDJ, Version D090808.
Note:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.
11
HV5308B
Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
44-Lead PQFP Package Outline (PG)
10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch
Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ
Dimension
(mm)
MIN 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80*
0.80
BSC
0.73
1.95
REF
0.25
BSC
0O
NOM - - 2.00 - 13.90 10.00 13.90 10.00 0.88 3.5O
MAX 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* 1.03 7O
JEDEC Registration MO-112, Variation AA-2, Issue B, Sep.1995.
* This dimension is not specied in the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-44PQFPPG, Version C041309.
1
44
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
View B
Seating
Plane
Top View
D
D1
E
E1
be
Side View
A2
A
A1
Note 1
(Index Area
D1/4 x E1/4)
Note:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2011 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA
94089
Tel: 408-222-8888
www
.supertex.com
12
HV5308B
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline information go to http://www.
supertex.com/packaging.html.)
Doc.# DSFP-HV5308B
C042811
44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max), .050in pitch
Symbol A A1 A2 b b1 D D1 E E1 e R
Dimension
(inches)
MIN .165 .090 .062 .013 .026 .685 .650 .685 .650
.050
BSC
.025
NOM .172 .105 - - - .690 .653 .690 .653 .035
MAX .180 .120 .083 .021 .036†.695 .656 .695 .656 .045
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-44PLCCPJ, Version F031111.
.150 MAX
.048/.042 x 45O
1
.075 MAX
6 40
D
D1
E1 E
Top View
Horizontal Side View
View B
A A2
A1
Seating
Plane
e
b
Note 1
(Index Area)
.056/.042 x 45O
.020max
(3 Places)
.020 MIN
Vertical Side View
View B
Note 2
44
b1
Base
Plane
R
Notes:
1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or
a printed indicator.
2. Actual shape of this feature may vary.